[Zrouter-src-freebsd] ZRouter.org: push to FreeBSD HEAD tree

zrouter-src-freebsd at zrouter.org zrouter-src-freebsd at zrouter.org
Tue Apr 17 08:58:22 UTC 2012


details:   http://zrouter.org/hg/FreeBSD/head//rev/428842767fa6
changeset: 452:428842767fa6
user:      Aleksandr Rybalko <ray at ddteam.net>
date:      Tue Apr 17 11:36:47 2012 +0300
description:
Remove old files from FreeBSD HEAD @svn 234370r.

diffstat:

 head/contrib/bind9/RELEASE-NOTES-BIND-9.8.1.html                                                   |   368 -
 head/contrib/bind9/RELEASE-NOTES-BIND-9.8.1.pdf                                                    |   Bin 
 head/contrib/bind9/RELEASE-NOTES-BIND-9.8.1.txt                                                    |   268 -
 head/contrib/bind9/release-notes.css                                                               |    60 -
 head/contrib/com_err/Makefile.am                                                                   |    39 -
 head/contrib/com_err/Makefile.in                                                                   |   910 -
 head/contrib/com_err/getarg.c                                                                      |   379 -
 head/contrib/com_err/getarg.h                                                                      |    76 -
 head/contrib/com_err/lex.c                                                                         |  1896 ---
 head/contrib/com_err/parse.c                                                                       |  1716 --
 head/contrib/com_err/parse.h                                                                       |    81 -
 head/contrib/libcxxrt/typeinfo                                                                     |    26 -
 head/contrib/llvm/include/llvm/ADT/VectorExtras.h                                                  |    41 -
 head/contrib/llvm/include/llvm/CodeGen/BinaryObject.h                                              |   353 -
 head/contrib/llvm/include/llvm/CodeGen/ObjectCodeEmitter.h                                         |   171 -
 head/contrib/llvm/include/llvm/DebugInfoProbe.h                                                    |    67 -
 head/contrib/llvm/include/llvm/IntrinsicsAlpha.td                                                  |    18 -
 head/contrib/llvm/include/llvm/Transforms/Utils/BasicInliner.h                                     |    55 -
 head/contrib/llvm/lib/CodeGen/ELF.h                                                                |   227 -
 head/contrib/llvm/lib/CodeGen/ELFCodeEmitter.cpp                                                   |   205 -
 head/contrib/llvm/lib/CodeGen/ELFCodeEmitter.h                                                     |    78 -
 head/contrib/llvm/lib/CodeGen/ELFWriter.cpp                                                        |  1105 -
 head/contrib/llvm/lib/CodeGen/ELFWriter.h                                                          |   251 -
 head/contrib/llvm/lib/CodeGen/LiveRangeEdit.h                                                      |   206 -
 head/contrib/llvm/lib/CodeGen/ObjectCodeEmitter.cpp                                                |   141 -
 head/contrib/llvm/lib/CodeGen/RegAllocLinearScan.cpp                                               |  1543 --
 head/contrib/llvm/lib/CodeGen/ScheduleDAGEmit.cpp                                                  |    68 -
 head/contrib/llvm/lib/CodeGen/ScheduleDAGInstrs.h                                                  |   212 -
 head/contrib/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp                                     |   265 -
 head/contrib/llvm/lib/CodeGen/Splitter.cpp                                                         |   827 -
 head/contrib/llvm/lib/CodeGen/Splitter.h                                                           |   101 -
 head/contrib/llvm/lib/CodeGen/VirtRegRewriter.cpp                                                  |  2633 ----
 head/contrib/llvm/lib/CodeGen/VirtRegRewriter.h                                                    |    32 -
 head/contrib/llvm/lib/ExecutionEngine/JIT/Intercept.cpp                                            |   162 -
 head/contrib/llvm/lib/ExecutionEngine/JIT/JITDebugRegisterer.cpp                                   |   211 -
 head/contrib/llvm/lib/ExecutionEngine/JIT/JITDebugRegisterer.h                                     |   116 -
 head/contrib/llvm/lib/ExecutionEngine/JIT/OProfileJITEventListener.cpp                             |   192 -
 head/contrib/llvm/lib/ExecutionEngine/MCJIT/Intercept.cpp                                          |   162 -
 head/contrib/llvm/lib/MC/ELFObjectWriter.h                                                         |   446 -
 head/contrib/llvm/lib/MC/MCELFStreamer.h                                                           |   141 -
 head/contrib/llvm/lib/MC/MCLoggingStreamer.cpp                                                     |   250 -
 head/contrib/llvm/lib/Target/ARM/ARMGlobalMerge.cpp                                                |   219 -
 head/contrib/llvm/lib/Target/Alpha/Alpha.h                                                         |    43 -
 head/contrib/llvm/lib/Target/Alpha/Alpha.td                                                        |    68 -
 head/contrib/llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp                                             |   166 -
 head/contrib/llvm/lib/Target/Alpha/AlphaBranchSelector.cpp                                         |    66 -
 head/contrib/llvm/lib/Target/Alpha/AlphaCallingConv.td                                             |    38 -
 head/contrib/llvm/lib/Target/Alpha/AlphaFrameLowering.cpp                                          |   143 -
 head/contrib/llvm/lib/Target/Alpha/AlphaFrameLowering.h                                            |    43 -
 head/contrib/llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp                                           |   425 -
 head/contrib/llvm/lib/Target/Alpha/AlphaISelLowering.cpp                                           |   962 -
 head/contrib/llvm/lib/Target/Alpha/AlphaISelLowering.h                                             |   142 -
 head/contrib/llvm/lib/Target/Alpha/AlphaInstrFormats.td                                            |   268 -
 head/contrib/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp                                              |   382 -
 head/contrib/llvm/lib/Target/Alpha/AlphaInstrInfo.h                                                |    85 -
 head/contrib/llvm/lib/Target/Alpha/AlphaInstrInfo.td                                               |  1159 -
 head/contrib/llvm/lib/Target/Alpha/AlphaLLRP.cpp                                                   |   158 -
 head/contrib/llvm/lib/Target/Alpha/AlphaMachineFunctionInfo.h                                      |    62 -
 head/contrib/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp                                           |   199 -
 head/contrib/llvm/lib/Target/Alpha/AlphaRegisterInfo.h                                             |    56 -
 head/contrib/llvm/lib/Target/Alpha/AlphaRegisterInfo.td                                            |   133 -
 head/contrib/llvm/lib/Target/Alpha/AlphaRelocations.h                                              |    31 -
 head/contrib/llvm/lib/Target/Alpha/AlphaSchedule.td                                                |    85 -
 head/contrib/llvm/lib/Target/Alpha/AlphaSelectionDAGInfo.cpp                                       |    23 -
 head/contrib/llvm/lib/Target/Alpha/AlphaSelectionDAGInfo.h                                         |    31 -
 head/contrib/llvm/lib/Target/Alpha/AlphaSubtarget.cpp                                              |    35 -
 head/contrib/llvm/lib/Target/Alpha/AlphaSubtarget.h                                                |    49 -
 head/contrib/llvm/lib/Target/Alpha/AlphaTargetMachine.cpp                                          |    51 -
 head/contrib/llvm/lib/Target/Alpha/AlphaTargetMachine.h                                            |    66 -
 head/contrib/llvm/lib/Target/Alpha/MCTargetDesc/AlphaMCAsmInfo.cpp                                 |    23 -
 head/contrib/llvm/lib/Target/Alpha/MCTargetDesc/AlphaMCAsmInfo.h                                   |    29 -
 head/contrib/llvm/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp                              |    78 -
 head/contrib/llvm/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.h                                |    40 -
 head/contrib/llvm/lib/Target/Alpha/TargetInfo/AlphaTargetInfo.cpp                                  |    20 -
 head/contrib/llvm/lib/Target/Blackfin/Blackfin.h                                                   |    31 -
 head/contrib/llvm/lib/Target/Blackfin/Blackfin.td                                                  |   202 -
 head/contrib/llvm/lib/Target/Blackfin/BlackfinAsmPrinter.cpp                                       |   156 -
 head/contrib/llvm/lib/Target/Blackfin/BlackfinCallingConv.td                                       |    30 -
 head/contrib/llvm/lib/Target/Blackfin/BlackfinFrameLowering.cpp                                    |   130 -
 head/contrib/llvm/lib/Target/Blackfin/BlackfinFrameLowering.h                                      |    47 -
 head/contrib/llvm/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp                                     |   180 -
 head/contrib/llvm/lib/Target/Blackfin/BlackfinISelLowering.cpp                                     |   645 -
 head/contrib/llvm/lib/Target/Blackfin/BlackfinISelLowering.h                                       |    83 -
 head/contrib/llvm/lib/Target/Blackfin/BlackfinInstrFormats.td                                      |    34 -
 head/contrib/llvm/lib/Target/Blackfin/BlackfinInstrInfo.cpp                                        |   256 -
 head/contrib/llvm/lib/Target/Blackfin/BlackfinInstrInfo.h                                          |    81 -
 head/contrib/llvm/lib/Target/Blackfin/BlackfinInstrInfo.td                                         |   862 -
 head/contrib/llvm/lib/Target/Blackfin/BlackfinIntrinsicInfo.cpp                                    |   104 -
 head/contrib/llvm/lib/Target/Blackfin/BlackfinIntrinsicInfo.h                                      |    32 -
 head/contrib/llvm/lib/Target/Blackfin/BlackfinIntrinsics.td                                        |    34 -
 head/contrib/llvm/lib/Target/Blackfin/BlackfinRegisterInfo.cpp                                     |   344 -
 head/contrib/llvm/lib/Target/Blackfin/BlackfinRegisterInfo.h                                       |    77 -
 head/contrib/llvm/lib/Target/Blackfin/BlackfinRegisterInfo.td                                      |   277 -
 head/contrib/llvm/lib/Target/Blackfin/BlackfinSelectionDAGInfo.cpp                                 |    24 -
 head/contrib/llvm/lib/Target/Blackfin/BlackfinSelectionDAGInfo.h                                   |    31 -
 head/contrib/llvm/lib/Target/Blackfin/BlackfinSubtarget.cpp                                        |    44 -
 head/contrib/llvm/lib/Target/Blackfin/BlackfinSubtarget.h                                          |    49 -
 head/contrib/llvm/lib/Target/Blackfin/BlackfinTargetMachine.cpp                                    |    43 -
 head/contrib/llvm/lib/Target/Blackfin/BlackfinTargetMachine.h                                      |    68 -
 head/contrib/llvm/lib/Target/Blackfin/MCTargetDesc/BlackfinMCAsmInfo.cpp                           |    22 -
 head/contrib/llvm/lib/Target/Blackfin/MCTargetDesc/BlackfinMCAsmInfo.h                             |    29 -
 head/contrib/llvm/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.cpp                        |    81 -
 head/contrib/llvm/lib/Target/Blackfin/MCTargetDesc/BlackfinMCTargetDesc.h                          |    38 -
 head/contrib/llvm/lib/Target/Blackfin/TargetInfo/BlackfinTargetInfo.cpp                            |    21 -
 head/contrib/llvm/lib/Target/CBackend/CBackend.cpp                                                 |  3617 -----
 head/contrib/llvm/lib/Target/CBackend/CTargetMachine.h                                             |    42 -
 head/contrib/llvm/lib/Target/CBackend/TargetInfo/CBackendTargetInfo.cpp                            |    21 -
 head/contrib/llvm/lib/Target/Mips/MipsMCSymbolRefExpr.cpp                                          |    70 -
 head/contrib/llvm/lib/Target/Mips/MipsMCSymbolRefExpr.h                                            |    67 -
 head/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp                             |    32 -
 head/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.h                               |    30 -
 head/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp                          |    81 -
 head/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h                            |    38 -
 head/contrib/llvm/lib/Target/SystemZ/SystemZ.h                                                     |    52 -
 head/contrib/llvm/lib/Target/SystemZ/SystemZ.td                                                    |    61 -
 head/contrib/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp                                         |   221 -
 head/contrib/llvm/lib/Target/SystemZ/SystemZCallingConv.td                                         |    46 -
 head/contrib/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp                                      |   386 -
 head/contrib/llvm/lib/Target/SystemZ/SystemZFrameLowering.h                                        |    57 -
 head/contrib/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp                                       |   779 -
 head/contrib/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp                                       |   868 -
 head/contrib/llvm/lib/Target/SystemZ/SystemZISelLowering.h                                         |   145 -
 head/contrib/llvm/lib/Target/SystemZ/SystemZInstrBuilder.h                                         |   128 -
 head/contrib/llvm/lib/Target/SystemZ/SystemZInstrFP.td                                             |   340 -
 head/contrib/llvm/lib/Target/SystemZ/SystemZInstrFormats.td                                        |   133 -
 head/contrib/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp                                          |   439 -
 head/contrib/llvm/lib/Target/SystemZ/SystemZInstrInfo.h                                            |   113 -
 head/contrib/llvm/lib/Target/SystemZ/SystemZInstrInfo.td                                           |  1147 -
 head/contrib/llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.h                                  |    51 -
 head/contrib/llvm/lib/Target/SystemZ/SystemZOperands.td                                            |   325 -
 head/contrib/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp                                       |   143 -
 head/contrib/llvm/lib/Target/SystemZ/SystemZRegisterInfo.h                                         |    60 -
 head/contrib/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td                                        |   205 -
 head/contrib/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp                                   |    23 -
 head/contrib/llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.h                                     |    31 -
 head/contrib/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp                                          |    54 -
 head/contrib/llvm/lib/Target/SystemZ/SystemZSubtarget.h                                            |    48 -
 head/contrib/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp                                      |    40 -
 head/contrib/llvm/lib/Target/SystemZ/SystemZTargetMachine.h                                        |    68 -
 head/contrib/llvm/lib/Target/SystemZ/TargetInfo/SystemZTargetInfo.cpp                              |    19 -
 head/contrib/llvm/lib/Target/TargetFrameLowering.cpp                                               |    45 -
 head/contrib/llvm/lib/Transforms/Utils/BasicInliner.cpp                                            |   182 -
 head/contrib/llvm/lib/VMCore/DebugInfoProbe.cpp                                                    |   225 -
 head/contrib/llvm/tools/bugpoint/CMakeLists.txt                                                    |    14 -
 head/contrib/llvm/tools/bugpoint/Makefile                                                          |    16 -
 head/contrib/llvm/tools/clang/include/clang/AST/UsuallyTinyPtrVector.h                             |   114 -
 head/contrib/llvm/tools/clang/include/clang/Analysis/Support/SaveAndRestore.h                      |    47 -
 head/contrib/llvm/tools/clang/include/clang/Driver/HostInfo.h                                      |    94 -
 head/contrib/llvm/tools/clang/include/clang/Index/CallGraph.h                                      |   146 -
 head/contrib/llvm/tools/clang/include/clang/Sema/MultiInitializer.h                                |    72 -
 head/contrib/llvm/tools/clang/include/clang/Serialization/ChainedIncludesSource.h                  |    75 -
 head/contrib/llvm/tools/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ExprEngineBuilders.h |    80 -
 head/contrib/llvm/tools/clang/lib/Analysis/AnalysisContext.cpp                                     |   436 -
 head/contrib/llvm/tools/clang/lib/CodeGen/CGException.h                                            |    56 -
 head/contrib/llvm/tools/clang/lib/CodeGen/CGTemporaries.cpp                                        |    49 -
 head/contrib/llvm/tools/clang/lib/Driver/HostInfo.cpp                                              |   731 -
 head/contrib/llvm/tools/clang/lib/Index/CallGraph.cpp                                              |   150 -
 head/contrib/llvm/tools/clang/lib/Sema/MultiInitializer.cpp                                        |    92 -
 head/contrib/llvm/tools/clang/lib/Serialization/ChainedIncludesSource.cpp                          |   240 -
 head/contrib/llvm/tools/clang/lib/StaticAnalyzer/Core/AggExprVisitor.cpp                           |    69 -
 head/contrib/llvm/tools/clang/utils/TableGen/CMakeLists.txt                                        |    12 -
 head/contrib/llvm/tools/clang/utils/TableGen/Makefile                                              |    19 -
 head/contrib/llvm/tools/llc/CMakeLists.txt                                                         |     5 -
 head/contrib/llvm/tools/llc/Makefile                                                               |    21 -
 head/contrib/llvm/tools/lli/CMakeLists.txt                                                         |     5 -
 head/contrib/llvm/tools/lli/Makefile                                                               |    15 -
 head/contrib/llvm/tools/llvm-ar/CMakeLists.txt                                                     |     8 -
 head/contrib/llvm/tools/llvm-ar/Makefile                                                           |    25 -
 head/contrib/llvm/tools/llvm-as/CMakeLists.txt                                                     |     6 -
 head/contrib/llvm/tools/llvm-as/Makefile                                                           |    17 -
 head/contrib/llvm/tools/llvm-bcanalyzer/CMakeLists.txt                                             |     6 -
 head/contrib/llvm/tools/llvm-bcanalyzer/Makefile                                                   |    17 -
 head/contrib/llvm/tools/llvm-diff/CMakeLists.txt                                                   |     8 -
 head/contrib/llvm/tools/llvm-diff/Makefile                                                         |    17 -
 head/contrib/llvm/tools/llvm-dis/CMakeLists.txt                                                    |     6 -
 head/contrib/llvm/tools/llvm-dis/Makefile                                                          |    17 -
 head/contrib/llvm/tools/llvm-extract/CMakeLists.txt                                                |     5 -
 head/contrib/llvm/tools/llvm-extract/Makefile                                                      |    18 -
 head/contrib/llvm/tools/llvm-ld/CMakeLists.txt                                                     |     8 -
 head/contrib/llvm/tools/llvm-ld/Makefile                                                           |    15 -
 head/contrib/llvm/tools/llvm-link/CMakeLists.txt                                                   |     5 -
 head/contrib/llvm/tools/llvm-link/Makefile                                                         |    17 -
 head/contrib/llvm/tools/llvm-mc/CMakeLists.txt                                                     |     6 -
 head/contrib/llvm/tools/llvm-mc/Makefile                                                           |    24 -
 head/contrib/llvm/tools/llvm-nm/CMakeLists.txt                                                     |     5 -
 head/contrib/llvm/tools/llvm-nm/Makefile                                                           |    17 -
 head/contrib/llvm/tools/llvm-objdump/CMakeLists.txt                                                |    14 -
 head/contrib/llvm/tools/llvm-objdump/Makefile                                                      |    18 -
 head/contrib/llvm/tools/llvm-prof/CMakeLists.txt                                                   |     5 -
 head/contrib/llvm/tools/llvm-prof/Makefile                                                         |    17 -
 head/contrib/llvm/tools/llvm-ranlib/CMakeLists.txt                                                 |     6 -
 head/contrib/llvm/tools/llvm-ranlib/Makefile                                                       |    18 -
 head/contrib/llvm/tools/llvm-rtdyld/CMakeLists.txt                                                 |     5 -
 head/contrib/llvm/tools/llvm-rtdyld/Makefile                                                       |    23 -
 head/contrib/llvm/tools/llvm-stub/CMakeLists.txt                                                   |     3 -
 head/contrib/llvm/tools/llvm-stub/Makefile                                                         |    13 -
 head/contrib/llvm/tools/macho-dump/CMakeLists.txt                                                  |     5 -
 head/contrib/llvm/tools/macho-dump/Makefile                                                        |    23 -
 head/contrib/llvm/tools/opt/CMakeLists.txt                                                         |     8 -
 head/contrib/llvm/tools/opt/Makefile                                                               |    14 -
 head/contrib/llvm/utils/TableGen/ARMDecoderEmitter.cpp                                             |  1790 --
 head/contrib/llvm/utils/TableGen/ARMDecoderEmitter.h                                               |    49 -
 head/contrib/llvm/utils/TableGen/InstrEnumEmitter.cpp                                              |    48 -
 head/contrib/llvm/utils/TableGen/InstrEnumEmitter.h                                                |    33 -
 head/crypto/heimdal/appl/ftp/ftp/krb4.c                                                            |   340 -
 head/crypto/heimdal/appl/ftp/ftpd/krb4.c                                                           |   340 -
 head/crypto/heimdal/appl/login/login_protos.h                                                      |    91 -
 head/crypto/heimdal/appl/telnet/libtelnet/kerberos.c                                               |   723 -
 head/crypto/heimdal/appl/telnet/libtelnet/krb4encpwd.c                                             |   436 -
 head/crypto/heimdal/cf/ChangeLog                                                                   |  1232 -
 head/crypto/heimdal/cf/Makefile.am.common                                                          |   249 -
 head/crypto/heimdal/cf/aix.m4                                                                      |    57 -
 head/crypto/heimdal/cf/auth-modules.m4                                                             |    45 -
 head/crypto/heimdal/cf/autobuild.m4                                                                |    34 -
 head/crypto/heimdal/cf/broken-getaddrinfo.m4                                                       |    26 -
 head/crypto/heimdal/cf/broken-glob.m4                                                              |    29 -
 head/crypto/heimdal/cf/broken-realloc.m4                                                           |    25 -
 head/crypto/heimdal/cf/broken-snprintf.m4                                                          |    63 -
 head/crypto/heimdal/cf/broken.m4                                                                   |    12 -
 head/crypto/heimdal/cf/broken2.m4                                                                  |    25 -
 head/crypto/heimdal/cf/c-attribute.m4                                                              |    28 -
 head/crypto/heimdal/cf/c-function.m4                                                               |    33 -
 head/crypto/heimdal/cf/capabilities.m4                                                             |    14 -
 head/crypto/heimdal/cf/check-compile-et.m4                                                         |   109 -
 head/crypto/heimdal/cf/check-getpwnam_r-posix.m4                                                   |    25 -
 head/crypto/heimdal/cf/check-man.m4                                                                |    58 -
 head/crypto/heimdal/cf/check-netinet-ip-and-tcp.m4                                                 |    33 -
 head/crypto/heimdal/cf/check-type-extra.m4                                                         |    23 -
 head/crypto/heimdal/cf/check-var.m4                                                                |    27 -
 head/crypto/heimdal/cf/check-x.m4                                                                  |    53 -
 head/crypto/heimdal/cf/check-xau.m4                                                                |    64 -
 head/crypto/heimdal/cf/crypto.m4                                                                   |   177 -
 head/crypto/heimdal/cf/db.m4                                                                       |   211 -
 head/crypto/heimdal/cf/destdirs.m4                                                                 |    18 -
 head/crypto/heimdal/cf/dlopen.m4                                                                   |    11 -
 head/crypto/heimdal/cf/find-func-no-libs.m4                                                        |     9 -
 head/crypto/heimdal/cf/find-func-no-libs2.m4                                                       |    63 -
 head/crypto/heimdal/cf/find-func.m4                                                                |     9 -
 head/crypto/heimdal/cf/find-if-not-broken.m4                                                       |    12 -
 head/crypto/heimdal/cf/framework-security.m4                                                       |    31 -
 head/crypto/heimdal/cf/have-pragma-weak.m4                                                         |    37 -
 head/crypto/heimdal/cf/have-struct-field.m4                                                        |    21 -
 head/crypto/heimdal/cf/have-type.m4                                                                |    30 -
 head/crypto/heimdal/cf/have-types.m4                                                               |    12 -
 head/crypto/heimdal/cf/install-catman.sh                                                           |    72 -
 head/crypto/heimdal/cf/irix.m4                                                                     |    26 -
 head/crypto/heimdal/cf/krb-bigendian.m4                                                            |    62 -
 head/crypto/heimdal/cf/krb-func-getcwd-broken.m4                                                   |    41 -
 head/crypto/heimdal/cf/krb-func-getlogin.m4                                                        |    22 -
 head/crypto/heimdal/cf/krb-ipv6.m4                                                                 |   149 -
 head/crypto/heimdal/cf/krb-prog-ln-s.m4                                                            |    28 -
 head/crypto/heimdal/cf/krb-prog-ranlib.m4                                                          |     8 -
 head/crypto/heimdal/cf/krb-prog-yacc.m4                                                            |    12 -
 head/crypto/heimdal/cf/krb-readline.m4                                                             |    39 -
 head/crypto/heimdal/cf/krb-struct-spwd.m4                                                          |    21 -
 head/crypto/heimdal/cf/krb-struct-winsize.m4                                                       |    25 -
 head/crypto/heimdal/cf/krb-sys-aix.m4                                                              |    15 -
 head/crypto/heimdal/cf/krb-sys-nextstep.m4                                                         |    18 -
 head/crypto/heimdal/cf/krb-version.m4                                                              |    24 -
 head/crypto/heimdal/cf/largefile.m4                                                                |    16 -
 head/crypto/heimdal/cf/make-proto.pl                                                               |   337 -
 head/crypto/heimdal/cf/mips-abi.m4                                                                 |    87 -
 head/crypto/heimdal/cf/misc.m4                                                                     |    15 -
 head/crypto/heimdal/cf/need-proto.m4                                                               |    22 -
 head/crypto/heimdal/cf/osfc2.m4                                                                    |    14 -
 head/crypto/heimdal/cf/otp.m4                                                                      |    27 -
 head/crypto/heimdal/cf/proto-compat.m4                                                             |    21 -
 head/crypto/heimdal/cf/pthreads.m4                                                                 |    75 -
 head/crypto/heimdal/cf/resolv.m4                                                                   |   109 -
 head/crypto/heimdal/cf/retsigtype.m4                                                               |    18 -
 head/crypto/heimdal/cf/roken-frag.m4                                                               |   655 -
 head/crypto/heimdal/cf/roken.m4                                                                    |    64 -
 head/crypto/heimdal/cf/socket-wrapper.m4                                                           |    16 -
 head/crypto/heimdal/cf/sunos.m4                                                                    |    25 -
 head/crypto/heimdal/cf/telnet.m4                                                                   |    78 -
 head/crypto/heimdal/cf/test-package.m4                                                             |   133 -
 head/crypto/heimdal/cf/valgrind-suppressions                                                       |    84 -
 head/crypto/heimdal/cf/vararray.m4                                                                 |    16 -
 head/crypto/heimdal/cf/version-script.m4                                                           |    40 -
 head/crypto/heimdal/cf/wflags.m4                                                                   |    28 -
 head/crypto/heimdal/cf/win32.m4                                                                    |    12 -
 head/crypto/heimdal/cf/with-all.m4                                                                 |    42 -
 head/crypto/heimdal/configure.in                                                                   |   543 -
 head/crypto/heimdal/include/make_crypto.c                                                          |   111 -
 head/crypto/heimdal/kcm/cursor.c                                                                   |   151 -
 head/crypto/heimdal/kcm/kcm_protos.h                                                               |   288 -
 head/crypto/heimdal/kdc/524.c                                                                      |   400 -
 head/crypto/heimdal/kdc/kadb.h                                                                     |    84 -
 head/crypto/heimdal/kdc/kaserver.c                                                                 |   951 -
 head/crypto/heimdal/kdc/kerberos4.c                                                                |   805 -
 head/crypto/heimdal/kdc/v4_dump.c                                                                  |   143 -
 head/crypto/heimdal/kuser/kimpersonate.1                                                           |   152 -
 head/crypto/heimdal/lib/45/45_locl.h                                                               |    52 -
 head/crypto/heimdal/lib/45/Makefile.am                                                             |    11 -
 head/crypto/heimdal/lib/45/Makefile.in                                                             |   787 -
 head/crypto/heimdal/lib/45/get_ad_tkt.c                                                            |   116 -
 head/crypto/heimdal/lib/45/mk_req.c                                                                |   139 -
 head/crypto/heimdal/lib/asn1/CMS.asn1                                                              |   152 -
 head/crypto/heimdal/lib/asn1/k5.asn1                                                               |   634 -
 head/crypto/heimdal/lib/asn1/parse.c                                                               |  2831 ----
 head/crypto/heimdal/lib/asn1/parse.h                                                               |   249 -
 head/crypto/heimdal/lib/asn1/parse.y                                                               |  1015 -
 head/crypto/heimdal/lib/auth/ChangeLog                                                             |   206 -
 head/crypto/heimdal/lib/auth/Makefile.am                                                           |     6 -
 head/crypto/heimdal/lib/auth/Makefile.in                                                           |   815 -
 head/crypto/heimdal/lib/auth/afskauthlib/Makefile.am                                               |    51 -
 head/crypto/heimdal/lib/auth/afskauthlib/Makefile.in                                               |   723 -
 head/crypto/heimdal/lib/auth/afskauthlib/verify.c                                                  |   307 -
 head/crypto/heimdal/lib/auth/pam/Makefile.am                                                       |    69 -
 head/crypto/heimdal/lib/auth/pam/Makefile.in                                                       |   733 -
 head/crypto/heimdal/lib/auth/pam/pam.c                                                             |   443 -
 head/crypto/heimdal/lib/auth/pam/pam.conf.add                                                      |    97 -
 head/crypto/heimdal/lib/auth/sia/Makefile.am                                                       |   116 -
 head/crypto/heimdal/lib/auth/sia/Makefile.in                                                       |   778 -
 head/crypto/heimdal/lib/auth/sia/krb4+c2_matrix.conf                                               |    58 -
 head/crypto/heimdal/lib/auth/sia/krb4_matrix.conf                                                  |    59 -
 head/crypto/heimdal/lib/auth/sia/krb5+c2_matrix.conf                                               |    27 -
 head/crypto/heimdal/lib/auth/sia/krb5_matrix.conf                                                  |    27 -
 head/crypto/heimdal/lib/auth/sia/make-rpath                                                        |    34 -
 head/crypto/heimdal/lib/auth/sia/posix_getpw.c                                                     |    78 -
 head/crypto/heimdal/lib/auth/sia/security.patch                                                    |    11 -
 head/crypto/heimdal/lib/auth/sia/sia.c                                                             |   703 -
 head/crypto/heimdal/lib/auth/sia/sia_locl.h                                                        |    93 -
 head/crypto/heimdal/lib/gssapi/gss.c                                                               |   205 -
 head/crypto/heimdal/lib/gssapi/krb5/v1.c                                                           |   104 -
 head/crypto/heimdal/lib/gssapi/ntlm/digest.c                                                       |   435 -
 head/crypto/heimdal/lib/gssapi/ntlm/inquire_cred.c                                                 |    78 -
 head/crypto/heimdal/lib/hx509/data/bleichenbacher-bad.pem                                          |    12 -
 head/crypto/heimdal/lib/hx509/data/bleichenbacher-good.pem                                         |    12 -
 head/crypto/heimdal/lib/hx509/data/bleichenbacher-sf-pad-correct.pem                               |    16 -
 head/crypto/heimdal/lib/hx509/data/ca.crt                                                          |    15 -
 head/crypto/heimdal/lib/hx509/data/ca.key                                                          |    15 -
 head/crypto/heimdal/lib/hx509/data/crl1.crl                                                        |     8 -
 head/crypto/heimdal/lib/hx509/data/crl1.der                                                        |   Bin 
 head/crypto/heimdal/lib/hx509/data/gen-req.sh                                                      |   316 -
 head/crypto/heimdal/lib/hx509/data/j.pem                                                           |    26 -
 head/crypto/heimdal/lib/hx509/data/kdc.crt                                                         |    59 -
 head/crypto/heimdal/lib/hx509/data/kdc.key                                                         |    15 -
 head/crypto/heimdal/lib/hx509/data/key.der                                                         |   Bin 
 head/crypto/heimdal/lib/hx509/data/key2.der                                                        |   Bin 
 head/crypto/heimdal/lib/hx509/data/nist-data                                                       |    91 -
 head/crypto/heimdal/lib/hx509/data/nist-data2                                                      |   291 -
 head/crypto/heimdal/lib/hx509/data/no-proxy-test.crt                                               |    13 -
 head/crypto/heimdal/lib/hx509/data/no-proxy-test.key                                               |    15 -
 head/crypto/heimdal/lib/hx509/data/ocsp-req1.der                                                   |   Bin 
 head/crypto/heimdal/lib/hx509/data/ocsp-req2.der                                                   |   Bin 
 head/crypto/heimdal/lib/hx509/data/ocsp-resp1-2.der                                                |   Bin 
 head/crypto/heimdal/lib/hx509/data/ocsp-resp1-3.der                                                |   Bin 
 head/crypto/heimdal/lib/hx509/data/ocsp-resp1-ca.der                                               |   Bin 
 head/crypto/heimdal/lib/hx509/data/ocsp-resp1-keyhash.der                                          |   Bin 
 head/crypto/heimdal/lib/hx509/data/ocsp-resp1-ocsp-no-cert.der                                     |   Bin 
 head/crypto/heimdal/lib/hx509/data/ocsp-resp1-ocsp.der                                             |   Bin 
 head/crypto/heimdal/lib/hx509/data/ocsp-resp1.der                                                  |   Bin 
 head/crypto/heimdal/lib/hx509/data/ocsp-resp2.der                                                  |   Bin 
 head/crypto/heimdal/lib/hx509/data/ocsp-responder.crt                                              |    56 -
 head/crypto/heimdal/lib/hx509/data/ocsp-responder.key                                              |    15 -
 head/crypto/heimdal/lib/hx509/data/openssl.cnf                                                     |   182 -
 head/crypto/heimdal/lib/hx509/data/pkinit-proxy-chain.crt                                          |    70 -
 head/crypto/heimdal/lib/hx509/data/pkinit-proxy.crt                                                |    14 -
 head/crypto/heimdal/lib/hx509/data/pkinit-proxy.key                                                |    15 -
 head/crypto/heimdal/lib/hx509/data/pkinit-pw.key                                                   |    18 -
 head/crypto/heimdal/lib/hx509/data/pkinit.crt                                                      |    56 -
 head/crypto/heimdal/lib/hx509/data/pkinit.key                                                      |    15 -
 head/crypto/heimdal/lib/hx509/data/proxy-level-test.crt                                            |    15 -
 head/crypto/heimdal/lib/hx509/data/proxy-level-test.key                                            |    15 -
 head/crypto/heimdal/lib/hx509/data/proxy-test.crt                                                  |    14 -
 head/crypto/heimdal/lib/hx509/data/proxy-test.key                                                  |    15 -
 head/crypto/heimdal/lib/hx509/data/proxy10-child-child-test.crt                                    |    16 -
 head/crypto/heimdal/lib/hx509/data/proxy10-child-child-test.key                                    |    15 -
 head/crypto/heimdal/lib/hx509/data/proxy10-child-test.crt                                          |    15 -
 head/crypto/heimdal/lib/hx509/data/proxy10-child-test.key                                          |    15 -
 head/crypto/heimdal/lib/hx509/data/proxy10-test.crt                                                |    14 -
 head/crypto/heimdal/lib/hx509/data/proxy10-test.key                                                |    15 -
 head/crypto/heimdal/lib/hx509/data/revoke.crt                                                      |    53 -
 head/crypto/heimdal/lib/hx509/data/revoke.key                                                      |    15 -
 head/crypto/heimdal/lib/hx509/data/sf-class2-root.pem                                              |    24 -
 head/crypto/heimdal/lib/hx509/data/static-file                                                     |    84 -
 head/crypto/heimdal/lib/hx509/data/sub-ca.crt                                                      |    60 -
 head/crypto/heimdal/lib/hx509/data/sub-ca.key                                                      |    15 -
 head/crypto/heimdal/lib/hx509/data/sub-cert.crt                                                    |    53 -
 head/crypto/heimdal/lib/hx509/data/sub-cert.key                                                    |    15 -
 head/crypto/heimdal/lib/hx509/data/sub-cert.p12                                                    |   Bin 
 head/crypto/heimdal/lib/hx509/data/test-ds-only.crt                                                |    53 -
 head/crypto/heimdal/lib/hx509/data/test-ds-only.key                                                |    15 -
 head/crypto/heimdal/lib/hx509/data/test-enveloped-aes-128                                          |   Bin 
 head/crypto/heimdal/lib/hx509/data/test-enveloped-aes-256                                          |   Bin 
 head/crypto/heimdal/lib/hx509/data/test-enveloped-des                                              |   Bin 
 head/crypto/heimdal/lib/hx509/data/test-enveloped-des-ede3                                         |   Bin 
 head/crypto/heimdal/lib/hx509/data/test-enveloped-rc2-128                                          |   Bin 
 head/crypto/heimdal/lib/hx509/data/test-enveloped-rc2-40                                           |   Bin 
 head/crypto/heimdal/lib/hx509/data/test-enveloped-rc2-64                                           |   Bin 
 head/crypto/heimdal/lib/hx509/data/test-ke-only.crt                                                |    53 -
 head/crypto/heimdal/lib/hx509/data/test-ke-only.key                                                |    15 -
 head/crypto/heimdal/lib/hx509/data/test-nopw.p12                                                   |   Bin 
 head/crypto/heimdal/lib/hx509/data/test-pw.key                                                     |    18 -
 head/crypto/heimdal/lib/hx509/data/test-signed-data                                                |   Bin 
 head/crypto/heimdal/lib/hx509/data/test-signed-data-noattr                                         |   Bin 
 head/crypto/heimdal/lib/hx509/data/test-signed-data-noattr-nocerts                                 |   Bin 
 head/crypto/heimdal/lib/hx509/data/test.combined.crt                                               |    68 -
 head/crypto/heimdal/lib/hx509/data/test.crt                                                        |    53 -
 head/crypto/heimdal/lib/hx509/data/test.key                                                        |    15 -
 head/crypto/heimdal/lib/hx509/data/test.p12                                                        |   Bin 
 head/crypto/heimdal/lib/hx509/data/yutaka-pad-broken-ca.pem                                        |    16 -
 head/crypto/heimdal/lib/hx509/data/yutaka-pad-broken-cert.pem                                      |    18 -
 head/crypto/heimdal/lib/hx509/data/yutaka-pad-ok-ca.pem                                            |    16 -
 head/crypto/heimdal/lib/hx509/data/yutaka-pad-ok-cert.pem                                          |    18 -
 head/crypto/heimdal/lib/hx509/data/yutaka-pad.key                                                  |    15 -
 head/crypto/heimdal/lib/kafs/README.dlfcn                                                          |   246 -
 head/crypto/heimdal/lib/kafs/afskrb.c                                                              |   217 -
 head/crypto/heimdal/lib/kafs/dlfcn.c                                                               |   581 -
 head/crypto/heimdal/lib/kafs/dlfcn.h                                                               |    46 -
 head/crypto/heimdal/lib/krb5/config_file_netinfo.c                                                 |   180 -
 head/crypto/heimdal/lib/krb5/get_in_tkt_pw.c                                                       |    90 -
 head/crypto/heimdal/lib/krb5/get_in_tkt_with_keytab.c                                              |    99 -
 head/crypto/heimdal/lib/krb5/get_in_tkt_with_skey.c                                                |    82 -
 head/crypto/heimdal/lib/krb5/heim_threads.h                                                        |   175 -
 head/crypto/heimdal/lib/krb5/keytab_krb4.c                                                         |   448 -
 head/crypto/heimdal/lib/krb5/krb5.3                                                                |   526 -
 head/crypto/heimdal/lib/krb5/krb5_address.3                                                        |   359 -
 head/crypto/heimdal/lib/krb5/krb5_ccache.3                                                         |   517 -
 head/crypto/heimdal/lib/krb5/krb5_compare_creds.3                                                  |   104 -
 head/crypto/heimdal/lib/krb5/krb5_config.3                                                         |   307 -
 head/crypto/heimdal/lib/krb5/krb5_context.3                                                        |    56 -
 head/crypto/heimdal/lib/krb5/krb5_crypto_init.3                                                    |    67 -
 head/crypto/heimdal/lib/krb5/krb5_data.3                                                           |   159 -
 head/crypto/heimdal/lib/krb5/krb5_expand_hostname.3                                                |    93 -
 head/crypto/heimdal/lib/krb5/krb5_keyblock.3                                                       |   218 -
 head/crypto/heimdal/lib/krb5/krb5_keytab.3                                                         |   482 -
 head/crypto/heimdal/lib/krb5/krb5_kuserok.3                                                        |   103 -
 head/crypto/heimdal/lib/krb5/krb5_storage.3                                                        |   427 -
 head/crypto/heimdal/lib/krb5/krb5_ticket.3                                                         |   137 -
 head/crypto/heimdal/lib/krb5/krb5_unparse_name.3                                                   |    62 -
 head/crypto/heimdal/lib/krb5/krb5_warn.3                                                           |   233 -
 head/crypto/heimdal/lib/krb5/name-45-test.c                                                        |   294 -
 head/crypto/heimdal/lib/krb5/v4_glue.c                                                             |   939 -
 head/crypto/heimdal/lib/roken/snprintf-test.h                                                      |    52 -
 head/crypto/heimdal/lib/roken/vis.h                                                                |   115 -
 head/crypto/heimdal/lib/sl/lex.c                                                                   |  1880 --
 head/crypto/heimdal/lib/sl/lex.l                                                                   |   119 -
 head/crypto/heimdal/lib/sl/make_cmds.c                                                             |   239 -
 head/crypto/heimdal/lib/sl/make_cmds.h                                                             |    76 -
 head/crypto/heimdal/lib/sl/parse.c                                                                 |  1724 --
 head/crypto/heimdal/lib/sl/parse.h                                                                 |    78 -
 head/crypto/heimdal/lib/sl/parse.y                                                                 |   169 -
 head/crypto/heimdal/lib/sl/ss.c                                                                    |   162 -
 head/crypto/heimdal/lib/sl/ss.h                                                                    |    57 -
 head/crypto/heimdal/lib/vers/make-print-version.c                                                  |    76 -
 head/crypto/heimdal/packages/ChangeLog                                                             |    26 -
 head/crypto/heimdal/packages/Makefile.am                                                           |     6 -
 head/crypto/heimdal/packages/Makefile.in                                                           |   815 -
 head/crypto/heimdal/packages/debian/Makefile.am                                                    |    91 -
 head/crypto/heimdal/packages/debian/Makefile.in                                                    |   745 -
 head/crypto/heimdal/packages/debian/README                                                         |    15 -
 head/crypto/heimdal/packages/debian/README.Debian                                                  |   120 -
 head/crypto/heimdal/packages/debian/changelog                                                      |  1168 -
 head/crypto/heimdal/packages/debian/compat                                                         |     1 -
 head/crypto/heimdal/packages/debian/control                                                        |   276 -
 head/crypto/heimdal/packages/debian/copyright                                                      |   195 -
 head/crypto/heimdal/packages/debian/extras/default                                                 |    17 -
 head/crypto/heimdal/packages/debian/extras/kadmind.acl                                             |     1 -
 head/crypto/heimdal/packages/debian/extras/kdc.conf                                                |    91 -
 head/crypto/heimdal/packages/debian/heimdal-clients-x.install                                      |    10 -
 head/crypto/heimdal/packages/debian/heimdal-clients.install                                        |    43 -
 head/crypto/heimdal/packages/debian/heimdal-clients.postinst                                       |    10 -
 head/crypto/heimdal/packages/debian/heimdal-clients.prerm                                          |    13 -
 head/crypto/heimdal/packages/debian/heimdal-dev.install                                            |     8 -
 head/crypto/heimdal/packages/debian/heimdal-docs.install                                           |     2 -
 head/crypto/heimdal/packages/debian/heimdal-kcm.init                                               |    69 -
 head/crypto/heimdal/packages/debian/heimdal-kcm.install                                            |     2 -
 head/crypto/heimdal/packages/debian/heimdal-kdc.dirs                                               |     5 -
 head/crypto/heimdal/packages/debian/heimdal-kdc.examples                                           |     2 -
 head/crypto/heimdal/packages/debian/heimdal-kdc.init                                               |   124 -
 head/crypto/heimdal/packages/debian/heimdal-kdc.install                                            |    20 -
 head/crypto/heimdal/packages/debian/heimdal-kdc.logrotate                                          |     5 -
 head/crypto/heimdal/packages/debian/heimdal-kdc.postinst                                           |    98 -
 head/crypto/heimdal/packages/debian/heimdal-kdc.postrm                                             |    32 -
 head/crypto/heimdal/packages/debian/heimdal-kdc.templates                                          |    12 -
 head/crypto/heimdal/packages/debian/heimdal-servers-x.dirs                                         |     1 -
 head/crypto/heimdal/packages/debian/heimdal-servers-x.install                                      |     2 -
 head/crypto/heimdal/packages/debian/heimdal-servers-x.postinst                                     |    34 -
 head/crypto/heimdal/packages/debian/heimdal-servers-x.postrm                                       |    23 -
 head/crypto/heimdal/packages/debian/heimdal-servers-x.prerm                                        |    11 -
 head/crypto/heimdal/packages/debian/heimdal-servers.dirs                                           |     1 -
 head/crypto/heimdal/packages/debian/heimdal-servers.install                                        |    12 -
 head/crypto/heimdal/packages/debian/heimdal-servers.postinst                                       |    47 -
 head/crypto/heimdal/packages/debian/heimdal-servers.postrm                                         |    26 -
 head/crypto/heimdal/packages/debian/heimdal-servers.prerm                                          |    14 -
 head/crypto/heimdal/packages/debian/libasn1-8-heimdal.install                                      |     2 -
 head/crypto/heimdal/packages/debian/libasn1-8-heimdal.postinst.debhelper                           |     5 -
 head/crypto/heimdal/packages/debian/libasn1-8-heimdal.postrm.debhelper                             |     5 -
 head/crypto/heimdal/packages/debian/libasn1-8-heimdal.substvars                                    |     1 -
 head/crypto/heimdal/packages/debian/libgssapi2-heimdal.install                                     |     2 -
 head/crypto/heimdal/packages/debian/libgssapi2-heimdal.postinst.debhelper                          |     5 -
 head/crypto/heimdal/packages/debian/libgssapi2-heimdal.postrm.debhelper                            |     5 -
 head/crypto/heimdal/packages/debian/libgssapi2-heimdal.substvars                                   |     1 -
 head/crypto/heimdal/packages/debian/libhdb9-heimdal.install                                        |     3 -
 head/crypto/heimdal/packages/debian/libhdb9-heimdal.postinst.debhelper                             |     5 -
 head/crypto/heimdal/packages/debian/libhdb9-heimdal.postrm.debhelper                               |     5 -
 head/crypto/heimdal/packages/debian/libhdb9-heimdal.substvars                                      |     1 -
 head/crypto/heimdal/packages/debian/libkadm5clnt7-heimdal.install                                  |     3 -
 head/crypto/heimdal/packages/debian/libkadm5clnt7-heimdal.postinst.debhelper                       |     5 -
 head/crypto/heimdal/packages/debian/libkadm5clnt7-heimdal.postrm.debhelper                         |     5 -
 head/crypto/heimdal/packages/debian/libkadm5clnt7-heimdal.substvars                                |     1 -
 head/crypto/heimdal/packages/debian/libkadm5srv7-heimdal.install                                   |     2 -
 head/crypto/heimdal/packages/debian/libkadm5srv8-heimdal.install                                   |     3 -
 head/crypto/heimdal/packages/debian/libkafs0-heimdal.install                                       |     2 -
 head/crypto/heimdal/packages/debian/libkrb5-22-heimdal.install                                     |     3 -
 head/crypto/heimdal/packages/debian/libkrb5-22-heimdal.postinst.debhelper                          |     5 -
 head/crypto/heimdal/packages/debian/libkrb5-22-heimdal.postrm.debhelper                            |     5 -
 head/crypto/heimdal/packages/debian/libkrb5-22-heimdal.substvars                                   |     1 -
 head/crypto/heimdal/packages/debian/libotp0-heimdal.install                                        |     1 -
 head/crypto/heimdal/packages/debian/libroken18-heimdal.install                                     |     2 -
 head/crypto/heimdal/packages/debian/libroken18-heimdal.postinst.debhelper                          |     5 -
 head/crypto/heimdal/packages/debian/libroken18-heimdal.postrm.debhelper                            |     5 -
 head/crypto/heimdal/packages/debian/libroken18-heimdal.substvars                                   |     1 -
 head/crypto/heimdal/packages/debian/libsl0-heimdal.install                                         |     2 -
 head/crypto/heimdal/packages/debian/patches/021_debian                                             |   204 -
 head/crypto/heimdal/packages/debian/patches/022_ftp-roken-glob                                     |   270 -
 head/crypto/heimdal/packages/debian/patches/022_openafs                                            |    15 -
 head/crypto/heimdal/packages/debian/patches/025_pthreads                                           |    13 -
 head/crypto/heimdal/packages/debian/patches/026_posix_max                                          |   293 -
 head/crypto/heimdal/packages/debian/po/POTFILES.in                                                 |     1 -
 head/crypto/heimdal/packages/debian/po/templates.pot                                               |    54 -
 head/crypto/heimdal/packages/debian/rules                                                          |    62 -
 head/crypto/heimdal/packages/debian/scripts/convert_source                                         |    17 -
 head/crypto/heimdal/packages/mac/Info.plist                                                        |    36 -
 head/crypto/heimdal/packages/mac/Makefile.am                                                       |     9 -
 head/crypto/heimdal/packages/mac/Makefile.in                                                       |   663 -
 head/crypto/heimdal/packages/mac/Resources/Description.plist                                       |    10 -
 head/crypto/heimdal/packages/mac/Resources/English.lproj/Welcome.rtf                               |     8 -
 head/crypto/heimdal/packages/mac/mac.sh                                                            |    52 -
 head/crypto/heimdal/tests/ChangeLog                                                                |   742 -
 head/crypto/heimdal/tests/Makefile.am                                                              |    11 -
 head/crypto/heimdal/tests/Makefile.in                                                              |   816 -
 head/crypto/heimdal/tests/can/Makefile.am                                                          |    56 -
 head/crypto/heimdal/tests/can/Makefile.in                                                          |   781 -
 head/crypto/heimdal/tests/can/apple-10.4.kadm                                                      |     4 -
 head/crypto/heimdal/tests/can/apple-10.4.req                                                       |   Bin 
 head/crypto/heimdal/tests/can/check-can.in                                                         |    47 -
 head/crypto/heimdal/tests/can/heim-0.8.kadm                                                        |     4 -
 head/crypto/heimdal/tests/can/heim-0.8.req                                                         |   Bin 
 head/crypto/heimdal/tests/can/krb5.conf.in                                                         |    24 -
 head/crypto/heimdal/tests/can/mit-pkinit-20070607.ca.crt                                           |    23 -
 head/crypto/heimdal/tests/can/mit-pkinit-20070607.kadm                                             |     3 -
 head/crypto/heimdal/tests/can/mit-pkinit-20070607.req                                              |   Bin 
 head/crypto/heimdal/tests/can/mit-pkinit-20070607.xf                                               |    28 -
 head/crypto/heimdal/tests/can/test_can.in                                                          |    79 -
 head/crypto/heimdal/tests/db/Makefile.am                                                           |    66 -
 head/crypto/heimdal/tests/db/Makefile.in                                                           |   793 -
 head/crypto/heimdal/tests/db/add-modify-delete.in                                                  |   137 -
 head/crypto/heimdal/tests/db/check-dbinfo.in                                                       |    45 -
 head/crypto/heimdal/tests/db/have-db.in                                                            |    60 -
 head/crypto/heimdal/tests/db/krb5.conf.in                                                          |    28 -
 head/crypto/heimdal/tests/db/loaddump-db.in                                                        |   132 -
 head/crypto/heimdal/tests/db/text-dump-0.7                                                         |     7 -
 head/crypto/heimdal/tests/db/text-dump-known-ext                                                   |     7 -
 head/crypto/heimdal/tests/db/text-dump-no-ext                                                      |     7 -
 head/crypto/heimdal/tests/db/text-dump-unknown-ext                                                 |     7 -
 head/crypto/heimdal/tests/gss/Makefile.am                                                          |    78 -
 head/crypto/heimdal/tests/gss/Makefile.in                                                          |   804 -
 head/crypto/heimdal/tests/gss/check-basic.in                                                       |   156 -
 head/crypto/heimdal/tests/gss/check-context.in                                                     |   188 -
 head/crypto/heimdal/tests/gss/check-gss.in                                                         |    45 -
 head/crypto/heimdal/tests/gss/check-gssmask.in                                                     |   133 -
 head/crypto/heimdal/tests/gss/check-ntlm.in                                                        |   170 -
 head/crypto/heimdal/tests/gss/check-spnego.in                                                      |   209 -
 head/crypto/heimdal/tests/gss/krb5.conf.in                                                         |    33 -
 head/crypto/heimdal/tests/gss/ntlm-user-file.txt                                                   |     2 -
 head/crypto/heimdal/tests/java/KerberosInit.java                                                   |    95 -
 head/crypto/heimdal/tests/java/Makefile.am                                                         |    44 -
 head/crypto/heimdal/tests/java/Makefile.in                                                         |   768 -
 head/crypto/heimdal/tests/java/check-kinit.in                                                      |   101 -
 head/crypto/heimdal/tests/java/have-java.sh                                                        |    58 -
 head/crypto/heimdal/tests/java/jaas.conf                                                           |     5 -
 head/crypto/heimdal/tests/java/krb5.conf.in                                                        |    30 -
 head/crypto/heimdal/tests/kdc/Makefile.am                                                          |   159 -
 head/crypto/heimdal/tests/kdc/Makefile.in                                                          |   971 -
 head/crypto/heimdal/tests/kdc/ap-req.c                                                             |   221 -
 head/crypto/heimdal/tests/kdc/check-digest.in                                                      |   295 -
 head/crypto/heimdal/tests/kdc/check-iprop.in                                                       |   248 -
 head/crypto/heimdal/tests/kdc/check-kadmin.in                                                      |   151 -
 head/crypto/heimdal/tests/kdc/check-kdc.in                                                         |   413 -
 head/crypto/heimdal/tests/kdc/check-keys.in                                                        |   101 -
 head/crypto/heimdal/tests/kdc/check-pkinit.in                                                      |   273 -
 head/crypto/heimdal/tests/kdc/check-referral.in                                                    |   200 -
 head/crypto/heimdal/tests/kdc/check-uu.in                                                          |   138 -
 head/crypto/heimdal/tests/kdc/donotexists.txt                                                      |     1 -
 head/crypto/heimdal/tests/kdc/heimdal.acl                                                          |     3 -
 head/crypto/heimdal/tests/kdc/iprop-acl                                                            |     1 -
 head/crypto/heimdal/tests/kdc/krb5-pkinit.conf.in                                                  |    33 -
 head/crypto/heimdal/tests/kdc/krb5.conf.in                                                         |    56 -
 head/crypto/heimdal/tests/kdc/krb5.conf.keys.in                                                    |    13 -
 head/crypto/heimdal/tests/kdc/ntlm-user-file.txt                                                   |     2 -
 head/crypto/heimdal/tests/kdc/pki-mapping                                                          |     3 -
 head/crypto/heimdal/tests/kdc/uuserver.txt                                                         |     4 -
 head/crypto/heimdal/tests/kdc/wait-kdc.sh                                                          |    66 -
 head/crypto/heimdal/tests/ldap/Makefile.am                                                         |    52 -
 head/crypto/heimdal/tests/ldap/Makefile.in                                                         |   779 -
 head/crypto/heimdal/tests/ldap/check-ldap.in                                                       |   143 -
 head/crypto/heimdal/tests/ldap/init.ldif                                                           |    44 -
 head/crypto/heimdal/tests/ldap/krb5.conf.in                                                        |    21 -
 head/crypto/heimdal/tests/ldap/samba.schema                                                        |   554 -
 head/crypto/heimdal/tests/ldap/slapd-init.in                                                       |    39 -
 head/crypto/heimdal/tests/ldap/slapd-stop                                                          |    18 -
 head/crypto/heimdal/tests/ldap/slapd.conf                                                          |    28 -
 head/crypto/heimdal/tests/plugin/Makefile.am                                                       |    43 -
 head/crypto/heimdal/tests/plugin/Makefile.in                                                       |   890 -
 head/crypto/heimdal/tests/plugin/check-pac.in                                                      |   147 -
 head/crypto/heimdal/tests/plugin/krb5.conf.in                                                      |    29 -
 head/crypto/heimdal/tests/plugin/windc.c                                                           |    77 -
 head/crypto/heimdal/tools/heimdal-build.sh                                                         |   295 -
 head/kerberos5/lib/libgssapi_spnego/prefix.c                                                       |    45 -
 head/kerberos5/tools/make-print-version/Makefile                                                   |     8 -
 head/kerberos5/usr.bin/klist/Makefile                                                              |    12 -
 head/lib/libc/arm/gen/__aeabi_read_tp.c                                                            |    42 -
 head/lib/libc/stdlib/aligned_alloc.3                                                               |   126 -
 head/lib/libc/stdlib/malloc.3                                                                      |   591 -
 head/lib/libc/stdlib/malloc.c                                                                      |  6270 ----------
 head/lib/libc/stdlib/ql.h                                                                          |   122 -
 head/lib/libc/stdlib/qr.h                                                                          |   106 -
 head/lib/libc/stdlib/rb.h                                                                          |  1002 -
 head/lib/libpmc/pmc.mips.3                                                                         |   413 -
 head/sys/amd64/amd64/legacy.c                                                                      |   332 -
 head/sys/amd64/include/legacyvar.h                                                                 |    57 -
 head/sys/dev/hwpmc/hwpmc_mips24k.h                                                                 |    64 -
 head/sys/dev/mpt/mpilib/mpi_inb.h                                                                  |   250 -
 head/sys/dev/uart/uart_cpu_amd64.c                                                                 |   107 -
 head/sys/dev/uart/uart_cpu_i386.c                                                                  |   107 -
 head/sys/i386/i386/legacy.c                                                                        |   353 -
 head/sys/i386/include/legacyvar.h                                                                  |    57 -
 head/sys/mips/nlm/intern_dev.c                                                                     |    86 -
 head/sys/mips/nlm/uart_pci_xlp.c                                                                   |    83 -
 head/sys/pc98/include/legacyvar.h                                                                  |     6 -
 633 files changed, 0 insertions(+), 107808 deletions(-)

diffs (110322 lines):

diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/bind9/RELEASE-NOTES-BIND-9.8.1.html
--- a/head/contrib/bind9/RELEASE-NOTES-BIND-9.8.1.html	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,368 +0,0 @@
-<html><head><meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1"><title></title><link rel="stylesheet" href="release-notes.css" type="text/css"><meta name="generator" content="DocBook XSL Stylesheets V1.71.1"></head><body bgcolor="white" text="black" link="#0000FF" vlink="#840084" alink="#0000FF"><div class="article" lang="en"><div class="titlepage"><hr></div>
-
-  <div class="section" lang="en"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a name="id3359008"></a>Introduction</h2></div></div></div>
-    
-    <p>
-			BIND 9.8.1 is the current production release of BIND 9.8.
-		</p>
-    <p>
-			This document summarizes changes from BIND 9.8.0 to BIND 9.8.1.
-			Please see the CHANGES file in the source code release for a
-			complete list of all changes.
-		</p>
-  </div>
-
-  <div class="section" lang="en"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a name="id3359050"></a>Download</h2></div></div></div>
-    
-    <p>
-			The latest versions of BIND 9 software can always be found
-	 		on our web site at
- <a href="http://www.isc.org/downloads/all" target="_top">http://www.isc.org/downloads/all</a>.
-                There you will find additional information about each
-		release, source code, and some pre-compiled versions for certain operating systems.
-		</p>
-  </div>
-
-  <div class="section" lang="en"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a name="id2545549"></a>Support</h2></div></div></div>
-    
-    <p>Product support information is available on
-      <a href="http://www.isc.org/services/support" target="_top">http://www.isc.org/services/support</a>
-      for paid support options.  Free support is provided by our user
- 			community via a mailing list.  Information on all public email
- 			lists is available at
-      <a href="https://lists.isc.org/mailman/listinfo" target="_top">https://lists.isc.org/mailman/listinfo</a>.
-    </p>
-  </div>
-
-  <div class="section" lang="en"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a name="id3358108"></a>New Features</h2></div></div></div>
-    
-		<div class="section" lang="en"><div class="titlepage"><div><div><h3 class="title"><a name="id3358149"></a>9.8.1</h3></div></div></div>
-			
-	    <div class="itemizedlist"><ul type="disc"><li>
-Added a new include file with function typedefs
-for the DLZ "dlopen" driver. [RT #23629]
-</li><li>
-Added a tool able to generate malformed packets to allow testing
-of how named handles them.
-[RT #24096]
-</li><li>
-The root key is now provided in the file bind.keys allowing DNSSEC validation to be switched on at start up by adding "dnssec-validation auto;" to named.conf. If the root key provided has expired, named will log the expiration and validation will not work.  More information and the most current copy of bind.keys can be found at http://www.isc.org/bind-keys. *Please note this feature was actually added in 9.8.0 but was not included in the 9.8.0 release notes. [RT #21727]
-</li></ul></div>
-		</div>
-  </div>
-
-  <div class="section" lang="en"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a name="id3358206"></a>Security Fixes</h2></div></div></div>
-    
-		<div class="section" lang="en"><div class="titlepage"><div><div><h3 class="title"><a name="id3358226"></a>9.8.1</h3></div></div></div>
-			
-	    <div class="itemizedlist"><ul type="disc"><li>
-If named is configured with a response policy zone (RPZ) and a query
-of type RRSIG is received for a name configured for RRset replacement
-in that RPZ, it will trigger an INSIST and crash the server.
-RRSIG. [RT #24280]
-</li><li>
-named, set up to be a caching resolver, is vulnerable to a
-user querying a domain with very large resource record sets (RRSets)
-when trying to negatively cache the response. Due to an off-by-one
-error, caching the response could cause named to crash. [RT #24650]
-[CVE-2011-1910]
-</li><li>
-Using Response Policy Zone (RPZ) to query a wildcard CNAME label with
-QUERY type SIG/RRSIG, it can cause named to crash. Fix is query type
-independant.
-[RT #24715]
-</li><li>
-Using Response Policy Zone (RPZ) with DNAME records and querying the
-subdomain of that label can cause named to crash. Now logs that DNAME
-is not supported.
-[RT #24766]
-</li><li>
-Change #2912 populated the message section in replies to UPDATE requests,
-which some Windows clients wanted. This exposed a latent bug that allowed
-the response message to crash named. With this fix, change 2912 has been
-reduced to copy only the zone section to the reply. A more complete fix
-for the latent bug will be released later.
-[RT #24777]
-</li></ul></div>
-		</div>
-  </div>
-
-
-  <div class="section" lang="en"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a name="id3358283"></a>Feature Changes</h2></div></div></div>
-    
-		<div class="section" lang="en"><div class="titlepage"><div><div><h3 class="title"><a name="id3358291"></a>9.8.1</h3></div></div></div>
-			
-	    <div class="itemizedlist"><ul type="disc"><li>
-Merged in the NetBSD ATF test framework (currently
-version 0.12) for development of future unit tests.
-Use configure --with-atf to build ATF internally
-or configure --with-atf=prefix to use an external
-copy. [RT #23209]
-</li><li>
-Added more verbose error reporting from DLZ LDAP. [RT #23402]
-</li><li>
-The DLZ "dlopen" driver is now built by default,
-no longer requiring a configure option. To
-disable it, use "configure --without-dlopen".
-(Note: driver not supported on win32.) [RT #23467]
-</li><li>
-Replaced compile time constant with STDTIME_ON_32BITS.
-[RT #23587]
-</li><li>
-Make --with-gssapi default for ./configure. [RT #23738]
-</li><li>
-Improved the startup time for an authoritative server with a large 
-number of zones by making the zone task table of variable size
-rather than fixed size.  This means that authoritative servers with
-lots of zones will be serving that zone data much sooner. [RT #24406]
-</li><li>
-Per RFC 6303, RFC 1918 reverse zones are now part of the built-in list of empty zones. [RT #24990]
-</li></ul></div>
-		</div>
-  </div>
-  <div class="section" lang="en"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a name="id3358460"></a>Bug Fixes</h2></div></div></div>
-    
-		<div class="section" lang="en"><div class="titlepage"><div><div><h3 class="title"><a name="id3358468"></a>9.8.1</h3></div></div></div>
-			
-	    <div class="itemizedlist"><ul type="disc"><li>
-During RFC5011 processing some journal write errors were not detected.
-This could lead to managed-keys changes being committed but not 
-recorded in the journal files, causing potential inconsistencies  
-during later processing.  [RT #20256]
-</li><li>
-A potential NULL pointer deference in the DNS64 code could cause 
-named to terminate unexpectedly. [RT #20256]
-</li><li>
-A state variable relating to DNSSEC could fail to be set during 
-some infrequently-executed code paths, allowing it to be used whilst
-in an unitialized state during cache updates, with unpredictable results.
-[RT #20256]
-</li><li>
-A potential NULL pointer deference in DNSSEC signing code could 
-cause named to terminate unexpectedly  [RT #20256]
-</li><li>
-Several cosmetic code changes were made to silence warnings
-generated by a static code analysis tool. [RT #20256]
-</li><li>
-When using the -x (sign with only KSK) option on dnssec-signzone,
-it could incorrectly count the number of ZSKs in the zone. (And in 9.9.0,
-some code cleanup and improved warning messages). [RT #20852]
-</li><li>
-When using _builtin in named.conf, named.conf changes were not found
-when reloading the config file. Now checks _builtin zone arguments
-to see if the zone is re-usable or not. [RT #21914]
-</li><li>
-Running dnssec-settime -f on an old-style key will
-now force the key to be rewritten to the new key format even if no
-other change has been specified, using "-P now -A now"
-as default values. [RT #22474]
-</li><li>
-After an external code review, a code cleanup was done. [RT #22521]
-</li><li>
-Cause named to terminate at startup or rndc reconfig
-reload to fail, if a log file specified in the
-conf file isn't a plain file. (RT #22771]
-</li><li>
-named now forces the ADB cache time for glue related data to zero  
-instead of relying on TTL.  This corrects problematic behavior in cases  
-where a server was authoritative for the A record of a nameserver for a  
-delegated zone and was queried to recursively resolve records within  
-that zone.  [RT #22842]
-</li><li>
-When a validating resolver got a NODATA response for DNSKEY, it was
-not caching the NODATA. Fixed and test added. [RT #22908]
-</li><li>
-Fixed a bug in which zone keys that were published
-and but not immediately activated, automatic signing could fail to trigger.
-[RT #22911]
-</li><li>
-Fixed precedence order bug with NS and DNAME records if both are present.
-(Also fixed timing of autosign test in 9.7+) [RT #23035]
-</li><li>
-When a DNSSEC signed dynamic zone's signatures need to be refreshed,
-named would first delete the old signatures in the zone. If a private
-key of the same algorithm isn't available to named, the signing would
-fail but the old signatures would already be deleted. named now checks
-if it can access the private key before deleting the old signatures and 
-leaves the old signature if no private key is found. [RT #23136]
-</li><li>
-When using "auto-dnssec maintain" and rolling to a new key, a
-private-type record (only used internally by named) could be created
-and not marked as complete. [RT #23253]
-</li><li>
-Fixed last autosign test report. [RT #23256]
-</li><li>
-named didn't save gid at startup and later assumed gid 0.
-named now saves/restores the gid when creating creating
-named.pid at startup. [RT #23290]
-</li><li>
-If the server has an IPv6 address but does not have IPv6 connectivity
-to the internet, dig +trace could fail attempting to use IPv6
-addresses. [RT #23297]
-</li><li>
-If named is configured with managed zones, the managed key maint timer
-can exercise a race condition that can crash the server.
-[RT #23303]
-</li><li>
-Changing TTL did not cause dnssec-signzone to generate new signatures.
-[RT #23330]
-</li><li>
-Have the validating resolver use RRSIG original TTL to compute
-validated RRset and RRSIG TTL. [RT #23332]
-</li><li>
-In "make test" bin/tests/resolver, hold the socket manager lock
-while freeing the socket.
-[RT #23333]
-</li><li>
-If named encountered a CNAME instead of a DS record when walking
-the chain of trust down from the trust anchor, it incorrectly stopped
-validating. [RT #23338]
-</li><li>
-dns/view.h needed dns/rpz.h but it wasn't in the Makfile.in
-HEADERS variable. [RT #23342]
-</li><li>
-RRSIG records could have time stamps too far in the future.
-[RT #23356]
-</li><li>
-named stores cached data in an in-memory database and keeps track of
-how recently the data is used with a heap. The heap is stored within the
-cache's memory space. Under a sustained high query load and with a small
-cache size, this could lead to the heap exhausting the cache space. This
-would result in cache misses and SERVFAILs, with named never releasing
-the cache memory the heap used up and never recovering.
-
-This fix removes the heap into its own memory space, preventing the heap
-from exhausting the cache space and allowing named to recover gracefully
-when the high query load abates. [RT #23371]
-</li><li>
-Fully separated key management on a per view basis. [RT #23419]
-</li><li>
-If running on a powerpc CPU and with atomic operations enabled,
-named could lock up. Added sync instructions to the end of atomic
-operations. [RT #23469]
-</li><li>
-If OpenSSL was built without engine support, named would have
-compile errors and fail to build.
-[RT #23473]
-</li><li>
-If ./configure finds GOST but not elliptic curve, named fails to
-build. Added elliptic curve support check in GOST OpenSSL engine
-detection. [RT #23485]
-</li><li>
-"rndc secroots" would abort on the first error
-and so could miss remaining views. [RT #23488]
-</li><li>
-Handle isc_event_allocate failures in t_tasks test.
-[RT #23572]
-</li><li>
-ixfr-from-differences {master|slave};
-failed to select the master/slave zones, resulting in on diff/journal
-file being created.
-[RT #23580]
-</li><li>
-If a DNAME substitution failed, named returned NOERROR. The correct
-response should be YXDOMAIN.
-[RT #23591]
-</li><li>
-dns_dnssec_findzonekeys{2} used a inconsistant
-timestamp when determining which keys are active. This could result in
-some RRsets not being signed/re-signed.
-[RT #23642]
-</li><li>
-Remove bin/tests/system/logfileconfig/ns1/named.conf and
-add setup.sh in order to resolve changing named.conf issue. [RT #23687]
-</li><li>
-NOTIFY messages were not being sent when generating
-a NSEC3 chain incrementally. [RT #23702]
-</li><li>
-DDNS updates using SIG(0) with update-policy match
-type "external" could cause a crash. Also fixed nsupdate core
-dump on shutdown when using a SIG(0) key, due to the key
-not being freed. [RT #23735]
-</li><li>
-Zones using automatic key maintenance could fail to check the key
-repository for updates. named now checks once per hour and the
-automatic check bug has been fixed. [RT #23744]
-</li><li>
-named now uses the correct strtok/strtok_r/strtok_s based on OS.
-[RT #23747]
-</li><li>
-Signatures for records at the zone apex could go
-stale due to an incorrect timer setting. [RT #23769]
-</li><li>
-The autosign tests attempted to open ports within reserved ranges. Test
-now avoids those ports.
-[RT #23957]
-</li><li>
-GSS TGIS test was failing, since log_cred() caused KRB5_KTNAME to
-be cached. Now sets KRB5_KTNAME before calling log_cred() in
-dst_gssapi_acceptctx(). [RT #24004]
-</li><li>
-named, acting as authoritative server for DLZ zones, was not correctly
-setting the authoritative (AA) bit.
-[RT #24146]
-</li><li>
-Clean up some cross-compiling issues and added two undocumented
-configure options, --with-gost and --with-rlimtype, to allow over-riding
-default settings (gost=no and rlimtype="long int") when cross-compiling.
-[RT #24367]
-</li><li>
-When trying sign with NSEC3, if dnssec-signzone couldn't find the
-KSK, it would give an incorrect error "NSEC3 iterations too big for
-weakest DNSKEY strength" rather than the correct "failed to find
-keys at the zone apex: not found" [RT #24369]
-</li><li>
-Configuring 'dnssec-validation auto' in a view instead of in the
-options statement could trigger an assertion failure in named-checkconf.
-[RT #24382]
-</li><li>
-Improved consistency checks for dnssec-enable and
-dnssec-validation, added test cases to the
-checkconf system test. [RT #24398]
-</li><li>
-If named is configured to be both authoritative and recursive and receives
-a recursive query for a CNAME in a zone that it is authoritative for, if that
-CNAME also points to a zone the server is authoritative for, the recursive part of name will not follow the CNAME change and the response will not be a
-complete CNAME chain. [RT #24455]
-</li><li>
-nsupdate could dump core on shutdown when using SIG(0) keys. [RT #24604]
-</li><li>
-Named could fail to validate zones list in a DLV that validated insecure
-without using DLV and had DS records in the parent zone. [RT #24631]
-</li><li>
-dnssec-signzone now records timestamps just before and just after signing, improving the accuracy of signing statistics. [RT #16030]
-</li><li>
-If allow-new-zones was set to yes and name-based ACLs were used, named could crash when "rndc reconfig" was issued. [RT #22739]
-</li><li>
-RT #23136 fixed a problem where named would delete old signatures even
-when the private key wasn't available to re-sign the zone, resulting in
-a zone with missing signatures. This fix (CHANGES 3114) did not
-completely fix all issues. [RT #24577]
-</li><li>
-A bug in FreeBSD kernels causes IPv6 UDP responses greater than
-1280 bytes to not fragment as they should. Until there is a kernel
-fix, named will work around this by setting IPV6_USE_MIN_MTU on a
-per packet basis. [RT #24950]
-</li></ul></div>
-		</div>
-  </div>
-
-  <div class="section" lang="en"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a name="id3359134"></a>Known issues in this release</h2></div></div></div>
-    
-    <div class="itemizedlist"><ul type="disc"><li>
-        <p>
-          None.
-        </p>
-      </li></ul></div>
-  </div>
-
-  <div class="section" lang="en"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a name="id3359152"></a>Thank You</h2></div></div></div>
-    
-    <p>
-      Thank you to everyone who assisted us in making this release possible.
-      If you would like to contribute to ISC to assist us in continuing to make
-      quality open source software, please visit our donations page at
-      <a href="http://www.isc.org/supportisc" target="_top">http://www.isc.org/supportisc</a>.
-    </p>
-  </div>
-</div></body></html>
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/bind9/RELEASE-NOTES-BIND-9.8.1.pdf
Binary file head/contrib/bind9/RELEASE-NOTES-BIND-9.8.1.pdf has changed
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/bind9/RELEASE-NOTES-BIND-9.8.1.txt
--- a/head/contrib/bind9/RELEASE-NOTES-BIND-9.8.1.txt	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,268 +0,0 @@
-     __________________________________________________________________
-
-Introduction
-
-   BIND 9.8.1 is the current production release of BIND 9.8.
-
-   This document summarizes changes from BIND 9.8.0 to BIND 9.8.1. Please
-   see the CHANGES file in the source code release for a complete list of
-   all changes.
-
-Download
-
-   The latest versions of BIND 9 software can always be found on our web
-   site at http://www.isc.org/downloads/all. There you will find
-   additional information about each release, source code, and some
-   pre-compiled versions for certain operating systems.
-
-Support
-
-   Product support information is available on
-   http://www.isc.org/services/support for paid support options. Free
-   support is provided by our user community via a mailing list.
-   Information on all public email lists is available at
-   https://lists.isc.org/mailman/listinfo.
-
-New Features
-
-9.8.1
-
-     * Added a new include file with function typedefs for the DLZ
-       "dlopen" driver. [RT #23629]
-     * Added a tool able to generate malformed packets to allow testing of
-       how named handles them. [RT #24096]
-     * The root key is now provided in the file bind.keys allowing DNSSEC
-       validation to be switched on at start up by adding
-       "dnssec-validation auto;" to named.conf. If the root key provided
-       has expired, named will log the expiration and validation will not
-       work. More information and the most current copy of bind.keys can
-       be found at http://www.isc.org/bind-keys. *Please note this feature
-       was actually added in 9.8.0 but was not included in the 9.8.0
-       release notes. [RT #21727]
-
-Security Fixes
-
-9.8.1
-
-     * If named is configured with a response policy zone (RPZ) and a
-       query of type RRSIG is received for a name configured for RRset
-       replacement in that RPZ, it will trigger an INSIST and crash the
-       server. RRSIG. [RT #24280]
-     * named, set up to be a caching resolver, is vulnerable to a user
-       querying a domain with very large resource record sets (RRSets)
-       when trying to negatively cache the response. Due to an off-by-one
-       error, caching the response could cause named to crash. [RT #24650]
-       [CVE-2011-1910]
-     * Using Response Policy Zone (RPZ) to query a wildcard CNAME label
-       with QUERY type SIG/RRSIG, it can cause named to crash. Fix is
-       query type independant. [RT #24715]
-     * Using Response Policy Zone (RPZ) with DNAME records and querying
-       the subdomain of that label can cause named to crash. Now logs that
-       DNAME is not supported. [RT #24766]
-     * Change #2912 populated the message section in replies to UPDATE
-       requests, which some Windows clients wanted. This exposed a latent
-       bug that allowed the response message to crash named. With this
-       fix, change 2912 has been reduced to copy only the zone section to
-       the reply. A more complete fix for the latent bug will be released
-       later. [RT #24777]
-
-Feature Changes
-
-9.8.1
-
-     * Merged in the NetBSD ATF test framework (currently version 0.12)
-       for development of future unit tests. Use configure --with-atf to
-       build ATF internally or configure --with-atf=prefix to use an
-       external copy. [RT #23209]
-     * Added more verbose error reporting from DLZ LDAP. [RT #23402]
-     * The DLZ "dlopen" driver is now built by default, no longer
-       requiring a configure option. To disable it, use "configure
-       --without-dlopen". (Note: driver not supported on win32.) [RT
-       #23467]
-     * Replaced compile time constant with STDTIME_ON_32BITS. [RT #23587]
-     * Make --with-gssapi default for ./configure. [RT #23738]
-     * Improved the startup time for an authoritative server with a large
-       number of zones by making the zone task table of variable size
-       rather than fixed size. This means that authoritative servers with
-       lots of zones will be serving that zone data much sooner. [RT
-       #24406]
-     * Per RFC 6303, RFC 1918 reverse zones are now part of the built-in
-       list of empty zones. [RT #24990]
-
-Bug Fixes
-
-9.8.1
-
-     * During RFC5011 processing some journal write errors were not
-       detected. This could lead to managed-keys changes being committed
-       but not recorded in the journal files, causing potential
-       inconsistencies during later processing. [RT #20256]
-     * A potential NULL pointer deference in the DNS64 code could cause
-       named to terminate unexpectedly. [RT #20256]
-     * A state variable relating to DNSSEC could fail to be set during
-       some infrequently-executed code paths, allowing it to be used
-       whilst in an unitialized state during cache updates, with
-       unpredictable results. [RT #20256]
-     * A potential NULL pointer deference in DNSSEC signing code could
-       cause named to terminate unexpectedly [RT #20256]
-     * Several cosmetic code changes were made to silence warnings
-       generated by a static code analysis tool. [RT #20256]
-     * When using the -x (sign with only KSK) option on dnssec-signzone,
-       it could incorrectly count the number of ZSKs in the zone. (And in
-       9.9.0, some code cleanup and improved warning messages). [RT
-       #20852]
-     * When using _builtin in named.conf, named.conf changes were not
-       found when reloading the config file. Now checks _builtin zone
-       arguments to see if the zone is re-usable or not. [RT #21914]
-     * Running dnssec-settime -f on an old-style key will now force the
-       key to be rewritten to the new key format even if no other change
-       has been specified, using "-P now -A now" as default values. [RT
-       #22474]
-     * After an external code review, a code cleanup was done. [RT #22521]
-     * Cause named to terminate at startup or rndc reconfig reload to
-       fail, if a log file specified in the conf file isn't a plain file.
-       (RT #22771]
-     * named now forces the ADB cache time for glue related data to zero
-       instead of relying on TTL. This corrects problematic behavior in
-       cases where a server was authoritative for the A record of a
-       nameserver for a delegated zone and was queried to recursively
-       resolve records within that zone. [RT #22842]
-     * When a validating resolver got a NODATA response for DNSKEY, it was
-       not caching the NODATA. Fixed and test added. [RT #22908]
-     * Fixed a bug in which zone keys that were published and but not
-       immediately activated, automatic signing could fail to trigger. [RT
-       #22911]
-     * Fixed precedence order bug with NS and DNAME records if both are
-       present. (Also fixed timing of autosign test in 9.7+) [RT #23035]
-     * When a DNSSEC signed dynamic zone's signatures need to be
-       refreshed, named would first delete the old signatures in the zone.
-       If a private key of the same algorithm isn't available to named,
-       the signing would fail but the old signatures would already be
-       deleted. named now checks if it can access the private key before
-       deleting the old signatures and leaves the old signature if no
-       private key is found. [RT #23136]
-     * When using "auto-dnssec maintain" and rolling to a new key, a
-       private-type record (only used internally by named) could be
-       created and not marked as complete. [RT #23253]
-     * Fixed last autosign test report. [RT #23256]
-     * named didn't save gid at startup and later assumed gid 0. named now
-       saves/restores the gid when creating creating named.pid at startup.
-       [RT #23290]
-     * If the server has an IPv6 address but does not have IPv6
-       connectivity to the internet, dig +trace could fail attempting to
-       use IPv6 addresses. [RT #23297]
-     * If named is configured with managed zones, the managed key maint
-       timer can exercise a race condition that can crash the server. [RT
-       #23303]
-     * Changing TTL did not cause dnssec-signzone to generate new
-       signatures. [RT #23330]
-     * Have the validating resolver use RRSIG original TTL to compute
-       validated RRset and RRSIG TTL. [RT #23332]
-     * In "make test" bin/tests/resolver, hold the socket manager lock
-       while freeing the socket. [RT #23333]
-     * If named encountered a CNAME instead of a DS record when walking
-       the chain of trust down from the trust anchor, it incorrectly
-       stopped validating. [RT #23338]
-     * dns/view.h needed dns/rpz.h but it wasn't in the Makfile.in HEADERS
-       variable. [RT #23342]
-     * RRSIG records could have time stamps too far in the future. [RT
-       #23356]
-     * named stores cached data in an in-memory database and keeps track
-       of how recently the data is used with a heap. The heap is stored
-       within the cache's memory space. Under a sustained high query load
-       and with a small cache size, this could lead to the heap exhausting
-       the cache space. This would result in cache misses and SERVFAILs,
-       with named never releasing the cache memory the heap used up and
-       never recovering. This fix removes the heap into its own memory
-       space, preventing the heap from exhausting the cache space and
-       allowing named to recover gracefully when the high query load
-       abates. [RT #23371]
-     * Fully separated key management on a per view basis. [RT #23419]
-     * If running on a powerpc CPU and with atomic operations enabled,
-       named could lock up. Added sync instructions to the end of atomic
-       operations. [RT #23469]
-     * If OpenSSL was built without engine support, named would have
-       compile errors and fail to build. [RT #23473]
-     * If ./configure finds GOST but not elliptic curve, named fails to
-       build. Added elliptic curve support check in GOST OpenSSL engine
-       detection. [RT #23485]
-     * "rndc secroots" would abort on the first error and so could miss
-       remaining views. [RT #23488]
-     * Handle isc_event_allocate failures in t_tasks test. [RT #23572]
-     * ixfr-from-differences {master|slave}; failed to select the
-       master/slave zones, resulting in on diff/journal file being
-       created. [RT #23580]
-     * If a DNAME substitution failed, named returned NOERROR. The correct
-       response should be YXDOMAIN. [RT #23591]
-     * dns_dnssec_findzonekeys{2} used a inconsistant timestamp when
-       determining which keys are active. This could result in some RRsets
-       not being signed/re-signed. [RT #23642]
-     * Remove bin/tests/system/logfileconfig/ns1/named.conf and add
-       setup.sh in order to resolve changing named.conf issue. [RT #23687]
-     * NOTIFY messages were not being sent when generating a NSEC3 chain
-       incrementally. [RT #23702]
-     * DDNS updates using SIG(0) with update-policy match type "external"
-       could cause a crash. Also fixed nsupdate core dump on shutdown when
-       using a SIG(0) key, due to the key not being freed. [RT #23735]
-     * Zones using automatic key maintenance could fail to check the key
-       repository for updates. named now checks once per hour and the
-       automatic check bug has been fixed. [RT #23744]
-     * named now uses the correct strtok/strtok_r/strtok_s based on OS.
-       [RT #23747]
-     * Signatures for records at the zone apex could go stale due to an
-       incorrect timer setting. [RT #23769]
-     * The autosign tests attempted to open ports within reserved ranges.
-       Test now avoids those ports. [RT #23957]
-     * GSS TGIS test was failing, since log_cred() caused KRB5_KTNAME to
-       be cached. Now sets KRB5_KTNAME before calling log_cred() in
-       dst_gssapi_acceptctx(). [RT #24004]
-     * named, acting as authoritative server for DLZ zones, was not
-       correctly setting the authoritative (AA) bit. [RT #24146]
-     * Clean up some cross-compiling issues and added two undocumented
-       configure options, --with-gost and --with-rlimtype, to allow
-       over-riding default settings (gost=no and rlimtype="long int") when
-       cross-compiling. [RT #24367]
-     * When trying sign with NSEC3, if dnssec-signzone couldn't find the
-       KSK, it would give an incorrect error "NSEC3 iterations too big for
-       weakest DNSKEY strength" rather than the correct "failed to find
-       keys at the zone apex: not found" [RT #24369]
-     * Configuring 'dnssec-validation auto' in a view instead of in the
-       options statement could trigger an assertion failure in
-       named-checkconf. [RT #24382]
-     * Improved consistency checks for dnssec-enable and
-       dnssec-validation, added test cases to the checkconf system test.
-       [RT #24398]
-     * If named is configured to be both authoritative and recursive and
-       receives a recursive query for a CNAME in a zone that it is
-       authoritative for, if that CNAME also points to a zone the server
-       is authoritative for, the recursive part of name will not follow
-       the CNAME change and the response will not be a complete CNAME
-       chain. [RT #24455]
-     * nsupdate could dump core on shutdown when using SIG(0) keys. [RT
-       #24604]
-     * Named could fail to validate zones list in a DLV that validated
-       insecure without using DLV and had DS records in the parent zone.
-       [RT #24631]
-     * dnssec-signzone now records timestamps just before and just after
-       signing, improving the accuracy of signing statistics. [RT #16030]
-     * If allow-new-zones was set to yes and name-based ACLs were used,
-       named could crash when "rndc reconfig" was issued. [RT #22739]
-     * RT #23136 fixed a problem where named would delete old signatures
-       even when the private key wasn't available to re-sign the zone,
-       resulting in a zone with missing signatures. This fix (CHANGES
-       3114) did not completely fix all issues. [RT #24577]
-     * A bug in FreeBSD kernels causes IPv6 UDP responses greater than
-       1280 bytes to not fragment as they should. Until there is a kernel
-       fix, named will work around this by setting IPV6_USE_MIN_MTU on a
-       per packet basis. [RT #24950]
-
-Known issues in this release
-
-     * None.
-
-Thank You
-
-   Thank you to everyone who assisted us in making this release possible.
-   If you would like to contribute to ISC to assist us in continuing to
-   make quality open source software, please visit our donations page at
-   http://www.isc.org/supportisc.
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/bind9/release-notes.css
--- a/head/contrib/bind9/release-notes.css	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,60 +0,0 @@
-/*
- * Copyright (C) 2010, 2011  Internet Systems Consortium, Inc. ("ISC")
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND ISC DISCLAIMS ALL WARRANTIES WITH
- * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS.  IN NO EVENT SHALL ISC BE LIABLE FOR ANY SPECIAL, DIRECT,
- * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
- * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
- * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
- */
-
-/* $Id: release-notes.css,v 1.1.38.2 2011-08-24 01:53:51 marka Exp $ */
-
-body {
-	background-color: #ffffff;
-	color: #333333;
-	font-family: "Helvetica Neue", "ArialMT", "Verdana", "Arial", "Helvetica", sans-serif;
-	font-size: 14px;
-	line-height: 18px;
-	margin: 2em auto;
-	width: 700px;
-}
-
-.command {
-	font-family: "Courier New", "Courier", monospace;
-	font-weight: normal;
-}
-
-.note {
-	background-color: #ddeedd;
-	border: 1px solid #aaccaa;
-	margin: 1em 0 1em 0;
-	padding: 0.5em 1em 0.5em 1em;
-	-moz-border-radius: 10px;
-	-webkit-border-radius: 10px;
-}
-
-.screen {
-	background-color: #ffffee;
-	border: 1px solid #ddddaa;
-	padding: 0.25em 1em 0.25em 1em;
-	margin: 1em 0 1em 0;
-	-moz-border-radius: 10px;
-	-webkit-border-radius: 10px;
-}
-
-.section.title {
-	font-size: 150%;
-	font-weight: bold;
-}
-
-.section.section.title {
-  font-size: 130%;
-  font-weight: bold;
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/com_err/Makefile.am
--- a/head/contrib/com_err/Makefile.am	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,39 +0,0 @@
-# $Id: Makefile.am 21619 2007-07-17 07:34:00Z lha $
-
-include $(top_srcdir)/Makefile.am.common
-
-YFLAGS = -d
-
-lib_LTLIBRARIES = libcom_err.la
-libcom_err_la_LDFLAGS = -version-info 2:3:1
-
-if versionscript
-libcom_err_la_LDFLAGS += $(LDFLAGS_VERSION_SCRIPT)$(srcdir)/version-script.map
-endif
-
-bin_PROGRAMS = compile_et
-
-include_HEADERS = com_err.h com_right.h
-
-compile_et_SOURCES = compile_et.c compile_et.h parse.y lex.l lex.h
-
-libcom_err_la_CPPFLAGS = $(ROKEN_RENAME)
-dist_libcom_err_la_SOURCES = error.c com_err.c roken_rename.h
-
-if do_roken_rename
-nodist_libcom_err_la_SOURCES = snprintf.c strlcpy.c
-endif
-
-$(compile_et_OBJECTS): parse.h parse.c ## XXX broken automake 1.4s
-
-compile_et_LDADD = \
-	libcom_err.la \
-	$(LIB_roken) \
-	$(LEXLIB)
-
-snprintf.c:
-	$(LN_S) $(srcdir)/../roken/snprintf.c .
-strlcpy.c:
-	$(LN_S) $(srcdir)/../roken/strlcpy.c .
-
-EXTRA_DIST = version-script.map
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/com_err/Makefile.in
--- a/head/contrib/com_err/Makefile.in	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,910 +0,0 @@
-# Makefile.in generated by automake 1.10 from Makefile.am.
-# @[email protected]
-
-# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
-# 2003, 2004, 2005, 2006  Free Software Foundation, Inc.
-# This Makefile.in is free software; the Free Software Foundation
-# gives unlimited permission to copy and/or distribute it,
-# with or without modifications, as long as this notice is preserved.
-
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
-# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-# PARTICULAR PURPOSE.
-
- at SET_MAKE@
-
-# $Id: Makefile.am 21619 2007-07-17 07:34:00Z lha $
-
-# $Id: Makefile.am.common 10998 2002-05-19 18:35:37Z joda $
-
-# $Id: Makefile.am.common 22488 2008-01-21 11:47:22Z lha $
-
-
-
-VPATH = @[email protected]
-pkgdatadir = $(datadir)/@[email protected]
-pkglibdir = $(libdir)/@[email protected]
-pkgincludedir = $(includedir)/@[email protected]
-am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
-install_sh_DATA = $(install_sh) -c -m 644
-install_sh_PROGRAM = $(install_sh) -c
-install_sh_SCRIPT = $(install_sh) -c
-INSTALL_HEADER = $(INSTALL_DATA)
-transform = $(program_transform_name)
-NORMAL_INSTALL = :
-PRE_INSTALL = :
-POST_INSTALL = :
-NORMAL_UNINSTALL = :
-PRE_UNINSTALL = :
-POST_UNINSTALL = :
-build_triplet = @[email protected]
-host_triplet = @[email protected]
-DIST_COMMON = $(include_HEADERS) $(srcdir)/Makefile.am \
-	$(srcdir)/Makefile.in $(top_srcdir)/Makefile.am.common \
-	$(top_srcdir)/cf/Makefile.am.common ChangeLog lex.c parse.c \
-	parse.h
- at versionscript_TRUE@am__append_1 = $(LDFLAGS_VERSION_SCRIPT)$(srcdir)/version-script.map
-bin_PROGRAMS = compile_et$(EXEEXT)
-subdir = lib/com_err
-ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
-am__aclocal_m4_deps = $(top_srcdir)/cf/aix.m4 \
-	$(top_srcdir)/cf/auth-modules.m4 $(top_srcdir)/cf/autobuild.m4 \
-	$(top_srcdir)/cf/broken-getaddrinfo.m4 \
-	$(top_srcdir)/cf/broken-glob.m4 \
-	$(top_srcdir)/cf/broken-realloc.m4 \
-	$(top_srcdir)/cf/broken-snprintf.m4 $(top_srcdir)/cf/broken.m4 \
-	$(top_srcdir)/cf/broken2.m4 $(top_srcdir)/cf/c-attribute.m4 \
-	$(top_srcdir)/cf/capabilities.m4 \
-	$(top_srcdir)/cf/check-compile-et.m4 \
-	$(top_srcdir)/cf/check-getpwnam_r-posix.m4 \
-	$(top_srcdir)/cf/check-man.m4 \
-	$(top_srcdir)/cf/check-netinet-ip-and-tcp.m4 \
-	$(top_srcdir)/cf/check-type-extra.m4 \
-	$(top_srcdir)/cf/check-var.m4 $(top_srcdir)/cf/check-x.m4 \
-	$(top_srcdir)/cf/check-xau.m4 $(top_srcdir)/cf/crypto.m4 \
-	$(top_srcdir)/cf/db.m4 $(top_srcdir)/cf/destdirs.m4 \
-	$(top_srcdir)/cf/dlopen.m4 \
-	$(top_srcdir)/cf/find-func-no-libs.m4 \
-	$(top_srcdir)/cf/find-func-no-libs2.m4 \
-	$(top_srcdir)/cf/find-func.m4 \
-	$(top_srcdir)/cf/find-if-not-broken.m4 \
-	$(top_srcdir)/cf/framework-security.m4 \
-	$(top_srcdir)/cf/have-struct-field.m4 \
-	$(top_srcdir)/cf/have-type.m4 $(top_srcdir)/cf/irix.m4 \
-	$(top_srcdir)/cf/krb-bigendian.m4 \
-	$(top_srcdir)/cf/krb-func-getlogin.m4 \
-	$(top_srcdir)/cf/krb-ipv6.m4 $(top_srcdir)/cf/krb-prog-ln-s.m4 \
-	$(top_srcdir)/cf/krb-readline.m4 \
-	$(top_srcdir)/cf/krb-struct-spwd.m4 \
-	$(top_srcdir)/cf/krb-struct-winsize.m4 \
-	$(top_srcdir)/cf/largefile.m4 $(top_srcdir)/cf/mips-abi.m4 \
-	$(top_srcdir)/cf/misc.m4 $(top_srcdir)/cf/need-proto.m4 \
-	$(top_srcdir)/cf/osfc2.m4 $(top_srcdir)/cf/otp.m4 \
-	$(top_srcdir)/cf/proto-compat.m4 $(top_srcdir)/cf/pthreads.m4 \
-	$(top_srcdir)/cf/resolv.m4 $(top_srcdir)/cf/retsigtype.m4 \
-	$(top_srcdir)/cf/roken-frag.m4 \
-	$(top_srcdir)/cf/socket-wrapper.m4 $(top_srcdir)/cf/sunos.m4 \
-	$(top_srcdir)/cf/telnet.m4 $(top_srcdir)/cf/test-package.m4 \
-	$(top_srcdir)/cf/version-script.m4 $(top_srcdir)/cf/wflags.m4 \
-	$(top_srcdir)/cf/win32.m4 $(top_srcdir)/cf/with-all.m4 \
-	$(top_srcdir)/acinclude.m4 $(top_srcdir)/configure.in
-am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
-	$(ACLOCAL_M4)
-mkinstalldirs = $(install_sh) -d
-CONFIG_HEADER = $(top_builddir)/include/config.h
-CONFIG_CLEAN_FILES =
-am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`;
-am__vpath_adj = case $$p in \
-    $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \
-    *) f=$$p;; \
-  esac;
-am__strip_dir = `echo $$p | sed -e 's|^.*/||'`;
-am__installdirs = "$(DESTDIR)$(libdir)" "$(DESTDIR)$(bindir)" \
-	"$(DESTDIR)$(includedir)"
-libLTLIBRARIES_INSTALL = $(INSTALL)
-LTLIBRARIES = $(lib_LTLIBRARIES)
-libcom_err_la_LIBADD =
-dist_libcom_err_la_OBJECTS = libcom_err_la-error.lo \
-	libcom_err_la-com_err.lo
- at do_roken_rename_TRUE@nodist_libcom_err_la_OBJECTS =  \
- at do_roken_rename_TRUE@	libcom_err_la-snprintf.lo \
- at do_roken_rename_TRUE@	libcom_err_la-strlcpy.lo
-libcom_err_la_OBJECTS = $(dist_libcom_err_la_OBJECTS) \
-	$(nodist_libcom_err_la_OBJECTS)
-libcom_err_la_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \
-	$(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \
-	$(libcom_err_la_LDFLAGS) $(LDFLAGS) -o [email protected]
-binPROGRAMS_INSTALL = $(INSTALL_PROGRAM)
-PROGRAMS = $(bin_PROGRAMS)
-am_compile_et_OBJECTS = compile_et.$(OBJEXT) parse.$(OBJEXT) \
-	lex.$(OBJEXT)
-compile_et_OBJECTS = $(am_compile_et_OBJECTS)
-am__DEPENDENCIES_1 =
-compile_et_DEPENDENCIES = libcom_err.la $(am__DEPENDENCIES_1) \
-	$(am__DEPENDENCIES_1)
-DEFAULT_INCLUDES = -I. -I$(top_builddir)/include at am__isrc@
-depcomp =
-am__depfiles_maybe =
-COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
-	$(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
-LTCOMPILE = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \
-	--mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \
-	$(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
-CCLD = $(CC)
-LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \
-	--mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \
-	$(LDFLAGS) -o [email protected]
- at MAINTAINER_MODE_FALSE@am__skiplex = test -f [email protected] ||
-LEXCOMPILE = $(LEX) $(LFLAGS) $(AM_LFLAGS)
-LTLEXCOMPILE = $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \
-	--mode=compile $(LEX) $(LFLAGS) $(AM_LFLAGS)
-YLWRAP = $(top_srcdir)/ylwrap
- at MAINTAINER_MODE_FALSE@am__skipyacc = test -f [email protected] ||
-YACCCOMPILE = $(YACC) $(YFLAGS) $(AM_YFLAGS)
-LTYACCCOMPILE = $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \
-	--mode=compile $(YACC) $(YFLAGS) $(AM_YFLAGS)
-SOURCES = $(dist_libcom_err_la_SOURCES) \
-	$(nodist_libcom_err_la_SOURCES) $(compile_et_SOURCES)
-DIST_SOURCES = $(dist_libcom_err_la_SOURCES) $(compile_et_SOURCES)
-includeHEADERS_INSTALL = $(INSTALL_HEADER)
-HEADERS = $(include_HEADERS)
-ETAGS = etags
-CTAGS = ctags
-DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
-ACLOCAL = @[email protected]
-AIX_EXTRA_KAFS = @[email protected]
-AMTAR = @[email protected]
-AR = @[email protected]
-AUTOCONF = @[email protected]
-AUTOHEADER = @[email protected]
-AUTOMAKE = @[email protected]
-AWK = @[email protected]
-CANONICAL_HOST = @[email protected]
-CATMAN = @[email protected]
-CATMANEXT = @[email protected]
-CC = @[email protected]
-CFLAGS = @[email protected]
-COMPILE_ET = @[email protected]
-CPP = @[email protected]
-CPPFLAGS = @[email protected]
-CXX = @[email protected]
-CXXCPP = @[email protected]
-CXXFLAGS = @[email protected]
-CYGPATH_W = @[email protected]
-DBLIB = @[email protected]
-DEFS = @[email protected]
-DIR_com_err = @[email protected]
-DIR_hcrypto = @[email protected]
-DIR_hdbdir = @[email protected]
-DIR_roken = @[email protected]
-ECHO = @[email protected]
-ECHO_C = @[email protected]
-ECHO_N = @[email protected]
-ECHO_T = @[email protected]
-EGREP = @[email protected]
-EXEEXT = @[email protected]
-F77 = @[email protected]
-FFLAGS = @[email protected]
-GREP = @[email protected]
-GROFF = @[email protected]
-INCLUDES_roken = @[email protected]
-INCLUDE_hcrypto = @[email protected]
-INCLUDE_hesiod = @[email protected]
-INCLUDE_krb4 = @[email protected]
-INCLUDE_openldap = @[email protected]
-INCLUDE_readline = @[email protected]
-INSTALL = @[email protected]
-INSTALL_DATA = @[email protected]
-INSTALL_PROGRAM = @[email protected]
-INSTALL_SCRIPT = @[email protected]
-INSTALL_STRIP_PROGRAM = @[email protected]
-LDFLAGS = @[email protected]
-LDFLAGS_VERSION_SCRIPT = @[email protected]
-LEX = @[email protected]
-LEXLIB = @[email protected]
-LEX_OUTPUT_ROOT = @[email protected]
-LIBADD_roken = @[email protected]
-LIBOBJS = @[email protected]
-LIBS = @[email protected]
-LIBTOOL = @[email protected]
-LIB_AUTH_SUBDIRS = @[email protected]
-LIB_NDBM = @[email protected]
-LIB_XauFileName = @[email protected]
-LIB_XauReadAuth = @[email protected]
-LIB_XauWriteAuth = @[email protected]
-LIB_bswap16 = @[email protected]
-LIB_bswap32 = @[email protected]
-LIB_com_err = @[email protected]
-LIB_com_err_a = @[email protected]
-LIB_com_err_so = @[email protected]
-LIB_crypt = @[email protected]
-LIB_db_create = @[email protected]
-LIB_dbm_firstkey = @[email protected]
-LIB_dbopen = @[email protected]
-LIB_dlopen = @[email protected]
-LIB_dn_expand = @[email protected]
-LIB_door_create = @[email protected]
-LIB_el_init = @[email protected]
-LIB_freeaddrinfo = @[email protected]
-LIB_gai_strerror = @[email protected]
-LIB_getaddrinfo = @[email protected]
-LIB_gethostbyname = @[email protected]
-LIB_gethostbyname2 = @[email protected]
-LIB_getnameinfo = @[email protected]
-LIB_getpwnam_r = @[email protected]
-LIB_getsockopt = @[email protected]
-LIB_hcrypto = @[email protected]
-LIB_hcrypto_a = @[email protected]
-LIB_hcrypto_appl = @[email protected]
-LIB_hcrypto_so = @[email protected]
-LIB_hesiod = @[email protected]
-LIB_hstrerror = @[email protected]
-LIB_kdb = @[email protected]
-LIB_krb4 = @[email protected]
-LIB_loadquery = @[email protected]
-LIB_logout = @[email protected]
-LIB_logwtmp = @[email protected]
-LIB_openldap = @[email protected]
-LIB_openpty = @[email protected]
-LIB_otp = @[email protected]
-LIB_pidfile = @[email protected]
-LIB_readline = @[email protected]
-LIB_res_ndestroy = @[email protected]
-LIB_res_nsearch = @[email protected]
-LIB_res_search = @[email protected]
-LIB_roken = @[email protected]
-LIB_security = @[email protected]
-LIB_setsockopt = @[email protected]
-LIB_socket = @[email protected]
-LIB_syslog = @[email protected]
-LIB_tgetent = @[email protected]
-LN_S = @[email protected]
-LTLIBOBJS = @[email protected]
-MAINT = @[email protected]
-MAKEINFO = @[email protected]
-MKDIR_P = @[email protected]
-NROFF = @[email protected]
-OBJEXT = @[email protected]
-PACKAGE = @[email protected]
-PACKAGE_BUGREPORT = @[email protected]
-PACKAGE_NAME = @[email protected]
-PACKAGE_STRING = @[email protected]
-PACKAGE_TARNAME = @PACKAGE_TARNAM[email protected]
-PACKAGE_VERSION = @[email protected]
-PATH_SEPARATOR = @[email protected]
-PTHREADS_CFLAGS = @[email protected]
-PTHREADS_LIBS = @[email protected]
-RANLIB = @[email protected]
-SET_MAKE = @[email protected]
-SHELL = @[email protected]
-STRIP = @[email protected]
-VERSION = @[email protected]
-VERSIONING = @[email protected]
-VOID_RETSIGTYPE = @[email protected]
-WFLAGS = @[email protected]
-WFLAGS_NOIMPLICITINT = @[email protected]
-WFLAGS_NOUNUSED = @[email protected]
-XMKMF = @[email protected]
-X_CFLAGS = @[email protected]
-X_EXTRA_LIBS = @[email protected]
-X_LIBS = @[email protected]
-X_PRE_LIBS = @[email protected]
-YACC = @[email protected]
-YFLAGS = -d
-abs_builddir = @[email protected]
-abs_srcdir = @[email protected]
-abs_top_builddir = @[email protected]
-abs_top_srcdir = @[email protected]
-ac_ct_CC = @[email protected]
-ac_ct_CXX = @[email protected]
-ac_ct_F77 = @[email protected]
-am__leading_dot = @[email protected]
-am__tar = @[email protected]
-am__untar = @[email protected]
-bindir = @[email protected]
-build = @[email protected]
-build_alias = @[email protected]
-build_cpu = @[email protected]
-build_os = @[email protected]
-build_vendor = @[email protected]
-builddir = @[email protected]
-datadir = @[email protected]
-datarootdir = @[email protected]
-docdir = @[email protected]
-dpagaix_cflags = @[email protected]
-dpagaix_ldadd = @[email protected]
-dpagaix_ldflags = @[email protected]
-dvidir = @[email protected]
-exec_prefix = @[email protected]
-host = @[email protected]
-host_alias = @[email protected]
-host_cpu = @[email protected]
-host_os = @[email protected]
-host_vendor = @[email protected]
-htmldir = @[email protected]
-includedir = @[email protected]
-infodir = @[email protected]
-install_sh = @[email protected]
-libdir = @[email protected]
-libexecdir = @[email protected]
-localedir = @[email protected]
-localstatedir = @[email protected]
-mandir = @[email protected]
-mkdir_p = @[email protected]
-oldincludedir = @[email protected]
-pdfdir = @[email protected]
-prefix = @[email protected]
-program_transform_name = @[email protected]
-psdir = @[email protected]
-sbindir = @[email protected]
-sharedstatedir = @[email protected]
-srcdir = @[email protected]
-sysconfdir = @[email protected]
-target_alias = @[email protected]
-top_builddir = @[email protected]
-top_srcdir = @[email protected]
-SUFFIXES = .et .h .x .z .1 .3 .5 .8 .cat1 .cat3 .cat5 .cat8
-AM_CPPFLAGS = -I$(top_builddir)/include $(INCLUDES_roken)
- at do_roken_rename_TRUE@ROKEN_RENAME = -DROKEN_RENAME
-AM_CFLAGS = $(WFLAGS)
-CP = cp
-buildinclude = $(top_builddir)/include
-LIB_getattr = @[email protected]
-LIB_getpwent_r = @[email protected]
-LIB_odm_initialize = @[email protected]
-LIB_setpcred = @[email protected]
-HESIODLIB = @[email protected]
-HESIODINCLUDE = @[email protected]
-NROFF_MAN = groff -mandoc -Tascii
-LIB_kafs = $(top_builddir)/lib/kafs/libkafs.la $(AIX_EXTRA_KAFS)
- at KRB5_TRUE@LIB_krb5 = $(top_builddir)/lib/krb5/libkrb5.la \
- at KRB5_TRUE@	$(top_builddir)/lib/asn1/libasn1.la
-
- at KRB5_TRUE@LIB_gssapi = $(top_builddir)/lib/gssapi/libgssapi.la
- at KRB5_TRUE@LIB_tsasl = $(top_builddir)/lib/tsasl/libtsasl.la
- at DCE_TRUE@LIB_kdfs = $(top_builddir)/lib/kdfs/libkdfs.la
-lib_LTLIBRARIES = libcom_err.la
-libcom_err_la_LDFLAGS = -version-info 2:3:1 $(am__append_1)
-include_HEADERS = com_err.h com_right.h
-compile_et_SOURCES = compile_et.c compile_et.h parse.y lex.l lex.h
-libcom_err_la_CPPFLAGS = $(ROKEN_RENAME)
-dist_libcom_err_la_SOURCES = error.c com_err.c roken_rename.h
- at do_roken_rename_TRUE@nodist_libcom_err_la_SOURCES = snprintf.c strlcpy.c
-compile_et_LDADD = \
-	libcom_err.la \
-	$(LIB_roken) \
-	$(LEXLIB)
-
-EXTRA_DIST = version-script.map
-all: all-am
-
-.SUFFIXES:
-.SUFFIXES: .et .h .x .z .1 .3 .5 .8 .cat1 .cat3 .cat5 .cat8 .c .l .lo .o .obj .y
-$(srcdir)/Makefile.in: @[email protected] $(srcdir)/Makefile.am $(top_srcdir)/Makefile.am.common $(top_srcdir)/cf/Makefile.am.common $(am__configure_deps)
-	@for dep in $?; do \
-	  case '$(am__configure_deps)' in \
-	    *$$dep*) \
-	      cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh \
-		&& exit 0; \
-	      exit 1;; \
-	  esac; \
-	done; \
-	echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign  --ignore-deps lib/com_err/Makefile'; \
-	cd $(top_srcdir) && \
-	  $(AUTOMAKE) --foreign  --ignore-deps lib/com_err/Makefile
-.PRECIOUS: Makefile
-Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
-	@case '$?' in \
-	  *config.status*) \
-	    cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
-	  *) \
-	    echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/[email protected] $(am__depfiles_maybe)'; \
-	    cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/[email protected] $(am__depfiles_maybe);; \
-	esac;
-
-$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
-	cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
-
-$(top_srcdir)/configure: @[email protected] $(am__configure_deps)
-	cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
-$(ACLOCAL_M4): @[email protected] $(am__aclocal_m4_deps)
-	cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
-install-libLTLIBRARIES: $(lib_LTLIBRARIES)
-	@$(NORMAL_INSTALL)
-	test -z "$(libdir)" || $(MKDIR_P) "$(DESTDIR)$(libdir)"
-	@list='$(lib_LTLIBRARIES)'; for p in $$list; do \
-	  if test -f $$p; then \
-	    f=$(am__strip_dir) \
-	    echo " $(LIBTOOL) --mode=install $(libLTLIBRARIES_INSTALL) $(INSTALL_STRIP_FLAG) '$$p' '$(DESTDIR)$(libdir)/$$f'"; \
-	    $(LIBTOOL) --mode=install $(libLTLIBRARIES_INSTALL) $(INSTALL_STRIP_FLAG) "$$p" "$(DESTDIR)$(libdir)/$$f"; \
-	  else :; fi; \
-	done
-
-uninstall-libLTLIBRARIES:
-	@$(NORMAL_UNINSTALL)
-	@list='$(lib_LTLIBRARIES)'; for p in $$list; do \
-	  p=$(am__strip_dir) \
-	  echo " $(LIBTOOL) --mode=uninstall rm -f '$(DESTDIR)$(libdir)/$$p'"; \
-	  $(LIBTOOL) --mode=uninstall rm -f "$(DESTDIR)$(libdir)/$$p"; \
-	done
-
-clean-libLTLIBRARIES:
-	-test -z "$(lib_LTLIBRARIES)" || rm -f $(lib_LTLIBRARIES)
-	@list='$(lib_LTLIBRARIES)'; for p in $$list; do \
-	  dir="`echo $$p | sed -e 's|/[^/]*$$||'`"; \
-	  test "$$dir" != "$$p" || dir=.; \
-	  echo "rm -f \"$${dir}/so_locations\""; \
-	  rm -f "$${dir}/so_locations"; \
-	done
-libcom_err.la: $(libcom_err_la_OBJECTS) $(libcom_err_la_DEPENDENCIES) 
-	$(libcom_err_la_LINK) -rpath $(libdir) $(libcom_err_la_OBJECTS) $(libcom_err_la_LIBADD) $(LIBS)
-install-binPROGRAMS: $(bin_PROGRAMS)
-	@$(NORMAL_INSTALL)
-	test -z "$(bindir)" || $(MKDIR_P) "$(DESTDIR)$(bindir)"
-	@list='$(bin_PROGRAMS)'; for p in $$list; do \
-	  p1=`echo $$p|sed 's/$(EXEEXT)$$//'`; \
-	  if test -f $$p \
-	     || test -f $$p1 \
-	  ; then \
-	    f=`echo "$$p1" | sed 's,^.*/,,;$(transform);s/$$/$(EXEEXT)/'`; \
-	   echo " $(INSTALL_PROGRAM_ENV) $(LIBTOOL) --mode=install $(binPROGRAMS_INSTALL) '$$p' '$(DESTDIR)$(bindir)/$$f'"; \
-	   $(INSTALL_PROGRAM_ENV) $(LIBTOOL) --mode=install $(binPROGRAMS_INSTALL) "$$p" "$(DESTDIR)$(bindir)/$$f" || exit 1; \
-	  else :; fi; \
-	done
-
-uninstall-binPROGRAMS:
-	@$(NORMAL_UNINSTALL)
-	@list='$(bin_PROGRAMS)'; for p in $$list; do \
-	  f=`echo "$$p" | sed 's,^.*/,,;s/$(EXEEXT)$$//;$(transform);s/$$/$(EXEEXT)/'`; \
-	  echo " rm -f '$(DESTDIR)$(bindir)/$$f'"; \
-	  rm -f "$(DESTDIR)$(bindir)/$$f"; \
-	done
-
-clean-binPROGRAMS:
-	@list='$(bin_PROGRAMS)'; for p in $$list; do \
-	  f=`echo $$p|sed 's/$(EXEEXT)$$//'`; \
-	  echo " rm -f $$p $$f"; \
-	  rm -f $$p $$f ; \
-	done
-parse.h: parse.c
-	@if test ! -f [email protected]; then \
-	  rm -f parse.c; \
-	  $(MAKE) $(AM_MAKEFLAGS) parse.c; \
-	else :; fi
-compile_et$(EXEEXT): $(compile_et_OBJECTS) $(compile_et_DEPENDENCIES) 
-	@rm -f compile_et$(EXEEXT)
-	$(LINK) $(compile_et_OBJECTS) $(compile_et_LDADD) $(LIBS)
-
-mostlyclean-compile:
-	-rm -f *.$(OBJEXT)
-
-distclean-compile:
-	-rm -f *.tab.c
-
-.c.o:
-	$(COMPILE) -c $<
-
-.c.obj:
-	$(COMPILE) -c `$(CYGPATH_W) '$<'`
-
-.c.lo:
-	$(LTCOMPILE) -c -o [email protected] $<
-
-libcom_err_la-error.lo: error.c
-	$(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcom_err_la_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o libcom_err_la-error.lo `test -f 'error.c' || echo '$(srcdir)/'`error.c
-
-libcom_err_la-com_err.lo: com_err.c
-	$(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcom_err_la_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o libcom_err_la-com_err.lo `test -f 'com_err.c' || echo '$(srcdir)/'`com_err.c
-
-libcom_err_la-snprintf.lo: snprintf.c
-	$(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcom_err_la_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o libcom_err_la-snprintf.lo `test -f 'snprintf.c' || echo '$(srcdir)/'`snprintf.c
-
-libcom_err_la-strlcpy.lo: strlcpy.c
-	$(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libcom_err_la_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o libcom_err_la-strlcpy.lo `test -f 'strlcpy.c' || echo '$(srcdir)/'`strlcpy.c
-
-.l.c:
-	$(am__skiplex) $(SHELL) $(YLWRAP) $< $(LEX_OUTPUT_ROOT).c [email protected] -- $(LEXCOMPILE)
-
-.y.c:
-	$(am__skipyacc) $(SHELL) $(YLWRAP) $< y.tab.c [email protected] y.tab.h $*.h y.output $*.output -- $(YACCCOMPILE)
-
-mostlyclean-libtool:
-	-rm -f *.lo
-
-clean-libtool:
-	-rm -rf .libs _libs
-install-includeHEADERS: $(include_HEADERS)
-	@$(NORMAL_INSTALL)
-	test -z "$(includedir)" || $(MKDIR_P) "$(DESTDIR)$(includedir)"
-	@list='$(include_HEADERS)'; for p in $$list; do \
-	  if test -f "$$p"; then d=; else d="$(srcdir)/"; fi; \
-	  f=$(am__strip_dir) \
-	  echo " $(includeHEADERS_INSTALL) '$$d$$p' '$(DESTDIR)$(includedir)/$$f'"; \
-	  $(includeHEADERS_INSTALL) "$$d$$p" "$(DESTDIR)$(includedir)/$$f"; \
-	done
-
-uninstall-includeHEADERS:
-	@$(NORMAL_UNINSTALL)
-	@list='$(include_HEADERS)'; for p in $$list; do \
-	  f=$(am__strip_dir) \
-	  echo " rm -f '$(DESTDIR)$(includedir)/$$f'"; \
-	  rm -f "$(DESTDIR)$(includedir)/$$f"; \
-	done
-
-ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES)
-	list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \
-	unique=`for i in $$list; do \
-	    if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
-	  done | \
-	  $(AWK) '    { files[$$0] = 1; } \
-	       END { for (i in files) print i; }'`; \
-	mkid -fID $$unique
-tags: TAGS
-
-TAGS:  $(HEADERS) $(SOURCES)  $(TAGS_DEPENDENCIES) \
-		$(TAGS_FILES) $(LISP)
-	tags=; \
-	here=`pwd`; \
-	list='$(SOURCES) $(HEADERS)  $(LISP) $(TAGS_FILES)'; \
-	unique=`for i in $$list; do \
-	    if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
-	  done | \
-	  $(AWK) '    { files[$$0] = 1; } \
-	       END { for (i in files) print i; }'`; \
-	if test -z "$(ETAGS_ARGS)$$tags$$unique"; then :; else \
-	  test -n "$$unique" || unique=$$empty_fix; \
-	  $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
-	    $$tags $$unique; \
-	fi
-ctags: CTAGS
-CTAGS:  $(HEADERS) $(SOURCES)  $(TAGS_DEPENDENCIES) \
-		$(TAGS_FILES) $(LISP)
-	tags=; \
-	here=`pwd`; \
-	list='$(SOURCES) $(HEADERS)  $(LISP) $(TAGS_FILES)'; \
-	unique=`for i in $$list; do \
-	    if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \
-	  done | \
-	  $(AWK) '    { files[$$0] = 1; } \
-	       END { for (i in files) print i; }'`; \
-	test -z "$(CTAGS_ARGS)$$tags$$unique" \
-	  || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \
-	     $$tags $$unique
-
-GTAGS:
-	here=`$(am__cd) $(top_builddir) && pwd` \
-	  && cd $(top_srcdir) \
-	  && gtags -i $(GTAGS_ARGS) $$here
-
-distclean-tags:
-	-rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags
-
-distdir: $(DISTFILES)
-	@srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
-	topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \
-	list='$(DISTFILES)'; \
-	  dist_files=`for file in $$list; do echo $$file; done | \
-	  sed -e "s|^$$srcdirstrip/||;t" \
-	      -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \
-	case $$dist_files in \
-	  */*) $(MKDIR_P) `echo "$$dist_files" | \
-			   sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \
-			   sort -u` ;; \
-	esac; \
-	for file in $$dist_files; do \
-	  if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
-	  if test -d $$d/$$file; then \
-	    dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \
-	    if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
-	      cp -pR $(srcdir)/$$file $(distdir)$$dir || exit 1; \
-	    fi; \
-	    cp -pR $$d/$$file $(distdir)$$dir || exit 1; \
-	  else \
-	    test -f $(distdir)/$$file \
-	    || cp -p $$d/$$file $(distdir)/$$file \
-	    || exit 1; \
-	  fi; \
-	done
-	$(MAKE) $(AM_MAKEFLAGS) \
-	  top_distdir="$(top_distdir)" distdir="$(distdir)" \
-	  dist-hook
-check-am: all-am
-	$(MAKE) $(AM_MAKEFLAGS) check-local
-check: check-am
-all-am: Makefile $(LTLIBRARIES) $(PROGRAMS) $(HEADERS) all-local
-install-binPROGRAMS: install-libLTLIBRARIES
-
-installdirs:
-	for dir in "$(DESTDIR)$(libdir)" "$(DESTDIR)$(bindir)" "$(DESTDIR)$(includedir)"; do \
-	  test -z "$$dir" || $(MKDIR_P) "$$dir"; \
-	done
-install: install-am
-install-exec: install-exec-am
-install-data: install-data-am
-uninstall: uninstall-am
-
-install-am: all-am
-	@$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
-
-installcheck: installcheck-am
-install-strip:
-	$(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
-	  install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
-	  `test -z '$(STRIP)' || \
-	    echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
-mostlyclean-generic:
-
-clean-generic:
-
-distclean-generic:
-	-test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
-
-maintainer-clean-generic:
-	@echo "This command is intended for maintainers to use"
-	@echo "it deletes files that may require special tools to rebuild."
-	-rm -f lex.c
-	-rm -f parse.c
-	-rm -f parse.h
-clean: clean-am
-
-clean-am: clean-binPROGRAMS clean-generic clean-libLTLIBRARIES \
-	clean-libtool mostlyclean-am
-
-distclean: distclean-am
-	-rm -f Makefile
-distclean-am: clean-am distclean-compile distclean-generic \
-	distclean-tags
-
-dvi: dvi-am
-
-dvi-am:
-
-html: html-am
-
-info: info-am
-
-info-am:
-
-install-data-am: install-includeHEADERS
-	@$(NORMAL_INSTALL)
-	$(MAKE) $(AM_MAKEFLAGS) install-data-hook
-
-install-dvi: install-dvi-am
-
-install-exec-am: install-binPROGRAMS install-libLTLIBRARIES
-	@$(NORMAL_INSTALL)
-	$(MAKE) $(AM_MAKEFLAGS) install-exec-hook
-
-install-html: install-html-am
-
-install-info: install-info-am
-
-install-man:
-
-install-pdf: install-pdf-am
-
-install-ps: install-ps-am
-
-installcheck-am:
-
-maintainer-clean: maintainer-clean-am
-	-rm -f Makefile
-maintainer-clean-am: distclean-am maintainer-clean-generic
-
-mostlyclean: mostlyclean-am
-
-mostlyclean-am: mostlyclean-compile mostlyclean-generic \
-	mostlyclean-libtool
-
-pdf: pdf-am
-
-pdf-am:
-
-ps: ps-am
-
-ps-am:
-
-uninstall-am: uninstall-binPROGRAMS uninstall-includeHEADERS \
-	uninstall-libLTLIBRARIES
-	@$(NORMAL_INSTALL)
-	$(MAKE) $(AM_MAKEFLAGS) uninstall-hook
-
-.MAKE: install-am install-data-am install-exec-am install-strip \
-	uninstall-am
-
-.PHONY: CTAGS GTAGS all all-am all-local check check-am check-local \
-	clean clean-binPROGRAMS clean-generic clean-libLTLIBRARIES \
-	clean-libtool ctags dist-hook distclean distclean-compile \
-	distclean-generic distclean-libtool distclean-tags distdir dvi \
-	dvi-am html html-am info info-am install install-am \
-	install-binPROGRAMS install-data install-data-am \
-	install-data-hook install-dvi install-dvi-am install-exec \
-	install-exec-am install-exec-hook install-html install-html-am \
-	install-includeHEADERS install-info install-info-am \
-	install-libLTLIBRARIES install-man install-pdf install-pdf-am \
-	install-ps install-ps-am install-strip installcheck \
-	installcheck-am installdirs maintainer-clean \
-	maintainer-clean-generic mostlyclean mostlyclean-compile \
-	mostlyclean-generic mostlyclean-libtool pdf pdf-am ps ps-am \
-	tags uninstall uninstall-am uninstall-binPROGRAMS \
-	uninstall-hook uninstall-includeHEADERS \
-	uninstall-libLTLIBRARIES
-
-
-install-suid-programs:
-	@foo='$(bin_SUIDS)'; \
-	for file in $$foo; do \
-	x=$(DESTDIR)$(bindir)/$$file; \
-	if chown 0:0 $$x && chmod u+s $$x; then :; else \
-	echo "*"; \
-	echo "* Failed to install $$x setuid root"; \
-	echo "*"; \
-	fi; done
-
-install-exec-hook: install-suid-programs
-
-install-build-headers:: $(include_HEADERS) $(dist_include_HEADERS) $(nodist_include_HEADERS) $(build_HEADERZ) $(nobase_include_HEADERS)
-	@foo='$(include_HEADERS) $(dist_include_HEADERS) $(nodist_include_HEADERS) $(build_HEADERZ)'; \
-	for f in $$foo; do \
-		f=`basename $$f`; \
-		if test -f "$(srcdir)/$$f"; then file="$(srcdir)/$$f"; \
-		else file="$$f"; fi; \
-		if cmp -s  $$file $(buildinclude)/$$f 2> /dev/null ; then \
-		: ; else \
-			echo " $(CP) $$file $(buildinclude)/$$f"; \
-			$(CP) $$file $(buildinclude)/$$f; \
-		fi ; \
-	done ; \
-	foo='$(nobase_include_HEADERS)'; \
-	for f in $$foo; do \
-		if test -f "$(srcdir)/$$f"; then file="$(srcdir)/$$f"; \
-		else file="$$f"; fi; \
-		$(mkdir_p) $(buildinclude)/`dirname $$f` ; \
-		if cmp -s  $$file $(buildinclude)/$$f 2> /dev/null ; then \
-		: ; else \
-			echo " $(CP) $$file $(buildinclude)/$$f"; \
-			$(CP) $$file $(buildinclude)/$$f; \
-		fi ; \
-	done
-
-all-local: install-build-headers
-
-check-local::
-	@if test '$(CHECK_LOCAL)' = "no-check-local"; then \
-	  foo=''; elif test '$(CHECK_LOCAL)'; then \
-	  foo='$(CHECK_LOCAL)'; else \
-	  foo='$(PROGRAMS)'; fi; \
-	  if test "$$foo"; then \
-	  failed=0; all=0; \
-	  for i in $$foo; do \
-	    all=`expr $$all + 1`; \
-	    if (./$$i --version && ./$$i --help) > /dev/null 2>&1; then \
-	      echo "PASS: $$i"; \
-	    else \
-	      echo "FAIL: $$i"; \
-	      failed=`expr $$failed + 1`; \
-	    fi; \
-	  done; \
-	  if test "$$failed" -eq 0; then \
-	    banner="All $$all tests passed"; \
-	  else \
-	    banner="$$failed of $$all tests failed"; \
-	  fi; \
-	  dashes=`echo "$$banner" | sed s/./=/g`; \
-	  echo "$$dashes"; \
-	  echo "$$banner"; \
-	  echo "$$dashes"; \
-	  test "$$failed" -eq 0 || exit 1; \
-	fi
-
-.x.c:
-	@cmp -s $< [email protected] 2> /dev/null || cp $< [email protected]
-#NROFF_MAN = nroff -man
-.1.cat1:
-	$(NROFF_MAN) $< > [email protected]
-.3.cat3:
-	$(NROFF_MAN) $< > [email protected]
-.5.cat5:
-	$(NROFF_MAN) $< > [email protected]
-.8.cat8:
-	$(NROFF_MAN) $< > [email protected]
-
-dist-cat1-mans:
-	@foo='$(man1_MANS)'; \
-	bar='$(man_MANS)'; \
-	for i in $$bar; do \
-	case $$i in \
-	*.1) foo="$$foo $$i";; \
-	esac; done ;\
-	for i in $$foo; do \
-		x=`echo $$i | sed 's/\.[^.]*$$/.cat1/'`; \
-		echo "$(NROFF_MAN) $(srcdir)/$$i > $(distdir)/$$x"; \
-		$(NROFF_MAN) $(srcdir)/$$i > $(distdir)/$$x; \
-	done
-
-dist-cat3-mans:
-	@foo='$(man3_MANS)'; \
-	bar='$(man_MANS)'; \
-	for i in $$bar; do \
-	case $$i in \
-	*.3) foo="$$foo $$i";; \
-	esac; done ;\
-	for i in $$foo; do \
-		x=`echo $$i | sed 's/\.[^.]*$$/.cat3/'`; \
-		echo "$(NROFF_MAN) $(srcdir)/$$i > $(distdir)/$$x"; \
-		$(NROFF_MAN) $(srcdir)/$$i > $(distdir)/$$x; \
-	done
-
-dist-cat5-mans:
-	@foo='$(man5_MANS)'; \
-	bar='$(man_MANS)'; \
-	for i in $$bar; do \
-	case $$i in \
-	*.5) foo="$$foo $$i";; \
-	esac; done ;\
-	for i in $$foo; do \
-		x=`echo $$i | sed 's/\.[^.]*$$/.cat5/'`; \
-		echo "$(NROFF_MAN) $(srcdir)/$$i > $(distdir)/$$x"; \
-		$(NROFF_MAN) $(srcdir)/$$i > $(distdir)/$$x; \
-	done
-
-dist-cat8-mans:
-	@foo='$(man8_MANS)'; \
-	bar='$(man_MANS)'; \
-	for i in $$bar; do \
-	case $$i in \
-	*.8) foo="$$foo $$i";; \
-	esac; done ;\
-	for i in $$foo; do \
-		x=`echo $$i | sed 's/\.[^.]*$$/.cat8/'`; \
-		echo "$(NROFF_MAN) $(srcdir)/$$i > $(distdir)/$$x"; \
-		$(NROFF_MAN) $(srcdir)/$$i > $(distdir)/$$x; \
-	done
-
-dist-hook: dist-cat1-mans dist-cat3-mans dist-cat5-mans dist-cat8-mans
-
-install-cat-mans:
-	$(SHELL) $(top_srcdir)/cf/install-catman.sh install "$(INSTALL_DATA)" "$(mkinstalldirs)" "$(srcdir)" "$(DESTDIR)$(mandir)" '$(CATMANEXT)' $(man_MANS) $(man1_MANS) $(man3_MANS) $(man5_MANS) $(man8_MANS)
-
-uninstall-cat-mans:
-	$(SHELL) $(top_srcdir)/cf/install-catman.sh uninstall "$(INSTALL_DATA)" "$(mkinstalldirs)" "$(srcdir)" "$(DESTDIR)$(mandir)" '$(CATMANEXT)' $(man_MANS) $(man1_MANS) $(man3_MANS) $(man5_MANS) $(man8_MANS)
-
-install-data-hook: install-cat-mans
-uninstall-hook: uninstall-cat-mans
-
-.et.h:
-	$(COMPILE_ET) $<
-.et.c:
-	$(COMPILE_ET) $<
-
-#
-# Useful target for debugging
-#
-
-check-valgrind:
-	tobjdir=`cd $(top_builddir) && pwd` ; \
-	tsrcdir=`cd $(top_srcdir) && pwd` ; \
-	env TESTS_ENVIRONMENT="$${tobjdir}/libtool --mode execute valgrind --leak-check=full --trace-children=yes --quiet -q --num-callers=30 --suppressions=$${tsrcdir}/cf/valgrind-suppressions" make check
-
-#
-# Target to please samba build farm, builds distfiles in-tree.
-# Will break when automake changes...
-#
-
-distdir-in-tree: $(DISTFILES) $(INFO_DEPS)
-	list='$(DIST_SUBDIRS)'; for subdir in $$list; do \
-	  if test "$$subdir" != .; then \
-	  (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) distdir-in-tree) ; \
-	  fi ; \
-	done
-
-$(compile_et_OBJECTS): parse.h parse.c ## XXX broken automake 1.4s
-
-snprintf.c:
-	$(LN_S) $(srcdir)/../roken/snprintf.c .
-strlcpy.c:
-	$(LN_S) $(srcdir)/../roken/strlcpy.c .
-# Tell versions [3.59,3.63) of GNU make to not export all variables.
-# Otherwise a system limit (for SysV at least) may be exceeded.
-.NOEXPORT:
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/com_err/getarg.c
--- a/head/contrib/com_err/getarg.c	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,379 +0,0 @@
-/*
- * Copyright (c) 1997, 1998 Kungliga Tekniska Högskolan
- * (Royal Institute of Technology, Stockholm, Sweden). 
- * All rights reserved. 
- *
- * Redistribution and use in source and binary forms, with or without 
- * modification, are permitted provided that the following conditions 
- * are met: 
- *
- * 1. Redistributions of source code must retain the above copyright 
- *    notice, this list of conditions and the following disclaimer. 
- *
- * 2. Redistributions in binary form must reproduce the above copyright 
- *    notice, this list of conditions and the following disclaimer in the 
- *    documentation and/or other materials provided with the distribution. 
- *
- * 3. All advertising materials mentioning features or use of this software 
- *    must display the following acknowledgement: 
- *      This product includes software developed by Kungliga Tekniska 
- *      Högskolan and its contributors. 
- *
- * 4. Neither the name of the Institute nor the names of its contributors 
- *    may be used to endorse or promote products derived from this software 
- *    without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
- * SUCH DAMAGE. 
- *
- * $FreeBSD$
- */
-
-#if 0
-RCSID("$Id: getarg.c,v 1.25 1998/11/22 09:45:05 assar Exp $");
-#endif
-
-#include <sys/ttycom.h>
-#include <time.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include "getarg.h"
-
-#define ISFLAG(X) ((X).type == arg_flag || (X).type == arg_negative_flag)
-
-static size_t
-print_arg (char *string, size_t len, int mdoc, int longp, struct getargs *arg)
-{
-    const char *s;
-
-    *string = '\0';
-
-    if (ISFLAG(*arg))
-	return 0;
-
-    if(mdoc){
-	if(longp)
-	    strncat(string, "= Ns", len);
-	strncat(string, " Ar ", len);
-    }else
-	if (longp)
-	    strncat (string, "=", len);
-	else
-	    strncat (string, " ", len);
-
-    if (arg->arg_help)
-	s = arg->arg_help;
-    else if (arg->type == arg_integer)
-	s = "number";
-    else if (arg->type == arg_string)
-	s = "string";
-    else
-	s = "<undefined>";
-
-    strncat(string, s, len);
-    return 1 + strlen(s);
-}
-
-static int
-check_column(FILE *f, int col, int len, int columns)
-{
-    if(col + len > columns) {
-	fprintf(f, "\n");
-	col = fprintf(f, "  ");
-    }
-    return col;
-}
-
-void
-arg_printusage (struct getargs *args,
-		size_t num_args,
-		const char *progname,
-		const char *extra_string)
-{
-    int i;
-    size_t max_len = 0;
-    char buf[128];
-    int col = 0, columns;
-    struct winsize ws;
-
-    columns = 80;
-    col = 0;
-    col += fprintf (stderr, "Usage: %s", progname);
-    for (i = 0; i < num_args; ++i) {
-	size_t len = 0;
-
-	if (args[i].long_name) {
-	    buf[0] = '\0';
-	    strncat(buf, "[--", sizeof(buf));
-	    len += 2;
-	    if(args[i].type == arg_negative_flag) {
-		strncat(buf, "no-", sizeof(buf));
-		len += 3;
-	    }
-	    strncat(buf, args[i].long_name, sizeof(buf));
-	    len += strlen(args[i].long_name);
-	    len += print_arg(buf + strlen(buf), sizeof(buf) - strlen(buf), 
-			     0, 1, &args[i]);
-	    strncat(buf, "]", sizeof(buf));
-	    if(args[i].type == arg_strings)
-		strncat(buf, "...", sizeof(buf));
-	    col = check_column(stderr, col, strlen(buf) + 1, columns);
-	    col += fprintf(stderr, " %s", buf);
-	}
-	if (args[i].short_name) {
-	    snprintf(buf, sizeof(buf), "[-%c", args[i].short_name);
-	    len += 2;
-	    len += print_arg(buf + strlen(buf), sizeof(buf) - strlen(buf), 
-			     0, 0, &args[i]);
-	    strncat(buf, "]", sizeof(buf));
-	    if(args[i].type == arg_strings)
-		strncat(buf, "...", sizeof(buf));
-	    col = check_column(stderr, col, strlen(buf) + 1, columns);
-	    col += fprintf(stderr, " %s", buf);
-	}
-	if (args[i].long_name && args[i].short_name)
-	    len += 2; /* ", " */
-	max_len = max(max_len, len);
-    }
-    if (extra_string) {
-	col = check_column(stderr, col, strlen(extra_string) + 1, columns);
-	fprintf (stderr, " %s\n", extra_string);
-    } else
-	fprintf (stderr, "\n");
-    for (i = 0; i < num_args; ++i) {
-	if (args[i].help) {
-	    size_t count = 0;
-
-	    if (args[i].short_name) {
-		count += fprintf (stderr, "-%c", args[i].short_name);
-		print_arg (buf, sizeof(buf), 0, 0, &args[i]);
-		count += fprintf(stderr, "%s", buf);
-	    }
-	    if (args[i].short_name && args[i].long_name)
-		count += fprintf (stderr, ", ");
-	    if (args[i].long_name) {
-		count += fprintf (stderr, "--");
-		if (args[i].type == arg_negative_flag)
-		    count += fprintf (stderr, "no-");
-		count += fprintf (stderr, "%s", args[i].long_name);
-		print_arg (buf, sizeof(buf), 0, 1, &args[i]);
-		count += fprintf(stderr, "%s", buf);
-	    }
-	    while(count++ <= max_len)
-		putc (' ', stderr);
-	    fprintf (stderr, "%s\n", args[i].help);
-	}
-    }
-}
-
-static void
-add_string(getarg_strings *s, char *value)
-{
-    s->strings = realloc(s->strings, (s->num_strings + 1) * sizeof(*s->strings));
-    s->strings[s->num_strings] = value;
-    s->num_strings++;
-}
-
-static int
-arg_match_long(struct getargs *args, size_t num_args,
-	       char *argv)
-{
-    int i;
-    char *optarg = NULL;
-    int negate = 0;
-    int partial_match = 0;
-    struct getargs *partial = NULL;
-    struct getargs *current = NULL;
-    int argv_len;
-    char *p;
-
-    argv_len = strlen(argv);
-    p = strchr (argv, '=');
-    if (p != NULL)
-	argv_len = p - argv;
-
-    for (i = 0; i < num_args; ++i) {
-	if(args[i].long_name) {
-	    int len = strlen(args[i].long_name);
-	    char *p = argv;
-	    int p_len = argv_len;
-	    negate = 0;
-
-	    for (;;) {
-		if (strncmp (args[i].long_name, p, p_len) == 0) {
-		    if(p_len == len)
-			current = &args[i];
-		    else {
-			++partial_match;
-			partial = &args[i];
-		    }
-		    optarg  = p + p_len;
-		} else if (ISFLAG(args[i]) && strncmp (p, "no-", 3) == 0) {
-		    negate = !negate;
-		    p += 3;
-		    p_len -= 3;
-		    continue;
-		}
-		break;
-	    }
-	    if (current)
-		break;
-	}
-    }
-    if (current == NULL) {
-	if (partial_match == 1)
-	    current = partial;
-	else
-	    return ARG_ERR_NO_MATCH;
-    }
-    
-    if(*optarg == '\0' && !ISFLAG(*current))
-	return ARG_ERR_NO_MATCH;
-    switch(current->type){
-    case arg_integer:
-    {
-	int tmp;
-	if(sscanf(optarg + 1, "%d", &tmp) != 1)
-	    return ARG_ERR_BAD_ARG;
-	*(int*)current->value = tmp;
-	return 0;
-    }
-    case arg_string:
-    {
-	*(char**)current->value = optarg + 1;
-	return 0;
-    }
-    case arg_strings:
-    {
-	add_string((getarg_strings*)current->value, optarg + 1);
-	return 0;
-    }
-    case arg_flag:
-    case arg_negative_flag:
-    {
-	int *flag = current->value;
-	if(*optarg == '\0' ||
-	   strcmp(optarg + 1, "yes") == 0 || 
-	   strcmp(optarg + 1, "true") == 0){
-	    *flag = !negate;
-	    return 0;
-	} else if (*optarg && strcmp(optarg + 1, "maybe") == 0) {
-	    *flag = rand() & 1;
-	} else {
-	    *flag = negate;
-	    return 0;
-	}
-	return ARG_ERR_BAD_ARG;
-    }
-    default:
-	abort ();
-    }
-}
-
-int
-getarg(struct getargs *args, size_t num_args, 
-       int argc, char **argv, int *optind)
-{
-    int i, j, k;
-    int ret = 0;
-
-    srand (time(NULL));
-    (*optind)++;
-    for(i = *optind; i < argc; i++) {
-	if(argv[i][0] != '-')
-	    break;
-	if(argv[i][1] == '-'){
-	    if(argv[i][2] == 0){
-		i++;
-		break;
-	    }
-	    ret = arg_match_long (args, num_args, argv[i] + 2);
-	    if(ret)
-		return ret;
-	}else{
-	    for(j = 1; argv[i][j]; j++) {
-		for(k = 0; k < num_args; k++) {
-		    char *optarg;
-		    if(args[k].short_name == 0)
-			continue;
-		    if(argv[i][j] == args[k].short_name){
-			if(args[k].type == arg_flag){
-			    *(int*)args[k].value = 1;
-			    break;
-			}
-			if(args[k].type == arg_negative_flag){
-			    *(int*)args[k].value = 0;
-			    break;
-			}
-			if(argv[i][j + 1])
-			    optarg = &argv[i][j + 1];
-			else{
-			    i++;
-			    optarg = argv[i];
-			}
-			if(optarg == NULL)
-			    return ARG_ERR_NO_ARG;
-			if(args[k].type == arg_integer){
-			    int tmp;
-			    if(sscanf(optarg, "%d", &tmp) != 1)
-				return ARG_ERR_BAD_ARG;
-			    *(int*)args[k].value = tmp;
-			    goto out;
-			}else if(args[k].type == arg_string){
-			    *(char**)args[k].value = optarg;
-			    goto out;
-			}else if(args[k].type == arg_strings){
-			    add_string((getarg_strings*)args[k].value, optarg);
-			    goto out;
-			}
-			return ARG_ERR_BAD_ARG;
-		    }
-			
-		}
-		if (k == num_args)
-		    return ARG_ERR_NO_MATCH;
-	    }
-	out:;
-	}
-    }
-    *optind = i;
-    return 0;
-}
-
-#if TEST
-int foo_flag = 2;
-int flag1 = 0;
-int flag2 = 0;
-int bar_int;
-char *baz_string;
-
-struct getargs args[] = {
-    { NULL, '1', arg_flag, &flag1, "one", NULL },
-    { NULL, '2', arg_flag, &flag2, "two", NULL },
-    { "foo", 'f', arg_negative_flag, &foo_flag, "foo", NULL },
-    { "bar", 'b', arg_integer, &bar_int, "bar", "seconds"},
-    { "baz", 'x', arg_string, &baz_string, "baz", "name" },
-};
-
-int main(int argc, char **argv)
-{
-    int optind = 0;
-    while(getarg(args, 5, argc, argv, &optind))
-	printf("Bad arg: %s\n", argv[optind]);
-    printf("flag1 = %d\n", flag1);  
-    printf("flag2 = %d\n", flag2);  
-    printf("foo_flag = %d\n", foo_flag);  
-    printf("bar_int = %d\n", bar_int);
-    printf("baz_flag = %s\n", baz_string);
-    arg_printusage (args, 5, argv[0], "nothing here");
-}
-#endif
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/com_err/getarg.h
--- a/head/contrib/com_err/getarg.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,76 +0,0 @@
-/*
- * Copyright (c) 1997 Kungliga Tekniska Högskolan
- * (Royal Institute of Technology, Stockholm, Sweden). 
- * All rights reserved. 
- *
- * Redistribution and use in source and binary forms, with or without 
- * modification, are permitted provided that the following conditions 
- * are met: 
- *
- * 1. Redistributions of source code must retain the above copyright 
- *    notice, this list of conditions and the following disclaimer. 
- *
- * 2. Redistributions in binary form must reproduce the above copyright 
- *    notice, this list of conditions and the following disclaimer in the 
- *    documentation and/or other materials provided with the distribution. 
- *
- * 3. All advertising materials mentioning features or use of this software 
- *    must display the following acknowledgement: 
- *      This product includes software developed by Kungliga Tekniska 
- *      Högskolan and its contributors. 
- *
- * 4. Neither the name of the Institute nor the names of its contributors 
- *    may be used to endorse or promote products derived from this software 
- *    without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
- * SUCH DAMAGE. 
- */
-
-/* $Id: getarg.h,v 1.5 1998/08/18 20:26:11 assar Exp $ */
-
-#ifndef __GETARG_H__
-#define __GETARG_H__
-
-#include <stddef.h>
-
-#define max(a,b) (((a)>(b))?(a):(b))
-
-struct getargs{
-    const char *long_name;
-    char short_name;
-    enum { arg_integer, arg_string, arg_flag, arg_negative_flag, arg_strings } type;
-    void *value;
-    const char *help;
-    const char *arg_help;
-};
-
-enum {
-    ARG_ERR_NO_MATCH  = 1,
-    ARG_ERR_BAD_ARG,
-    ARG_ERR_NO_ARG
-};
-
-typedef struct getarg_strings {
-    int num_strings;
-    char **strings;
-} getarg_strings;
-
-int getarg(struct getargs *args, size_t num_args, 
-	   int argc, char **argv, int *optind);
-
-void arg_printusage (struct getargs *args,
-		     size_t num_args,
-		     const char *progname,
-		     const char *extra_string);
-
-#endif /* __GETARG_H__ */
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/com_err/lex.c
--- a/head/contrib/com_err/lex.c	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1896 +0,0 @@
-
-#line 3 "lex.c"
-
-#define  YY_INT_ALIGNED short int
-
-/* A lexical scanner generated by flex */
-
-#define FLEX_SCANNER
-#define YY_FLEX_MAJOR_VERSION 2
-#define YY_FLEX_MINOR_VERSION 5
-#define YY_FLEX_SUBMINOR_VERSION 33
-#if YY_FLEX_SUBMINOR_VERSION > 0
-#define FLEX_BETA
-#endif
-
-/* First, we deal with  platform-specific or compiler-specific issues. */
-
-/* begin standard C headers. */
-#include <stdio.h>
-#include <string.h>
-#include <errno.h>
-#include <stdlib.h>
-
-/* end standard C headers. */
-
-/* flex integer type definitions */
-
-#ifndef FLEXINT_H
-#define FLEXINT_H
-
-/* C99 systems have <inttypes.h>. Non-C99 systems may or may not. */
-
-#if __STDC_VERSION__ >= 199901L
-
-/* C99 says to define __STDC_LIMIT_MACROS before including stdint.h,
- * if you want the limit (max/min) macros for int types. 
- */
-#ifndef __STDC_LIMIT_MACROS
-#define __STDC_LIMIT_MACROS 1
-#endif
-
-#include <inttypes.h>
-typedef int8_t flex_int8_t;
-typedef uint8_t flex_uint8_t;
-typedef int16_t flex_int16_t;
-typedef uint16_t flex_uint16_t;
-typedef int32_t flex_int32_t;
-typedef uint32_t flex_uint32_t;
-#else
-typedef signed char flex_int8_t;
-typedef short int flex_int16_t;
-typedef int flex_int32_t;
-typedef unsigned char flex_uint8_t; 
-typedef unsigned short int flex_uint16_t;
-typedef unsigned int flex_uint32_t;
-#endif /* ! C99 */
-
-/* Limits of integral types. */
-#ifndef INT8_MIN
-#define INT8_MIN               (-128)
-#endif
-#ifndef INT16_MIN
-#define INT16_MIN              (-32767-1)
-#endif
-#ifndef INT32_MIN
-#define INT32_MIN              (-2147483647-1)
-#endif
-#ifndef INT8_MAX
-#define INT8_MAX               (127)
-#endif
-#ifndef INT16_MAX
-#define INT16_MAX              (32767)
-#endif
-#ifndef INT32_MAX
-#define INT32_MAX              (2147483647)
-#endif
-#ifndef UINT8_MAX
-#define UINT8_MAX              (255U)
-#endif
-#ifndef UINT16_MAX
-#define UINT16_MAX             (65535U)
-#endif
-#ifndef UINT32_MAX
-#define UINT32_MAX             (4294967295U)
-#endif
-
-#endif /* ! FLEXINT_H */
-
-#ifdef __cplusplus
-
-/* The "const" storage-class-modifier is valid. */
-#define YY_USE_CONST
-
-#else	/* ! __cplusplus */
-
-#if __STDC__
-
-#define YY_USE_CONST
-
-#endif	/* __STDC__ */
-#endif	/* ! __cplusplus */
-
-#ifdef YY_USE_CONST
-#define yyconst const
-#else
-#define yyconst
-#endif
-
-/* Returned upon end-of-file. */
-#define YY_NULL 0
-
-/* Promotes a possibly negative, possibly signed char to an unsigned
- * integer for use as an array index.  If the signed char is negative,
- * we want to instead treat it as an 8-bit unsigned char, hence the
- * double cast.
- */
-#define YY_SC_TO_UI(c) ((unsigned int) (unsigned char) c)
-
-/* Enter a start condition.  This macro really ought to take a parameter,
- * but we do it the disgusting crufty way forced on us by the ()-less
- * definition of BEGIN.
- */
-#define BEGIN (yy_start) = 1 + 2 *
-
-/* Translate the current start state into a value that can be later handed
- * to BEGIN to return to the state.  The YYSTATE alias is for lex
- * compatibility.
- */
-#define YY_START (((yy_start) - 1) / 2)
-#define YYSTATE YY_START
-
-/* Action number for EOF rule of a given start state. */
-#define YY_STATE_EOF(state) (YY_END_OF_BUFFER + state + 1)
-
-/* Special action meaning "start processing a new file". */
-#define YY_NEW_FILE yyrestart(yyin  )
-
-#define YY_END_OF_BUFFER_CHAR 0
-
-/* Size of default input buffer. */
-#ifndef YY_BUF_SIZE
-#define YY_BUF_SIZE 16384
-#endif
-
-/* The state buf must be large enough to hold one state per character in the main buffer.
- */
-#define YY_STATE_BUF_SIZE   ((YY_BUF_SIZE + 2) * sizeof(yy_state_type))
-
-#ifndef YY_TYPEDEF_YY_BUFFER_STATE
-#define YY_TYPEDEF_YY_BUFFER_STATE
-typedef struct yy_buffer_state *YY_BUFFER_STATE;
-#endif
-
-extern int yyleng;
-
-extern FILE *yyin, *yyout;
-
-#define EOB_ACT_CONTINUE_SCAN 0
-#define EOB_ACT_END_OF_FILE 1
-#define EOB_ACT_LAST_MATCH 2
-
-    #define YY_LESS_LINENO(n)
-    
-/* Return all but the first "n" matched characters back to the input stream. */
-#define yyless(n) \
-	do \
-		{ \
-		/* Undo effects of setting up yytext. */ \
-        int yyless_macro_arg = (n); \
-        YY_LESS_LINENO(yyless_macro_arg);\
-		*yy_cp = (yy_hold_char); \
-		YY_RESTORE_YY_MORE_OFFSET \
-		(yy_c_buf_p) = yy_cp = yy_bp + yyless_macro_arg - YY_MORE_ADJ; \
-		YY_DO_BEFORE_ACTION; /* set up yytext again */ \
-		} \
-	while ( 0 )
-
-#define unput(c) yyunput( c, (yytext_ptr)  )
-
-/* The following is because we cannot portably get our hands on size_t
- * (without autoconf's help, which isn't available because we want
- * flex-generated scanners to compile on their own).
- */
-
-#ifndef YY_TYPEDEF_YY_SIZE_T
-#define YY_TYPEDEF_YY_SIZE_T
-typedef unsigned int yy_size_t;
-#endif
-
-#ifndef YY_STRUCT_YY_BUFFER_STATE
-#define YY_STRUCT_YY_BUFFER_STATE
-struct yy_buffer_state
-	{
-	FILE *yy_input_file;
-
-	char *yy_ch_buf;		/* input buffer */
-	char *yy_buf_pos;		/* current position in input buffer */
-
-	/* Size of input buffer in bytes, not including room for EOB
-	 * characters.
-	 */
-	yy_size_t yy_buf_size;
-
-	/* Number of characters read into yy_ch_buf, not including EOB
-	 * characters.
-	 */
-	int yy_n_chars;
-
-	/* Whether we "own" the buffer - i.e., we know we created it,
-	 * and can realloc() it to grow it, and should free() it to
-	 * delete it.
-	 */
-	int yy_is_our_buffer;
-
-	/* Whether this is an "interactive" input source; if so, and
-	 * if we're using stdio for input, then we want to use getc()
-	 * instead of fread(), to make sure we stop fetching input after
-	 * each newline.
-	 */
-	int yy_is_interactive;
-
-	/* Whether we're considered to be at the beginning of a line.
-	 * If so, '^' rules will be active on the next match, otherwise
-	 * not.
-	 */
-	int yy_at_bol;
-
-    int yy_bs_lineno; /**< The line count. */
-    int yy_bs_column; /**< The column count. */
-    
-	/* Whether to try to fill the input buffer when we reach the
-	 * end of it.
-	 */
-	int yy_fill_buffer;
-
-	int yy_buffer_status;
-
-#define YY_BUFFER_NEW 0
-#define YY_BUFFER_NORMAL 1
-	/* When an EOF's been seen but there's still some text to process
-	 * then we mark the buffer as YY_EOF_PENDING, to indicate that we
-	 * shouldn't try reading from the input source any more.  We might
-	 * still have a bunch of tokens to match, though, because of
-	 * possible backing-up.
-	 *
-	 * When we actually see the EOF, we change the status to "new"
-	 * (via yyrestart()), so that the user can continue scanning by
-	 * just pointing yyin at a new input file.
-	 */
-#define YY_BUFFER_EOF_PENDING 2
-
-	};
-#endif /* !YY_STRUCT_YY_BUFFER_STATE */
-
-/* Stack of input buffers. */
-static size_t yy_buffer_stack_top = 0; /**< index of top of stack. */
-static size_t yy_buffer_stack_max = 0; /**< capacity of stack. */
-static YY_BUFFER_STATE * yy_buffer_stack = 0; /**< Stack as an array. */
-
-/* We provide macros for accessing buffer states in case in the
- * future we want to put the buffer states in a more general
- * "scanner state".
- *
- * Returns the top of the stack, or NULL.
- */
-#define YY_CURRENT_BUFFER ( (yy_buffer_stack) \
-                          ? (yy_buffer_stack)[(yy_buffer_stack_top)] \
-                          : NULL)
-
-/* Same as previous macro, but useful when we know that the buffer stack is not
- * NULL or when we need an lvalue. For internal use only.
- */
-#define YY_CURRENT_BUFFER_LVALUE (yy_buffer_stack)[(yy_buffer_stack_top)]
-
-/* yy_hold_char holds the character lost when yytext is formed. */
-static char yy_hold_char;
-static int yy_n_chars;		/* number of characters read into yy_ch_buf */
-int yyleng;
-
-/* Points to current character in buffer. */
-static char *yy_c_buf_p = (char *) 0;
-static int yy_init = 0;		/* whether we need to initialize */
-static int yy_start = 0;	/* start state number */
-
-/* Flag which is used to allow yywrap()'s to do buffer switches
- * instead of setting up a fresh yyin.  A bit of a hack ...
- */
-static int yy_did_buffer_switch_on_eof;
-
-void yyrestart (FILE *input_file  );
-void yy_switch_to_buffer (YY_BUFFER_STATE new_buffer  );
-YY_BUFFER_STATE yy_create_buffer (FILE *file,int size  );
-void yy_delete_buffer (YY_BUFFER_STATE b  );
-void yy_flush_buffer (YY_BUFFER_STATE b  );
-void yypush_buffer_state (YY_BUFFER_STATE new_buffer  );
-void yypop_buffer_state (void );
-
-static void yyensure_buffer_stack (void );
-static void yy_load_buffer_state (void );
-static void yy_init_buffer (YY_BUFFER_STATE b,FILE *file  );
-
-#define YY_FLUSH_BUFFER yy_flush_buffer(YY_CURRENT_BUFFER )
-
-YY_BUFFER_STATE yy_scan_buffer (char *base,yy_size_t size  );
-YY_BUFFER_STATE yy_scan_string (yyconst char *yy_str  );
-YY_BUFFER_STATE yy_scan_bytes (yyconst char *bytes,int len  );
-
-void *yyalloc (yy_size_t  );
-void *yyrealloc (void *,yy_size_t  );
-void yyfree (void *  );
-
-#define yy_new_buffer yy_create_buffer
-
-#define yy_set_interactive(is_interactive) \
-	{ \
-	if ( ! YY_CURRENT_BUFFER ){ \
-        yyensure_buffer_stack (); \
-		YY_CURRENT_BUFFER_LVALUE =    \
-            yy_create_buffer(yyin,YY_BUF_SIZE ); \
-	} \
-	YY_CURRENT_BUFFER_LVALUE->yy_is_interactive = is_interactive; \
-	}
-
-#define yy_set_bol(at_bol) \
-	{ \
-	if ( ! YY_CURRENT_BUFFER ){\
-        yyensure_buffer_stack (); \
-		YY_CURRENT_BUFFER_LVALUE =    \
-            yy_create_buffer(yyin,YY_BUF_SIZE ); \
-	} \
-	YY_CURRENT_BUFFER_LVALUE->yy_at_bol = at_bol; \
-	}
-
-#define YY_AT_BOL() (YY_CURRENT_BUFFER_LVALUE->yy_at_bol)
-
-/* Begin user sect3 */
-
-typedef unsigned char YY_CHAR;
-
-FILE *yyin = (FILE *) 0, *yyout = (FILE *) 0;
-
-typedef int yy_state_type;
-
-extern int yylineno;
-
-int yylineno = 1;
-
-extern char *yytext;
-#define yytext_ptr yytext
-
-static yy_state_type yy_get_previous_state (void );
-static yy_state_type yy_try_NUL_trans (yy_state_type current_state  );
-static int yy_get_next_buffer (void );
-static void yy_fatal_error (yyconst char msg[]  );
-
-/* Done after the current pattern has been matched and before the
- * corresponding action - sets up yytext.
- */
-#define YY_DO_BEFORE_ACTION \
-	(yytext_ptr) = yy_bp; \
-	yyleng = (size_t) (yy_cp - yy_bp); \
-	(yy_hold_char) = *yy_cp; \
-	*yy_cp = '\0'; \
-	(yy_c_buf_p) = yy_cp;
-
-#define YY_NUM_RULES 16
-#define YY_END_OF_BUFFER 17
-/* This struct is not used in this scanner,
-   but its presence is necessary. */
-struct yy_trans_info
-	{
-	flex_int32_t yy_verify;
-	flex_int32_t yy_nxt;
-	};
-static yyconst flex_int16_t yy_accept[46] =
-    {   0,
-        0,    0,   17,   15,   11,   12,   13,   10,    9,   14,
-       14,   14,   14,   10,    9,   14,    3,   14,   14,    1,
-        7,   14,   14,    8,   14,   14,   14,   14,   14,   14,
-       14,    6,   14,   14,    5,   14,   14,   14,   14,   14,
-       14,    4,   14,    2,    0
-    } ;
-
-static yyconst flex_int32_t yy_ec[256] =
-    {   0,
-        1,    1,    1,    1,    1,    1,    1,    1,    2,    3,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    2,    1,    4,    5,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    6,    6,    6,
-        6,    6,    6,    6,    6,    6,    6,    1,    1,    1,
-        1,    1,    1,    1,    7,    7,    7,    7,    7,    7,
-        7,    7,    7,    7,    7,    7,    7,    7,    7,    7,
-        7,    7,    7,    7,    7,    7,    7,    7,    7,    7,
-        1,    1,    1,    1,    8,    1,    9,   10,   11,   12,
-
-       13,   14,    7,    7,   15,    7,    7,   16,    7,   17,
-       18,   19,    7,   20,    7,   21,    7,    7,    7,   22,
-        7,    7,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1
-    } ;
-
-static yyconst flex_int32_t yy_meta[23] =
-    {   0,
-        1,    1,    2,    1,    1,    3,    3,    3,    3,    3,
-        3,    3,    3,    3,    3,    3,    3,    3,    3,    3,
-        3,    3
-    } ;
-
-static yyconst flex_int16_t yy_base[48] =
-    {   0,
-        0,    0,   56,   57,   57,   57,   57,    0,   49,    0,
-       12,   13,   34,    0,   47,    0,    0,   40,   31,    0,
-        0,   38,   36,    0,   30,   34,   32,   25,   22,   28,
-       34,    0,   19,   13,    0,   22,   30,   26,   26,   18,
-       12,    0,   14,    0,   57,   34,   23
-    } ;
-
-static yyconst flex_int16_t yy_def[48] =
-    {   0,
-       45,    1,   45,   45,   45,   45,   45,   46,   47,   47,
-       47,   47,   47,   46,   47,   47,   47,   47,   47,   47,
-       47,   47,   47,   47,   47,   47,   47,   47,   47,   47,
-       47,   47,   47,   47,   47,   47,   47,   47,   47,   47,
-       47,   47,   47,   47,    0,   45,   45
-    } ;
-
-static yyconst flex_int16_t yy_nxt[80] =
-    {   0,
-        4,    5,    6,    7,    8,    9,   10,   10,   10,   10,
-       10,   10,   11,   10,   12,   10,   10,   10,   13,   10,
-       10,   10,   17,   36,   21,   16,   44,   43,   18,   22,
-       42,   19,   20,   37,   14,   41,   14,   40,   39,   38,
-       35,   34,   33,   32,   31,   30,   29,   28,   27,   26,
-       25,   24,   15,   23,   15,   45,    3,   45,   45,   45,
-       45,   45,   45,   45,   45,   45,   45,   45,   45,   45,
-       45,   45,   45,   45,   45,   45,   45,   45,   45
-    } ;
-
-static yyconst flex_int16_t yy_chk[80] =
-    {   0,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
-        1,    1,   11,   34,   12,   47,   43,   41,   11,   12,
-       40,   11,   11,   34,   46,   39,   46,   38,   37,   36,
-       33,   31,   30,   29,   28,   27,   26,   25,   23,   22,
-       19,   18,   15,   13,    9,    3,   45,   45,   45,   45,
-       45,   45,   45,   45,   45,   45,   45,   45,   45,   45,
-       45,   45,   45,   45,   45,   45,   45,   45,   45
-    } ;
-
-static yy_state_type yy_last_accepting_state;
-static char *yy_last_accepting_cpos;
-
-extern int yy_flex_debug;
-int yy_flex_debug = 0;
-
-/* The intent behind this definition is that it'll catch
- * any uses of REJECT which flex missed.
- */
-#define REJECT reject_used_but_not_detected
-#define yymore() yymore_used_but_not_detected
-#define YY_MORE_ADJ 0
-#define YY_RESTORE_YY_MORE_OFFSET
-char *yytext;
-#line 1 "lex.l"
-#line 2 "lex.l"
-/*
- * Copyright (c) 1998 - 2000 Kungliga Tekniska Högskolan
- * (Royal Institute of Technology, Stockholm, Sweden). 
- * All rights reserved. 
- *
- * Redistribution and use in source and binary forms, with or without 
- * modification, are permitted provided that the following conditions 
- * are met: 
- *
- * 1. Redistributions of source code must retain the above copyright 
- *    notice, this list of conditions and the following disclaimer. 
- *
- * 2. Redistributions in binary form must reproduce the above copyright 
- *    notice, this list of conditions and the following disclaimer in the 
- *    documentation and/or other materials provided with the distribution. 
- *
- * 3. Neither the name of the Institute nor the names of its contributors 
- *    may be used to endorse or promote products derived from this software 
- *    without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
- * SUCH DAMAGE. 
- */
-
-/*
- * This is to handle the definition of this symbol in some AIX
- * headers, which will conflict with the definition that lex will
- * generate for it.  It's only a problem for AIX lex.
- */
-
-#undef ECHO
-
-#include "compile_et.h"
-#include "parse.h"
-#include "lex.h"
-
-RCSID("$Id: lex.l 15143 2005-05-16 08:52:54Z lha $");
-
-static unsigned lineno = 1;
-static int getstring(void);
-
-#define YY_NO_UNPUT
-
-#undef ECHO
-
-#line 536 "lex.c"
-
-#define INITIAL 0
-
-#ifndef YY_NO_UNISTD_H
-/* Special case for "unistd.h", since it is non-ANSI. We include it way
- * down here because we want the user's section 1 to have been scanned first.
- * The user has a chance to override it with an option.
- */
-#include <unistd.h>
-#endif
-
-#ifndef YY_EXTRA_TYPE
-#define YY_EXTRA_TYPE void *
-#endif
-
-static int yy_init_globals (void );
-
-/* Macros after this point can all be overridden by user definitions in
- * section 1.
- */
-
-#ifndef YY_SKIP_YYWRAP
-#ifdef __cplusplus
-extern "C" int yywrap (void );
-#else
-extern int yywrap (void );
-#endif
-#endif
-
-    static void yyunput (int c,char *buf_ptr  );
-    
-#ifndef yytext_ptr
-static void yy_flex_strncpy (char *,yyconst char *,int );
-#endif
-
-#ifdef YY_NEED_STRLEN
-static int yy_flex_strlen (yyconst char * );
-#endif
-
-#ifndef YY_NO_INPUT
-
-#ifdef __cplusplus
-static int yyinput (void );
-#else
-static int input (void );
-#endif
-
-#endif
-
-/* Amount of stuff to slurp up with each read. */
-#ifndef YY_READ_BUF_SIZE
-#define YY_READ_BUF_SIZE 8192
-#endif
-
-/* Copy whatever the last rule matched to the standard output. */
-#ifndef ECHO
-/* This used to be an fputs(), but since the string might contain NUL's,
- * we now use fwrite().
- */
-#define ECHO (void) fwrite( yytext, yyleng, 1, yyout )
-#endif
-
-/* Gets input and stuffs it into "buf".  number of characters read, or YY_NULL,
- * is returned in "result".
- */
-#ifndef YY_INPUT
-#define YY_INPUT(buf,result,max_size) \
-	if ( YY_CURRENT_BUFFER_LVALUE->yy_is_interactive ) \
-		{ \
-		int c = '*'; \
-		size_t n; \
-		for ( n = 0; n < max_size && \
-			     (c = getc( yyin )) != EOF && c != '\n'; ++n ) \
-			buf[n] = (char) c; \
-		if ( c == '\n' ) \
-			buf[n++] = (char) c; \
-		if ( c == EOF && ferror( yyin ) ) \
-			YY_FATAL_ERROR( "input in flex scanner failed" ); \
-		result = n; \
-		} \
-	else \
-		{ \
-		errno=0; \
-		while ( (result = fread(buf, 1, max_size, yyin))==0 && ferror(yyin)) \
-			{ \
-			if( errno != EINTR) \
-				{ \
-				YY_FATAL_ERROR( "input in flex scanner failed" ); \
-				break; \
-				} \
-			errno=0; \
-			clearerr(yyin); \
-			} \
-		}\
-\
-
-#endif
-
-/* No semi-colon after return; correct usage is to write "yyterminate();" -
- * we don't want an extra ';' after the "return" because that will cause
- * some compilers to complain about unreachable statements.
- */
-#ifndef yyterminate
-#define yyterminate() return YY_NULL
-#endif
-
-/* Number of entries by which start-condition stack grows. */
-#ifndef YY_START_STACK_INCR
-#define YY_START_STACK_INCR 25
-#endif
-
-/* Report a fatal error. */
-#ifndef YY_FATAL_ERROR
-#define YY_FATAL_ERROR(msg) yy_fatal_error( msg )
-#endif
-
-/* end tables serialization structures and prototypes */
-
-/* Default declaration of generated scanner - a define so the user can
- * easily add parameters.
- */
-#ifndef YY_DECL
-#define YY_DECL_IS_OURS 1
-
-extern int yylex (void);
-
-#define YY_DECL int yylex (void)
-#endif /* !YY_DECL */
-
-/* Code executed at the beginning of each rule, after yytext and yyleng
- * have been set up.
- */
-#ifndef YY_USER_ACTION
-#define YY_USER_ACTION
-#endif
-
-/* Code executed at the end of each rule. */
-#ifndef YY_BREAK
-#define YY_BREAK break;
-#endif
-
-#define YY_RULE_SETUP \
-	YY_USER_ACTION
-
-/** The main scanner function which does all the work.
- */
-YY_DECL
-{
-	register yy_state_type yy_current_state;
-	register char *yy_cp, *yy_bp;
-	register int yy_act;
-    
-#line 59 "lex.l"
-
-#line 691 "lex.c"
-
-	if ( !(yy_init) )
-		{
-		(yy_init) = 1;
-
-#ifdef YY_USER_INIT
-		YY_USER_INIT;
-#endif
-
-		if ( ! (yy_start) )
-			(yy_start) = 1;	/* first start state */
-
-		if ( ! yyin )
-			yyin = stdin;
-
-		if ( ! yyout )
-			yyout = stdout;
-
-		if ( ! YY_CURRENT_BUFFER ) {
-			yyensure_buffer_stack ();
-			YY_CURRENT_BUFFER_LVALUE =
-				yy_create_buffer(yyin,YY_BUF_SIZE );
-		}
-
-		yy_load_buffer_state( );
-		}
-
-	while ( 1 )		/* loops until end-of-file is reached */
-		{
-		yy_cp = (yy_c_buf_p);
-
-		/* Support of yytext. */
-		*yy_cp = (yy_hold_char);
-
-		/* yy_bp points to the position in yy_ch_buf of the start of
-		 * the current run.
-		 */
-		yy_bp = yy_cp;
-
-		yy_current_state = (yy_start);
-yy_match:
-		do
-			{
-			register YY_CHAR yy_c = yy_ec[YY_SC_TO_UI(*yy_cp)];
-			if ( yy_accept[yy_current_state] )
-				{
-				(yy_last_accepting_state) = yy_current_state;
-				(yy_last_accepting_cpos) = yy_cp;
-				}
-			while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
-				{
-				yy_current_state = (int) yy_def[yy_current_state];
-				if ( yy_current_state >= 46 )
-					yy_c = yy_meta[(unsigned int) yy_c];
-				}
-			yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
-			++yy_cp;
-			}
-		while ( yy_base[yy_current_state] != 57 );
-
-yy_find_action:
-		yy_act = yy_accept[yy_current_state];
-		if ( yy_act == 0 )
-			{ /* have to back up */
-			yy_cp = (yy_last_accepting_cpos);
-			yy_current_state = (yy_last_accepting_state);
-			yy_act = yy_accept[yy_current_state];
-			}
-
-		YY_DO_BEFORE_ACTION;
-
-do_action:	/* This label is used only to access EOF actions. */
-
-		switch ( yy_act )
-	{ /* beginning of action switch */
-			case 0: /* must back up */
-			/* undo the effects of YY_DO_BEFORE_ACTION */
-			*yy_cp = (yy_hold_char);
-			yy_cp = (yy_last_accepting_cpos);
-			yy_current_state = (yy_last_accepting_state);
-			goto yy_find_action;
-
-case 1:
-YY_RULE_SETUP
-#line 60 "lex.l"
-{ return ET; }
-	YY_BREAK
-case 2:
-YY_RULE_SETUP
-#line 61 "lex.l"
-{ return ET; }
-	YY_BREAK
-case 3:
-YY_RULE_SETUP
-#line 62 "lex.l"
-{ return EC; }
-	YY_BREAK
-case 4:
-YY_RULE_SETUP
-#line 63 "lex.l"
-{ return EC; }
-	YY_BREAK
-case 5:
-YY_RULE_SETUP
-#line 64 "lex.l"
-{ return PREFIX; }
-	YY_BREAK
-case 6:
-YY_RULE_SETUP
-#line 65 "lex.l"
-{ return INDEX; }
-	YY_BREAK
-case 7:
-YY_RULE_SETUP
-#line 66 "lex.l"
-{ return ID; }
-	YY_BREAK
-case 8:
-YY_RULE_SETUP
-#line 67 "lex.l"
-{ return END; }
-	YY_BREAK
-case 9:
-YY_RULE_SETUP
-#line 68 "lex.l"
-{ yylval.number = atoi(yytext); return NUMBER; }
-	YY_BREAK
-case 10:
-YY_RULE_SETUP
-#line 69 "lex.l"
-;
-	YY_BREAK
-case 11:
-YY_RULE_SETUP
-#line 70 "lex.l"
-;
-	YY_BREAK
-case 12:
-/* rule 12 can match eol */
-YY_RULE_SETUP
-#line 71 "lex.l"
-{ lineno++; }
-	YY_BREAK
-case 13:
-YY_RULE_SETUP
-#line 72 "lex.l"
-{ return getstring(); }
-	YY_BREAK
-case 14:
-YY_RULE_SETUP
-#line 73 "lex.l"
-{ yylval.string = strdup(yytext); return STRING; }
-	YY_BREAK
-case 15:
-YY_RULE_SETUP
-#line 74 "lex.l"
-{ return *yytext; }
-	YY_BREAK
-case 16:
-YY_RULE_SETUP
-#line 75 "lex.l"
-ECHO;
-	YY_BREAK
-#line 855 "lex.c"
-case YY_STATE_EOF(INITIAL):
-	yyterminate();
-
-	case YY_END_OF_BUFFER:
-		{
-		/* Amount of text matched not including the EOB char. */
-		int yy_amount_of_matched_text = (int) (yy_cp - (yytext_ptr)) - 1;
-
-		/* Undo the effects of YY_DO_BEFORE_ACTION. */
-		*yy_cp = (yy_hold_char);
-		YY_RESTORE_YY_MORE_OFFSET
-
-		if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_NEW )
-			{
-			/* We're scanning a new file or input source.  It's
-			 * possible that this happened because the user
-			 * just pointed yyin at a new source and called
-			 * yylex().  If so, then we have to assure
-			 * consistency between YY_CURRENT_BUFFER and our
-			 * globals.  Here is the right place to do so, because
-			 * this is the first action (other than possibly a
-			 * back-up) that will match for the new input source.
-			 */
-			(yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars;
-			YY_CURRENT_BUFFER_LVALUE->yy_input_file = yyin;
-			YY_CURRENT_BUFFER_LVALUE->yy_buffer_status = YY_BUFFER_NORMAL;
-			}
-
-		/* Note that here we test for yy_c_buf_p "<=" to the position
-		 * of the first EOB in the buffer, since yy_c_buf_p will
-		 * already have been incremented past the NUL character
-		 * (since all states make transitions on EOB to the
-		 * end-of-buffer state).  Contrast this with the test
-		 * in input().
-		 */
-		if ( (yy_c_buf_p) <= &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] )
-			{ /* This was really a NUL. */
-			yy_state_type yy_next_state;
-
-			(yy_c_buf_p) = (yytext_ptr) + yy_amount_of_matched_text;
-
-			yy_current_state = yy_get_previous_state(  );
-
-			/* Okay, we're now positioned to make the NUL
-			 * transition.  We couldn't have
-			 * yy_get_previous_state() go ahead and do it
-			 * for us because it doesn't know how to deal
-			 * with the possibility of jamming (and we don't
-			 * want to build jamming into it because then it
-			 * will run more slowly).
-			 */
-
-			yy_next_state = yy_try_NUL_trans( yy_current_state );
-
-			yy_bp = (yytext_ptr) + YY_MORE_ADJ;
-
-			if ( yy_next_state )
-				{
-				/* Consume the NUL. */
-				yy_cp = ++(yy_c_buf_p);
-				yy_current_state = yy_next_state;
-				goto yy_match;
-				}
-
-			else
-				{
-				yy_cp = (yy_c_buf_p);
-				goto yy_find_action;
-				}
-			}
-
-		else switch ( yy_get_next_buffer(  ) )
-			{
-			case EOB_ACT_END_OF_FILE:
-				{
-				(yy_did_buffer_switch_on_eof) = 0;
-
-				if ( yywrap( ) )
-					{
-					/* Note: because we've taken care in
-					 * yy_get_next_buffer() to have set up
-					 * yytext, we can now set up
-					 * yy_c_buf_p so that if some total
-					 * hoser (like flex itself) wants to
-					 * call the scanner after we return the
-					 * YY_NULL, it'll still work - another
-					 * YY_NULL will get returned.
-					 */
-					(yy_c_buf_p) = (yytext_ptr) + YY_MORE_ADJ;
-
-					yy_act = YY_STATE_EOF(YY_START);
-					goto do_action;
-					}
-
-				else
-					{
-					if ( ! (yy_did_buffer_switch_on_eof) )
-						YY_NEW_FILE;
-					}
-				break;
-				}
-
-			case EOB_ACT_CONTINUE_SCAN:
-				(yy_c_buf_p) =
-					(yytext_ptr) + yy_amount_of_matched_text;
-
-				yy_current_state = yy_get_previous_state(  );
-
-				yy_cp = (yy_c_buf_p);
-				yy_bp = (yytext_ptr) + YY_MORE_ADJ;
-				goto yy_match;
-
-			case EOB_ACT_LAST_MATCH:
-				(yy_c_buf_p) =
-				&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)];
-
-				yy_current_state = yy_get_previous_state(  );
-
-				yy_cp = (yy_c_buf_p);
-				yy_bp = (yytext_ptr) + YY_MORE_ADJ;
-				goto yy_find_action;
-			}
-		break;
-		}
-
-	default:
-		YY_FATAL_ERROR(
-			"fatal flex scanner internal error--no action found" );
-	} /* end of action switch */
-		} /* end of scanning one token */
-} /* end of yylex */
-
-/* yy_get_next_buffer - try to read in a new buffer
- *
- * Returns a code representing an action:
- *	EOB_ACT_LAST_MATCH -
- *	EOB_ACT_CONTINUE_SCAN - continue scanning from current position
- *	EOB_ACT_END_OF_FILE - end of file
- */
-static int yy_get_next_buffer (void)
-{
-    	register char *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf;
-	register char *source = (yytext_ptr);
-	register int number_to_move, i;
-	int ret_val;
-
-	if ( (yy_c_buf_p) > &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] )
-		YY_FATAL_ERROR(
-		"fatal flex scanner internal error--end of buffer missed" );
-
-	if ( YY_CURRENT_BUFFER_LVALUE->yy_fill_buffer == 0 )
-		{ /* Don't try to fill the buffer, so this is an EOF. */
-		if ( (yy_c_buf_p) - (yytext_ptr) - YY_MORE_ADJ == 1 )
-			{
-			/* We matched a single character, the EOB, so
-			 * treat this as a final EOF.
-			 */
-			return EOB_ACT_END_OF_FILE;
-			}
-
-		else
-			{
-			/* We matched some text prior to the EOB, first
-			 * process it.
-			 */
-			return EOB_ACT_LAST_MATCH;
-			}
-		}
-
-	/* Try to read more data. */
-
-	/* First move last chars to start of buffer. */
-	number_to_move = (int) ((yy_c_buf_p) - (yytext_ptr)) - 1;
-
-	for ( i = 0; i < number_to_move; ++i )
-		*(dest++) = *(source++);
-
-	if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_EOF_PENDING )
-		/* don't do the read, it's not guaranteed to return an EOF,
-		 * just force an EOF
-		 */
-		YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars) = 0;
-
-	else
-		{
-			int num_to_read =
-			YY_CURRENT_BUFFER_LVALUE->yy_buf_size - number_to_move - 1;
-
-		while ( num_to_read <= 0 )
-			{ /* Not enough room in the buffer - grow it. */
-
-			/* just a shorter name for the current buffer */
-			YY_BUFFER_STATE b = YY_CURRENT_BUFFER;
-
-			int yy_c_buf_p_offset =
-				(int) ((yy_c_buf_p) - b->yy_ch_buf);
-
-			if ( b->yy_is_our_buffer )
-				{
-				int new_size = b->yy_buf_size * 2;
-
-				if ( new_size <= 0 )
-					b->yy_buf_size += b->yy_buf_size / 8;
-				else
-					b->yy_buf_size *= 2;
-
-				b->yy_ch_buf = (char *)
-					/* Include room in for 2 EOB chars. */
-					yyrealloc((void *) b->yy_ch_buf,b->yy_buf_size + 2  );
-				}
-			else
-				/* Can't grow it, we don't own it. */
-				b->yy_ch_buf = 0;
-
-			if ( ! b->yy_ch_buf )
-				YY_FATAL_ERROR(
-				"fatal error - scanner input buffer overflow" );
-
-			(yy_c_buf_p) = &b->yy_ch_buf[yy_c_buf_p_offset];
-
-			num_to_read = YY_CURRENT_BUFFER_LVALUE->yy_buf_size -
-						number_to_move - 1;
-
-			}
-
-		if ( num_to_read > YY_READ_BUF_SIZE )
-			num_to_read = YY_READ_BUF_SIZE;
-
-		/* Read in more data. */
-		YY_INPUT( (&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move]),
-			(yy_n_chars), num_to_read );
-
-		YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
-		}
-
-	if ( (yy_n_chars) == 0 )
-		{
-		if ( number_to_move == YY_MORE_ADJ )
-			{
-			ret_val = EOB_ACT_END_OF_FILE;
-			yyrestart(yyin  );
-			}
-
-		else
-			{
-			ret_val = EOB_ACT_LAST_MATCH;
-			YY_CURRENT_BUFFER_LVALUE->yy_buffer_status =
-				YY_BUFFER_EOF_PENDING;
-			}
-		}
-
-	else
-		ret_val = EOB_ACT_CONTINUE_SCAN;
-
-	(yy_n_chars) += number_to_move;
-	YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] = YY_END_OF_BUFFER_CHAR;
-	YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] = YY_END_OF_BUFFER_CHAR;
-
-	(yytext_ptr) = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[0];
-
-	return ret_val;
-}
-
-/* yy_get_previous_state - get the state just before the EOB char was reached */
-
-    static yy_state_type yy_get_previous_state (void)
-{
-	register yy_state_type yy_current_state;
-	register char *yy_cp;
-    
-	yy_current_state = (yy_start);
-
-	for ( yy_cp = (yytext_ptr) + YY_MORE_ADJ; yy_cp < (yy_c_buf_p); ++yy_cp )
-		{
-		register YY_CHAR yy_c = (*yy_cp ? yy_ec[YY_SC_TO_UI(*yy_cp)] : 1);
-		if ( yy_accept[yy_current_state] )
-			{
-			(yy_last_accepting_state) = yy_current_state;
-			(yy_last_accepting_cpos) = yy_cp;
-			}
-		while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
-			{
-			yy_current_state = (int) yy_def[yy_current_state];
-			if ( yy_current_state >= 46 )
-				yy_c = yy_meta[(unsigned int) yy_c];
-			}
-		yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
-		}
-
-	return yy_current_state;
-}
-
-/* yy_try_NUL_trans - try to make a transition on the NUL character
- *
- * synopsis
- *	next_state = yy_try_NUL_trans( current_state );
- */
-    static yy_state_type yy_try_NUL_trans  (yy_state_type yy_current_state )
-{
-	register int yy_is_jam;
-    	register char *yy_cp = (yy_c_buf_p);
-
-	register YY_CHAR yy_c = 1;
-	if ( yy_accept[yy_current_state] )
-		{
-		(yy_last_accepting_state) = yy_current_state;
-		(yy_last_accepting_cpos) = yy_cp;
-		}
-	while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
-		{
-		yy_current_state = (int) yy_def[yy_current_state];
-		if ( yy_current_state >= 46 )
-			yy_c = yy_meta[(unsigned int) yy_c];
-		}
-	yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
-	yy_is_jam = (yy_current_state == 45);
-
-	return yy_is_jam ? 0 : yy_current_state;
-}
-
-    static void yyunput (int c, register char * yy_bp )
-{
-	register char *yy_cp;
-    
-    yy_cp = (yy_c_buf_p);
-
-	/* undo effects of setting up yytext */
-	*yy_cp = (yy_hold_char);
-
-	if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 )
-		{ /* need to shift things up to make room */
-		/* +2 for EOB chars. */
-		register int number_to_move = (yy_n_chars) + 2;
-		register char *dest = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[
-					YY_CURRENT_BUFFER_LVALUE->yy_buf_size + 2];
-		register char *source =
-				&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move];
-
-		while ( source > YY_CURRENT_BUFFER_LVALUE->yy_ch_buf )
-			*--dest = *--source;
-
-		yy_cp += (int) (dest - source);
-		yy_bp += (int) (dest - source);
-		YY_CURRENT_BUFFER_LVALUE->yy_n_chars =
-			(yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_buf_size;
-
-		if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 )
-			YY_FATAL_ERROR( "flex scanner push-back overflow" );
-		}
-
-	*--yy_cp = (char) c;
-
-	(yytext_ptr) = yy_bp;
-	(yy_hold_char) = *yy_cp;
-	(yy_c_buf_p) = yy_cp;
-}
-
-#ifndef YY_NO_INPUT
-#ifdef __cplusplus
-    static int yyinput (void)
-#else
-    static int input  (void)
-#endif
-
-{
-	int c;
-    
-	*(yy_c_buf_p) = (yy_hold_char);
-
-	if ( *(yy_c_buf_p) == YY_END_OF_BUFFER_CHAR )
-		{
-		/* yy_c_buf_p now points to the character we want to return.
-		 * If this occurs *before* the EOB characters, then it's a
-		 * valid NUL; if not, then we've hit the end of the buffer.
-		 */
-		if ( (yy_c_buf_p) < &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] )
-			/* This was really a NUL. */
-			*(yy_c_buf_p) = '\0';
-
-		else
-			{ /* need more input */
-			int offset = (yy_c_buf_p) - (yytext_ptr);
-			++(yy_c_buf_p);
-
-			switch ( yy_get_next_buffer(  ) )
-				{
-				case EOB_ACT_LAST_MATCH:
-					/* This happens because yy_g_n_b()
-					 * sees that we've accumulated a
-					 * token and flags that we need to
-					 * try matching the token before
-					 * proceeding.  But for input(),
-					 * there's no matching to consider.
-					 * So convert the EOB_ACT_LAST_MATCH
-					 * to EOB_ACT_END_OF_FILE.
-					 */
-
-					/* Reset buffer status. */
-					yyrestart(yyin );
-
-					/*FALLTHROUGH*/
-
-				case EOB_ACT_END_OF_FILE:
-					{
-					if ( yywrap( ) )
-						return 0;
-
-					if ( ! (yy_did_buffer_switch_on_eof) )
-						YY_NEW_FILE;
-#ifdef __cplusplus
-					return yyinput();
-#else
-					return input();
-#endif
-					}
-
-				case EOB_ACT_CONTINUE_SCAN:
-					(yy_c_buf_p) = (yytext_ptr) + offset;
-					break;
-				}
-			}
-		}
-
-	c = *(unsigned char *) (yy_c_buf_p);	/* cast for 8-bit char's */
-	*(yy_c_buf_p) = '\0';	/* preserve yytext */
-	(yy_hold_char) = *++(yy_c_buf_p);
-
-	return c;
-}
-#endif	/* ifndef YY_NO_INPUT */
-
-/** Immediately switch to a different input stream.
- * @param input_file A readable stream.
- * 
- * @note This function does not reset the start condition to @c INITIAL .
- */
-    void yyrestart  (FILE * input_file )
-{
-    
-	if ( ! YY_CURRENT_BUFFER ){
-        yyensure_buffer_stack ();
-		YY_CURRENT_BUFFER_LVALUE =
-            yy_create_buffer(yyin,YY_BUF_SIZE );
-	}
-
-	yy_init_buffer(YY_CURRENT_BUFFER,input_file );
-	yy_load_buffer_state( );
-}
-
-/** Switch to a different input buffer.
- * @param new_buffer The new input buffer.
- * 
- */
-    void yy_switch_to_buffer  (YY_BUFFER_STATE  new_buffer )
-{
-    
-	/* TODO. We should be able to replace this entire function body
-	 * with
-	 *		yypop_buffer_state();
-	 *		yypush_buffer_state(new_buffer);
-     */
-	yyensure_buffer_stack ();
-	if ( YY_CURRENT_BUFFER == new_buffer )
-		return;
-
-	if ( YY_CURRENT_BUFFER )
-		{
-		/* Flush out information for old buffer. */
-		*(yy_c_buf_p) = (yy_hold_char);
-		YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p);
-		YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
-		}
-
-	YY_CURRENT_BUFFER_LVALUE = new_buffer;
-	yy_load_buffer_state( );
-
-	/* We don't actually know whether we did this switch during
-	 * EOF (yywrap()) processing, but the only time this flag
-	 * is looked at is after yywrap() is called, so it's safe
-	 * to go ahead and always set it.
-	 */
-	(yy_did_buffer_switch_on_eof) = 1;
-}
-
-static void yy_load_buffer_state  (void)
-{
-    	(yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars;
-	(yytext_ptr) = (yy_c_buf_p) = YY_CURRENT_BUFFER_LVALUE->yy_buf_pos;
-	yyin = YY_CURRENT_BUFFER_LVALUE->yy_input_file;
-	(yy_hold_char) = *(yy_c_buf_p);
-}
-
-/** Allocate and initialize an input buffer state.
- * @param file A readable stream.
- * @param size The character buffer size in bytes. When in doubt, use @c YY_BUF_SIZE.
- * 
- * @return the allocated buffer state.
- */
-    YY_BUFFER_STATE yy_create_buffer  (FILE * file, int  size )
-{
-	YY_BUFFER_STATE b;
-    
-	b = (YY_BUFFER_STATE) yyalloc(sizeof( struct yy_buffer_state )  );
-	if ( ! b )
-		YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" );
-
-	b->yy_buf_size = size;
-
-	/* yy_ch_buf has to be 2 characters longer than the size given because
-	 * we need to put in 2 end-of-buffer characters.
-	 */
-	b->yy_ch_buf = (char *) yyalloc(b->yy_buf_size + 2  );
-	if ( ! b->yy_ch_buf )
-		YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" );
-
-	b->yy_is_our_buffer = 1;
-
-	yy_init_buffer(b,file );
-
-	return b;
-}
-
-/** Destroy the buffer.
- * @param b a buffer created with yy_create_buffer()
- * 
- */
-    void yy_delete_buffer (YY_BUFFER_STATE  b )
-{
-    
-	if ( ! b )
-		return;
-
-	if ( b == YY_CURRENT_BUFFER ) /* Not sure if we should pop here. */
-		YY_CURRENT_BUFFER_LVALUE = (YY_BUFFER_STATE) 0;
-
-	if ( b->yy_is_our_buffer )
-		yyfree((void *) b->yy_ch_buf  );
-
-	yyfree((void *) b  );
-}
-
-#ifndef __cplusplus
-extern int isatty (int );
-#endif /* __cplusplus */
-    
-/* Initializes or reinitializes a buffer.
- * This function is sometimes called more than once on the same buffer,
- * such as during a yyrestart() or at EOF.
- */
-    static void yy_init_buffer  (YY_BUFFER_STATE  b, FILE * file )
-
-{
-	int oerrno = errno;
-    
-	yy_flush_buffer(b );
-
-	b->yy_input_file = file;
-	b->yy_fill_buffer = 1;
-
-    /* If b is the current buffer, then yy_init_buffer was _probably_
-     * called from yyrestart() or through yy_get_next_buffer.
-     * In that case, we don't want to reset the lineno or column.
-     */
-    if (b != YY_CURRENT_BUFFER){
-        b->yy_bs_lineno = 1;
-        b->yy_bs_column = 0;
-    }
-
-        b->yy_is_interactive = file ? (isatty( fileno(file) ) > 0) : 0;
-    
-	errno = oerrno;
-}
-
-/** Discard all buffered characters. On the next scan, YY_INPUT will be called.
- * @param b the buffer state to be flushed, usually @c YY_CURRENT_BUFFER.
- * 
- */
-    void yy_flush_buffer (YY_BUFFER_STATE  b )
-{
-    	if ( ! b )
-		return;
-
-	b->yy_n_chars = 0;
-
-	/* We always need two end-of-buffer characters.  The first causes
-	 * a transition to the end-of-buffer state.  The second causes
-	 * a jam in that state.
-	 */
-	b->yy_ch_buf[0] = YY_END_OF_BUFFER_CHAR;
-	b->yy_ch_buf[1] = YY_END_OF_BUFFER_CHAR;
-
-	b->yy_buf_pos = &b->yy_ch_buf[0];
-
-	b->yy_at_bol = 1;
-	b->yy_buffer_status = YY_BUFFER_NEW;
-
-	if ( b == YY_CURRENT_BUFFER )
-		yy_load_buffer_state( );
-}
-
-/** Pushes the new state onto the stack. The new state becomes
- *  the current state. This function will allocate the stack
- *  if necessary.
- *  @param new_buffer The new state.
- *  
- */
-void yypush_buffer_state (YY_BUFFER_STATE new_buffer )
-{
-    	if (new_buffer == NULL)
-		return;
-
-	yyensure_buffer_stack();
-
-	/* This block is copied from yy_switch_to_buffer. */
-	if ( YY_CURRENT_BUFFER )
-		{
-		/* Flush out information for old buffer. */
-		*(yy_c_buf_p) = (yy_hold_char);
-		YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p);
-		YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
-		}
-
-	/* Only push if top exists. Otherwise, replace top. */
-	if (YY_CURRENT_BUFFER)
-		(yy_buffer_stack_top)++;
-	YY_CURRENT_BUFFER_LVALUE = new_buffer;
-
-	/* copied from yy_switch_to_buffer. */
-	yy_load_buffer_state( );
-	(yy_did_buffer_switch_on_eof) = 1;
-}
-
-/** Removes and deletes the top of the stack, if present.
- *  The next element becomes the new top.
- *  
- */
-void yypop_buffer_state (void)
-{
-    	if (!YY_CURRENT_BUFFER)
-		return;
-
-	yy_delete_buffer(YY_CURRENT_BUFFER );
-	YY_CURRENT_BUFFER_LVALUE = NULL;
-	if ((yy_buffer_stack_top) > 0)
-		--(yy_buffer_stack_top);
-
-	if (YY_CURRENT_BUFFER) {
-		yy_load_buffer_state( );
-		(yy_did_buffer_switch_on_eof) = 1;
-	}
-}
-
-/* Allocates the stack if it does not exist.
- *  Guarantees space for at least one push.
- */
-static void yyensure_buffer_stack (void)
-{
-	int num_to_alloc;
-    
-	if (!(yy_buffer_stack)) {
-
-		/* First allocation is just for 2 elements, since we don't know if this
-		 * scanner will even need a stack. We use 2 instead of 1 to avoid an
-		 * immediate realloc on the next call.
-         */
-		num_to_alloc = 1;
-		(yy_buffer_stack) = (struct yy_buffer_state**)yyalloc
-								(num_to_alloc * sizeof(struct yy_buffer_state*)
-								);
-		
-		memset((yy_buffer_stack), 0, num_to_alloc * sizeof(struct yy_buffer_state*));
-				
-		(yy_buffer_stack_max) = num_to_alloc;
-		(yy_buffer_stack_top) = 0;
-		return;
-	}
-
-	if ((yy_buffer_stack_top) >= ((yy_buffer_stack_max)) - 1){
-
-		/* Increase the buffer to prepare for a possible push. */
-		int grow_size = 8 /* arbitrary grow size */;
-
-		num_to_alloc = (yy_buffer_stack_max) + grow_size;
-		(yy_buffer_stack) = (struct yy_buffer_state**)yyrealloc
-								((yy_buffer_stack),
-								num_to_alloc * sizeof(struct yy_buffer_state*)
-								);
-
-		/* zero only the new slots.*/
-		memset((yy_buffer_stack) + (yy_buffer_stack_max), 0, grow_size * sizeof(struct yy_buffer_state*));
-		(yy_buffer_stack_max) = num_to_alloc;
-	}
-}
-
-/** Setup the input buffer state to scan directly from a user-specified character buffer.
- * @param base the character buffer
- * @param size the size in bytes of the character buffer
- * 
- * @return the newly allocated buffer state object. 
- */
-YY_BUFFER_STATE yy_scan_buffer  (char * base, yy_size_t  size )
-{
-	YY_BUFFER_STATE b;
-    
-	if ( size < 2 ||
-	     base[size-2] != YY_END_OF_BUFFER_CHAR ||
-	     base[size-1] != YY_END_OF_BUFFER_CHAR )
-		/* They forgot to leave room for the EOB's. */
-		return 0;
-
-	b = (YY_BUFFER_STATE) yyalloc(sizeof( struct yy_buffer_state )  );
-	if ( ! b )
-		YY_FATAL_ERROR( "out of dynamic memory in yy_scan_buffer()" );
-
-	b->yy_buf_size = size - 2;	/* "- 2" to take care of EOB's */
-	b->yy_buf_pos = b->yy_ch_buf = base;
-	b->yy_is_our_buffer = 0;
-	b->yy_input_file = 0;
-	b->yy_n_chars = b->yy_buf_size;
-	b->yy_is_interactive = 0;
-	b->yy_at_bol = 1;
-	b->yy_fill_buffer = 0;
-	b->yy_buffer_status = YY_BUFFER_NEW;
-
-	yy_switch_to_buffer(b  );
-
-	return b;
-}
-
-/** Setup the input buffer state to scan a string. The next call to yylex() will
- * scan from a @e copy of @a str.
- * @param str a NUL-terminated string to scan
- * 
- * @return the newly allocated buffer state object.
- * @note If you want to scan bytes that may contain NUL values, then use
- *       yy_scan_bytes() instead.
- */
-YY_BUFFER_STATE yy_scan_string (yyconst char * yystr )
-{
-    
-	return yy_scan_bytes(yystr,strlen(yystr) );
-}
-
-/** Setup the input buffer state to scan the given bytes. The next call to yylex() will
- * scan from a @e copy of @a bytes.
- * @param bytes the byte buffer to scan
- * @param len the number of bytes in the buffer pointed to by @a bytes.
- * 
- * @return the newly allocated buffer state object.
- */
-YY_BUFFER_STATE yy_scan_bytes  (yyconst char * yybytes, int  _yybytes_len )
-{
-	YY_BUFFER_STATE b;
-	char *buf;
-	yy_size_t n;
-	int i;
-    
-	/* Get memory for full buffer, including space for trailing EOB's. */
-	n = _yybytes_len + 2;
-	buf = (char *) yyalloc(n  );
-	if ( ! buf )
-		YY_FATAL_ERROR( "out of dynamic memory in yy_scan_bytes()" );
-
-	for ( i = 0; i < _yybytes_len; ++i )
-		buf[i] = yybytes[i];
-
-	buf[_yybytes_len] = buf[_yybytes_len+1] = YY_END_OF_BUFFER_CHAR;
-
-	b = yy_scan_buffer(buf,n );
-	if ( ! b )
-		YY_FATAL_ERROR( "bad buffer in yy_scan_bytes()" );
-
-	/* It's okay to grow etc. this buffer, and we should throw it
-	 * away when we're done.
-	 */
-	b->yy_is_our_buffer = 1;
-
-	return b;
-}
-
-#ifndef YY_EXIT_FAILURE
-#define YY_EXIT_FAILURE 2
-#endif
-
-static void yy_fatal_error (yyconst char* msg )
-{
-    	(void) fprintf( stderr, "%s\n", msg );
-	exit( YY_EXIT_FAILURE );
-}
-
-/* Redefine yyless() so it works in section 3 code. */
-
-#undef yyless
-#define yyless(n) \
-	do \
-		{ \
-		/* Undo effects of setting up yytext. */ \
-        int yyless_macro_arg = (n); \
-        YY_LESS_LINENO(yyless_macro_arg);\
-		yytext[yyleng] = (yy_hold_char); \
-		(yy_c_buf_p) = yytext + yyless_macro_arg; \
-		(yy_hold_char) = *(yy_c_buf_p); \
-		*(yy_c_buf_p) = '\0'; \
-		yyleng = yyless_macro_arg; \
-		} \
-	while ( 0 )
-
-/* Accessor  methods (get/set functions) to struct members. */
-
-/** Get the current line number.
- * 
- */
-int yyget_lineno  (void)
-{
-        
-    return yylineno;
-}
-
-/** Get the input stream.
- * 
- */
-FILE *yyget_in  (void)
-{
-        return yyin;
-}
-
-/** Get the output stream.
- * 
- */
-FILE *yyget_out  (void)
-{
-        return yyout;
-}
-
-/** Get the length of the current token.
- * 
- */
-int yyget_leng  (void)
-{
-        return yyleng;
-}
-
-/** Get the current token.
- * 
- */
-
-char *yyget_text  (void)
-{
-        return yytext;
-}
-
-/** Set the current line number.
- * @param line_number
- * 
- */
-void yyset_lineno (int  line_number )
-{
-    
-    yylineno = line_number;
-}
-
-/** Set the input stream. This does not discard the current
- * input buffer.
- * @param in_str A readable stream.
- * 
- * @see yy_switch_to_buffer
- */
-void yyset_in (FILE *  in_str )
-{
-        yyin = in_str ;
-}
-
-void yyset_out (FILE *  out_str )
-{
-        yyout = out_str ;
-}
-
-int yyget_debug  (void)
-{
-        return yy_flex_debug;
-}
-
-void yyset_debug (int  bdebug )
-{
-        yy_flex_debug = bdebug ;
-}
-
-static int yy_init_globals (void)
-{
-        /* Initialization is the same as for the non-reentrant scanner.
-     * This function is called from yylex_destroy(), so don't allocate here.
-     */
-
-    (yy_buffer_stack) = 0;
-    (yy_buffer_stack_top) = 0;
-    (yy_buffer_stack_max) = 0;
-    (yy_c_buf_p) = (char *) 0;
-    (yy_init) = 0;
-    (yy_start) = 0;
-
-/* Defined in main.c */
-#ifdef YY_STDINIT
-    yyin = stdin;
-    yyout = stdout;
-#else
-    yyin = (FILE *) 0;
-    yyout = (FILE *) 0;
-#endif
-
-    /* For future reference: Set errno on error, since we are called by
-     * yylex_init()
-     */
-    return 0;
-}
-
-/* yylex_destroy is for both reentrant and non-reentrant scanners. */
-int yylex_destroy  (void)
-{
-    
-    /* Pop the buffer stack, destroying each element. */
-	while(YY_CURRENT_BUFFER){
-		yy_delete_buffer(YY_CURRENT_BUFFER  );
-		YY_CURRENT_BUFFER_LVALUE = NULL;
-		yypop_buffer_state();
-	}
-
-	/* Destroy the stack itself. */
-	yyfree((yy_buffer_stack) );
-	(yy_buffer_stack) = NULL;
-
-    /* Reset the globals. This is important in a non-reentrant scanner so the next time
-     * yylex() is called, initialization will occur. */
-    yy_init_globals( );
-
-    return 0;
-}
-
-/*
- * Internal utility routines.
- */
-
-#ifndef yytext_ptr
-static void yy_flex_strncpy (char* s1, yyconst char * s2, int n )
-{
-	register int i;
-	for ( i = 0; i < n; ++i )
-		s1[i] = s2[i];
-}
-#endif
-
-#ifdef YY_NEED_STRLEN
-static int yy_flex_strlen (yyconst char * s )
-{
-	register int n;
-	for ( n = 0; s[n]; ++n )
-		;
-
-	return n;
-}
-#endif
-
-void *yyalloc (yy_size_t  size )
-{
-	return (void *) malloc( size );
-}
-
-void *yyrealloc  (void * ptr, yy_size_t  size )
-{
-	/* The cast to (char *) in the following accommodates both
-	 * implementations that use char* generic pointers, and those
-	 * that use void* generic pointers.  It works with the latter
-	 * because both ANSI C and C++ allow castless assignment from
-	 * any pointer type to void*, and deal with argument conversions
-	 * as though doing an assignment.
-	 */
-	return (void *) realloc( (char *) ptr, size );
-}
-
-void yyfree (void * ptr )
-{
-	free( (char *) ptr );	/* see yyrealloc() for (char *) cast */
-}
-
-#define YYTABLES_NAME "yytables"
-
-#line 75 "lex.l"
-
-
-
-#ifndef yywrap /* XXX */
-int
-yywrap () 
-{
-     return 1;
-}
-#endif
-
-static int
-getstring(void)
-{
-    char x[128];
-    int i = 0;
-    int c;
-    int quote = 0;
-    while(i < sizeof(x) - 1 && (c = input()) != EOF){
-	if(quote) {
-	    x[i++] = c;
-	    quote = 0;
-	    continue;
-	}
-	if(c == '\n'){
-	    error_message("unterminated string");
-	    lineno++;
-	    break;
-	}
-	if(c == '\\'){
-	    quote++;
-	    continue;
-	}
-	if(c == '\"')
-	    break;
-	x[i++] = c;
-    }
-    x[i] = '\0';
-    yylval.string = strdup(x);
-    if (yylval.string == NULL)
-        err(1, "malloc");
-    return STRING;
-}
-
-void
-error_message (const char *format, ...)
-{
-     va_list args;
-
-     va_start (args, format);
-     fprintf (stderr, "%s:%d:", filename, lineno);
-     vfprintf (stderr, format, args);
-     va_end (args);
-     numerror++;
-}
-
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/com_err/parse.c
--- a/head/contrib/com_err/parse.c	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1716 +0,0 @@
-/* A Bison parser, made by GNU Bison 2.3.  */
-
-/* Skeleton implementation for Bison's Yacc-like parsers in C
-
-   Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005, 2006
-   Free Software Foundation, Inc.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street, Fifth Floor,
-   Boston, MA 02110-1301, USA.  */
-
-/* As a special exception, you may create a larger work that contains
-   part or all of the Bison parser skeleton and distribute that work
-   under terms of your choice, so long as that work isn't itself a
-   parser generator using the skeleton or a modified version thereof
-   as a parser skeleton.  Alternatively, if you modify or redistribute
-   the parser skeleton itself, you may (at your option) remove this
-   special exception, which will cause the skeleton and the resulting
-   Bison output files to be licensed under the GNU General Public
-   License without this special exception.
-
-   This special exception was added by the Free Software Foundation in
-   version 2.2 of Bison.  */
-
-/* C LALR(1) parser skeleton written by Richard Stallman, by
-   simplifying the original so-called "semantic" parser.  */
-
-/* All symbols defined below should begin with yy or YY, to avoid
-   infringing on user name space.  This should be done even for local
-   variables, as they might otherwise be expanded by user macros.
-   There are some unavoidable exceptions within include files to
-   define necessary library symbols; they are noted "INFRINGES ON
-   USER NAME SPACE" below.  */
-
-/* Identify Bison output.  */
-#define YYBISON 1
-
-/* Bison version.  */
-#define YYBISON_VERSION "2.3"
-
-/* Skeleton name.  */
-#define YYSKELETON_NAME "yacc.c"
-
-/* Pure parsers.  */
-#define YYPURE 0
-
-/* Using locations.  */
-#define YYLSP_NEEDED 0
-
-
-
-/* Tokens.  */
-#ifndef YYTOKENTYPE
-# define YYTOKENTYPE
-   /* Put the tokens into the symbol table, so that GDB and other debuggers
-      know about them.  */
-   enum yytokentype {
-     ET = 258,
-     INDEX = 259,
-     PREFIX = 260,
-     EC = 261,
-     ID = 262,
-     END = 263,
-     STRING = 264,
-     NUMBER = 265
-   };
-#endif
-/* Tokens.  */
-#define ET 258
-#define INDEX 259
-#define PREFIX 260
-#define EC 261
-#define ID 262
-#define END 263
-#define STRING 264
-#define NUMBER 265
-
-
-
-
-/* Copy the first part of user declarations.  */
-#line 1 "parse.y"
-
-/*
- * Copyright (c) 1998 - 2000 Kungliga Tekniska Högskolan
- * (Royal Institute of Technology, Stockholm, Sweden). 
- * All rights reserved. 
- *
- * Redistribution and use in source and binary forms, with or without 
- * modification, are permitted provided that the following conditions 
- * are met: 
- *
- * 1. Redistributions of source code must retain the above copyright 
- *    notice, this list of conditions and the following disclaimer. 
- *
- * 2. Redistributions in binary form must reproduce the above copyright 
- *    notice, this list of conditions and the following disclaimer in the 
- *    documentation and/or other materials provided with the distribution. 
- *
- * 3. Neither the name of the Institute nor the names of its contributors 
- *    may be used to endorse or promote products derived from this software 
- *    without specific prior written permission. 
- *
- * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
- * SUCH DAMAGE. 
- */
-
-#include "compile_et.h"
-#include "lex.h"
-
-RCSID("$Id: parse.y 15426 2005-06-16 19:21:42Z lha $");
-
-void yyerror (char *s);
-static long name2number(const char *str);
-
-extern char *yytext;
-
-/* This is for bison */
-
-#if !defined(alloca) && !defined(HAVE_ALLOCA)
-#define alloca(x) malloc(x)
-#endif
-
-
-
-/* Enabling traces.  */
-#ifndef YYDEBUG
-# define YYDEBUG 0
-#endif
-
-/* Enabling verbose error messages.  */
-#ifdef YYERROR_VERBOSE
-# undef YYERROR_VERBOSE
-# define YYERROR_VERBOSE 1
-#else
-# define YYERROR_VERBOSE 0
-#endif
-
-/* Enabling the token table.  */
-#ifndef YYTOKEN_TABLE
-# define YYTOKEN_TABLE 0
-#endif
-
-#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
-typedef union YYSTYPE
-#line 53 "parse.y"
-{
-  char *string;
-  int number;
-}
-/* Line 193 of yacc.c.  */
-#line 173 "parse.c"
-	YYSTYPE;
-# define yystype YYSTYPE /* obsolescent; will be withdrawn */
-# define YYSTYPE_IS_DECLARED 1
-# define YYSTYPE_IS_TRIVIAL 1
-#endif
-
-
-
-/* Copy the second part of user declarations.  */
-
-
-/* Line 216 of yacc.c.  */
-#line 186 "parse.c"
-
-#ifdef short
-# undef short
-#endif
-
-#ifdef YYTYPE_UINT8
-typedef YYTYPE_UINT8 yytype_uint8;
-#else
-typedef unsigned char yytype_uint8;
-#endif
-
-#ifdef YYTYPE_INT8
-typedef YYTYPE_INT8 yytype_int8;
-#elif (defined __STDC__ || defined __C99__FUNC__ \
-     || defined __cplusplus || defined _MSC_VER)
-typedef signed char yytype_int8;
-#else
-typedef short int yytype_int8;
-#endif
-
-#ifdef YYTYPE_UINT16
-typedef YYTYPE_UINT16 yytype_uint16;
-#else
-typedef unsigned short int yytype_uint16;
-#endif
-
-#ifdef YYTYPE_INT16
-typedef YYTYPE_INT16 yytype_int16;
-#else
-typedef short int yytype_int16;
-#endif
-
-#ifndef YYSIZE_T
-# ifdef __SIZE_TYPE__
-#  define YYSIZE_T __SIZE_TYPE__
-# elif defined size_t
-#  define YYSIZE_T size_t
-# elif ! defined YYSIZE_T && (defined __STDC__ || defined __C99__FUNC__ \
-     || defined __cplusplus || defined _MSC_VER)
-#  include <stddef.h> /* INFRINGES ON USER NAME SPACE */
-#  define YYSIZE_T size_t
-# else
-#  define YYSIZE_T unsigned int
-# endif
-#endif
-
-#define YYSIZE_MAXIMUM ((YYSIZE_T) -1)
-
-#ifndef YY_
-# if defined YYENABLE_NLS && YYENABLE_NLS
-#  if ENABLE_NLS
-#   include <libintl.h> /* INFRINGES ON USER NAME SPACE */
-#   define YY_(msgid) dgettext ("bison-runtime", msgid)
-#  endif
-# endif
-# ifndef YY_
-#  define YY_(msgid) msgid
-# endif
-#endif
-
-/* Suppress unused-variable warnings by "using" E.  */
-#if ! defined lint || defined __GNUC__
-# define YYUSE(e) ((void) (e))
-#else
-# define YYUSE(e) /* empty */
-#endif
-
-/* Identity function, used to suppress warnings about constant conditions.  */
-#ifndef lint
-# define YYID(n) (n)
-#else
-#if (defined __STDC__ || defined __C99__FUNC__ \
-     || defined __cplusplus || defined _MSC_VER)
-static int
-YYID (int i)
-#else
-static int
-YYID (i)
-    int i;
-#endif
-{
-  return i;
-}
-#endif
-
-#if ! defined yyoverflow || YYERROR_VERBOSE
-
-/* The parser invokes alloca or malloc; define the necessary symbols.  */
-
-# ifdef YYSTACK_USE_ALLOCA
-#  if YYSTACK_USE_ALLOCA
-#   ifdef __GNUC__
-#    define YYSTACK_ALLOC __builtin_alloca
-#   elif defined __BUILTIN_VA_ARG_INCR
-#    include <alloca.h> /* INFRINGES ON USER NAME SPACE */
-#   elif defined _AIX
-#    define YYSTACK_ALLOC __alloca
-#   elif defined _MSC_VER
-#    include <malloc.h> /* INFRINGES ON USER NAME SPACE */
-#    define alloca _alloca
-#   else
-#    define YYSTACK_ALLOC alloca
-#    if ! defined _ALLOCA_H && ! defined _STDLIB_H && (defined __STDC__ || defined __C99__FUNC__ \
-     || defined __cplusplus || defined _MSC_VER)
-#     include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
-#     ifndef _STDLIB_H
-#      define _STDLIB_H 1
-#     endif
-#    endif
-#   endif
-#  endif
-# endif
-
-# ifdef YYSTACK_ALLOC
-   /* Pacify GCC's `empty if-body' warning.  */
-#  define YYSTACK_FREE(Ptr) do { /* empty */; } while (YYID (0))
-#  ifndef YYSTACK_ALLOC_MAXIMUM
-    /* The OS might guarantee only one guard page at the bottom of the stack,
-       and a page size can be as small as 4096 bytes.  So we cannot safely
-       invoke alloca (N) if N exceeds 4096.  Use a slightly smaller number
-       to allow for a few compiler-allocated temporary stack slots.  */
-#   define YYSTACK_ALLOC_MAXIMUM 4032 /* reasonable circa 2006 */
-#  endif
-# else
-#  define YYSTACK_ALLOC YYMALLOC
-#  define YYSTACK_FREE YYFREE
-#  ifndef YYSTACK_ALLOC_MAXIMUM
-#   define YYSTACK_ALLOC_MAXIMUM YYSIZE_MAXIMUM
-#  endif
-#  if (defined __cplusplus && ! defined _STDLIB_H \
-       && ! ((defined YYMALLOC || defined malloc) \
-	     && (defined YYFREE || defined free)))
-#   include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
-#   ifndef _STDLIB_H
-#    define _STDLIB_H 1
-#   endif
-#  endif
-#  ifndef YYMALLOC
-#   define YYMALLOC malloc
-#   if ! defined malloc && ! defined _STDLIB_H && (defined __STDC__ || defined __C99__FUNC__ \
-     || defined __cplusplus || defined _MSC_VER)
-void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */
-#   endif
-#  endif
-#  ifndef YYFREE
-#   define YYFREE free
-#   if ! defined free && ! defined _STDLIB_H && (defined __STDC__ || defined __C99__FUNC__ \
-     || defined __cplusplus || defined _MSC_VER)
-void free (void *); /* INFRINGES ON USER NAME SPACE */
-#   endif
-#  endif
-# endif
-#endif /* ! defined yyoverflow || YYERROR_VERBOSE */
-
-
-#if (! defined yyoverflow \
-     && (! defined __cplusplus \
-	 || (defined YYSTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL)))
-
-/* A type that is properly aligned for any stack member.  */
-union yyalloc
-{
-  yytype_int16 yyss;
-  YYSTYPE yyvs;
-  };
-
-/* The size of the maximum gap between one aligned stack and the next.  */
-# define YYSTACK_GAP_MAXIMUM (sizeof (union yyalloc) - 1)
-
-/* The size of an array large to enough to hold all stacks, each with
-   N elements.  */
-# define YYSTACK_BYTES(N) \
-     ((N) * (sizeof (yytype_int16) + sizeof (YYSTYPE)) \
-      + YYSTACK_GAP_MAXIMUM)
-
-/* Copy COUNT objects from FROM to TO.  The source and destination do
-   not overlap.  */
-# ifndef YYCOPY
-#  if defined __GNUC__ && 1 < __GNUC__
-#   define YYCOPY(To, From, Count) \
-      __builtin_memcpy (To, From, (Count) * sizeof (*(From)))
-#  else
-#   define YYCOPY(To, From, Count)		\
-      do					\
-	{					\
-	  YYSIZE_T yyi;				\
-	  for (yyi = 0; yyi < (Count); yyi++)	\
-	    (To)[yyi] = (From)[yyi];		\
-	}					\
-      while (YYID (0))
-#  endif
-# endif
-
-/* Relocate STACK from its old location to the new one.  The
-   local variables YYSIZE and YYSTACKSIZE give the old and new number of
-   elements in the stack, and YYPTR gives the new location of the
-   stack.  Advance YYPTR to a properly aligned location for the next
-   stack.  */
-# define YYSTACK_RELOCATE(Stack)					\
-    do									\
-      {									\
-	YYSIZE_T yynewbytes;						\
-	YYCOPY (&yyptr->Stack, Stack, yysize);				\
-	Stack = &yyptr->Stack;						\
-	yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \
-	yyptr += yynewbytes / sizeof (*yyptr);				\
-      }									\
-    while (YYID (0))
-
-#endif
-
-/* YYFINAL -- State number of the termination state.  */
-#define YYFINAL  9
-/* YYLAST -- Last index in YYTABLE.  */
-#define YYLAST   23
-
-/* YYNTOKENS -- Number of terminals.  */
-#define YYNTOKENS  12
-/* YYNNTS -- Number of nonterminals.  */
-#define YYNNTS  7
-/* YYNRULES -- Number of rules.  */
-#define YYNRULES  15
-/* YYNRULES -- Number of states.  */
-#define YYNSTATES  24
-
-/* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX.  */
-#define YYUNDEFTOK  2
-#define YYMAXUTOK   265
-
-#define YYTRANSLATE(YYX)						\
-  ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK)
-
-/* YYTRANSLATE[YYLEX] -- Bison symbol number corresponding to YYLEX.  */
-static const yytype_uint8 yytranslate[] =
-{
-       0,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,    11,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     1,     2,     3,     4,
-       5,     6,     7,     8,     9,    10
-};
-
-#if YYDEBUG
-/* YYPRHS[YYN] -- Index of the first RHS symbol of rule number YYN in
-   YYRHS.  */
-static const yytype_uint8 yyprhs[] =
-{
-       0,     0,     3,     4,     7,    10,    12,    15,    18,    22,
-      24,    27,    30,    33,    35,    40
-};
-
-/* YYRHS -- A `-1'-separated list of the rules' RHS.  */
-static const yytype_int8 yyrhs[] =
-{
-      13,     0,    -1,    -1,    14,    17,    -1,    15,    16,    -1,
-      16,    -1,     7,     9,    -1,     3,     9,    -1,     3,     9,
-       9,    -1,    18,    -1,    17,    18,    -1,     4,    10,    -1,
-       5,     9,    -1,     5,    -1,     6,     9,    11,     9,    -1,
-       8,    -1
-};
-
-/* YYRLINE[YYN] -- source line where rule number YYN was defined.  */
-static const yytype_uint8 yyrline[] =
-{
-       0,    64,    64,    65,    68,    69,    72,    78,    84,    93,
-      94,    97,   101,   109,   116,   136
-};
-#endif
-
-#if YYDEBUG || YYERROR_VERBOSE || YYTOKEN_TABLE
-/* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM.
-   First, the terminals, then, starting at YYNTOKENS, nonterminals.  */
-static const char *const yytname[] =
-{
-  "$end", "error", "$undefined", "ET", "INDEX", "PREFIX", "EC", "ID",
-  "END", "STRING", "NUMBER", "','", "$accept", "file", "header", "id",
-  "et", "statements", "statement", 0
-};
-#endif
-
-# ifdef YYPRINT
-/* YYTOKNUM[YYLEX-NUM] -- Internal token number corresponding to
-   token YYLEX-NUM.  */
-static const yytype_uint16 yytoknum[] =
-{
-       0,   256,   257,   258,   259,   260,   261,   262,   263,   264,
-     265,    44
-};
-# endif
-
-/* YYR1[YYN] -- Symbol number of symbol that rule YYN derives.  */
-static const yytype_uint8 yyr1[] =
-{
-       0,    12,    13,    13,    14,    14,    15,    16,    16,    17,
-      17,    18,    18,    18,    18,    18
-};
-
-/* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN.  */
-static const yytype_uint8 yyr2[] =
-{
-       0,     2,     0,     2,     2,     1,     2,     2,     3,     1,
-       2,     2,     2,     1,     4,     1
-};
-
-/* YYDEFACT[STATE-NAME] -- Default rule to reduce with in state
-   STATE-NUM when YYTABLE doesn't specify something else to do.  Zero
-   means the default is an error.  */
-static const yytype_uint8 yydefact[] =
-{
-       2,     0,     0,     0,     0,     0,     5,     7,     6,     1,
-       0,    13,     0,    15,     3,     9,     4,     8,    11,    12,
-       0,    10,     0,    14
-};
-
-/* YYDEFGOTO[NTERM-NUM].  */
-static const yytype_int8 yydefgoto[] =
-{
-      -1,     3,     4,     5,     6,    14,    15
-};
-
-/* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing
-   STATE-NUM.  */
-#define YYPACT_NINF -5
-static const yytype_int8 yypact[] =
-{
-       0,    -3,    -1,     5,    -4,     6,    -5,     1,    -5,    -5,
-       2,     4,     7,    -5,    -4,    -5,    -5,    -5,    -5,    -5,
-       3,    -5,     8,    -5
-};
-
-/* YYPGOTO[NTERM-NUM].  */
-static const yytype_int8 yypgoto[] =
-{
-      -5,    -5,    -5,    -5,    10,    -5,     9
-};
-
-/* YYTABLE[YYPACT[STATE-NUM]].  What to do in state STATE-NUM.  If
-   positive, shift that token.  If negative, reduce the rule which
-   number is the opposite.  If zero, do what YYDEFACT says.
-   If YYTABLE_NINF, syntax error.  */
-#define YYTABLE_NINF -1
-static const yytype_uint8 yytable[] =
-{
-      10,    11,    12,     1,    13,     9,     7,     2,     8,     1,
-      17,     0,    18,    19,    22,    16,    20,    23,     0,     0,
-       0,     0,     0,    21
-};
-
-static const yytype_int8 yycheck[] =
-{
-       4,     5,     6,     3,     8,     0,     9,     7,     9,     3,
-       9,    -1,    10,     9,    11,     5,     9,     9,    -1,    -1,
-      -1,    -1,    -1,    14
-};
-
-/* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
-   symbol of state STATE-NUM.  */
-static const yytype_uint8 yystos[] =
-{
-       0,     3,     7,    13,    14,    15,    16,     9,     9,     0,
-       4,     5,     6,     8,    17,    18,    16,     9,    10,     9,
-       9,    18,    11,     9
-};
-
-#define yyerrok		(yyerrstatus = 0)
-#define yyclearin	(yychar = YYEMPTY)
-#define YYEMPTY		(-2)
-#define YYEOF		0
-
-#define YYACCEPT	goto yyacceptlab
-#define YYABORT		goto yyabortlab
-#define YYERROR		goto yyerrorlab
-
-
-/* Like YYERROR except do call yyerror.  This remains here temporarily
-   to ease the transition to the new meaning of YYERROR, for GCC.
-   Once GCC version 2 has supplanted version 1, this can go.  */
-
-#define YYFAIL		goto yyerrlab
-
-#define YYRECOVERING()  (!!yyerrstatus)
-
-#define YYBACKUP(Token, Value)					\
-do								\
-  if (yychar == YYEMPTY && yylen == 1)				\
-    {								\
-      yychar = (Token);						\
-      yylval = (Value);						\
-      yytoken = YYTRANSLATE (yychar);				\
-      YYPOPSTACK (1);						\
-      goto yybackup;						\
-    }								\
-  else								\
-    {								\
-      yyerror (YY_("syntax error: cannot back up")); \
-      YYERROR;							\
-    }								\
-while (YYID (0))
-
-
-#define YYTERROR	1
-#define YYERRCODE	256
-
-
-/* YYLLOC_DEFAULT -- Set CURRENT to span from RHS[1] to RHS[N].
-   If N is 0, then set CURRENT to the empty location which ends
-   the previous symbol: RHS[0] (always defined).  */
-
-#define YYRHSLOC(Rhs, K) ((Rhs)[K])
-#ifndef YYLLOC_DEFAULT
-# define YYLLOC_DEFAULT(Current, Rhs, N)				\
-    do									\
-      if (YYID (N))                                                    \
-	{								\
-	  (Current).first_line   = YYRHSLOC (Rhs, 1).first_line;	\
-	  (Current).first_column = YYRHSLOC (Rhs, 1).first_column;	\
-	  (Current).last_line    = YYRHSLOC (Rhs, N).last_line;		\
-	  (Current).last_column  = YYRHSLOC (Rhs, N).last_column;	\
-	}								\
-      else								\
-	{								\
-	  (Current).first_line   = (Current).last_line   =		\
-	    YYRHSLOC (Rhs, 0).last_line;				\
-	  (Current).first_column = (Current).last_column =		\
-	    YYRHSLOC (Rhs, 0).last_column;				\
-	}								\
-    while (YYID (0))
-#endif
-
-
-/* YY_LOCATION_PRINT -- Print the location on the stream.
-   This macro was not mandated originally: define only if we know
-   we won't break user code: when these are the locations we know.  */
-
-#ifndef YY_LOCATION_PRINT
-# if defined YYLTYPE_IS_TRIVIAL && YYLTYPE_IS_TRIVIAL
-#  define YY_LOCATION_PRINT(File, Loc)			\
-     fprintf (File, "%d.%d-%d.%d",			\
-	      (Loc).first_line, (Loc).first_column,	\
-	      (Loc).last_line,  (Loc).last_column)
-# else
-#  define YY_LOCATION_PRINT(File, Loc) ((void) 0)
-# endif
-#endif
-
-
-/* YYLEX -- calling `yylex' with the right arguments.  */
-
-#ifdef YYLEX_PARAM
-# define YYLEX yylex (YYLEX_PARAM)
-#else
-# define YYLEX yylex ()
-#endif
-
-/* Enable debugging if requested.  */
-#if YYDEBUG
-
-# ifndef YYFPRINTF
-#  include <stdio.h> /* INFRINGES ON USER NAME SPACE */
-#  define YYFPRINTF fprintf
-# endif
-
-# define YYDPRINTF(Args)			\
-do {						\
-  if (yydebug)					\
-    YYFPRINTF Args;				\
-} while (YYID (0))
-
-# define YY_SYMBOL_PRINT(Title, Type, Value, Location)			  \
-do {									  \
-  if (yydebug)								  \
-    {									  \
-      YYFPRINTF (stderr, "%s ", Title);					  \
-      yy_symbol_print (stderr,						  \
-		  Type, Value); \
-      YYFPRINTF (stderr, "\n");						  \
-    }									  \
-} while (YYID (0))
-
-
-/*--------------------------------.
-| Print this symbol on YYOUTPUT.  |
-`--------------------------------*/
-
-/*ARGSUSED*/
-#if (defined __STDC__ || defined __C99__FUNC__ \
-     || defined __cplusplus || defined _MSC_VER)
-static void
-yy_symbol_value_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)
-#else
-static void
-yy_symbol_value_print (yyoutput, yytype, yyvaluep)
-    FILE *yyoutput;
-    int yytype;
-    YYSTYPE const * const yyvaluep;
-#endif
-{
-  if (!yyvaluep)
-    return;
-# ifdef YYPRINT
-  if (yytype < YYNTOKENS)
-    YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep);
-# else
-  YYUSE (yyoutput);
-# endif
-  switch (yytype)
-    {
-      default:
-	break;
-    }
-}
-
-
-/*--------------------------------.
-| Print this symbol on YYOUTPUT.  |
-`--------------------------------*/
-
-#if (defined __STDC__ || defined __C99__FUNC__ \
-     || defined __cplusplus || defined _MSC_VER)
-static void
-yy_symbol_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)
-#else
-static void
-yy_symbol_print (yyoutput, yytype, yyvaluep)
-    FILE *yyoutput;
-    int yytype;
-    YYSTYPE const * const yyvaluep;
-#endif
-{
-  if (yytype < YYNTOKENS)
-    YYFPRINTF (yyoutput, "token %s (", yytname[yytype]);
-  else
-    YYFPRINTF (yyoutput, "nterm %s (", yytname[yytype]);
-
-  yy_symbol_value_print (yyoutput, yytype, yyvaluep);
-  YYFPRINTF (yyoutput, ")");
-}
-
-/*------------------------------------------------------------------.
-| yy_stack_print -- Print the state stack from its BOTTOM up to its |
-| TOP (included).                                                   |
-`------------------------------------------------------------------*/
-
-#if (defined __STDC__ || defined __C99__FUNC__ \
-     || defined __cplusplus || defined _MSC_VER)
-static void
-yy_stack_print (yytype_int16 *bottom, yytype_int16 *top)
-#else
-static void
-yy_stack_print (bottom, top)
-    yytype_int16 *bottom;
-    yytype_int16 *top;
-#endif
-{
-  YYFPRINTF (stderr, "Stack now");
-  for (; bottom <= top; ++bottom)
-    YYFPRINTF (stderr, " %d", *bottom);
-  YYFPRINTF (stderr, "\n");
-}
-
-# define YY_STACK_PRINT(Bottom, Top)				\
-do {								\
-  if (yydebug)							\
-    yy_stack_print ((Bottom), (Top));				\
-} while (YYID (0))
-
-
-/*------------------------------------------------.
-| Report that the YYRULE is going to be reduced.  |
-`------------------------------------------------*/
-
-#if (defined __STDC__ || defined __C99__FUNC__ \
-     || defined __cplusplus || defined _MSC_VER)
-static void
-yy_reduce_print (YYSTYPE *yyvsp, int yyrule)
-#else
-static void
-yy_reduce_print (yyvsp, yyrule)
-    YYSTYPE *yyvsp;
-    int yyrule;
-#endif
-{
-  int yynrhs = yyr2[yyrule];
-  int yyi;
-  unsigned long int yylno = yyrline[yyrule];
-  YYFPRINTF (stderr, "Reducing stack by rule %d (line %lu):\n",
-	     yyrule - 1, yylno);
-  /* The symbols being reduced.  */
-  for (yyi = 0; yyi < yynrhs; yyi++)
-    {
-      fprintf (stderr, "   $%d = ", yyi + 1);
-      yy_symbol_print (stderr, yyrhs[yyprhs[yyrule] + yyi],
-		       &(yyvsp[(yyi + 1) - (yynrhs)])
-		       		       );
-      fprintf (stderr, "\n");
-    }
-}
-
-# define YY_REDUCE_PRINT(Rule)		\
-do {					\
-  if (yydebug)				\
-    yy_reduce_print (yyvsp, Rule); \
-} while (YYID (0))
-
-/* Nonzero means print parse trace.  It is left uninitialized so that
-   multiple parsers can coexist.  */
-int yydebug;
-#else /* !YYDEBUG */
-# define YYDPRINTF(Args)
-# define YY_SYMBOL_PRINT(Title, Type, Value, Location)
-# define YY_STACK_PRINT(Bottom, Top)
-# define YY_REDUCE_PRINT(Rule)
-#endif /* !YYDEBUG */
-
-
-/* YYINITDEPTH -- initial size of the parser's stacks.  */
-#ifndef	YYINITDEPTH
-# define YYINITDEPTH 200
-#endif
-
-/* YYMAXDEPTH -- maximum size the stacks can grow to (effective only
-   if the built-in stack extension method is used).
-
-   Do not make this value too large; the results are undefined if
-   YYSTACK_ALLOC_MAXIMUM < YYSTACK_BYTES (YYMAXDEPTH)
-   evaluated with infinite-precision integer arithmetic.  */
-
-#ifndef YYMAXDEPTH
-# define YYMAXDEPTH 10000
-#endif
-
-

-
-#if YYERROR_VERBOSE
-
-# ifndef yystrlen
-#  if defined __GLIBC__ && defined _STRING_H
-#   define yystrlen strlen
-#  else
-/* Return the length of YYSTR.  */
-#if (defined __STDC__ || defined __C99__FUNC__ \
-     || defined __cplusplus || defined _MSC_VER)
-static YYSIZE_T
-yystrlen (const char *yystr)
-#else
-static YYSIZE_T
-yystrlen (yystr)
-    const char *yystr;
-#endif
-{
-  YYSIZE_T yylen;
-  for (yylen = 0; yystr[yylen]; yylen++)
-    continue;
-  return yylen;
-}
-#  endif
-# endif
-
-# ifndef yystpcpy
-#  if defined __GLIBC__ && defined _STRING_H && defined _GNU_SOURCE
-#   define yystpcpy stpcpy
-#  else
-/* Copy YYSRC to YYDEST, returning the address of the terminating '\0' in
-   YYDEST.  */
-#if (defined __STDC__ || defined __C99__FUNC__ \
-     || defined __cplusplus || defined _MSC_VER)
-static char *
-yystpcpy (char *yydest, const char *yysrc)
-#else
-static char *
-yystpcpy (yydest, yysrc)
-    char *yydest;
-    const char *yysrc;
-#endif
-{
-  char *yyd = yydest;
-  const char *yys = yysrc;
-
-  while ((*yyd++ = *yys++) != '\0')
-    continue;
-
-  return yyd - 1;
-}
-#  endif
-# endif
-
-# ifndef yytnamerr
-/* Copy to YYRES the contents of YYSTR after stripping away unnecessary
-   quotes and backslashes, so that it's suitable for yyerror.  The
-   heuristic is that double-quoting is unnecessary unless the string
-   contains an apostrophe, a comma, or backslash (other than
-   backslash-backslash).  YYSTR is taken from yytname.  If YYRES is
-   null, do not copy; instead, return the length of what the result
-   would have been.  */
-static YYSIZE_T
-yytnamerr (char *yyres, const char *yystr)
-{
-  if (*yystr == '"')
-    {
-      YYSIZE_T yyn = 0;
-      char const *yyp = yystr;
-
-      for (;;)
-	switch (*++yyp)
-	  {
-	  case '\'':
-	  case ',':
-	    goto do_not_strip_quotes;
-
-	  case '\\':
-	    if (*++yyp != '\\')
-	      goto do_not_strip_quotes;
-	    /* Fall through.  */
-	  default:
-	    if (yyres)
-	      yyres[yyn] = *yyp;
-	    yyn++;
-	    break;
-
-	  case '"':
-	    if (yyres)
-	      yyres[yyn] = '\0';
-	    return yyn;
-	  }
-    do_not_strip_quotes: ;
-    }
-
-  if (! yyres)
-    return yystrlen (yystr);
-
-  return yystpcpy (yyres, yystr) - yyres;
-}
-# endif
-
-/* Copy into YYRESULT an error message about the unexpected token
-   YYCHAR while in state YYSTATE.  Return the number of bytes copied,
-   including the terminating null byte.  If YYRESULT is null, do not
-   copy anything; just return the number of bytes that would be
-   copied.  As a special case, return 0 if an ordinary "syntax error"
-   message will do.  Return YYSIZE_MAXIMUM if overflow occurs during
-   size calculation.  */
-static YYSIZE_T
-yysyntax_error (char *yyresult, int yystate, int yychar)
-{
-  int yyn = yypact[yystate];
-
-  if (! (YYPACT_NINF < yyn && yyn <= YYLAST))
-    return 0;
-  else
-    {
-      int yytype = YYTRANSLATE (yychar);
-      YYSIZE_T yysize0 = yytnamerr (0, yytname[yytype]);
-      YYSIZE_T yysize = yysize0;
-      YYSIZE_T yysize1;
-      int yysize_overflow = 0;
-      enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 };
-      char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM];
-      int yyx;
-
-# if 0
-      /* This is so xgettext sees the translatable formats that are
-	 constructed on the fly.  */
-      YY_("syntax error, unexpected %s");
-      YY_("syntax error, unexpected %s, expecting %s");
-      YY_("syntax error, unexpected %s, expecting %s or %s");
-      YY_("syntax error, unexpected %s, expecting %s or %s or %s");
-      YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s");
-# endif
-      char *yyfmt;
-      char const *yyf;
-      static char const yyunexpected[] = "syntax error, unexpected %s";
-      static char const yyexpecting[] = ", expecting %s";
-      static char const yyor[] = " or %s";
-      char yyformat[sizeof yyunexpected
-		    + sizeof yyexpecting - 1
-		    + ((YYERROR_VERBOSE_ARGS_MAXIMUM - 2)
-		       * (sizeof yyor - 1))];
-      char const *yyprefix = yyexpecting;
-
-      /* Start YYX at -YYN if negative to avoid negative indexes in
-	 YYCHECK.  */
-      int yyxbegin = yyn < 0 ? -yyn : 0;
-
-      /* Stay within bounds of both yycheck and yytname.  */
-      int yychecklim = YYLAST - yyn + 1;
-      int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS;
-      int yycount = 1;
-
-      yyarg[0] = yytname[yytype];
-      yyfmt = yystpcpy (yyformat, yyunexpected);
-
-      for (yyx = yyxbegin; yyx < yyxend; ++yyx)
-	if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR)
-	  {
-	    if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM)
-	      {
-		yycount = 1;
-		yysize = yysize0;
-		yyformat[sizeof yyunexpected - 1] = '\0';
-		break;
-	      }
-	    yyarg[yycount++] = yytname[yyx];
-	    yysize1 = yysize + yytnamerr (0, yytname[yyx]);
-	    yysize_overflow |= (yysize1 < yysize);
-	    yysize = yysize1;
-	    yyfmt = yystpcpy (yyfmt, yyprefix);
-	    yyprefix = yyor;
-	  }
-
-      yyf = YY_(yyformat);
-      yysize1 = yysize + yystrlen (yyf);
-      yysize_overflow |= (yysize1 < yysize);
-      yysize = yysize1;
-
-      if (yysize_overflow)
-	return YYSIZE_MAXIMUM;
-
-      if (yyresult)
-	{
-	  /* Avoid sprintf, as that infringes on the user's name space.
-	     Don't have undefined behavior even if the translation
-	     produced a string with the wrong number of "%s"s.  */
-	  char *yyp = yyresult;
-	  int yyi = 0;
-	  while ((*yyp = *yyf) != '\0')
-	    {
-	      if (*yyp == '%' && yyf[1] == 's' && yyi < yycount)
-		{
-		  yyp += yytnamerr (yyp, yyarg[yyi++]);
-		  yyf += 2;
-		}
-	      else
-		{
-		  yyp++;
-		  yyf++;
-		}
-	    }
-	}
-      return yysize;
-    }
-}
-#endif /* YYERROR_VERBOSE */
-

-
-/*-----------------------------------------------.
-| Release the memory associated to this symbol.  |
-`-----------------------------------------------*/
-
-/*ARGSUSED*/
-#if (defined __STDC__ || defined __C99__FUNC__ \
-     || defined __cplusplus || defined _MSC_VER)
-static void
-yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep)
-#else
-static void
-yydestruct (yymsg, yytype, yyvaluep)
-    const char *yymsg;
-    int yytype;
-    YYSTYPE *yyvaluep;
-#endif
-{
-  YYUSE (yyvaluep);
-
-  if (!yymsg)
-    yymsg = "Deleting";
-  YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp);
-
-  switch (yytype)
-    {
-
-      default:
-	break;
-    }
-}
-

-
-/* Prevent warnings from -Wmissing-prototypes.  */
-
-#ifdef YYPARSE_PARAM
-#if defined __STDC__ || defined __cplusplus
-int yyparse (void *YYPARSE_PARAM);
-#else
-int yyparse ();
-#endif
-#else /* ! YYPARSE_PARAM */
-#if defined __STDC__ || defined __cplusplus
-int yyparse (void);
-#else
-int yyparse ();
-#endif
-#endif /* ! YYPARSE_PARAM */
-
-
-
-/* The look-ahead symbol.  */
-int yychar;
-
-/* The semantic value of the look-ahead symbol.  */
-YYSTYPE yylval;
-
-/* Number of syntax errors so far.  */
-int yynerrs;
-
-
-
-/*----------.
-| yyparse.  |
-`----------*/
-
-#ifdef YYPARSE_PARAM
-#if (defined __STDC__ || defined __C99__FUNC__ \
-     || defined __cplusplus || defined _MSC_VER)
-int
-yyparse (void *YYPARSE_PARAM)
-#else
-int
-yyparse (YYPARSE_PARAM)
-    void *YYPARSE_PARAM;
-#endif
-#else /* ! YYPARSE_PARAM */
-#if (defined __STDC__ || defined __C99__FUNC__ \
-     || defined __cplusplus || defined _MSC_VER)
-int
-yyparse (void)
-#else
-int
-yyparse ()
-
-#endif
-#endif
-{
-  
-  int yystate;
-  int yyn;
-  int yyresult;
-  /* Number of tokens to shift before error messages enabled.  */
-  int yyerrstatus;
-  /* Look-ahead token as an internal (translated) token number.  */
-  int yytoken = 0;
-#if YYERROR_VERBOSE
-  /* Buffer for error messages, and its allocated size.  */
-  char yymsgbuf[128];
-  char *yymsg = yymsgbuf;
-  YYSIZE_T yymsg_alloc = sizeof yymsgbuf;
-#endif
-
-  /* Three stacks and their tools:
-     `yyss': related to states,
-     `yyvs': related to semantic values,
-     `yyls': related to locations.
-
-     Refer to the stacks thru separate pointers, to allow yyoverflow
-     to reallocate them elsewhere.  */
-
-  /* The state stack.  */
-  yytype_int16 yyssa[YYINITDEPTH];
-  yytype_int16 *yyss = yyssa;
-  yytype_int16 *yyssp;
-
-  /* The semantic value stack.  */
-  YYSTYPE yyvsa[YYINITDEPTH];
-  YYSTYPE *yyvs = yyvsa;
-  YYSTYPE *yyvsp;
-
-
-
-#define YYPOPSTACK(N)   (yyvsp -= (N), yyssp -= (N))
-
-  YYSIZE_T yystacksize = YYINITDEPTH;
-
-  /* The variables used to return semantic value and location from the
-     action routines.  */
-  YYSTYPE yyval;
-
-
-  /* The number of symbols on the RHS of the reduced rule.
-     Keep to zero when no symbol should be popped.  */
-  int yylen = 0;
-
-  YYDPRINTF ((stderr, "Starting parse\n"));
-
-  yystate = 0;
-  yyerrstatus = 0;
-  yynerrs = 0;
-  yychar = YYEMPTY;		/* Cause a token to be read.  */
-
-  /* Initialize stack pointers.
-     Waste one element of value and location stack
-     so that they stay on the same level as the state stack.
-     The wasted elements are never initialized.  */
-
-  yyssp = yyss;
-  yyvsp = yyvs;
-
-  goto yysetstate;
-
-/*------------------------------------------------------------.
-| yynewstate -- Push a new state, which is found in yystate.  |
-`------------------------------------------------------------*/
- yynewstate:
-  /* In all cases, when you get here, the value and location stacks
-     have just been pushed.  So pushing a state here evens the stacks.  */
-  yyssp++;
-
- yysetstate:
-  *yyssp = yystate;
-
-  if (yyss + yystacksize - 1 <= yyssp)
-    {
-      /* Get the current used size of the three stacks, in elements.  */
-      YYSIZE_T yysize = yyssp - yyss + 1;
-
-#ifdef yyoverflow
-      {
-	/* Give user a chance to reallocate the stack.  Use copies of
-	   these so that the &'s don't force the real ones into
-	   memory.  */
-	YYSTYPE *yyvs1 = yyvs;
-	yytype_int16 *yyss1 = yyss;
-
-
-	/* Each stack pointer address is followed by the size of the
-	   data in use in that stack, in bytes.  This used to be a
-	   conditional around just the two extra args, but that might
-	   be undefined if yyoverflow is a macro.  */
-	yyoverflow (YY_("memory exhausted"),
-		    &yyss1, yysize * sizeof (*yyssp),
-		    &yyvs1, yysize * sizeof (*yyvsp),
-
-		    &yystacksize);
-
-	yyss = yyss1;
-	yyvs = yyvs1;
-      }
-#else /* no yyoverflow */
-# ifndef YYSTACK_RELOCATE
-      goto yyexhaustedlab;
-# else
-      /* Extend the stack our own way.  */
-      if (YYMAXDEPTH <= yystacksize)
-	goto yyexhaustedlab;
-      yystacksize *= 2;
-      if (YYMAXDEPTH < yystacksize)
-	yystacksize = YYMAXDEPTH;
-
-      {
-	yytype_int16 *yyss1 = yyss;
-	union yyalloc *yyptr =
-	  (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize));
-	if (! yyptr)
-	  goto yyexhaustedlab;
-	YYSTACK_RELOCATE (yyss);
-	YYSTACK_RELOCATE (yyvs);
-
-#  undef YYSTACK_RELOCATE
-	if (yyss1 != yyssa)
-	  YYSTACK_FREE (yyss1);
-      }
-# endif
-#endif /* no yyoverflow */
-
-      yyssp = yyss + yysize - 1;
-      yyvsp = yyvs + yysize - 1;
-
-
-      YYDPRINTF ((stderr, "Stack size increased to %lu\n",
-		  (unsigned long int) yystacksize));
-
-      if (yyss + yystacksize - 1 <= yyssp)
-	YYABORT;
-    }
-
-  YYDPRINTF ((stderr, "Entering state %d\n", yystate));
-
-  goto yybackup;
-
-/*-----------.
-| yybackup.  |
-`-----------*/
-yybackup:
-
-  /* Do appropriate processing given the current state.  Read a
-     look-ahead token if we need one and don't already have one.  */
-
-  /* First try to decide what to do without reference to look-ahead token.  */
-  yyn = yypact[yystate];
-  if (yyn == YYPACT_NINF)
-    goto yydefault;
-
-  /* Not known => get a look-ahead token if don't already have one.  */
-
-  /* YYCHAR is either YYEMPTY or YYEOF or a valid look-ahead symbol.  */
-  if (yychar == YYEMPTY)
-    {
-      YYDPRINTF ((stderr, "Reading a token: "));
-      yychar = YYLEX;
-    }
-
-  if (yychar <= YYEOF)
-    {
-      yychar = yytoken = YYEOF;
-      YYDPRINTF ((stderr, "Now at end of input.\n"));
-    }
-  else
-    {
-      yytoken = YYTRANSLATE (yychar);
-      YY_SYMBOL_PRINT ("Next token is", yytoken, &yylval, &yylloc);
-    }
-
-  /* If the proper action on seeing token YYTOKEN is to reduce or to
-     detect an error, take that action.  */
-  yyn += yytoken;
-  if (yyn < 0 || YYLAST < yyn || yycheck[yyn] != yytoken)
-    goto yydefault;
-  yyn = yytable[yyn];
-  if (yyn <= 0)
-    {
-      if (yyn == 0 || yyn == YYTABLE_NINF)
-	goto yyerrlab;
-      yyn = -yyn;
-      goto yyreduce;
-    }
-
-  if (yyn == YYFINAL)
-    YYACCEPT;
-
-  /* Count tokens shifted since error; after three, turn off error
-     status.  */
-  if (yyerrstatus)
-    yyerrstatus--;
-
-  /* Shift the look-ahead token.  */
-  YY_SYMBOL_PRINT ("Shifting", yytoken, &yylval, &yylloc);
-
-  /* Discard the shifted token unless it is eof.  */
-  if (yychar != YYEOF)
-    yychar = YYEMPTY;
-
-  yystate = yyn;
-  *++yyvsp = yylval;
-
-  goto yynewstate;
-
-
-/*-----------------------------------------------------------.
-| yydefault -- do the default action for the current state.  |
-`-----------------------------------------------------------*/
-yydefault:
-  yyn = yydefact[yystate];
-  if (yyn == 0)
-    goto yyerrlab;
-  goto yyreduce;
-
-
-/*-----------------------------.
-| yyreduce -- Do a reduction.  |
-`-----------------------------*/
-yyreduce:
-  /* yyn is the number of a rule to reduce with.  */
-  yylen = yyr2[yyn];
-
-  /* If YYLEN is nonzero, implement the default value of the action:
-     `$$ = $1'.
-
-     Otherwise, the following line sets YYVAL to garbage.
-     This behavior is undocumented and Bison
-     users should not rely upon it.  Assigning to YYVAL
-     unconditionally makes the parser a bit smaller, and it avoids a
-     GCC warning that YYVAL may be used uninitialized.  */
-  yyval = yyvsp[1-yylen];
-
-
-  YY_REDUCE_PRINT (yyn);
-  switch (yyn)
-    {
-        case 6:
-#line 73 "parse.y"
-    {
-		    id_str = (yyvsp[(2) - (2)].string);
-		}
-    break;
-
-  case 7:
-#line 79 "parse.y"
-    {
-		    base_id = name2number((yyvsp[(2) - (2)].string));
-		    strlcpy(name, (yyvsp[(2) - (2)].string), sizeof(name));
-		    free((yyvsp[(2) - (2)].string));
-		}
-    break;
-
-  case 8:
-#line 85 "parse.y"
-    {
-		    base_id = name2number((yyvsp[(2) - (3)].string));
-		    strlcpy(name, (yyvsp[(3) - (3)].string), sizeof(name));
-		    free((yyvsp[(2) - (3)].string));
-		    free((yyvsp[(3) - (3)].string));
-		}
-    break;
-
-  case 11:
-#line 98 "parse.y"
-    {
-			number = (yyvsp[(2) - (2)].number);
-		}
-    break;
-
-  case 12:
-#line 102 "parse.y"
-    {
-		    free(prefix);
-		    asprintf (&prefix, "%s_", (yyvsp[(2) - (2)].string));
-		    if (prefix == NULL)
-			errx(1, "malloc");
-		    free((yyvsp[(2) - (2)].string));
-		}
-    break;
-
-  case 13:
-#line 110 "parse.y"
-    {
-		    prefix = realloc(prefix, 1);
-		    if (prefix == NULL)
-			errx(1, "malloc");
-		    *prefix = '\0';
-		}
-    break;
-
-  case 14:
-#line 117 "parse.y"
-    {
-		    struct error_code *ec = malloc(sizeof(*ec));
-		    
-		    if (ec == NULL)
-			errx(1, "malloc");
-
-		    ec->next = NULL;
-		    ec->number = number;
-		    if(prefix && *prefix != '\0') {
-			asprintf (&ec->name, "%s%s", prefix, (yyvsp[(2) - (4)].string));
-			if (ec->name == NULL)
-			    errx(1, "malloc");
-			free((yyvsp[(2) - (4)].string));
-		    } else
-			ec->name = (yyvsp[(2) - (4)].string);
-		    ec->string = (yyvsp[(4) - (4)].string);
-		    APPEND(codes, ec);
-		    number++;
-		}
-    break;
-
-  case 15:
-#line 137 "parse.y"
-    {
-			YYACCEPT;
-		}
-    break;
-
-
-/* Line 1267 of yacc.c.  */
-#line 1470 "parse.c"
-      default: break;
-    }
-  YY_SYMBOL_PRINT ("-> $$ =", yyr1[yyn], &yyval, &yyloc);
-
-  YYPOPSTACK (yylen);
-  yylen = 0;
-  YY_STACK_PRINT (yyss, yyssp);
-
-  *++yyvsp = yyval;
-
-
-  /* Now `shift' the result of the reduction.  Determine what state
-     that goes to, based on the state we popped back to and the rule
-     number reduced by.  */
-
-  yyn = yyr1[yyn];
-
-  yystate = yypgoto[yyn - YYNTOKENS] + *yyssp;
-  if (0 <= yystate && yystate <= YYLAST && yycheck[yystate] == *yyssp)
-    yystate = yytable[yystate];
-  else
-    yystate = yydefgoto[yyn - YYNTOKENS];
-
-  goto yynewstate;
-
-
-/*------------------------------------.
-| yyerrlab -- here on detecting error |
-`------------------------------------*/
-yyerrlab:
-  /* If not already recovering from an error, report this error.  */
-  if (!yyerrstatus)
-    {
-      ++yynerrs;
-#if ! YYERROR_VERBOSE
-      yyerror (YY_("syntax error"));
-#else
-      {
-	YYSIZE_T yysize = yysyntax_error (0, yystate, yychar);
-	if (yymsg_alloc < yysize && yymsg_alloc < YYSTACK_ALLOC_MAXIMUM)
-	  {
-	    YYSIZE_T yyalloc = 2 * yysize;
-	    if (! (yysize <= yyalloc && yyalloc <= YYSTACK_ALLOC_MAXIMUM))
-	      yyalloc = YYSTACK_ALLOC_MAXIMUM;
-	    if (yymsg != yymsgbuf)
-	      YYSTACK_FREE (yymsg);
-	    yymsg = (char *) YYSTACK_ALLOC (yyalloc);
-	    if (yymsg)
-	      yymsg_alloc = yyalloc;
-	    else
-	      {
-		yymsg = yymsgbuf;
-		yymsg_alloc = sizeof yymsgbuf;
-	      }
-	  }
-
-	if (0 < yysize && yysize <= yymsg_alloc)
-	  {
-	    (void) yysyntax_error (yymsg, yystate, yychar);
-	    yyerror (yymsg);
-	  }
-	else
-	  {
-	    yyerror (YY_("syntax error"));
-	    if (yysize != 0)
-	      goto yyexhaustedlab;
-	  }
-      }
-#endif
-    }
-
-
-
-  if (yyerrstatus == 3)
-    {
-      /* If just tried and failed to reuse look-ahead token after an
-	 error, discard it.  */
-
-      if (yychar <= YYEOF)
-	{
-	  /* Return failure if at end of input.  */
-	  if (yychar == YYEOF)
-	    YYABORT;
-	}
-      else
-	{
-	  yydestruct ("Error: discarding",
-		      yytoken, &yylval);
-	  yychar = YYEMPTY;
-	}
-    }
-
-  /* Else will try to reuse look-ahead token after shifting the error
-     token.  */
-  goto yyerrlab1;
-
-
-/*---------------------------------------------------.
-| yyerrorlab -- error raised explicitly by YYERROR.  |
-`---------------------------------------------------*/
-yyerrorlab:
-
-  /* Pacify compilers like GCC when the user code never invokes
-     YYERROR and the label yyerrorlab therefore never appears in user
-     code.  */
-  if (/*CONSTCOND*/ 0)
-     goto yyerrorlab;
-
-  /* Do not reclaim the symbols of the rule which action triggered
-     this YYERROR.  */
-  YYPOPSTACK (yylen);
-  yylen = 0;
-  YY_STACK_PRINT (yyss, yyssp);
-  yystate = *yyssp;
-  goto yyerrlab1;
-
-
-/*-------------------------------------------------------------.
-| yyerrlab1 -- common code for both syntax error and YYERROR.  |
-`-------------------------------------------------------------*/
-yyerrlab1:
-  yyerrstatus = 3;	/* Each real token shifted decrements this.  */
-
-  for (;;)
-    {
-      yyn = yypact[yystate];
-      if (yyn != YYPACT_NINF)
-	{
-	  yyn += YYTERROR;
-	  if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR)
-	    {
-	      yyn = yytable[yyn];
-	      if (0 < yyn)
-		break;
-	    }
-	}
-
-      /* Pop the current state because it cannot handle the error token.  */
-      if (yyssp == yyss)
-	YYABORT;
-
-
-      yydestruct ("Error: popping",
-		  yystos[yystate], yyvsp);
-      YYPOPSTACK (1);
-      yystate = *yyssp;
-      YY_STACK_PRINT (yyss, yyssp);
-    }
-
-  if (yyn == YYFINAL)
-    YYACCEPT;
-
-  *++yyvsp = yylval;
-
-
-  /* Shift the error token.  */
-  YY_SYMBOL_PRINT ("Shifting", yystos[yyn], yyvsp, yylsp);
-
-  yystate = yyn;
-  goto yynewstate;
-
-
-/*-------------------------------------.
-| yyacceptlab -- YYACCEPT comes here.  |
-`-------------------------------------*/
-yyacceptlab:
-  yyresult = 0;
-  goto yyreturn;
-
-/*-----------------------------------.
-| yyabortlab -- YYABORT comes here.  |
-`-----------------------------------*/
-yyabortlab:
-  yyresult = 1;
-  goto yyreturn;
-
-#ifndef yyoverflow
-/*-------------------------------------------------.
-| yyexhaustedlab -- memory exhaustion comes here.  |
-`-------------------------------------------------*/
-yyexhaustedlab:
-  yyerror (YY_("memory exhausted"));
-  yyresult = 2;
-  /* Fall through.  */
-#endif
-
-yyreturn:
-  if (yychar != YYEOF && yychar != YYEMPTY)
-     yydestruct ("Cleanup: discarding lookahead",
-		 yytoken, &yylval);
-  /* Do not reclaim the symbols of the rule which action triggered
-     this YYABORT or YYACCEPT.  */
-  YYPOPSTACK (yylen);
-  YY_STACK_PRINT (yyss, yyssp);
-  while (yyssp != yyss)
-    {
-      yydestruct ("Cleanup: popping",
-		  yystos[*yyssp], yyvsp);
-      YYPOPSTACK (1);
-    }
-#ifndef yyoverflow
-  if (yyss != yyssa)
-    YYSTACK_FREE (yyss);
-#endif
-#if YYERROR_VERBOSE
-  if (yymsg != yymsgbuf)
-    YYSTACK_FREE (yymsg);
-#endif
-  /* Make sure YYID is used.  */
-  return YYID (yyresult);
-}
-
-
-#line 142 "parse.y"
-
-
-static long
-name2number(const char *str)
-{
-    const char *p;
-    long num = 0;
-    const char *x = "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
-	"abcdefghijklmnopqrstuvwxyz0123456789_";
-    if(strlen(str) > 4) {
-	yyerror("table name too long");
-	return 0;
-    }
-    for(p = str; *p; p++){
-	char *q = strchr(x, *p);
-	if(q == NULL) {
-	    yyerror("invalid character in table name");
-	    return 0;
-	}
-	num = (num << 6) + (q - x) + 1;
-    }
-    num <<= 8;
-    if(num > 0x7fffffff)
-	num = -(0xffffffff - num + 1);
-    return num;
-}
-
-void
-yyerror (char *s)
-{
-     error_message ("%s\n", s);
-}
-
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/com_err/parse.h
--- a/head/contrib/com_err/parse.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,81 +0,0 @@
-/* A Bison parser, made by GNU Bison 2.3.  */
-
-/* Skeleton interface for Bison's Yacc-like parsers in C
-
-   Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005, 2006
-   Free Software Foundation, Inc.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street, Fifth Floor,
-   Boston, MA 02110-1301, USA.  */
-
-/* As a special exception, you may create a larger work that contains
-   part or all of the Bison parser skeleton and distribute that work
-   under terms of your choice, so long as that work isn't itself a
-   parser generator using the skeleton or a modified version thereof
-   as a parser skeleton.  Alternatively, if you modify or redistribute
-   the parser skeleton itself, you may (at your option) remove this
-   special exception, which will cause the skeleton and the resulting
-   Bison output files to be licensed under the GNU General Public
-   License without this special exception.
-
-   This special exception was added by the Free Software Foundation in
-   version 2.2 of Bison.  */
-
-/* Tokens.  */
-#ifndef YYTOKENTYPE
-# define YYTOKENTYPE
-   /* Put the tokens into the symbol table, so that GDB and other debuggers
-      know about them.  */
-   enum yytokentype {
-     ET = 258,
-     INDEX = 259,
-     PREFIX = 260,
-     EC = 261,
-     ID = 262,
-     END = 263,
-     STRING = 264,
-     NUMBER = 265
-   };
-#endif
-/* Tokens.  */
-#define ET 258
-#define INDEX 259
-#define PREFIX 260
-#define EC 261
-#define ID 262
-#define END 263
-#define STRING 264
-#define NUMBER 265
-
-
-
-
-#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
-typedef union YYSTYPE
-#line 53 "parse.y"
-{
-  char *string;
-  int number;
-}
-/* Line 1529 of yacc.c.  */
-#line 74 "parse.h"
-	YYSTYPE;
-# define yystype YYSTYPE /* obsolescent; will be withdrawn */
-# define YYSTYPE_IS_DECLARED 1
-# define YYSTYPE_IS_TRIVIAL 1
-#endif
-
-extern YYSTYPE yylval;
-
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/libcxxrt/typeinfo
--- a/head/contrib/libcxxrt/typeinfo	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,26 +0,0 @@
-namespace std
-{
-	/**
-	  * Standard type info class.  The layout of this class is specified by the
-	  * ABI.
-	  */
-	class type_info
-	{
-		public:
-		/**
-		 * Virtual destructor.  This class must have one virtual function to
-		 * ensure that it has a vtable.
-		 */
-		virtual ~type_info();
-		bool operator==(const type_info &) const;
-		bool operator!=(const type_info &) const;
-		bool before(const type_info &) const;
-		const char* name() const;
-		type_info();
-		private:
-		type_info(const type_info& rhs);
-		type_info& operator= (const type_info& rhs);
-		const char *__type_name;
-	};
-}
-
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/include/llvm/ADT/VectorExtras.h
--- a/head/contrib/llvm/include/llvm/ADT/VectorExtras.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,41 +0,0 @@
-//===-- llvm/ADT/VectorExtras.h - Helpers for std::vector -------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains helper functions which are useful for working with the
-// std::vector class.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_ADT_VECTOREXTRAS_H
-#define LLVM_ADT_VECTOREXTRAS_H
-
-#include <cstdarg>
-#include <vector>
-
-namespace llvm {
-
-/// make_vector - Helper function which is useful for building temporary vectors
-/// to pass into type construction of CallInst ctors.  This turns a null
-/// terminated list of pointers (or other value types) into a real live vector.
-///
-template<typename T>
-inline std::vector<T> make_vector(T A, ...) {
-  va_list Args;
-  va_start(Args, A);
-  std::vector<T> Result;
-  Result.push_back(A);
-  while (T Val = va_arg(Args, T))
-    Result.push_back(Val);
-  va_end(Args);
-  return Result;
-}
-
-} // End llvm namespace
-
-#endif
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/include/llvm/CodeGen/BinaryObject.h
--- a/head/contrib/llvm/include/llvm/CodeGen/BinaryObject.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,353 +0,0 @@
-//===-- llvm/CodeGen/BinaryObject.h - Binary Object. -----------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines a Binary Object Aka. "blob" for holding data from code
-// generators, ready for data to the object module code writters.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_CODEGEN_BINARYOBJECT_H
-#define LLVM_CODEGEN_BINARYOBJECT_H
-
-#include "llvm/CodeGen/MachineRelocation.h"
-#include "llvm/Support/DataTypes.h"
-
-#include <string>
-#include <vector>
-
-namespace llvm {
-
-typedef std::vector<uint8_t> BinaryData;
-
-class BinaryObject {
-protected:
-  std::string Name;
-  bool IsLittleEndian;
-  bool Is64Bit;
-  BinaryData Data;
-  std::vector<MachineRelocation> Relocations;
-
-public:
-  /// Constructors and destructor
-  BinaryObject() {}
-
-  BinaryObject(bool isLittleEndian, bool is64Bit)
-    : IsLittleEndian(isLittleEndian), Is64Bit(is64Bit) {}
-
-  BinaryObject(const std::string &name, bool isLittleEndian, bool is64Bit)
-    : Name(name), IsLittleEndian(isLittleEndian), Is64Bit(is64Bit) {}
-
-  ~BinaryObject() {}
-
-  /// getName - get name of BinaryObject
-  inline std::string getName() const { return Name; }
-
-  /// get size of binary data
-  size_t size() const {
-    return Data.size();
-  }
-
-  /// get binary data
-  BinaryData& getData() {
-    return Data;
-  }
-
-  /// get machine relocations
-  const std::vector<MachineRelocation>& getRelocations() const {
-    return Relocations;
-  }
-
-  /// hasRelocations - Return true if 'Relocations' is not empty
-  bool hasRelocations() const {
-    return !Relocations.empty();
-  }
-
-  /// emitZeros - This callback is invoked to emit a arbitrary number 
-  /// of zero bytes to the data stream.
-  inline void emitZeros(unsigned Size) {
-    for (unsigned i=0; i < Size; ++i)
-      emitByte(0);
-  }
-
-  /// emitByte - This callback is invoked when a byte needs to be
-  /// written to the data stream.
-  inline void emitByte(uint8_t B) {
-    Data.push_back(B);
-  }
-
-  /// emitWord16 - This callback is invoked when a 16-bit word needs to be
-  /// written to the data stream in correct endian format and correct size.
-  inline void emitWord16(uint16_t W) {
-    if (IsLittleEndian)
-      emitWord16LE(W);
-    else
-      emitWord16BE(W);
-  }
-
-  /// emitWord16LE - This callback is invoked when a 16-bit word needs to be
-  /// written to the data stream in correct endian format and correct size.
-  inline void emitWord16LE(uint16_t W) {
-    Data.push_back((uint8_t)(W >> 0));
-    Data.push_back((uint8_t)(W >> 8));
-  }
-
-  /// emitWord16BE - This callback is invoked when a 16-bit word needs to be
-  /// written to the data stream in correct endian format and correct size.
-  inline void emitWord16BE(uint16_t W) {
-    Data.push_back((uint8_t)(W >> 8));
-    Data.push_back((uint8_t)(W >> 0));
-  }
-
-  /// emitWord - This callback is invoked when a word needs to be
-  /// written to the data stream in correct endian format and correct size.
-  inline void emitWord(uint64_t W) {
-    if (!Is64Bit)
-      emitWord32(W);
-    else
-      emitWord64(W);
-  }
-
-  /// emitWord32 - This callback is invoked when a 32-bit word needs to be
-  /// written to the data stream in correct endian format.
-  inline void emitWord32(uint32_t W) {
-    if (IsLittleEndian)
-      emitWordLE(W);
-    else
-      emitWordBE(W);
-  }
-
-  /// emitWord64 - This callback is invoked when a 32-bit word needs to be
-  /// written to the data stream in correct endian format.
-  inline void emitWord64(uint64_t W) {
-    if (IsLittleEndian)
-      emitDWordLE(W);
-    else
-      emitDWordBE(W);
-  }
-
-  /// emitWord64 - This callback is invoked when a x86_fp80 needs to be
-  /// written to the data stream in correct endian format.
-  inline void emitWordFP80(const uint64_t *W, unsigned PadSize) {
-    if (IsLittleEndian) {
-      emitWord64(W[0]);
-      emitWord16(W[1]);  
-    } else {
-      emitWord16(W[1]);  
-      emitWord64(W[0]);
-    }
-    emitZeros(PadSize);
-  }
-
-  /// emitWordLE - This callback is invoked when a 32-bit word needs to be
-  /// written to the data stream in little-endian format.
-  inline void emitWordLE(uint32_t W) {
-    Data.push_back((uint8_t)(W >>  0));
-    Data.push_back((uint8_t)(W >>  8));
-    Data.push_back((uint8_t)(W >> 16));
-    Data.push_back((uint8_t)(W >> 24));
-  }
-
-  /// emitWordBE - This callback is invoked when a 32-bit word needs to be
-  /// written to the data stream in big-endian format.
-  ///
-  inline void emitWordBE(uint32_t W) {
-    Data.push_back((uint8_t)(W >> 24));
-    Data.push_back((uint8_t)(W >> 16));
-    Data.push_back((uint8_t)(W >>  8));
-    Data.push_back((uint8_t)(W >>  0));
-  }
-
-  /// emitDWordLE - This callback is invoked when a 64-bit word needs to be
-  /// written to the data stream in little-endian format.
-  inline void emitDWordLE(uint64_t W) {
-    Data.push_back((uint8_t)(W >>  0));
-    Data.push_back((uint8_t)(W >>  8));
-    Data.push_back((uint8_t)(W >> 16));
-    Data.push_back((uint8_t)(W >> 24));
-    Data.push_back((uint8_t)(W >> 32));
-    Data.push_back((uint8_t)(W >> 40));
-    Data.push_back((uint8_t)(W >> 48));
-    Data.push_back((uint8_t)(W >> 56));
-  }
-
-  /// emitDWordBE - This callback is invoked when a 64-bit word needs to be
-  /// written to the data stream in big-endian format.
-  inline void emitDWordBE(uint64_t W) {
-    Data.push_back((uint8_t)(W >> 56));
-    Data.push_back((uint8_t)(W >> 48));
-    Data.push_back((uint8_t)(W >> 40));
-    Data.push_back((uint8_t)(W >> 32));
-    Data.push_back((uint8_t)(W >> 24));
-    Data.push_back((uint8_t)(W >> 16));
-    Data.push_back((uint8_t)(W >>  8));
-    Data.push_back((uint8_t)(W >>  0));
-  }
-
-  /// fixByte - This callback is invoked when a byte needs to be
-  /// fixup the buffer.
-  inline void fixByte(uint8_t B, uint32_t offset) {
-    Data[offset] = B;
-  }
-
-  /// fixWord16 - This callback is invoked when a 16-bit word needs to
-  /// fixup the data stream in correct endian format.
-  inline void fixWord16(uint16_t W, uint32_t offset) {
-    if (IsLittleEndian)
-      fixWord16LE(W, offset);
-    else
-      fixWord16BE(W, offset);
-  }
-
-  /// emitWord16LE - This callback is invoked when a 16-bit word needs to
-  /// fixup the data stream in little endian format.
-  inline void fixWord16LE(uint16_t W, uint32_t offset) {
-    Data[offset]   = (uint8_t)(W >> 0);
-    Data[++offset] = (uint8_t)(W >> 8);
-  }
-
-  /// fixWord16BE - This callback is invoked when a 16-bit word needs to
-  /// fixup data stream in big endian format.
-  inline void fixWord16BE(uint16_t W, uint32_t offset) {
-    Data[offset]   = (uint8_t)(W >> 8);
-    Data[++offset] = (uint8_t)(W >> 0);
-  }
-
-  /// emitWord - This callback is invoked when a word needs to
-  /// fixup the data in correct endian format and correct size.
-  inline void fixWord(uint64_t W, uint32_t offset) {
-    if (!Is64Bit)
-      fixWord32(W, offset);
-    else
-      fixWord64(W, offset);
-  }
-
-  /// fixWord32 - This callback is invoked when a 32-bit word needs to
-  /// fixup the data in correct endian format.
-  inline void fixWord32(uint32_t W, uint32_t offset) {
-    if (IsLittleEndian)
-      fixWord32LE(W, offset);
-    else
-      fixWord32BE(W, offset);
-  }
-
-  /// fixWord32LE - This callback is invoked when a 32-bit word needs to
-  /// fixup the data in little endian format.
-  inline void fixWord32LE(uint32_t W, uint32_t offset) {
-    Data[offset]   = (uint8_t)(W >>  0);
-    Data[++offset] = (uint8_t)(W >>  8);
-    Data[++offset] = (uint8_t)(W >> 16);
-    Data[++offset] = (uint8_t)(W >> 24);
-  }
-
-  /// fixWord32BE - This callback is invoked when a 32-bit word needs to
-  /// fixup the data in big endian format.
-  inline void fixWord32BE(uint32_t W, uint32_t offset) {
-    Data[offset]   = (uint8_t)(W >> 24);
-    Data[++offset] = (uint8_t)(W >> 16);
-    Data[++offset] = (uint8_t)(W >>  8);
-    Data[++offset] = (uint8_t)(W >>  0);
-  }
-
-  /// fixWord64 - This callback is invoked when a 64-bit word needs to
-  /// fixup the data in correct endian format.
-  inline void fixWord64(uint64_t W, uint32_t offset) {
-    if (IsLittleEndian)
-      fixWord64LE(W, offset);
-    else
-      fixWord64BE(W, offset);
-  }
-
-  /// fixWord64BE - This callback is invoked when a 64-bit word needs to
-  /// fixup the data in little endian format.
-  inline void fixWord64LE(uint64_t W, uint32_t offset) {
-    Data[offset]   = (uint8_t)(W >>  0);
-    Data[++offset] = (uint8_t)(W >>  8);
-    Data[++offset] = (uint8_t)(W >> 16);
-    Data[++offset] = (uint8_t)(W >> 24);
-    Data[++offset] = (uint8_t)(W >> 32);
-    Data[++offset] = (uint8_t)(W >> 40);
-    Data[++offset] = (uint8_t)(W >> 48);
-    Data[++offset] = (uint8_t)(W >> 56);
-  }
-
-  /// fixWord64BE - This callback is invoked when a 64-bit word needs to
-  /// fixup the data in big endian format.
-  inline void fixWord64BE(uint64_t W, uint32_t offset) {
-    Data[offset]   = (uint8_t)(W >> 56);
-    Data[++offset] = (uint8_t)(W >> 48);
-    Data[++offset] = (uint8_t)(W >> 40);
-    Data[++offset] = (uint8_t)(W >> 32);
-    Data[++offset] = (uint8_t)(W >> 24);
-    Data[++offset] = (uint8_t)(W >> 16);
-    Data[++offset] = (uint8_t)(W >>  8);
-    Data[++offset] = (uint8_t)(W >>  0);
-  }
-
-  /// emitAlignment - Pad the data to the specified alignment.
-  void emitAlignment(unsigned Alignment, uint8_t fill = 0) {
-    if (Alignment <= 1) return;
-    unsigned PadSize = -Data.size() & (Alignment-1);
-    for (unsigned i = 0; i<PadSize; ++i)
-      Data.push_back(fill);
-  }
-
-  /// emitULEB128Bytes - This callback is invoked when a ULEB128 needs to be
-  /// written to the data stream.
-  void emitULEB128Bytes(uint64_t Value) {
-    do {
-      uint8_t Byte = (uint8_t)(Value & 0x7f);
-      Value >>= 7;
-      if (Value) Byte |= 0x80;
-      emitByte(Byte);
-    } while (Value);
-  }
-
-  /// emitSLEB128Bytes - This callback is invoked when a SLEB128 needs to be
-  /// written to the data stream.
-  void emitSLEB128Bytes(int64_t Value) {
-    int Sign = Value >> (8 * sizeof(Value) - 1);
-    bool IsMore;
-
-    do {
-      uint8_t Byte = (uint8_t)(Value & 0x7f);
-      Value >>= 7;
-      IsMore = Value != Sign || ((Byte ^ Sign) & 0x40) != 0;
-      if (IsMore) Byte |= 0x80;
-      emitByte(Byte);
-    } while (IsMore);
-  }
-
-  /// emitString - This callback is invoked when a String needs to be
-  /// written to the data stream.
-  void emitString(const std::string &String) {
-    for (unsigned i = 0, N = static_cast<unsigned>(String.size()); i<N; ++i) {
-      unsigned char C = String[i];
-      emitByte(C);
-    }
-    emitByte(0);
-  }
-
-  /// getCurrentPCOffset - Return the offset from the start of the emitted
-  /// buffer that we are currently writing to.
-  uintptr_t getCurrentPCOffset() const {
-    return Data.size();
-  }
-
-  /// addRelocation - Whenever a relocatable address is needed, it should be
-  /// noted with this interface.
-  void addRelocation(const MachineRelocation& relocation) {
-    Relocations.push_back(relocation);
-  }
-
-};
-
-} // end namespace llvm
-
-#endif
-
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/include/llvm/CodeGen/ObjectCodeEmitter.h
--- a/head/contrib/llvm/include/llvm/CodeGen/ObjectCodeEmitter.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,171 +0,0 @@
-//===-- llvm/CodeGen/ObjectCodeEmitter.h - Object Code Emitter -*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-//  Generalized Object Code Emitter, works with ObjectModule and BinaryObject.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_CODEGEN_OBJECTCODEEMITTER_H
-#define LLVM_CODEGEN_OBJECTCODEEMITTER_H
-
-#include "llvm/CodeGen/MachineCodeEmitter.h"
-
-namespace llvm {
-
-class BinaryObject;
-class MachineBasicBlock;
-class MachineCodeEmitter;
-class MachineFunction;
-class MachineConstantPool;
-class MachineJumpTableInfo;
-class MachineModuleInfo;
-
-class ObjectCodeEmitter : public MachineCodeEmitter {
-protected:
-
-  /// Binary Object (Section or Segment) we are emitting to.
-  BinaryObject *BO;
-
-  /// MBBLocations - This vector is a mapping from MBB ID's to their address.
-  /// It is filled in by the StartMachineBasicBlock callback and queried by
-  /// the getMachineBasicBlockAddress callback.
-  std::vector<uintptr_t> MBBLocations;
-
-  /// LabelLocations - This vector is a mapping from Label ID's to their 
-  /// address.
-  std::vector<uintptr_t> LabelLocations;
-
-  /// CPLocations - This is a map of constant pool indices to offsets from the
-  /// start of the section for that constant pool index.
-  std::vector<uintptr_t> CPLocations;
-
-  /// CPSections - This is a map of constant pool indices to the Section
-  /// containing the constant pool entry for that index.
-  std::vector<uintptr_t> CPSections;
-
-  /// JTLocations - This is a map of jump table indices to offsets from the
-  /// start of the section for that jump table index.
-  std::vector<uintptr_t> JTLocations;
-
-public:
-  ObjectCodeEmitter();
-  ObjectCodeEmitter(BinaryObject *bo);
-  virtual ~ObjectCodeEmitter();
-
-  /// setBinaryObject - set the BinaryObject we are writting to
-  void setBinaryObject(BinaryObject *bo);
-
-  /// emitByte - This callback is invoked when a byte needs to be 
-  /// written to the data stream, without buffer overflow testing.
-  void emitByte(uint8_t B);
-
-  /// emitWordLE - This callback is invoked when a 32-bit word needs to be
-  /// written to the data stream in little-endian format.
-  void emitWordLE(uint32_t W);
-
-  /// emitWordBE - This callback is invoked when a 32-bit word needs to be
-  /// written to the data stream in big-endian format.
-  void emitWordBE(uint32_t W);
-
-  /// emitDWordLE - This callback is invoked when a 64-bit word needs to be
-  /// written to the data stream in little-endian format.
-  void emitDWordLE(uint64_t W);
-
-  /// emitDWordBE - This callback is invoked when a 64-bit word needs to be
-  /// written to the data stream in big-endian format.
-  void emitDWordBE(uint64_t W);
-
-  /// emitAlignment - Move the CurBufferPtr pointer up to the specified
-  /// alignment (saturated to BufferEnd of course).
-  void emitAlignment(unsigned Alignment = 0, uint8_t fill = 0);
-
-  /// emitULEB128Bytes - This callback is invoked when a ULEB128 needs to be
-  /// written to the data stream.
-  void emitULEB128Bytes(uint64_t Value);
-
-  /// emitSLEB128Bytes - This callback is invoked when a SLEB128 needs to be
-  /// written to the data stream.
-  void emitSLEB128Bytes(uint64_t Value);
-
-  /// emitString - This callback is invoked when a String needs to be
-  /// written to the data stream.
-  void emitString(const std::string &String);
-
-  /// getCurrentPCValue - This returns the address that the next emitted byte
-  /// will be output to.
-  uintptr_t getCurrentPCValue() const;
-
-  /// getCurrentPCOffset - Return the offset from the start of the emitted
-  /// buffer that we are currently writing to.
-  uintptr_t getCurrentPCOffset() const;
-
-  /// addRelocation - Whenever a relocatable address is needed, it should be
-  /// noted with this interface.
-  void addRelocation(const MachineRelocation& relocation);
-
-  /// earlyResolveAddresses - True if the code emitter can use symbol addresses 
-  /// during code emission time. The JIT is capable of doing this because it
-  /// creates jump tables or constant pools in memory on the fly while the
-  /// object code emitters rely on a linker to have real addresses and should
-  /// use relocations instead.
-  bool earlyResolveAddresses() const { return false; }
-
-  /// startFunction - This callback is invoked when the specified function is
-  /// about to be code generated.  This initializes the BufferBegin/End/Ptr
-  /// fields.
-  virtual void startFunction(MachineFunction &F) = 0;
-
-  /// finishFunction - This callback is invoked when the specified function has
-  /// finished code generation.  If a buffer overflow has occurred, this method
-  /// returns true (the callee is required to try again), otherwise it returns
-  /// false.
-  virtual bool finishFunction(MachineFunction &F) = 0;
-
-  /// StartMachineBasicBlock - This should be called by the target when a new
-  /// basic block is about to be emitted.  This way the MCE knows where the
-  /// start of the block is, and can implement getMachineBasicBlockAddress.
-  virtual void StartMachineBasicBlock(MachineBasicBlock *MBB);
-
-  /// getMachineBasicBlockAddress - Return the address of the specified
-  /// MachineBasicBlock, only usable after the label for the MBB has been
-  /// emitted.
-  virtual uintptr_t getMachineBasicBlockAddress(MachineBasicBlock *MBB) const;
-
-  /// emitJumpTables - Emit all the jump tables for a given jump table info
-  /// record to the appropriate section.
-  virtual void emitJumpTables(MachineJumpTableInfo *MJTI) = 0;
-
-  /// getJumpTableEntryAddress - Return the address of the jump table with index
-  /// 'Index' in the function that last called initJumpTableInfo.
-  virtual uintptr_t getJumpTableEntryAddress(unsigned Index) const;
-
-  /// emitConstantPool - For each constant pool entry, figure out which section
-  /// the constant should live in, allocate space for it, and emit it to the 
-  /// Section data buffer.
-  virtual void emitConstantPool(MachineConstantPool *MCP) = 0;
-
-  /// getConstantPoolEntryAddress - Return the address of the 'Index' entry in
-  /// the constant pool that was last emitted with the emitConstantPool method.
-  virtual uintptr_t getConstantPoolEntryAddress(unsigned Index) const;
-
-  /// getConstantPoolEntrySection - Return the section of the 'Index' entry in
-  /// the constant pool that was last emitted with the emitConstantPool method.
-  virtual uintptr_t getConstantPoolEntrySection(unsigned Index) const;
-
-  /// Specifies the MachineModuleInfo object. This is used for exception handling
-  /// purposes.
-  virtual void setModuleInfo(MachineModuleInfo* Info) = 0;
-  // to be implemented or depreciated with MachineModuleInfo
-
-}; // end class ObjectCodeEmitter
-
-} // end namespace llvm
-
-#endif
-
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/include/llvm/DebugInfoProbe.h
--- a/head/contrib/llvm/include/llvm/DebugInfoProbe.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,67 +0,0 @@
-//===-- DebugInfoProbe.h - DebugInfo Probe ----------------------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines a probe, DebugInfoProbe, that can be used by pass
-// manager to analyze how optimizer is treating debugging information.
-// 
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_TRANSFORMS_UTILS_DEBUGINFOPROBE_H
-#define LLVM_TRANSFORMS_UTILS_DEBUGINFOPROBE_H
-
-#include "llvm/ADT/StringMap.h"
-
-namespace llvm {
-  class Function;
-  class Pass;
-  class DebugInfoProbeImpl;
-
-  /// DebugInfoProbe - This class provides a interface to monitor
-  /// how an optimization pass is preserving debugging information.
-  class DebugInfoProbe {
-    public:
-    DebugInfoProbe();
-    ~DebugInfoProbe();
-
-    /// initialize - Collect information before running an optimization pass.
-    void initialize(StringRef PName, Function &F);
-
-    /// finalize - Collect information after running an optimization pass. This
-    /// must be used after initialization.
-    void finalize(Function &F);
-
-    /// report - Report findings. This should be invoked after finalize.
-    void report();
-
-    private:
-    DebugInfoProbeImpl *pImpl;
-  };
-
-  /// DebugInfoProbeInfo - This class provides an interface that a pass manager
-  /// can use to manage debug info probes.
-  class DebugInfoProbeInfo {
-    StringMap<DebugInfoProbe *> Probes;
-  public:
-    DebugInfoProbeInfo() {}
-
-    /// ~DebugInfoProbeInfo - Report data collected by all probes before deleting
-    /// them.
-    ~DebugInfoProbeInfo();
-
-    /// initialize - Collect information before running an optimization pass.
-    void initialize(Pass *P, Function &F);
-
-    /// finalize - Collect information after running an optimization pass. This
-    /// must be used after initialization.
-    void finalize(Pass *P, Function &F);
-  };
-
-} // End llvm namespace
-
-#endif
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/include/llvm/IntrinsicsAlpha.td
--- a/head/contrib/llvm/include/llvm/IntrinsicsAlpha.td	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,18 +0,0 @@
-//===- IntrinsicsAlpha.td - Defines Alpha intrinsics -------*- tablegen -*-===//
-// 
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-// 
-//===----------------------------------------------------------------------===//
-//
-// This file defines all of the Alpha-specific intrinsics.
-//
-//===----------------------------------------------------------------------===//
-
-
-let TargetPrefix = "alpha" in {  // All intrinsics start with "llvm.alpha.".
-  def int_alpha_umulh : GCCBuiltin<"__builtin_alpha_umulh">,
-              Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/include/llvm/Transforms/Utils/BasicInliner.h
--- a/head/contrib/llvm/include/llvm/Transforms/Utils/BasicInliner.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,55 +0,0 @@
-//===- BasicInliner.h - Basic function level inliner ------------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines a simple function based inliner that does not use
-// call graph information. 
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef BASICINLINER_H
-#define BASICINLINER_H
-
-#include "llvm/Analysis/InlineCost.h"
-
-namespace llvm {
-
-  class Function;
-  class TargetData;
-  struct BasicInlinerImpl;
-
-  /// BasicInliner - BasicInliner provides function level inlining interface.
-  /// Clients provide list of functions which are inline without using
-  /// module level call graph information. Note that the BasicInliner is
-  /// free to delete a function if it is inlined into all call sites.
-  class BasicInliner {
-  public:
-    
-    explicit BasicInliner(TargetData *T = NULL);
-    ~BasicInliner();
-
-    /// addFunction - Add function into the list of functions to process.
-    /// All functions must be inserted using this interface before invoking
-    /// inlineFunctions().
-    void addFunction(Function *F);
-
-    /// neverInlineFunction - Sometimes a function is never to be inlined 
-    /// because of one or other reason. 
-    void neverInlineFunction(Function *F);
-
-    /// inlineFuctions - Walk all call sites in all functions supplied by
-    /// client. Inline as many call sites as possible. Delete completely
-    /// inlined functions.
-    void inlineFunctions();
-
-  private:
-    BasicInlinerImpl *Impl;
-  };
-}
-
-#endif
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/CodeGen/ELF.h
--- a/head/contrib/llvm/lib/CodeGen/ELF.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,227 +0,0 @@
-//===-- lib/CodeGen/ELF.h - ELF constants and data structures ---*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This header contains common, non-processor-specific data structures and
-// constants for the ELF file format.
-//
-// The details of the ELF32 bits in this file are largely based on the Tool
-// Interface Standard (TIS) Executable and Linking Format (ELF) Specification
-// Version 1.2, May 1995. The ELF64 is based on HP/Intel definition of the
-// ELF-64 object file format document, Version 1.5 Draft 2 May 27, 1998
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef CODEGEN_ELF_H
-#define CODEGEN_ELF_H
-
-#include "llvm/CodeGen/BinaryObject.h"
-#include "llvm/CodeGen/MachineRelocation.h"
-#include "llvm/Support/ELF.h"
-#include "llvm/Support/DataTypes.h"
-
-namespace llvm {
-  class GlobalValue;
-
-  /// ELFSym - This struct contains information about each symbol that is
-  /// added to logical symbol table for the module.  This is eventually
-  /// turned into a real symbol table in the file.
-  struct ELFSym {
-
-    // ELF symbols are related to llvm ones by being one of the two llvm
-    // types, for the other ones (section, file, func) a null pointer is
-    // assumed by default.
-    union {
-      const GlobalValue *GV;  // If this is a pointer to a GV
-      const char *Ext;        // If this is a pointer to a named symbol
-    } Source;
-
-    // Describes from which source type this ELF symbol comes from,
-    // they can be GlobalValue, ExternalSymbol or neither.
-    enum {
-      isGV,      // The Source.GV field is valid.
-      isExtSym,  // The Source.ExtSym field is valid.
-      isOther    // Not a GlobalValue or External Symbol
-    };
-    unsigned SourceType;
-
-    bool isGlobalValue() const { return SourceType == isGV; }
-    bool isExternalSym() const { return SourceType == isExtSym; }
-
-    // getGlobalValue - If this is a global value which originated the
-    // elf symbol, return a reference to it.
-    const GlobalValue *getGlobalValue() const {
-      assert(SourceType == isGV && "This is not a global value");
-      return Source.GV;
-    }
-
-    // getExternalSym - If this is an external symbol which originated the
-    // elf symbol, return a reference to it.
-    const char *getExternalSymbol() const {
-      assert(SourceType == isExtSym && "This is not an external symbol");
-      return Source.Ext;
-    }
-
-    // getGV - From a global value return a elf symbol to represent it
-    static ELFSym *getGV(const GlobalValue *GV, unsigned Bind,
-                         unsigned Type, unsigned Visibility) {
-      ELFSym *Sym = new ELFSym();
-      Sym->Source.GV = GV;
-      Sym->setBind(Bind);
-      Sym->setType(Type);
-      Sym->setVisibility(Visibility);
-      Sym->SourceType = isGV;
-      return Sym;
-    }
-
-    // getExtSym - Create and return an elf symbol to represent an
-    // external symbol
-    static ELFSym *getExtSym(const char *Ext) {
-      ELFSym *Sym = new ELFSym();
-      Sym->Source.Ext = Ext;
-      Sym->setBind(ELF::STB_GLOBAL);
-      Sym->setType(ELF::STT_NOTYPE);
-      Sym->setVisibility(ELF::STV_DEFAULT);
-      Sym->SourceType = isExtSym;
-      return Sym;
-    }
-
-    // getSectionSym - Returns a elf symbol to represent an elf section
-    static ELFSym *getSectionSym() {
-      ELFSym *Sym = new ELFSym();
-      Sym->setBind(ELF::STB_LOCAL);
-      Sym->setType(ELF::STT_SECTION);
-      Sym->setVisibility(ELF::STV_DEFAULT);
-      Sym->SourceType = isOther;
-      return Sym;
-    }
-
-    // getFileSym - Returns a elf symbol to represent the module identifier
-    static ELFSym *getFileSym() {
-      ELFSym *Sym = new ELFSym();
-      Sym->setBind(ELF::STB_LOCAL);
-      Sym->setType(ELF::STT_FILE);
-      Sym->setVisibility(ELF::STV_DEFAULT);
-      Sym->SectionIdx = 0xfff1;  // ELFSection::SHN_ABS;
-      Sym->SourceType = isOther;
-      return Sym;
-    }
-
-    // getUndefGV - Returns a STT_NOTYPE symbol
-    static ELFSym *getUndefGV(const GlobalValue *GV, unsigned Bind) {
-      ELFSym *Sym = new ELFSym();
-      Sym->Source.GV = GV;
-      Sym->setBind(Bind);
-      Sym->setType(ELF::STT_NOTYPE);
-      Sym->setVisibility(ELF::STV_DEFAULT);
-      Sym->SectionIdx = 0;  //ELFSection::SHN_UNDEF;
-      Sym->SourceType = isGV;
-      return Sym;
-    }
-
-    // ELF specific fields
-    unsigned NameIdx;         // Index in .strtab of name, once emitted.
-    uint64_t Value;
-    unsigned Size;
-    uint8_t Info;
-    uint8_t Other;
-    unsigned short SectionIdx;
-
-    // Symbol index into the Symbol table
-    unsigned SymTabIdx;
-
-    ELFSym() : SourceType(isOther), NameIdx(0), Value(0),
-               Size(0), Info(0), Other(ELF::STV_DEFAULT), SectionIdx(0),
-               SymTabIdx(0) {}
-
-    unsigned getBind() const { return (Info >> 4) & 0xf; }
-    unsigned getType() const { return Info & 0xf; }
-    bool isLocalBind() const { return getBind() == ELF::STB_LOCAL; }
-    bool isFileType() const { return getType() == ELF::STT_FILE; }
-
-    void setBind(unsigned X) {
-      assert(X == (X & 0xF) && "Bind value out of range!");
-      Info = (Info & 0x0F) | (X << 4);
-    }
-
-    void setType(unsigned X) {
-      assert(X == (X & 0xF) && "Type value out of range!");
-      Info = (Info & 0xF0) | X;
-    }
-
-    void setVisibility(unsigned V) {
-      assert(V == (V & 0x3) && "Visibility value out of range!");
-      Other = V;
-    }
-  };
-
-  /// ELFSection - This struct contains information about each section that is
-  /// emitted to the file.  This is eventually turned into the section header
-  /// table at the end of the file.
-  class ELFSection : public BinaryObject {
-    public:
-    // ELF specific fields
-    unsigned NameIdx;   // sh_name - .shstrtab idx of name, once emitted.
-    unsigned Type;      // sh_type - Section contents & semantics 
-    unsigned Flags;     // sh_flags - Section flags.
-    uint64_t Addr;      // sh_addr - The mem addr this section is in.
-    unsigned Offset;    // sh_offset - Offset from the file start
-    unsigned Size;      // sh_size - The section size.
-    unsigned Link;      // sh_link - Section header table index link.
-    unsigned Info;      // sh_info - Auxiliary information.
-    unsigned Align;     // sh_addralign - Alignment of section.
-    unsigned EntSize;   // sh_entsize - Size of entries in the section e
-
-    /// SectionIdx - The number of the section in the Section Table.
-    unsigned short SectionIdx;
-
-    /// Sym - The symbol to represent this section if it has one.
-    ELFSym *Sym;
-
-    /// getSymIndex - Returns the symbol table index of the symbol
-    /// representing this section.
-    unsigned getSymbolTableIndex() const {
-      assert(Sym && "section not present in the symbol table");
-      return Sym->SymTabIdx;
-    }
-
-    ELFSection(const std::string &name, bool isLittleEndian, bool is64Bit)
-      : BinaryObject(name, isLittleEndian, is64Bit), Type(0), Flags(0), Addr(0),
-        Offset(0), Size(0), Link(0), Info(0), Align(0), EntSize(0), Sym(0) {}
-  };
-
-  /// ELFRelocation - This class contains all the information necessary to
-  /// to generate any 32-bit or 64-bit ELF relocation entry.
-  class ELFRelocation {
-    uint64_t r_offset;    // offset in the section of the object this applies to
-    uint32_t r_symidx;    // symbol table index of the symbol to use
-    uint32_t r_type;      // machine specific relocation type
-    int64_t  r_add;       // explicit relocation addend
-    bool     r_rela;      // if true then the addend is part of the entry
-                          // otherwise the addend is at the location specified
-                          // by r_offset
-  public:
-    uint64_t getInfo(bool is64Bit) const {
-      if (is64Bit)
-        return ((uint64_t)r_symidx << 32) + ((uint64_t)r_type & 0xFFFFFFFFL);
-      else
-        return (r_symidx << 8)  + (r_type & 0xFFL);
-    }
-
-    uint64_t getOffset() const { return r_offset; }
-    int64_t getAddend() const { return r_add; }
-
-    ELFRelocation(uint64_t off, uint32_t sym, uint32_t type,
-                  bool rela = true, int64_t addend = 0) :
-      r_offset(off), r_symidx(sym), r_type(type),
-      r_add(addend), r_rela(rela) {}
-  };
-
-} // end namespace llvm
-
-#endif
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/CodeGen/ELFCodeEmitter.cpp
--- a/head/contrib/llvm/lib/CodeGen/ELFCodeEmitter.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,205 +0,0 @@
-//===-- lib/CodeGen/ELFCodeEmitter.cpp ------------------------------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "elfce"
-
-#include "ELF.h"
-#include "ELFWriter.h"
-#include "ELFCodeEmitter.h"
-#include "llvm/Constants.h"
-#include "llvm/DerivedTypes.h"
-#include "llvm/Function.h"
-#include "llvm/CodeGen/BinaryObject.h"
-#include "llvm/CodeGen/MachineConstantPool.h"
-#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineJumpTableInfo.h"
-#include "llvm/CodeGen/MachineRelocation.h"
-#include "llvm/Target/TargetData.h"
-#include "llvm/Target/TargetELFWriterInfo.h"
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/MC/MCAsmInfo.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/raw_ostream.h"
-
-//===----------------------------------------------------------------------===//
-//                       ELFCodeEmitter Implementation
-//===----------------------------------------------------------------------===//
-
-namespace llvm {
-
-/// startFunction - This callback is invoked when a new machine function is
-/// about to be emitted.
-void ELFCodeEmitter::startFunction(MachineFunction &MF) {
-  DEBUG(dbgs() << "processing function: "
-        << MF.getFunction()->getName() << "\n");
-
-  // Get the ELF Section that this function belongs in.
-  ES = &EW.getTextSection(MF.getFunction());
-
-  // Set the desired binary object to be used by the code emitters
-  setBinaryObject(ES);
-
-  // Get the function alignment in bytes
-  unsigned Align = (1 << MF.getAlignment());
-
-  // The function must start on its required alignment
-  ES->emitAlignment(Align);
-
-  // Update the section alignment if needed.
-  ES->Align = std::max(ES->Align, Align);
-
-  // Record the function start offset
-  FnStartOff = ES->getCurrentPCOffset();
-
-  // Emit constant pool and jump tables to their appropriate sections.
-  // They need to be emitted before the function because in some targets
-  // the later may reference JT or CP entry address.
-  emitConstantPool(MF.getConstantPool());
-  if (MF.getJumpTableInfo())
-    emitJumpTables(MF.getJumpTableInfo());
-}
-
-/// finishFunction - This callback is invoked after the function is completely
-/// finished.
-bool ELFCodeEmitter::finishFunction(MachineFunction &MF) {
-  // Add a symbol to represent the function.
-  const Function *F = MF.getFunction();
-  ELFSym *FnSym = ELFSym::getGV(F, EW.getGlobalELFBinding(F), ELF::STT_FUNC,
-                                EW.getGlobalELFVisibility(F));
-  FnSym->SectionIdx = ES->SectionIdx;
-  FnSym->Size = ES->getCurrentPCOffset()-FnStartOff;
-  EW.AddPendingGlobalSymbol(F, true);
-
-  // Offset from start of Section
-  FnSym->Value = FnStartOff;
-
-  if (!F->hasPrivateLinkage())
-    EW.SymbolList.push_back(FnSym);
-
-  // Patch up Jump Table Section relocations to use the real MBBs offsets
-  // now that the MBB label offsets inside the function are known.
-  if (MF.getJumpTableInfo()) {
-    ELFSection &JTSection = EW.getJumpTableSection();
-    for (std::vector<MachineRelocation>::iterator MRI = JTRelocations.begin(),
-         MRE = JTRelocations.end(); MRI != MRE; ++MRI) {
-      MachineRelocation &MR = *MRI;
-      uintptr_t MBBOffset = getMachineBasicBlockAddress(MR.getBasicBlock());
-      MR.setResultPointer((void*)MBBOffset);
-      MR.setConstantVal(ES->SectionIdx);
-      JTSection.addRelocation(MR);
-    }
-  }
-
-  // If we have emitted any relocations to function-specific objects such as
-  // basic blocks, constant pools entries, or jump tables, record their
-  // addresses now so that we can rewrite them with the correct addresses later
-  for (unsigned i = 0, e = Relocations.size(); i != e; ++i) {
-    MachineRelocation &MR = Relocations[i];
-    intptr_t Addr;
-    if (MR.isGlobalValue()) {
-      EW.AddPendingGlobalSymbol(MR.getGlobalValue());
-    } else if (MR.isExternalSymbol()) {
-      EW.AddPendingExternalSymbol(MR.getExternalSymbol());
-    } else if (MR.isBasicBlock()) {
-      Addr = getMachineBasicBlockAddress(MR.getBasicBlock());
-      MR.setConstantVal(ES->SectionIdx);
-      MR.setResultPointer((void*)Addr);
-    } else if (MR.isConstantPoolIndex()) {
-      Addr = getConstantPoolEntryAddress(MR.getConstantPoolIndex());
-      MR.setConstantVal(CPSections[MR.getConstantPoolIndex()]);
-      MR.setResultPointer((void*)Addr);
-    } else if (MR.isJumpTableIndex()) {
-      ELFSection &JTSection = EW.getJumpTableSection();
-      Addr = getJumpTableEntryAddress(MR.getJumpTableIndex());
-      MR.setConstantVal(JTSection.SectionIdx);
-      MR.setResultPointer((void*)Addr);
-    } else {
-      llvm_unreachable("Unhandled relocation type");
-    }
-    ES->addRelocation(MR);
-  }
-
-  // Clear per-function data structures.
-  JTRelocations.clear();
-  Relocations.clear();
-  CPLocations.clear();
-  CPSections.clear();
-  JTLocations.clear();
-  MBBLocations.clear();
-  return false;
-}
-
-/// emitConstantPool - For each constant pool entry, figure out which section
-/// the constant should live in and emit the constant
-void ELFCodeEmitter::emitConstantPool(MachineConstantPool *MCP) {
-  const std::vector<MachineConstantPoolEntry> &CP = MCP->getConstants();
-  if (CP.empty()) return;
-
-  // TODO: handle PIC codegen
-  assert(TM.getRelocationModel() != Reloc::PIC_ &&
-         "PIC codegen not yet handled for elf constant pools!");
-
-  for (unsigned i = 0, e = CP.size(); i != e; ++i) {
-    MachineConstantPoolEntry CPE = CP[i];
-
-    // Record the constant pool location and the section index
-    ELFSection &CstPool = EW.getConstantPoolSection(CPE);
-    CPLocations.push_back(CstPool.size());
-    CPSections.push_back(CstPool.SectionIdx);
-
-    if (CPE.isMachineConstantPoolEntry())
-      assert(0 && "CPE.isMachineConstantPoolEntry not supported yet");
-
-    // Emit the constant to constant pool section
-    EW.EmitGlobalConstant(CPE.Val.ConstVal, CstPool);
-  }
-}
-
-/// emitJumpTables - Emit all the jump tables for a given jump table info
-/// record to the appropriate section.
-void ELFCodeEmitter::emitJumpTables(MachineJumpTableInfo *MJTI) {
-  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
-  if (JT.empty()) return;
-
-  // FIXME: handle PIC codegen
-  assert(TM.getRelocationModel() != Reloc::PIC_ &&
-         "PIC codegen not yet handled for elf jump tables!");
-
-  const TargetELFWriterInfo *TEW = TM.getELFWriterInfo();
-  unsigned EntrySize = 4; //MJTI->getEntrySize();
-
-  // Get the ELF Section to emit the jump table
-  ELFSection &JTSection = EW.getJumpTableSection();
-
-  // For each JT, record its offset from the start of the section
-  for (unsigned i = 0, e = JT.size(); i != e; ++i) {
-    const std::vector<MachineBasicBlock*> &MBBs = JT[i].MBBs;
-
-    // Record JT 'i' offset in the JT section
-    JTLocations.push_back(JTSection.size());
-
-    // Each MBB entry in the Jump table section has a relocation entry
-    // against the current text section.
-    for (unsigned mi = 0, me = MBBs.size(); mi != me; ++mi) {
-      unsigned MachineRelTy = TEW->getAbsoluteLabelMachineRelTy();
-      MachineRelocation MR =
-        MachineRelocation::getBB(JTSection.size(), MachineRelTy, MBBs[mi]);
-
-      // Add the relocation to the Jump Table section
-      JTRelocations.push_back(MR);
-
-      // Output placeholder for MBB in the JT section
-      for (unsigned s=0; s < EntrySize; ++s)
-        JTSection.emitByte(0);
-    }
-  }
-}
-
-} // end namespace llvm
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/CodeGen/ELFCodeEmitter.h
--- a/head/contrib/llvm/lib/CodeGen/ELFCodeEmitter.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,78 +0,0 @@
-//===-- lib/CodeGen/ELFCodeEmitter.h ----------------------------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef ELFCODEEMITTER_H
-#define ELFCODEEMITTER_H
-
-#include "llvm/CodeGen/ObjectCodeEmitter.h"
-#include <vector>
-
-namespace llvm {
-  class ELFWriter;
-  class ELFSection;
-
-  /// ELFCodeEmitter - This class is used by the ELFWriter to 
-  /// emit the code for functions to the ELF file.
-  class ELFCodeEmitter : public ObjectCodeEmitter {
-    ELFWriter &EW;
-
-    /// Target machine description
-    TargetMachine &TM;
-
-    /// Section containing code for functions
-    ELFSection *ES;
-
-    /// Relocations - Record relocations needed by the current function 
-    std::vector<MachineRelocation> Relocations;
-
-    /// JTRelocations - Record relocations needed by the relocation
-    /// section.
-    std::vector<MachineRelocation> JTRelocations;
-
-    /// FnStartPtr - Function offset from the beginning of ELFSection 'ES'
-    uintptr_t FnStartOff;
-  public:
-    explicit ELFCodeEmitter(ELFWriter &ew) : EW(ew), TM(EW.TM) {}
-
-    /// addRelocation - Register new relocations for this function
-    void addRelocation(const MachineRelocation &MR) {
-      Relocations.push_back(MR);
-    }
-
-    /// emitConstantPool - For each constant pool entry, figure out which
-    /// section the constant should live in and emit data to it
-    void emitConstantPool(MachineConstantPool *MCP);
-
-    /// emitJumpTables - Emit all the jump tables for a given jump table
-    /// info and record them to the appropriate section.
-    void emitJumpTables(MachineJumpTableInfo *MJTI);
-
-    void startFunction(MachineFunction &F);
-    bool finishFunction(MachineFunction &F);
-
-    /// emitLabel - Emits a label
-    virtual void emitLabel(MCSymbol *Label) {
-      assert(0 && "emitLabel not implemented");
-    }
-
-    /// getLabelAddress - Return the address of the specified LabelID, 
-    /// only usable after the LabelID has been emitted.
-    virtual uintptr_t getLabelAddress(MCSymbol *Label) const {
-      assert(0 && "getLabelAddress not implemented");
-      return 0;
-    }
-
-    virtual void setModuleInfo(llvm::MachineModuleInfo* MMI) {}
-
-};  // end class ELFCodeEmitter
-
-} // end namespace llvm
-
-#endif
-
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/CodeGen/ELFWriter.cpp
--- a/head/contrib/llvm/lib/CodeGen/ELFWriter.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1105 +0,0 @@
-//===-- ELFWriter.cpp - Target-independent ELF Writer code ----------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements the target-independent ELF writer.  This file writes out
-// the ELF file in the following order:
-//
-//  #1. ELF Header
-//  #2. '.text' section
-//  #3. '.data' section
-//  #4. '.bss' section  (conceptual position in file)
-//  ...
-//  #X. '.shstrtab' section
-//  #Y. Section Table
-//
-// The entries in the section table are laid out as:
-//  #0. Null entry [required]
-//  #1. ".text" entry - the program code
-//  #2. ".data" entry - global variables with initializers.     [ if needed ]
-//  #3. ".bss" entry  - global variables without initializers.  [ if needed ]
-//  ...
-//  #N. ".shstrtab" entry - String table for the section names.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "elfwriter"
-#include "ELF.h"
-#include "ELFWriter.h"
-#include "ELFCodeEmitter.h"
-#include "llvm/Constants.h"
-#include "llvm/Module.h"
-#include "llvm/PassManager.h"
-#include "llvm/DerivedTypes.h"
-#include "llvm/CodeGen/BinaryObject.h"
-#include "llvm/CodeGen/MachineCodeEmitter.h"
-#include "llvm/CodeGen/ObjectCodeEmitter.h"
-#include "llvm/CodeGen/MachineCodeEmitter.h"
-#include "llvm/CodeGen/MachineConstantPool.h"
-#include "llvm/MC/MCContext.h"
-#include "llvm/MC/MCSectionELF.h"
-#include "llvm/MC/MCAsmInfo.h"
-#include "llvm/Target/Mangler.h"
-#include "llvm/Target/TargetData.h"
-#include "llvm/Target/TargetELFWriterInfo.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/raw_ostream.h"
-#include "llvm/ADT/SmallString.h"
-using namespace llvm;
-
-char ELFWriter::ID = 0;
-
-//===----------------------------------------------------------------------===//
-//                          ELFWriter Implementation
-//===----------------------------------------------------------------------===//
-
-ELFWriter::ELFWriter(raw_ostream &o, TargetMachine &tm)
-  : MachineFunctionPass(ID), O(o), TM(tm),
-    OutContext(*new MCContext(*TM.getMCAsmInfo(), *TM.getRegisterInfo(),
-                              &TM.getTargetLowering()->getObjFileLowering())),
-    TLOF(TM.getTargetLowering()->getObjFileLowering()),
-    is64Bit(TM.getTargetData()->getPointerSizeInBits() == 64),
-    isLittleEndian(TM.getTargetData()->isLittleEndian()),
-    ElfHdr(isLittleEndian, is64Bit) {
-
-  MAI = TM.getMCAsmInfo();
-  TEW = TM.getELFWriterInfo();
-
-  // Create the object code emitter object for this target.
-  ElfCE = new ELFCodeEmitter(*this);
-
-  // Initial number of sections
-  NumSections = 0;
-}
-
-ELFWriter::~ELFWriter() {
-  delete ElfCE;
-  delete &OutContext;
-
-  while(!SymbolList.empty()) {
-    delete SymbolList.back(); 
-    SymbolList.pop_back();
-  }
-
-  while(!PrivateSyms.empty()) {
-    delete PrivateSyms.back(); 
-    PrivateSyms.pop_back();
-  }
-
-  while(!SectionList.empty()) {
-    delete SectionList.back(); 
-    SectionList.pop_back();
-  }
-
-  // Release the name mangler object.
-  delete Mang; Mang = 0;
-}
-
-// doInitialization - Emit the file header and all of the global variables for
-// the module to the ELF file.
-bool ELFWriter::doInitialization(Module &M) {
-  // Initialize TargetLoweringObjectFile.
-  const_cast<TargetLoweringObjectFile&>(TLOF).Initialize(OutContext, TM);
-  
-  Mang = new Mangler(OutContext, *TM.getTargetData());
-
-  // ELF Header
-  // ----------
-  // Fields e_shnum e_shstrndx are only known after all section have
-  // been emitted. They locations in the ouput buffer are recorded so
-  // to be patched up later.
-  //
-  // Note
-  // ----
-  // emitWord method behaves differently for ELF32 and ELF64, writing
-  // 4 bytes in the former and 8 in the last for *_off and *_addr elf types
-
-  ElfHdr.emitByte(0x7f); // e_ident[EI_MAG0]
-  ElfHdr.emitByte('E');  // e_ident[EI_MAG1]
-  ElfHdr.emitByte('L');  // e_ident[EI_MAG2]
-  ElfHdr.emitByte('F');  // e_ident[EI_MAG3]
-
-  ElfHdr.emitByte(TEW->getEIClass()); // e_ident[EI_CLASS]
-  ElfHdr.emitByte(TEW->getEIData());  // e_ident[EI_DATA]
-  ElfHdr.emitByte(ELF::EV_CURRENT);   // e_ident[EI_VERSION]
-  ElfHdr.emitAlignment(16);           // e_ident[EI_NIDENT-EI_PAD]
-
-  ElfHdr.emitWord16(ELF::ET_REL);        // e_type
-  ElfHdr.emitWord16(TEW->getEMachine()); // e_machine = target
-  ElfHdr.emitWord32(ELF::EV_CURRENT);    // e_version
-  ElfHdr.emitWord(0);                    // e_entry, no entry point in .o file
-  ElfHdr.emitWord(0);                    // e_phoff, no program header for .o
-  ELFHdr_e_shoff_Offset = ElfHdr.size();
-  ElfHdr.emitWord(0);                    // e_shoff = sec hdr table off in bytes
-  ElfHdr.emitWord32(TEW->getEFlags());   // e_flags = whatever the target wants
-  ElfHdr.emitWord16(TEW->getHdrSize());  // e_ehsize = ELF header size
-  ElfHdr.emitWord16(0);                  // e_phentsize = prog header entry size
-  ElfHdr.emitWord16(0);                  // e_phnum = # prog header entries = 0
-
-  // e_shentsize = Section header entry size
-  ElfHdr.emitWord16(TEW->getSHdrSize());
-
-  // e_shnum     = # of section header ents
-  ELFHdr_e_shnum_Offset = ElfHdr.size();
-  ElfHdr.emitWord16(0); // Placeholder
-
-  // e_shstrndx  = Section # of '.shstrtab'
-  ELFHdr_e_shstrndx_Offset = ElfHdr.size();
-  ElfHdr.emitWord16(0); // Placeholder
-
-  // Add the null section, which is required to be first in the file.
-  getNullSection();
-
-  // The first entry in the symtab is the null symbol and the second
-  // is a local symbol containing the module/file name
-  SymbolList.push_back(new ELFSym());
-  SymbolList.push_back(ELFSym::getFileSym());
-
-  return false;
-}
-
-// AddPendingGlobalSymbol - Add a global to be processed and to
-// the global symbol lookup, use a zero index because the table
-// index will be determined later.
-void ELFWriter::AddPendingGlobalSymbol(const GlobalValue *GV, 
-                                       bool AddToLookup /* = false */) {
-  PendingGlobals.insert(GV);
-  if (AddToLookup) 
-    GblSymLookup[GV] = 0;
-}
-
-// AddPendingExternalSymbol - Add the external to be processed
-// and to the external symbol lookup, use a zero index because
-// the symbol table index will be determined later.
-void ELFWriter::AddPendingExternalSymbol(const char *External) {
-  PendingExternals.insert(External);
-  ExtSymLookup[External] = 0;
-}
-
-ELFSection &ELFWriter::getDataSection() {
-  const MCSectionELF *Data = (const MCSectionELF *)TLOF.getDataSection();
-  return getSection(Data->getSectionName(), Data->getType(), 
-                    Data->getFlags(), 4);
-}
-
-ELFSection &ELFWriter::getBSSSection() {
-  const MCSectionELF *BSS = (const MCSectionELF *)TLOF.getBSSSection();
-  return getSection(BSS->getSectionName(), BSS->getType(), BSS->getFlags(), 4);
-}
-
-// getCtorSection - Get the static constructor section
-ELFSection &ELFWriter::getCtorSection() {
-  const MCSectionELF *Ctor = (const MCSectionELF *)TLOF.getStaticCtorSection();
-  return getSection(Ctor->getSectionName(), Ctor->getType(), Ctor->getFlags()); 
-}
-
-// getDtorSection - Get the static destructor section
-ELFSection &ELFWriter::getDtorSection() {
-  const MCSectionELF *Dtor = (const MCSectionELF *)TLOF.getStaticDtorSection();
-  return getSection(Dtor->getSectionName(), Dtor->getType(), Dtor->getFlags());
-}
-
-// getTextSection - Get the text section for the specified function
-ELFSection &ELFWriter::getTextSection(const Function *F) {
-  const MCSectionELF *Text = 
-    (const MCSectionELF *)TLOF.SectionForGlobal(F, Mang, TM);
-  return getSection(Text->getSectionName(), Text->getType(), Text->getFlags());
-}
-
-// getJumpTableSection - Get a read only section for constants when 
-// emitting jump tables. TODO: add PIC support
-ELFSection &ELFWriter::getJumpTableSection() {
-  const MCSectionELF *JT = 
-    (const MCSectionELF *)TLOF.getSectionForConstant(SectionKind::getReadOnly());
-  return getSection(JT->getSectionName(), JT->getType(), JT->getFlags(),
-                    TM.getTargetData()->getPointerABIAlignment());
-}
-
-// getConstantPoolSection - Get a constant pool section based on the machine 
-// constant pool entry type and relocation info.
-ELFSection &ELFWriter::getConstantPoolSection(MachineConstantPoolEntry &CPE) {
-  SectionKind Kind;
-  switch (CPE.getRelocationInfo()) {
-  default: llvm_unreachable("Unknown section kind");
-  case 2: Kind = SectionKind::getReadOnlyWithRel(); break;
-  case 1:
-    Kind = SectionKind::getReadOnlyWithRelLocal();
-    break;
-  case 0:
-    switch (TM.getTargetData()->getTypeAllocSize(CPE.getType())) {
-    case 4:  Kind = SectionKind::getMergeableConst4(); break;
-    case 8:  Kind = SectionKind::getMergeableConst8(); break;
-    case 16: Kind = SectionKind::getMergeableConst16(); break;
-    default: Kind = SectionKind::getMergeableConst(); break;
-    }
-  }
-
-  const MCSectionELF *CPSect = 
-    (const MCSectionELF *)TLOF.getSectionForConstant(Kind);
-  return getSection(CPSect->getSectionName(), CPSect->getType(), 
-                    CPSect->getFlags(), CPE.getAlignment());
-}
-
-// getRelocSection - Return the relocation section of section 'S'. 'RelA' 
-// is true if the relocation section contains entries with addends.
-ELFSection &ELFWriter::getRelocSection(ELFSection &S) {
-  unsigned SectionType = TEW->hasRelocationAddend() ?
-                ELF::SHT_RELA : ELF::SHT_REL;
-
-  std::string SectionName(".rel");
-  if (TEW->hasRelocationAddend())
-    SectionName.append("a");
-  SectionName.append(S.getName());
-
-  return getSection(SectionName, SectionType, 0, TEW->getPrefELFAlignment());
-}
-
-// getGlobalELFVisibility - Returns the ELF specific visibility type
-unsigned ELFWriter::getGlobalELFVisibility(const GlobalValue *GV) {
-  switch (GV->getVisibility()) {
-  default:
-    llvm_unreachable("unknown visibility type");
-  case GlobalValue::DefaultVisibility:
-    return ELF::STV_DEFAULT;
-  case GlobalValue::HiddenVisibility:
-    return ELF::STV_HIDDEN;
-  case GlobalValue::ProtectedVisibility:
-    return ELF::STV_PROTECTED;
-  }
-  return 0;
-}
-
-// getGlobalELFBinding - Returns the ELF specific binding type
-unsigned ELFWriter::getGlobalELFBinding(const GlobalValue *GV) {
-  if (GV->hasInternalLinkage())
-    return ELF::STB_LOCAL;
-
-  if (GV->isWeakForLinker() && !GV->hasCommonLinkage())
-    return ELF::STB_WEAK;
-
-  return ELF::STB_GLOBAL;
-}
-
-// getGlobalELFType - Returns the ELF specific type for a global
-unsigned ELFWriter::getGlobalELFType(const GlobalValue *GV) {
-  if (GV->isDeclaration())
-    return ELF::STT_NOTYPE;
-
-  if (isa<Function>(GV))
-    return ELF::STT_FUNC;
-
-  return ELF::STT_OBJECT;
-}
-
-// IsELFUndefSym - True if the global value must be marked as a symbol
-// which points to a SHN_UNDEF section. This means that the symbol has
-// no definition on the module.
-static bool IsELFUndefSym(const GlobalValue *GV) {
-  return GV->isDeclaration() || (isa<Function>(GV));
-}
-
-// AddToSymbolList - Update the symbol lookup and If the symbol is 
-// private add it to PrivateSyms list, otherwise to SymbolList. 
-void ELFWriter::AddToSymbolList(ELFSym *GblSym) {
-  assert(GblSym->isGlobalValue() && "Symbol must be a global value");
-
-  const GlobalValue *GV = GblSym->getGlobalValue(); 
-  if (GV->hasPrivateLinkage()) {
-    // For a private symbols, keep track of the index inside 
-    // the private list since it will never go to the symbol 
-    // table and won't be patched up later.
-    PrivateSyms.push_back(GblSym);
-    GblSymLookup[GV] = PrivateSyms.size()-1;
-  } else {
-    // Non private symbol are left with zero indices until 
-    // they are patched up during the symbol table emition 
-    // (where the indicies are created).
-    SymbolList.push_back(GblSym);
-    GblSymLookup[GV] = 0;
-  }
-}
-
-/// HasCommonSymbols - True if this section holds common symbols, this is
-/// indicated on the ELF object file by a symbol with SHN_COMMON section
-/// header index.
-static bool HasCommonSymbols(const MCSectionELF &S) {
-  // FIXME: this is wrong, a common symbol can be in .data for example.
-  if (StringRef(S.getSectionName()).startswith(".gnu.linkonce."))
-    return true;
-
-  return false;
-}
-
-
-// EmitGlobal - Choose the right section for global and emit it
-void ELFWriter::EmitGlobal(const GlobalValue *GV) {
-
-  // Check if the referenced symbol is already emitted
-  if (GblSymLookup.find(GV) != GblSymLookup.end())
-    return;
-
-  // Handle ELF Bind, Visibility and Type for the current symbol
-  unsigned SymBind = getGlobalELFBinding(GV);
-  unsigned SymType = getGlobalELFType(GV);
-  bool IsUndefSym = IsELFUndefSym(GV);
-
-  ELFSym *GblSym = IsUndefSym ? ELFSym::getUndefGV(GV, SymBind)
-    : ELFSym::getGV(GV, SymBind, SymType, getGlobalELFVisibility(GV));
-
-  if (!IsUndefSym) {
-    assert(isa<GlobalVariable>(GV) && "GV not a global variable!");
-    const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
-
-    // Handle special llvm globals
-    if (EmitSpecialLLVMGlobal(GVar))
-      return;
-
-    // Get the ELF section where this global belongs from TLOF
-    const MCSectionELF *S = 
-      (const MCSectionELF *)TLOF.SectionForGlobal(GV, Mang, TM);
-    ELFSection &ES = 
-      getSection(S->getSectionName(), S->getType(), S->getFlags());
-    SectionKind Kind = S->getKind();
-
-    // The symbol align should update the section alignment if needed
-    const TargetData *TD = TM.getTargetData();
-    unsigned Align = TD->getPreferredAlignment(GVar);
-    unsigned Size = TD->getTypeAllocSize(GVar->getInitializer()->getType());
-    GblSym->Size = Size;
-
-    if (HasCommonSymbols(*S)) { // Symbol must go to a common section
-      GblSym->SectionIdx = ELF::SHN_COMMON;
-
-      // A new linkonce section is created for each global in the
-      // common section, the default alignment is 1 and the symbol
-      // value contains its alignment.
-      ES.Align = 1;
-      GblSym->Value = Align;
-
-    } else if (Kind.isBSS() || Kind.isThreadBSS()) { // Symbol goes to BSS.
-      GblSym->SectionIdx = ES.SectionIdx;
-
-      // Update the size with alignment and the next object can
-      // start in the right offset in the section
-      if (Align) ES.Size = (ES.Size + Align-1) & ~(Align-1);
-      ES.Align = std::max(ES.Align, Align);
-
-      // GblSym->Value should contain the virtual offset inside the section.
-      // Virtual because the BSS space is not allocated on ELF objects
-      GblSym->Value = ES.Size;
-      ES.Size += Size;
-
-    } else { // The symbol must go to some kind of data section
-      GblSym->SectionIdx = ES.SectionIdx;
-
-      // GblSym->Value should contain the symbol offset inside the section,
-      // and all symbols should start on their required alignment boundary
-      ES.Align = std::max(ES.Align, Align);
-      ES.emitAlignment(Align);
-      GblSym->Value = ES.size();
-
-      // Emit the global to the data section 'ES'
-      EmitGlobalConstant(GVar->getInitializer(), ES);
-    }
-  }
-
-  AddToSymbolList(GblSym);
-}
-
-void ELFWriter::EmitGlobalConstantStruct(const ConstantStruct *CVS,
-                                         ELFSection &GblS) {
-
-  // Print the fields in successive locations. Pad to align if needed!
-  const TargetData *TD = TM.getTargetData();
-  unsigned Size = TD->getTypeAllocSize(CVS->getType());
-  const StructLayout *cvsLayout = TD->getStructLayout(CVS->getType());
-  uint64_t sizeSoFar = 0;
-  for (unsigned i = 0, e = CVS->getNumOperands(); i != e; ++i) {
-    const Constant* field = CVS->getOperand(i);
-
-    // Check if padding is needed and insert one or more 0s.
-    uint64_t fieldSize = TD->getTypeAllocSize(field->getType());
-    uint64_t padSize = ((i == e-1 ? Size : cvsLayout->getElementOffset(i+1))
-                        - cvsLayout->getElementOffset(i)) - fieldSize;
-    sizeSoFar += fieldSize + padSize;
-
-    // Now print the actual field value.
-    EmitGlobalConstant(field, GblS);
-
-    // Insert padding - this may include padding to increase the size of the
-    // current field up to the ABI size (if the struct is not packed) as well
-    // as padding to ensure that the next field starts at the right offset.
-    GblS.emitZeros(padSize);
-  }
-  assert(sizeSoFar == cvsLayout->getSizeInBytes() &&
-         "Layout of constant struct may be incorrect!");
-}
-
-void ELFWriter::EmitGlobalConstant(const Constant *CV, ELFSection &GblS) {
-  const TargetData *TD = TM.getTargetData();
-  unsigned Size = TD->getTypeAllocSize(CV->getType());
-
-  if (const ConstantArray *CVA = dyn_cast<ConstantArray>(CV)) {
-    for (unsigned i = 0, e = CVA->getNumOperands(); i != e; ++i)
-      EmitGlobalConstant(CVA->getOperand(i), GblS);
-    return;
-  } else if (isa<ConstantAggregateZero>(CV)) {
-    GblS.emitZeros(Size);
-    return;
-  } else if (const ConstantStruct *CVS = dyn_cast<ConstantStruct>(CV)) {
-    EmitGlobalConstantStruct(CVS, GblS);
-    return;
-  } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
-    APInt Val = CFP->getValueAPF().bitcastToAPInt();
-    if (CFP->getType()->isDoubleTy())
-      GblS.emitWord64(Val.getZExtValue());
-    else if (CFP->getType()->isFloatTy())
-      GblS.emitWord32(Val.getZExtValue());
-    else if (CFP->getType()->isX86_FP80Ty()) {
-      unsigned PadSize = TD->getTypeAllocSize(CFP->getType())-
-                         TD->getTypeStoreSize(CFP->getType());
-      GblS.emitWordFP80(Val.getRawData(), PadSize);
-    } else if (CFP->getType()->isPPC_FP128Ty())
-      llvm_unreachable("PPC_FP128Ty global emission not implemented");
-    return;
-  } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
-    if (Size == 1)
-      GblS.emitByte(CI->getZExtValue());
-    else if (Size == 2) 
-      GblS.emitWord16(CI->getZExtValue());
-    else if (Size == 4)
-      GblS.emitWord32(CI->getZExtValue());
-    else 
-      EmitGlobalConstantLargeInt(CI, GblS);
-    return;
-  } else if (const ConstantVector *CP = dyn_cast<ConstantVector>(CV)) {
-    VectorType *PTy = CP->getType();
-    for (unsigned I = 0, E = PTy->getNumElements(); I < E; ++I)
-      EmitGlobalConstant(CP->getOperand(I), GblS);
-    return;
-  } else if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(CV)) {
-    // Resolve a constant expression which returns a (Constant, Offset)
-    // pair. If 'Res.first' is a GlobalValue, emit a relocation with 
-    // the offset 'Res.second', otherwise emit a global constant like
-    // it is always done for not contant expression types.
-    CstExprResTy Res = ResolveConstantExpr(CE);
-    const Constant *Op = Res.first;
-
-    if (isa<GlobalValue>(Op))
-      EmitGlobalDataRelocation(cast<const GlobalValue>(Op), 
-                               TD->getTypeAllocSize(Op->getType()), 
-                               GblS, Res.second);
-    else
-      EmitGlobalConstant(Op, GblS);
-
-    return;
-  } else if (CV->getType()->getTypeID() == Type::PointerTyID) {
-    // Fill the data entry with zeros or emit a relocation entry
-    if (isa<ConstantPointerNull>(CV))
-      GblS.emitZeros(Size);
-    else 
-      EmitGlobalDataRelocation(cast<const GlobalValue>(CV), 
-                               Size, GblS);
-    return;
-  } else if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
-    // This is a constant address for a global variable or function and
-    // therefore must be referenced using a relocation entry.
-    EmitGlobalDataRelocation(GV, Size, GblS);
-    return;
-  }
-
-  std::string msg;
-  raw_string_ostream ErrorMsg(msg);
-  ErrorMsg << "Constant unimp for type: " << *CV->getType();
-  report_fatal_error(ErrorMsg.str());
-}
-
-// ResolveConstantExpr - Resolve the constant expression until it stop
-// yielding other constant expressions.
-CstExprResTy ELFWriter::ResolveConstantExpr(const Constant *CV) {
-  const TargetData *TD = TM.getTargetData();
-  
-  // There ins't constant expression inside others anymore
-  if (!isa<ConstantExpr>(CV))
-    return std::make_pair(CV, 0);
-
-  const ConstantExpr *CE = dyn_cast<ConstantExpr>(CV);
-  switch (CE->getOpcode()) {
-  case Instruction::BitCast:
-    return ResolveConstantExpr(CE->getOperand(0));
-  
-  case Instruction::GetElementPtr: {
-    const Constant *ptrVal = CE->getOperand(0);
-    SmallVector<Value*, 8> idxVec(CE->op_begin()+1, CE->op_end());
-    int64_t Offset = TD->getIndexedOffset(ptrVal->getType(), idxVec);
-    return std::make_pair(ptrVal, Offset);
-  }
-  case Instruction::IntToPtr: {
-    Constant *Op = CE->getOperand(0);
-    Op = ConstantExpr::getIntegerCast(Op, TD->getIntPtrType(CV->getContext()),
-                                      false/*ZExt*/);
-    return ResolveConstantExpr(Op);
-  }
-  case Instruction::PtrToInt: {
-    Constant *Op = CE->getOperand(0);
-    Type *Ty = CE->getType();
-
-    // We can emit the pointer value into this slot if the slot is an
-    // integer slot greater or equal to the size of the pointer.
-    if (TD->getTypeAllocSize(Ty) == TD->getTypeAllocSize(Op->getType()))
-      return ResolveConstantExpr(Op);
-
-    llvm_unreachable("Integer size less then pointer size");
-  }
-  case Instruction::Add:
-  case Instruction::Sub: {
-    // Only handle cases where there's a constant expression with GlobalValue
-    // as first operand and ConstantInt as second, which are the cases we can
-    // solve direclty using a relocation entry. GlobalValue=Op0, CstInt=Op1
-    // 1)  Instruction::Add  => (global) + CstInt
-    // 2)  Instruction::Sub  => (global) + -CstInt
-    const Constant *Op0 = CE->getOperand(0); 
-    const Constant *Op1 = CE->getOperand(1); 
-    assert(isa<ConstantInt>(Op1) && "Op1 must be a ConstantInt");
-
-    CstExprResTy Res = ResolveConstantExpr(Op0);
-    assert(isa<GlobalValue>(Res.first) && "Op0 must be a GlobalValue");
-
-    const APInt &RHS = cast<ConstantInt>(Op1)->getValue();
-    switch (CE->getOpcode()) {
-    case Instruction::Add: 
-      return std::make_pair(Res.first, RHS.getSExtValue());
-    case Instruction::Sub:
-      return std::make_pair(Res.first, (-RHS).getSExtValue());
-    }
-  }
-  }
-
-  report_fatal_error(CE->getOpcodeName() +
-                     StringRef(": Unsupported ConstantExpr type"));
-
-  return std::make_pair(CV, 0); // silence warning
-}
-
-void ELFWriter::EmitGlobalDataRelocation(const GlobalValue *GV, unsigned Size,
-                                         ELFSection &GblS, int64_t Offset) {
-  // Create the relocation entry for the global value
-  MachineRelocation MR =
-    MachineRelocation::getGV(GblS.getCurrentPCOffset(),
-                             TEW->getAbsoluteLabelMachineRelTy(),
-                             const_cast<GlobalValue*>(GV),
-                             Offset);
-
-  // Fill the data entry with zeros
-  GblS.emitZeros(Size);
-
-  // Add the relocation entry for the current data section
-  GblS.addRelocation(MR);
-}
-
-void ELFWriter::EmitGlobalConstantLargeInt(const ConstantInt *CI, 
-                                           ELFSection &S) {
-  const TargetData *TD = TM.getTargetData();
-  unsigned BitWidth = CI->getBitWidth();
-  assert(isPowerOf2_32(BitWidth) &&
-         "Non-power-of-2-sized integers not handled!");
-
-  const uint64_t *RawData = CI->getValue().getRawData();
-  uint64_t Val = 0;
-  for (unsigned i = 0, e = BitWidth / 64; i != e; ++i) {
-    Val = (TD->isBigEndian()) ? RawData[e - i - 1] : RawData[i];
-    S.emitWord64(Val);
-  }
-}
-
-/// EmitSpecialLLVMGlobal - Check to see if the specified global is a
-/// special global used by LLVM.  If so, emit it and return true, otherwise
-/// do nothing and return false.
-bool ELFWriter::EmitSpecialLLVMGlobal(const GlobalVariable *GV) {
-  if (GV->getName() == "llvm.used")
-    llvm_unreachable("not implemented yet");
-
-  // Ignore debug and non-emitted data.  This handles llvm.compiler.used.
-  if (GV->getSection() == "llvm.metadata" ||
-      GV->hasAvailableExternallyLinkage())
-    return true;
-  
-  if (!GV->hasAppendingLinkage()) return false;
-
-  assert(GV->hasInitializer() && "Not a special LLVM global!");
-  
-  const TargetData *TD = TM.getTargetData();
-  unsigned Align = TD->getPointerPrefAlignment();
-  if (GV->getName() == "llvm.global_ctors") {
-    ELFSection &Ctor = getCtorSection();
-    Ctor.emitAlignment(Align);
-    EmitXXStructorList(GV->getInitializer(), Ctor);
-    return true;
-  } 
-  
-  if (GV->getName() == "llvm.global_dtors") {
-    ELFSection &Dtor = getDtorSection();
-    Dtor.emitAlignment(Align);
-    EmitXXStructorList(GV->getInitializer(), Dtor);
-    return true;
-  }
-  
-  return false;
-}
-
-/// EmitXXStructorList - Emit the ctor or dtor list.  This just emits out the 
-/// function pointers, ignoring the init priority.
-void ELFWriter::EmitXXStructorList(const Constant *List, ELFSection &Xtor) {
-  // Should be an array of '{ i32, void ()* }' structs.  The first value is the
-  // init priority, which we ignore.
-  if (List->isNullValue()) return;
-  const ConstantArray *InitList = cast<ConstantArray>(List);
-  for (unsigned i = 0, e = InitList->getNumOperands(); i != e; ++i) {
-    if (InitList->getOperand(i)->isNullValue())
-      continue;
-    ConstantStruct *CS = cast<ConstantStruct>(InitList->getOperand(i));
-
-    if (CS->getOperand(1)->isNullValue())
-      continue;
-
-    // Emit the function pointer.
-    EmitGlobalConstant(CS->getOperand(1), Xtor);
-  }
-}
-
-bool ELFWriter::runOnMachineFunction(MachineFunction &MF) {
-  // Nothing to do here, this is all done through the ElfCE object above.
-  return false;
-}
-
-/// doFinalization - Now that the module has been completely processed, emit
-/// the ELF file to 'O'.
-bool ELFWriter::doFinalization(Module &M) {
-  // Emit .data section placeholder
-  getDataSection();
-
-  // Emit .bss section placeholder
-  getBSSSection();
-
-  // Build and emit data, bss and "common" sections.
-  for (Module::global_iterator I = M.global_begin(), E = M.global_end();
-       I != E; ++I)
-    EmitGlobal(I);
-
-  // Emit all pending globals
-  for (PendingGblsIter I = PendingGlobals.begin(), E = PendingGlobals.end();
-       I != E; ++I)
-    EmitGlobal(*I);
-
-  // Emit all pending externals
-  for (PendingExtsIter I = PendingExternals.begin(), E = PendingExternals.end();
-       I != E; ++I)
-    SymbolList.push_back(ELFSym::getExtSym(*I));
-
-  // Emit a symbol for each section created until now, skip null section
-  for (unsigned i = 1, e = SectionList.size(); i < e; ++i) {
-    ELFSection &ES = *SectionList[i];
-    ELFSym *SectionSym = ELFSym::getSectionSym();
-    SectionSym->SectionIdx = ES.SectionIdx;
-    SymbolList.push_back(SectionSym);
-    ES.Sym = SymbolList.back();
-  }
-
-  // Emit string table
-  EmitStringTable(M.getModuleIdentifier());
-
-  // Emit the symbol table now, if non-empty.
-  EmitSymbolTable();
-
-  // Emit the relocation sections.
-  EmitRelocations();
-
-  // Emit the sections string table.
-  EmitSectionTableStringTable();
-
-  // Dump the sections and section table to the .o file.
-  OutputSectionsAndSectionTable();
-
-  return false;
-}
-
-// RelocateField - Patch relocatable field with 'Offset' in 'BO'
-// using a 'Value' of known 'Size'
-void ELFWriter::RelocateField(BinaryObject &BO, uint32_t Offset,
-                              int64_t Value, unsigned Size) {
-  if (Size == 32)
-    BO.fixWord32(Value, Offset);
-  else if (Size == 64)
-    BO.fixWord64(Value, Offset);
-  else
-    llvm_unreachable("don't know howto patch relocatable field");
-}
-
-/// EmitRelocations - Emit relocations
-void ELFWriter::EmitRelocations() {
-
-  // True if the target uses the relocation entry to hold the addend,
-  // otherwise the addend is written directly to the relocatable field.
-  bool HasRelA = TEW->hasRelocationAddend();
-
-  // Create Relocation sections for each section which needs it.
-  for (unsigned i=0, e=SectionList.size(); i != e; ++i) {
-    ELFSection &S = *SectionList[i];
-
-    // This section does not have relocations
-    if (!S.hasRelocations()) continue;
-    ELFSection &RelSec = getRelocSection(S);
-
-    // 'Link' - Section hdr idx of the associated symbol table
-    // 'Info' - Section hdr idx of the section to which the relocation applies
-    ELFSection &SymTab = getSymbolTableSection();
-    RelSec.Link = SymTab.SectionIdx;
-    RelSec.Info = S.SectionIdx;
-    RelSec.EntSize = TEW->getRelocationEntrySize();
-
-    // Get the relocations from Section
-    std::vector<MachineRelocation> Relos = S.getRelocations();
-    for (std::vector<MachineRelocation>::iterator MRI = Relos.begin(),
-         MRE = Relos.end(); MRI != MRE; ++MRI) {
-      MachineRelocation &MR = *MRI;
-
-      // Relocatable field offset from the section start
-      unsigned RelOffset = MR.getMachineCodeOffset();
-
-      // Symbol index in the symbol table
-      unsigned SymIdx = 0;
-
-      // Target specific relocation field type and size
-      unsigned RelType = TEW->getRelocationType(MR.getRelocationType());
-      unsigned RelTySize = TEW->getRelocationTySize(RelType);
-      int64_t Addend = 0;
-
-      // There are several machine relocations types, and each one of
-      // them needs a different approach to retrieve the symbol table index.
-      if (MR.isGlobalValue()) {
-        const GlobalValue *G = MR.getGlobalValue();
-        int64_t GlobalOffset = MR.getConstantVal();
-        SymIdx = GblSymLookup[G];
-        if (G->hasPrivateLinkage()) {
-          // If the target uses a section offset in the relocation:
-          // SymIdx + Addend = section sym for global + section offset
-          unsigned SectionIdx = PrivateSyms[SymIdx]->SectionIdx;
-          Addend = PrivateSyms[SymIdx]->Value + GlobalOffset;
-          SymIdx = SectionList[SectionIdx]->getSymbolTableIndex();
-        } else {
-          Addend = TEW->getDefaultAddendForRelTy(RelType, GlobalOffset);
-        }
-      } else if (MR.isExternalSymbol()) {
-        const char *ExtSym = MR.getExternalSymbol();
-        SymIdx = ExtSymLookup[ExtSym];
-        Addend = TEW->getDefaultAddendForRelTy(RelType);
-      } else {
-        // Get the symbol index for the section symbol
-        unsigned SectionIdx = MR.getConstantVal();
-        SymIdx = SectionList[SectionIdx]->getSymbolTableIndex();
-
-        // The symbol offset inside the section
-        int64_t SymOffset = (int64_t)MR.getResultPointer();
-
-        // For pc relative relocations where symbols are defined in the same
-        // section they are referenced, ignore the relocation entry and patch
-        // the relocatable field with the symbol offset directly.
-        if (S.SectionIdx == SectionIdx && TEW->isPCRelativeRel(RelType)) {
-          int64_t Value = TEW->computeRelocation(SymOffset, RelOffset, RelType);
-          RelocateField(S, RelOffset, Value, RelTySize);
-          continue;
-        }
-
-        Addend = TEW->getDefaultAddendForRelTy(RelType, SymOffset);
-      }
-
-      // The target without addend on the relocation symbol must be
-      // patched in the relocation place itself to contain the addend
-      // otherwise write zeros to make sure there is no garbage there
-      RelocateField(S, RelOffset, HasRelA ? 0 : Addend, RelTySize);
-
-      // Get the relocation entry and emit to the relocation section
-      ELFRelocation Rel(RelOffset, SymIdx, RelType, HasRelA, Addend);
-      EmitRelocation(RelSec, Rel, HasRelA);
-    }
-  }
-}
-
-/// EmitRelocation - Write relocation 'Rel' to the relocation section 'Rel'
-void ELFWriter::EmitRelocation(BinaryObject &RelSec, ELFRelocation &Rel,
-                               bool HasRelA) {
-  RelSec.emitWord(Rel.getOffset());
-  RelSec.emitWord(Rel.getInfo(is64Bit));
-  if (HasRelA)
-    RelSec.emitWord(Rel.getAddend());
-}
-
-/// EmitSymbol - Write symbol 'Sym' to the symbol table 'SymbolTable'
-void ELFWriter::EmitSymbol(BinaryObject &SymbolTable, ELFSym &Sym) {
-  if (is64Bit) {
-    SymbolTable.emitWord32(Sym.NameIdx);
-    SymbolTable.emitByte(Sym.Info);
-    SymbolTable.emitByte(Sym.Other);
-    SymbolTable.emitWord16(Sym.SectionIdx);
-    SymbolTable.emitWord64(Sym.Value);
-    SymbolTable.emitWord64(Sym.Size);
-  } else {
-    SymbolTable.emitWord32(Sym.NameIdx);
-    SymbolTable.emitWord32(Sym.Value);
-    SymbolTable.emitWord32(Sym.Size);
-    SymbolTable.emitByte(Sym.Info);
-    SymbolTable.emitByte(Sym.Other);
-    SymbolTable.emitWord16(Sym.SectionIdx);
-  }
-}
-
-/// EmitSectionHeader - Write section 'Section' header in 'SHdrTab'
-/// Section Header Table
-void ELFWriter::EmitSectionHeader(BinaryObject &SHdrTab,
-                                  const ELFSection &SHdr) {
-  SHdrTab.emitWord32(SHdr.NameIdx);
-  SHdrTab.emitWord32(SHdr.Type);
-  if (is64Bit) {
-    SHdrTab.emitWord64(SHdr.Flags);
-    SHdrTab.emitWord(SHdr.Addr);
-    SHdrTab.emitWord(SHdr.Offset);
-    SHdrTab.emitWord64(SHdr.Size);
-    SHdrTab.emitWord32(SHdr.Link);
-    SHdrTab.emitWord32(SHdr.Info);
-    SHdrTab.emitWord64(SHdr.Align);
-    SHdrTab.emitWord64(SHdr.EntSize);
-  } else {
-    SHdrTab.emitWord32(SHdr.Flags);
-    SHdrTab.emitWord(SHdr.Addr);
-    SHdrTab.emitWord(SHdr.Offset);
-    SHdrTab.emitWord32(SHdr.Size);
-    SHdrTab.emitWord32(SHdr.Link);
-    SHdrTab.emitWord32(SHdr.Info);
-    SHdrTab.emitWord32(SHdr.Align);
-    SHdrTab.emitWord32(SHdr.EntSize);
-  }
-}
-
-/// EmitStringTable - If the current symbol table is non-empty, emit the string
-/// table for it
-void ELFWriter::EmitStringTable(const std::string &ModuleName) {
-  if (!SymbolList.size()) return;  // Empty symbol table.
-  ELFSection &StrTab = getStringTableSection();
-
-  // Set the zero'th symbol to a null byte, as required.
-  StrTab.emitByte(0);
-
-  // Walk on the symbol list and write symbol names into the string table.
-  unsigned Index = 1;
-  for (ELFSymIter I=SymbolList.begin(), E=SymbolList.end(); I != E; ++I) {
-    ELFSym &Sym = *(*I);
-
-    std::string Name;
-    if (Sym.isGlobalValue()) {
-      SmallString<40> NameStr;
-      Mang->getNameWithPrefix(NameStr, Sym.getGlobalValue(), false);
-      Name.append(NameStr.begin(), NameStr.end());
-    } else if (Sym.isExternalSym())
-      Name.append(Sym.getExternalSymbol());
-    else if (Sym.isFileType())
-      Name.append(ModuleName);
-
-    if (Name.empty()) {
-      Sym.NameIdx = 0;
-    } else {
-      Sym.NameIdx = Index;
-      StrTab.emitString(Name);
-
-      // Keep track of the number of bytes emitted to this section.
-      Index += Name.size()+1;
-    }
-  }
-  assert(Index == StrTab.size());
-  StrTab.Size = Index;
-}
-
-// SortSymbols - On the symbol table local symbols must come before
-// all other symbols with non-local bindings. The return value is
-// the position of the first non local symbol.
-unsigned ELFWriter::SortSymbols() {
-  unsigned FirstNonLocalSymbol;
-  std::vector<ELFSym*> LocalSyms, OtherSyms;
-
-  for (ELFSymIter I=SymbolList.begin(), E=SymbolList.end(); I != E; ++I) {
-    if ((*I)->isLocalBind())
-      LocalSyms.push_back(*I);
-    else
-      OtherSyms.push_back(*I);
-  }
-  SymbolList.clear();
-  FirstNonLocalSymbol = LocalSyms.size();
-
-  for (unsigned i = 0; i < FirstNonLocalSymbol; ++i)
-    SymbolList.push_back(LocalSyms[i]);
-
-  for (ELFSymIter I=OtherSyms.begin(), E=OtherSyms.end(); I != E; ++I)
-    SymbolList.push_back(*I);
-
-  LocalSyms.clear();
-  OtherSyms.clear();
-
-  return FirstNonLocalSymbol;
-}
-
-/// EmitSymbolTable - Emit the symbol table itself.
-void ELFWriter::EmitSymbolTable() {
-  if (!SymbolList.size()) return;  // Empty symbol table.
-
-  // Now that we have emitted the string table and know the offset into the
-  // string table of each symbol, emit the symbol table itself.
-  ELFSection &SymTab = getSymbolTableSection();
-  SymTab.Align = TEW->getPrefELFAlignment();
-
-  // Section Index of .strtab.
-  SymTab.Link = getStringTableSection().SectionIdx;
-
-  // Size of each symtab entry.
-  SymTab.EntSize = TEW->getSymTabEntrySize();
-
-  // Reorder the symbol table with local symbols first!
-  unsigned FirstNonLocalSymbol = SortSymbols();
-
-  // Emit all the symbols to the symbol table.
-  for (unsigned i = 0, e = SymbolList.size(); i < e; ++i) {
-    ELFSym &Sym = *SymbolList[i];
-
-    // Emit symbol to the symbol table
-    EmitSymbol(SymTab, Sym);
-
-    // Record the symbol table index for each symbol
-    if (Sym.isGlobalValue())
-      GblSymLookup[Sym.getGlobalValue()] = i;
-    else if (Sym.isExternalSym())
-      ExtSymLookup[Sym.getExternalSymbol()] = i;
-
-    // Keep track on the symbol index into the symbol table
-    Sym.SymTabIdx = i;
-  }
-
-  // One greater than the symbol table index of the last local symbol
-  SymTab.Info = FirstNonLocalSymbol;
-  SymTab.Size = SymTab.size();
-}
-
-/// EmitSectionTableStringTable - This method adds and emits a section for the
-/// ELF Section Table string table: the string table that holds all of the
-/// section names.
-void ELFWriter::EmitSectionTableStringTable() {
-  // First step: add the section for the string table to the list of sections:
-  ELFSection &SHStrTab = getSectionHeaderStringTableSection();
-
-  // Now that we know which section number is the .shstrtab section, update the
-  // e_shstrndx entry in the ELF header.
-  ElfHdr.fixWord16(SHStrTab.SectionIdx, ELFHdr_e_shstrndx_Offset);
-
-  // Set the NameIdx of each section in the string table and emit the bytes for
-  // the string table.
-  unsigned Index = 0;
-
-  for (ELFSectionIter I=SectionList.begin(), E=SectionList.end(); I != E; ++I) {
-    ELFSection &S = *(*I);
-    // Set the index into the table.  Note if we have lots of entries with
-    // common suffixes, we could memoize them here if we cared.
-    S.NameIdx = Index;
-    SHStrTab.emitString(S.getName());
-
-    // Keep track of the number of bytes emitted to this section.
-    Index += S.getName().size()+1;
-  }
-
-  // Set the size of .shstrtab now that we know what it is.
-  assert(Index == SHStrTab.size());
-  SHStrTab.Size = Index;
-}
-
-/// OutputSectionsAndSectionTable - Now that we have constructed the file header
-/// and all of the sections, emit these to the ostream destination and emit the
-/// SectionTable.
-void ELFWriter::OutputSectionsAndSectionTable() {
-  // Pass #1: Compute the file offset for each section.
-  size_t FileOff = ElfHdr.size();   // File header first.
-
-  // Adjust alignment of all section if needed, skip the null section.
-  for (unsigned i=1, e=SectionList.size(); i < e; ++i) {
-    ELFSection &ES = *SectionList[i];
-    if (!ES.size()) {
-      ES.Offset = FileOff;
-      continue;
-    }
-
-    // Update Section size
-    if (!ES.Size)
-      ES.Size = ES.size();
-
-    // Align FileOff to whatever the alignment restrictions of the section are.
-    if (ES.Align)
-      FileOff = (FileOff+ES.Align-1) & ~(ES.Align-1);
-
-    ES.Offset = FileOff;
-    FileOff += ES.Size;
-  }
-
-  // Align Section Header.
-  unsigned TableAlign = TEW->getPrefELFAlignment();
-  FileOff = (FileOff+TableAlign-1) & ~(TableAlign-1);
-
-  // Now that we know where all of the sections will be emitted, set the e_shnum
-  // entry in the ELF header.
-  ElfHdr.fixWord16(NumSections, ELFHdr_e_shnum_Offset);
-
-  // Now that we know the offset in the file of the section table, update the
-  // e_shoff address in the ELF header.
-  ElfHdr.fixWord(FileOff, ELFHdr_e_shoff_Offset);
-
-  // Now that we know all of the data in the file header, emit it and all of the
-  // sections!
-  O.write((char *)&ElfHdr.getData()[0], ElfHdr.size());
-  FileOff = ElfHdr.size();
-
-  // Section Header Table blob
-  BinaryObject SHdrTable(isLittleEndian, is64Bit);
-
-  // Emit all of sections to the file and build the section header table.
-  for (ELFSectionIter I=SectionList.begin(), E=SectionList.end(); I != E; ++I) {
-    ELFSection &S = *(*I);
-    DEBUG(dbgs() << "SectionIdx: " << S.SectionIdx << ", Name: " << S.getName()
-                 << ", Size: " << S.Size << ", Offset: " << S.Offset
-                 << ", SectionData Size: " << S.size() << "\n");
-
-    // Align FileOff to whatever the alignment restrictions of the section are.
-    if (S.size()) {
-      if (S.Align)  {
-        for (size_t NewFileOff = (FileOff+S.Align-1) & ~(S.Align-1);
-             FileOff != NewFileOff; ++FileOff)
-          O << (char)0xAB;
-      }
-      O.write((char *)&S.getData()[0], S.Size);
-      FileOff += S.Size;
-    }
-
-    EmitSectionHeader(SHdrTable, S);
-  }
-
-  // Align output for the section table.
-  for (size_t NewFileOff = (FileOff+TableAlign-1) & ~(TableAlign-1);
-       FileOff != NewFileOff; ++FileOff)
-    O << (char)0xAB;
-
-  // Emit the section table itself.
-  O.write((char *)&SHdrTable.getData()[0], SHdrTable.size());
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/CodeGen/ELFWriter.h
--- a/head/contrib/llvm/lib/CodeGen/ELFWriter.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,251 +0,0 @@
-//===-- ELFWriter.h - Target-independent ELF writer support -----*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines the ELFWriter class.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef ELFWRITER_H
-#define ELFWRITER_H
-
-#include "llvm/ADT/SetVector.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include <map>
-
-namespace llvm {
-  class BinaryObject;
-  class Constant;
-  class ConstantInt;
-  class ConstantStruct;
-  class ELFCodeEmitter;
-  class ELFRelocation;
-  class ELFSection;
-  struct ELFSym;
-  class GlobalVariable;
-  class JITDebugRegisterer;
-  class Mangler;
-  class MachineCodeEmitter;
-  class MachineConstantPoolEntry;
-  class ObjectCodeEmitter;
-  class MCAsmInfo;
-  class TargetELFWriterInfo;
-  class TargetLoweringObjectFile;
-  class raw_ostream;
-  class SectionKind;
-  class MCContext;
-  class TargetMachine;
-
-  typedef std::vector<ELFSym*>::iterator ELFSymIter;
-  typedef std::vector<ELFSection*>::iterator ELFSectionIter;
-  typedef SetVector<const GlobalValue*>::const_iterator PendingGblsIter;
-  typedef SetVector<const char *>::const_iterator PendingExtsIter;
-  typedef std::pair<const Constant *, int64_t> CstExprResTy;
-
-  /// ELFWriter - This class implements the common target-independent code for
-  /// writing ELF files.  Targets should derive a class from this to
-  /// parameterize the output format.
-  ///
-  class ELFWriter : public MachineFunctionPass {
-    friend class ELFCodeEmitter;
-    friend class JITDebugRegisterer;
-  public:
-    static char ID;
-
-    /// Return the ELFCodeEmitter as an instance of ObjectCodeEmitter
-    ObjectCodeEmitter *getObjectCodeEmitter() {
-      return reinterpret_cast<ObjectCodeEmitter*>(ElfCE);
-    }
-
-    ELFWriter(raw_ostream &O, TargetMachine &TM);
-    ~ELFWriter();
-
-  protected:
-    /// Output stream to send the resultant object file to.
-    raw_ostream &O;
-
-    /// Target machine description.
-    TargetMachine &TM;
-
-    /// Context object for machine code objects.
-    MCContext &OutContext;
-    
-    /// Target Elf Writer description.
-    const TargetELFWriterInfo *TEW;
-
-    /// Mang - The object used to perform name mangling for this module.
-    Mangler *Mang;
-
-    /// MCE - The MachineCodeEmitter object that we are exposing to emit machine
-    /// code for functions to the .o file.
-    ELFCodeEmitter *ElfCE;
-
-    /// TLOF - Target Lowering Object File, provide section names for globals 
-    /// and other object file specific stuff
-    const TargetLoweringObjectFile &TLOF;
-
-    /// MAI - Target Asm Info, provide information about section names for
-    /// globals and other target specific stuff.
-    const MCAsmInfo *MAI;
-
-    //===------------------------------------------------------------------===//
-    // Properties inferred automatically from the target machine.
-    //===------------------------------------------------------------------===//
-
-    /// is64Bit/isLittleEndian - This information is inferred from the target
-    /// machine directly, indicating whether to emit a 32- or 64-bit ELF file.
-    bool is64Bit, isLittleEndian;
-
-    /// doInitialization - Emit the file header and all of the global variables
-    /// for the module to the ELF file.
-    bool doInitialization(Module &M);
-    bool runOnMachineFunction(MachineFunction &MF);
-
-    /// doFinalization - Now that the module has been completely processed, emit
-    /// the ELF file to 'O'.
-    bool doFinalization(Module &M);
-
-  private:
-    /// Blob containing the Elf header
-    BinaryObject ElfHdr;
-
-    /// SectionList - This is the list of sections that we have emitted to the
-    /// file. Once the file has been completely built, the section header table
-    /// is constructed from this info.
-    std::vector<ELFSection*> SectionList;
-    unsigned NumSections;   // Always = SectionList.size()
-
-    /// SectionLookup - This is a mapping from section name to section number in
-    /// the SectionList. Used to quickly gather the Section Index from MAI names
-    std::map<std::string, ELFSection*> SectionLookup;
-
-    /// PendingGlobals - Globals not processed as symbols yet.
-    SetVector<const GlobalValue*> PendingGlobals;
-
-    /// GblSymLookup - This is a mapping from global value to a symbol index
-    /// in the symbol table or private symbols list. This is useful since reloc
-    /// symbol references must be quickly mapped to their indices on the lists.
-    std::map<const GlobalValue*, uint32_t> GblSymLookup;
-
-    /// PendingExternals - Externals not processed as symbols yet.
-    SetVector<const char *> PendingExternals;
-
-    /// ExtSymLookup - This is a mapping from externals to a symbol index
-    /// in the symbol table list. This is useful since reloc symbol references
-    /// must be quickly mapped to their symbol table indices.
-    std::map<const char *, uint32_t> ExtSymLookup;
-
-    /// SymbolList - This is the list of symbols emitted to the symbol table.
-    /// When the SymbolList is finally built, local symbols must be placed in
-    /// the beginning while non-locals at the end.
-    std::vector<ELFSym*> SymbolList;
-
-    /// PrivateSyms - Record private symbols, every symbol here must never be
-    /// present in the SymbolList.
-    std::vector<ELFSym*> PrivateSyms;
-
-    /// getSection - Return the section with the specified name, creating a new
-    /// section if one does not already exist.
-    ELFSection &getSection(const std::string &Name, unsigned Type,
-                           unsigned Flags = 0, unsigned Align = 0) {
-      ELFSection *&SN = SectionLookup[Name];
-      if (SN) return *SN;
-
-      SectionList.push_back(new ELFSection(Name, isLittleEndian, is64Bit));
-      SN = SectionList.back();
-      SN->SectionIdx = NumSections++;
-      SN->Type = Type;
-      SN->Flags = Flags;
-      SN->Link = ELF::SHN_UNDEF;
-      SN->Align = Align;
-      return *SN;
-    }
-
-    ELFSection &getNonExecStackSection() {
-      return getSection(".note.GNU-stack", ELF::SHT_PROGBITS, 0, 1);
-    }
-
-    ELFSection &getSymbolTableSection() {
-      return getSection(".symtab", ELF::SHT_SYMTAB, 0);
-    }
-
-    ELFSection &getStringTableSection() {
-      return getSection(".strtab", ELF::SHT_STRTAB, 0, 1);
-    }
-
-    ELFSection &getSectionHeaderStringTableSection() {
-      return getSection(".shstrtab", ELF::SHT_STRTAB, 0, 1);
-    }
-
-    ELFSection &getNullSection() {
-      return getSection("", ELF::SHT_NULL, 0);
-    }
-
-    ELFSection &getDataSection();
-    ELFSection &getBSSSection();
-    ELFSection &getCtorSection();
-    ELFSection &getDtorSection();
-    ELFSection &getJumpTableSection();
-    ELFSection &getConstantPoolSection(MachineConstantPoolEntry &CPE);
-    ELFSection &getTextSection(const Function *F);
-    ELFSection &getRelocSection(ELFSection &S);
-
-    // Helpers for obtaining ELF specific info.
-    unsigned getGlobalELFBinding(const GlobalValue *GV);
-    unsigned getGlobalELFType(const GlobalValue *GV);
-    unsigned getGlobalELFVisibility(const GlobalValue *GV);
-
-    // AddPendingGlobalSymbol - Add a global to be processed and to
-    // the global symbol lookup, use a zero index because the table
-    // index will be determined later.
-    void AddPendingGlobalSymbol(const GlobalValue *GV, 
-                                bool AddToLookup = false);
-    
-    // AddPendingExternalSymbol - Add the external to be processed
-    // and to the external symbol lookup, use a zero index because
-    // the symbol table index will be determined later.
-    void AddPendingExternalSymbol(const char *External);
-
-    // AddToSymbolList - Update the symbol lookup and If the symbol is 
-    // private add it to PrivateSyms list, otherwise to SymbolList. 
-    void AddToSymbolList(ELFSym *GblSym);
-
-    // As we complete the ELF file, we need to update fields in the ELF header
-    // (e.g. the location of the section table).  These members keep track of
-    // the offset in ELFHeader of these various pieces to update and other
-    // locations in the file.
-    unsigned ELFHdr_e_shoff_Offset;     // e_shoff    in ELF header.
-    unsigned ELFHdr_e_shstrndx_Offset;  // e_shstrndx in ELF header.
-    unsigned ELFHdr_e_shnum_Offset;     // e_shnum    in ELF header.
-
-  private:
-    void EmitGlobal(const GlobalValue *GV);
-    void EmitGlobalConstant(const Constant *C, ELFSection &GblS);
-    void EmitGlobalConstantStruct(const ConstantStruct *CVS,
-                                  ELFSection &GblS);
-    void EmitGlobalConstantLargeInt(const ConstantInt *CI, ELFSection &S);
-    void EmitGlobalDataRelocation(const GlobalValue *GV, unsigned Size, 
-                                  ELFSection &GblS, int64_t Offset = 0);
-    bool EmitSpecialLLVMGlobal(const GlobalVariable *GV);
-    void EmitXXStructorList(const Constant *List, ELFSection &Xtor);
-    void EmitRelocations();
-    void EmitRelocation(BinaryObject &RelSec, ELFRelocation &Rel, bool HasRelA);
-    void EmitSectionHeader(BinaryObject &SHdrTab, const ELFSection &SHdr);
-    void EmitSectionTableStringTable();
-    void EmitSymbol(BinaryObject &SymbolTable, ELFSym &Sym);
-    void EmitSymbolTable();
-    void EmitStringTable(const std::string &ModuleName);
-    void OutputSectionsAndSectionTable();
-    void RelocateField(BinaryObject &BO, uint32_t Offset, int64_t Value,
-                       unsigned Size);
-    unsigned SortSymbols();
-    CstExprResTy ResolveConstantExpr(const Constant *CV);
-  };
-}
-
-#endif
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/CodeGen/LiveRangeEdit.h
--- a/head/contrib/llvm/lib/CodeGen/LiveRangeEdit.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,206 +0,0 @@
-//===---- LiveRangeEdit.h - Basic tools for split and spill -----*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// The LiveRangeEdit class represents changes done to a virtual register when it
-// is spilled or split.
-//
-// The parent register is never changed. Instead, a number of new virtual
-// registers are created and added to the newRegs vector.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_CODEGEN_LIVERANGEEDIT_H
-#define LLVM_CODEGEN_LIVERANGEEDIT_H
-
-#include "llvm/ADT/ArrayRef.h"
-#include "llvm/ADT/SmallPtrSet.h"
-#include "llvm/CodeGen/LiveInterval.h"
-
-namespace llvm {
-
-class AliasAnalysis;
-class LiveIntervals;
-class MachineLoopInfo;
-class MachineRegisterInfo;
-class VirtRegMap;
-
-class LiveRangeEdit {
-public:
-  /// Callback methods for LiveRangeEdit owners.
-  struct Delegate {
-    /// Called immediately before erasing a dead machine instruction.
-    virtual void LRE_WillEraseInstruction(MachineInstr *MI) {}
-
-    /// Called when a virtual register is no longer used. Return false to defer
-    /// its deletion from LiveIntervals.
-    virtual bool LRE_CanEraseVirtReg(unsigned) { return true; }
-
-    /// Called before shrinking the live range of a virtual register.
-    virtual void LRE_WillShrinkVirtReg(unsigned) {}
-
-    /// Called after cloning a virtual register.
-    /// This is used for new registers representing connected components of Old.
-    virtual void LRE_DidCloneVirtReg(unsigned New, unsigned Old) {}
-
-    virtual ~Delegate() {}
-  };
-
-private:
-  LiveInterval &parent_;
-  SmallVectorImpl<LiveInterval*> &newRegs_;
-  Delegate *const delegate_;
-  const SmallVectorImpl<LiveInterval*> *uselessRegs_;
-
-  /// firstNew_ - Index of the first register added to newRegs_.
-  const unsigned firstNew_;
-
-  /// scannedRemattable_ - true when remattable values have been identified.
-  bool scannedRemattable_;
-
-  /// remattable_ - Values defined by remattable instructions as identified by
-  /// tii.isTriviallyReMaterializable().
-  SmallPtrSet<const VNInfo*,4> remattable_;
-
-  /// rematted_ - Values that were actually rematted, and so need to have their
-  /// live range trimmed or entirely removed.
-  SmallPtrSet<const VNInfo*,4> rematted_;
-
-  /// scanRemattable - Identify the parent_ values that may rematerialize.
-  void scanRemattable(LiveIntervals &lis,
-                      const TargetInstrInfo &tii,
-                      AliasAnalysis *aa);
-
-  /// allUsesAvailableAt - Return true if all registers used by OrigMI at
-  /// OrigIdx are also available with the same value at UseIdx.
-  bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,
-                          SlotIndex UseIdx, LiveIntervals &lis);
-
-  /// foldAsLoad - If LI has a single use and a single def that can be folded as
-  /// a load, eliminate the register by folding the def into the use.
-  bool foldAsLoad(LiveInterval *LI, SmallVectorImpl<MachineInstr*> &Dead,
-                  MachineRegisterInfo&, LiveIntervals&, const TargetInstrInfo&);
-
-public:
-  /// Create a LiveRangeEdit for breaking down parent into smaller pieces.
-  /// @param parent The register being spilled or split.
-  /// @param newRegs List to receive any new registers created. This needn't be
-  ///                empty initially, any existing registers are ignored.
-  /// @param uselessRegs List of registers that can't be used when
-  ///        rematerializing values because they are about to be removed.
-  LiveRangeEdit(LiveInterval &parent,
-                SmallVectorImpl<LiveInterval*> &newRegs,
-                Delegate *delegate = 0,
-                const SmallVectorImpl<LiveInterval*> *uselessRegs = 0)
-    : parent_(parent), newRegs_(newRegs),
-      delegate_(delegate),
-      uselessRegs_(uselessRegs),
-      firstNew_(newRegs.size()),
-      scannedRemattable_(false) {}
-
-  LiveInterval &getParent() const { return parent_; }
-  unsigned getReg() const { return parent_.reg; }
-
-  /// Iterator for accessing the new registers added by this edit.
-  typedef SmallVectorImpl<LiveInterval*>::const_iterator iterator;
-  iterator begin() const { return newRegs_.begin()+firstNew_; }
-  iterator end() const { return newRegs_.end(); }
-  unsigned size() const { return newRegs_.size()-firstNew_; }
-  bool empty() const { return size() == 0; }
-  LiveInterval *get(unsigned idx) const { return newRegs_[idx+firstNew_]; }
-
-  ArrayRef<LiveInterval*> regs() const {
-    return makeArrayRef(newRegs_).slice(firstNew_);
-  }
-
-  /// FIXME: Temporary accessors until we can get rid of
-  /// LiveIntervals::AddIntervalsForSpills
-  SmallVectorImpl<LiveInterval*> *getNewVRegs() { return &newRegs_; }
-  const SmallVectorImpl<LiveInterval*> *getUselessVRegs() {
-    return uselessRegs_;
-  }
-
-  /// createFrom - Create a new virtual register based on OldReg.
-  LiveInterval &createFrom(unsigned OldReg, LiveIntervals&, VirtRegMap&);
-
-  /// create - Create a new register with the same class and original slot as
-  /// parent.
-  LiveInterval &create(LiveIntervals &LIS, VirtRegMap &VRM) {
-    return createFrom(getReg(), LIS, VRM);
-  }
-
-  /// anyRematerializable - Return true if any parent values may be
-  /// rematerializable.
-  /// This function must be called before any rematerialization is attempted.
-  bool anyRematerializable(LiveIntervals&, const TargetInstrInfo&,
-                           AliasAnalysis*);
-
-  /// checkRematerializable - Manually add VNI to the list of rematerializable
-  /// values if DefMI may be rematerializable.
-  bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI,
-                             const TargetInstrInfo&, AliasAnalysis*);
-
-  /// Remat - Information needed to rematerialize at a specific location.
-  struct Remat {
-    VNInfo *ParentVNI;      // parent_'s value at the remat location.
-    MachineInstr *OrigMI;   // Instruction defining ParentVNI.
-    explicit Remat(VNInfo *ParentVNI) : ParentVNI(ParentVNI), OrigMI(0) {}
-  };
-
-  /// canRematerializeAt - Determine if ParentVNI can be rematerialized at
-  /// UseIdx. It is assumed that parent_.getVNINfoAt(UseIdx) == ParentVNI.
-  /// When cheapAsAMove is set, only cheap remats are allowed.
-  bool canRematerializeAt(Remat &RM,
-                          SlotIndex UseIdx,
-                          bool cheapAsAMove,
-                          LiveIntervals &lis);
-
-  /// rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an
-  /// instruction into MBB before MI. The new instruction is mapped, but
-  /// liveness is not updated.
-  /// Return the SlotIndex of the new instruction.
-  SlotIndex rematerializeAt(MachineBasicBlock &MBB,
-                            MachineBasicBlock::iterator MI,
-                            unsigned DestReg,
-                            const Remat &RM,
-                            LiveIntervals&,
-                            const TargetInstrInfo&,
-                            const TargetRegisterInfo&,
-                            bool Late = false);
-
-  /// markRematerialized - explicitly mark a value as rematerialized after doing
-  /// it manually.
-  void markRematerialized(const VNInfo *ParentVNI) {
-    rematted_.insert(ParentVNI);
-  }
-
-  /// didRematerialize - Return true if ParentVNI was rematerialized anywhere.
-  bool didRematerialize(const VNInfo *ParentVNI) const {
-    return rematted_.count(ParentVNI);
-  }
-
-  /// eraseVirtReg - Notify the delegate that Reg is no longer in use, and try
-  /// to erase it from LIS.
-  void eraseVirtReg(unsigned Reg, LiveIntervals &LIS);
-
-  /// eliminateDeadDefs - Try to delete machine instructions that are now dead
-  /// (allDefsAreDead returns true). This may cause live intervals to be trimmed
-  /// and further dead efs to be eliminated.
-  void eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead,
-                         LiveIntervals&, VirtRegMap&,
-                         const TargetInstrInfo&);
-
-  /// calculateRegClassAndHint - Recompute register class and hint for each new
-  /// register.
-  void calculateRegClassAndHint(MachineFunction&, LiveIntervals&,
-                                const MachineLoopInfo&);
-};
-
-}
-
-#endif
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/CodeGen/ObjectCodeEmitter.cpp
--- a/head/contrib/llvm/lib/CodeGen/ObjectCodeEmitter.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,141 +0,0 @@
-//===-- llvm/CodeGen/ObjectCodeEmitter.cpp -------------------- -*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#include "llvm/CodeGen/BinaryObject.h"
-#include "llvm/CodeGen/MachineBasicBlock.h"
-#include "llvm/CodeGen/MachineRelocation.h"
-#include "llvm/CodeGen/ObjectCodeEmitter.h"
-
-//===----------------------------------------------------------------------===//
-//                       ObjectCodeEmitter Implementation
-//===----------------------------------------------------------------------===//
-
-namespace llvm {
-
-ObjectCodeEmitter::ObjectCodeEmitter() : BO(0) {}
-ObjectCodeEmitter::ObjectCodeEmitter(BinaryObject *bo) : BO(bo) {}
-ObjectCodeEmitter::~ObjectCodeEmitter() {}
-
-/// setBinaryObject - set the BinaryObject we are writting to
-void ObjectCodeEmitter::setBinaryObject(BinaryObject *bo) { BO = bo; }
-
-/// emitByte - This callback is invoked when a byte needs to be
-/// written to the data stream, without buffer overflow testing.
-void ObjectCodeEmitter::emitByte(uint8_t B) {
-  BO->emitByte(B);
-}
-
-/// emitWordLE - This callback is invoked when a 32-bit word needs to be
-/// written to the data stream in little-endian format.
-void ObjectCodeEmitter::emitWordLE(uint32_t W) {
-  BO->emitWordLE(W);
-}
-
-/// emitWordBE - This callback is invoked when a 32-bit word needs to be
-/// written to the data stream in big-endian format.
-void ObjectCodeEmitter::emitWordBE(uint32_t W) {
-  BO->emitWordBE(W);
-}
-
-/// emitDWordLE - This callback is invoked when a 64-bit word needs to be
-/// written to the data stream in little-endian format.
-void ObjectCodeEmitter::emitDWordLE(uint64_t W) {
-  BO->emitDWordLE(W);
-}
-
-/// emitDWordBE - This callback is invoked when a 64-bit word needs to be
-/// written to the data stream in big-endian format.
-void ObjectCodeEmitter::emitDWordBE(uint64_t W) {
-  BO->emitDWordBE(W);
-}
-
-/// emitAlignment - Align 'BO' to the necessary alignment boundary.
-void ObjectCodeEmitter::emitAlignment(unsigned Alignment /* 0 */,
-                                      uint8_t fill /* 0 */) {
-  BO->emitAlignment(Alignment, fill);
-}
-
-/// emitULEB128Bytes - This callback is invoked when a ULEB128 needs to be
-/// written to the data stream.
-void ObjectCodeEmitter::emitULEB128Bytes(uint64_t Value) {
-  BO->emitULEB128Bytes(Value);
-}
-
-/// emitSLEB128Bytes - This callback is invoked when a SLEB128 needs to be
-/// written to the data stream.
-void ObjectCodeEmitter::emitSLEB128Bytes(uint64_t Value) {
-  BO->emitSLEB128Bytes(Value);
-}
-
-/// emitString - This callback is invoked when a String needs to be
-/// written to the data stream.
-void ObjectCodeEmitter::emitString(const std::string &String) {
-  BO->emitString(String);
-}
-
-/// getCurrentPCValue - This returns the address that the next emitted byte
-/// will be output to.
-uintptr_t ObjectCodeEmitter::getCurrentPCValue() const {
-  return BO->getCurrentPCOffset();
-}
-
-/// getCurrentPCOffset - Return the offset from the start of the emitted
-/// buffer that we are currently writing to.
-uintptr_t ObjectCodeEmitter::getCurrentPCOffset() const {
-  return BO->getCurrentPCOffset();
-}
-
-/// addRelocation - Whenever a relocatable address is needed, it should be
-/// noted with this interface.
-void ObjectCodeEmitter::addRelocation(const MachineRelocation& relocation) {
-  BO->addRelocation(relocation);
-}
-
-/// StartMachineBasicBlock - This should be called by the target when a new
-/// basic block is about to be emitted.  This way the MCE knows where the
-/// start of the block is, and can implement getMachineBasicBlockAddress.
-void ObjectCodeEmitter::StartMachineBasicBlock(MachineBasicBlock *MBB) {
-  if (MBBLocations.size() <= (unsigned)MBB->getNumber())
-    MBBLocations.resize((MBB->getNumber()+1)*2);
-  MBBLocations[MBB->getNumber()] = getCurrentPCOffset();
-}
-
-/// getMachineBasicBlockAddress - Return the address of the specified
-/// MachineBasicBlock, only usable after the label for the MBB has been
-/// emitted.
-uintptr_t
-ObjectCodeEmitter::getMachineBasicBlockAddress(MachineBasicBlock *MBB) const {
-  assert(MBBLocations.size() > (unsigned)MBB->getNumber() &&
-         MBBLocations[MBB->getNumber()] && "MBB not emitted!");
-  return MBBLocations[MBB->getNumber()];
-}
-
-/// getJumpTableEntryAddress - Return the address of the jump table with index
-/// 'Index' in the function that last called initJumpTableInfo.
-uintptr_t ObjectCodeEmitter::getJumpTableEntryAddress(unsigned Index) const {
-  assert(JTLocations.size() > Index && "JT not emitted!");
-  return JTLocations[Index];
-}
-
-/// getConstantPoolEntryAddress - Return the address of the 'Index' entry in
-/// the constant pool that was last emitted with the emitConstantPool method.
-uintptr_t ObjectCodeEmitter::getConstantPoolEntryAddress(unsigned Index) const {
-  assert(CPLocations.size() > Index && "CP not emitted!");
-  return CPLocations[Index];
-}
-
-/// getConstantPoolEntrySection - Return the section of the 'Index' entry in
-/// the constant pool that was last emitted with the emitConstantPool method.
-uintptr_t ObjectCodeEmitter::getConstantPoolEntrySection(unsigned Index) const {
-  assert(CPSections.size() > Index && "CP not emitted!");
-  return CPSections[Index];
-}
-
-} // end namespace llvm
-
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/CodeGen/RegAllocLinearScan.cpp
--- a/head/contrib/llvm/lib/CodeGen/RegAllocLinearScan.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1543 +0,0 @@
-//===-- RegAllocLinearScan.cpp - Linear Scan register allocator -----------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements a linear scan register allocator.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "regalloc"
-#include "LiveDebugVariables.h"
-#include "LiveRangeEdit.h"
-#include "VirtRegMap.h"
-#include "VirtRegRewriter.h"
-#include "RegisterClassInfo.h"
-#include "Spiller.h"
-#include "llvm/Analysis/AliasAnalysis.h"
-#include "llvm/Function.h"
-#include "llvm/CodeGen/CalcSpillWeights.h"
-#include "llvm/CodeGen/LiveIntervalAnalysis.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/MachineLoopInfo.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/Passes.h"
-#include "llvm/CodeGen/RegAllocRegistry.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/ADT/EquivalenceClasses.h"
-#include "llvm/ADT/SmallSet.h"
-#include "llvm/ADT/Statistic.h"
-#include "llvm/ADT/STLExtras.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/raw_ostream.h"
-#include <algorithm>
-#include <queue>
-#include <memory>
-#include <cmath>
-
-using namespace llvm;
-
-STATISTIC(NumIters     , "Number of iterations performed");
-STATISTIC(NumBacktracks, "Number of times we had to backtrack");
-STATISTIC(NumCoalesce,   "Number of copies coalesced");
-STATISTIC(NumDowngrade,  "Number of registers downgraded");
-
-static cl::opt<bool>
-NewHeuristic("new-spilling-heuristic",
-             cl::desc("Use new spilling heuristic"),
-             cl::init(false), cl::Hidden);
-
-static cl::opt<bool>
-TrivCoalesceEnds("trivial-coalesce-ends",
-                  cl::desc("Attempt trivial coalescing of interval ends"),
-                  cl::init(false), cl::Hidden);
-
-static cl::opt<bool>
-AvoidWAWHazard("avoid-waw-hazard",
-               cl::desc("Avoid write-write hazards for some register classes"),
-               cl::init(false), cl::Hidden);
-
-static RegisterRegAlloc
-linearscanRegAlloc("linearscan", "linear scan register allocator",
-                   createLinearScanRegisterAllocator);
-
-namespace {
-  // When we allocate a register, add it to a fixed-size queue of
-  // registers to skip in subsequent allocations. This trades a small
-  // amount of register pressure and increased spills for flexibility in
-  // the post-pass scheduler.
-  //
-  // Note that in a the number of registers used for reloading spills
-  // will be one greater than the value of this option.
-  //
-  // One big limitation of this is that it doesn't differentiate between
-  // different register classes. So on x86-64, if there is xmm register
-  // pressure, it can caused fewer GPRs to be held in the queue.
-  static cl::opt<unsigned>
-  NumRecentlyUsedRegs("linearscan-skip-count",
-                      cl::desc("Number of registers for linearscan to remember"
-                               "to skip."),
-                      cl::init(0),
-                      cl::Hidden);
-
-  struct RALinScan : public MachineFunctionPass {
-    static char ID;
-    RALinScan() : MachineFunctionPass(ID) {
-      initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
-      initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
-      initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
-      initializeRegisterCoalescerPass(
-        *PassRegistry::getPassRegistry());
-      initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
-      initializeLiveStacksPass(*PassRegistry::getPassRegistry());
-      initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
-      initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
-      initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
-      initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
-      
-      // Initialize the queue to record recently-used registers.
-      if (NumRecentlyUsedRegs > 0)
-        RecentRegs.resize(NumRecentlyUsedRegs, 0);
-      RecentNext = RecentRegs.begin();
-      avoidWAW_ = 0;
-    }
-
-    typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
-    typedef SmallVector<IntervalPtr, 32> IntervalPtrs;
-  private:
-    /// RelatedRegClasses - This structure is built the first time a function is
-    /// compiled, and keeps track of which register classes have registers that
-    /// belong to multiple classes or have aliases that are in other classes.
-    EquivalenceClasses<const TargetRegisterClass*> RelatedRegClasses;
-    DenseMap<unsigned, const TargetRegisterClass*> OneClassForEachPhysReg;
-
-    // NextReloadMap - For each register in the map, it maps to the another
-    // register which is defined by a reload from the same stack slot and
-    // both reloads are in the same basic block.
-    DenseMap<unsigned, unsigned> NextReloadMap;
-
-    // DowngradedRegs - A set of registers which are being "downgraded", i.e.
-    // un-favored for allocation.
-    SmallSet<unsigned, 8> DowngradedRegs;
-
-    // DowngradeMap - A map from virtual registers to physical registers being
-    // downgraded for the virtual registers.
-    DenseMap<unsigned, unsigned> DowngradeMap;
-
-    MachineFunction* mf_;
-    MachineRegisterInfo* mri_;
-    const TargetMachine* tm_;
-    const TargetRegisterInfo* tri_;
-    const TargetInstrInfo* tii_;
-    BitVector allocatableRegs_;
-    BitVector reservedRegs_;
-    LiveIntervals* li_;
-    MachineLoopInfo *loopInfo;
-    RegisterClassInfo RegClassInfo;
-
-    /// handled_ - Intervals are added to the handled_ set in the order of their
-    /// start value.  This is uses for backtracking.
-    std::vector<LiveInterval*> handled_;
-
-    /// fixed_ - Intervals that correspond to machine registers.
-    ///
-    IntervalPtrs fixed_;
-
-    /// active_ - Intervals that are currently being processed, and which have a
-    /// live range active for the current point.
-    IntervalPtrs active_;
-
-    /// inactive_ - Intervals that are currently being processed, but which have
-    /// a hold at the current point.
-    IntervalPtrs inactive_;
-
-    typedef std::priority_queue<LiveInterval*,
-                                SmallVector<LiveInterval*, 64>,
-                                greater_ptr<LiveInterval> > IntervalHeap;
-    IntervalHeap unhandled_;
-
-    /// regUse_ - Tracks register usage.
-    SmallVector<unsigned, 32> regUse_;
-    SmallVector<unsigned, 32> regUseBackUp_;
-
-    /// vrm_ - Tracks register assignments.
-    VirtRegMap* vrm_;
-
-    std::auto_ptr<VirtRegRewriter> rewriter_;
-
-    std::auto_ptr<Spiller> spiller_;
-
-    // The queue of recently-used registers.
-    SmallVector<unsigned, 4> RecentRegs;
-    SmallVector<unsigned, 4>::iterator RecentNext;
-
-    // Last write-after-write register written.
-    unsigned avoidWAW_;
-
-    // Record that we just picked this register.
-    void recordRecentlyUsed(unsigned reg) {
-      assert(reg != 0 && "Recently used register is NOREG!");
-      if (!RecentRegs.empty()) {
-        *RecentNext++ = reg;
-        if (RecentNext == RecentRegs.end())
-          RecentNext = RecentRegs.begin();
-      }
-    }
-
-  public:
-    virtual const char* getPassName() const {
-      return "Linear Scan Register Allocator";
-    }
-
-    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
-      AU.setPreservesCFG();
-      AU.addRequired<AliasAnalysis>();
-      AU.addPreserved<AliasAnalysis>();
-      AU.addRequired<LiveIntervals>();
-      AU.addPreserved<SlotIndexes>();
-      if (StrongPHIElim)
-        AU.addRequiredID(StrongPHIEliminationID);
-      // Make sure PassManager knows which analyses to make available
-      // to coalescing and which analyses coalescing invalidates.
-      AU.addRequiredTransitiveID(RegisterCoalescerPassID);
-      AU.addRequired<CalculateSpillWeights>();
-      AU.addRequiredID(LiveStacksID);
-      AU.addPreservedID(LiveStacksID);
-      AU.addRequired<MachineLoopInfo>();
-      AU.addPreserved<MachineLoopInfo>();
-      AU.addRequired<VirtRegMap>();
-      AU.addPreserved<VirtRegMap>();
-      AU.addRequired<LiveDebugVariables>();
-      AU.addPreserved<LiveDebugVariables>();
-      AU.addRequiredID(MachineDominatorsID);
-      AU.addPreservedID(MachineDominatorsID);
-      MachineFunctionPass::getAnalysisUsage(AU);
-    }
-
-    /// runOnMachineFunction - register allocate the whole function
-    bool runOnMachineFunction(MachineFunction&);
-
-    // Determine if we skip this register due to its being recently used.
-    bool isRecentlyUsed(unsigned reg) const {
-      return reg == avoidWAW_ ||
-       std::find(RecentRegs.begin(), RecentRegs.end(), reg) != RecentRegs.end();
-    }
-
-  private:
-    /// linearScan - the linear scan algorithm
-    void linearScan();
-
-    /// initIntervalSets - initialize the interval sets.
-    ///
-    void initIntervalSets();
-
-    /// processActiveIntervals - expire old intervals and move non-overlapping
-    /// ones to the inactive list.
-    void processActiveIntervals(SlotIndex CurPoint);
-
-    /// processInactiveIntervals - expire old intervals and move overlapping
-    /// ones to the active list.
-    void processInactiveIntervals(SlotIndex CurPoint);
-
-    /// hasNextReloadInterval - Return the next liveinterval that's being
-    /// defined by a reload from the same SS as the specified one.
-    LiveInterval *hasNextReloadInterval(LiveInterval *cur);
-
-    /// DowngradeRegister - Downgrade a register for allocation.
-    void DowngradeRegister(LiveInterval *li, unsigned Reg);
-
-    /// UpgradeRegister - Upgrade a register for allocation.
-    void UpgradeRegister(unsigned Reg);
-
-    /// assignRegOrStackSlotAtInterval - assign a register if one
-    /// is available, or spill.
-    void assignRegOrStackSlotAtInterval(LiveInterval* cur);
-
-    void updateSpillWeights(std::vector<float> &Weights,
-                            unsigned reg, float weight,
-                            const TargetRegisterClass *RC);
-
-    /// findIntervalsToSpill - Determine the intervals to spill for the
-    /// specified interval. It's passed the physical registers whose spill
-    /// weight is the lowest among all the registers whose live intervals
-    /// conflict with the interval.
-    void findIntervalsToSpill(LiveInterval *cur,
-                            std::vector<std::pair<unsigned,float> > &Candidates,
-                            unsigned NumCands,
-                            SmallVector<LiveInterval*, 8> &SpillIntervals);
-
-    /// attemptTrivialCoalescing - If a simple interval is defined by a copy,
-    /// try to allocate the definition to the same register as the source,
-    /// if the register is not defined during the life time of the interval.
-    /// This eliminates a copy, and is used to coalesce copies which were not
-    /// coalesced away before allocation either due to dest and src being in
-    /// different register classes or because the coalescer was overly
-    /// conservative.
-    unsigned attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg);
-
-    ///
-    /// Register usage / availability tracking helpers.
-    ///
-
-    void initRegUses() {
-      regUse_.resize(tri_->getNumRegs(), 0);
-      regUseBackUp_.resize(tri_->getNumRegs(), 0);
-    }
-
-    void finalizeRegUses() {
-#ifndef NDEBUG
-      // Verify all the registers are "freed".
-      bool Error = false;
-      for (unsigned i = 0, e = tri_->getNumRegs(); i != e; ++i) {
-        if (regUse_[i] != 0) {
-          dbgs() << tri_->getName(i) << " is still in use!\n";
-          Error = true;
-        }
-      }
-      if (Error)
-        llvm_unreachable(0);
-#endif
-      regUse_.clear();
-      regUseBackUp_.clear();
-    }
-
-    void addRegUse(unsigned physReg) {
-      assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
-             "should be physical register!");
-      ++regUse_[physReg];
-      for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as)
-        ++regUse_[*as];
-    }
-
-    void delRegUse(unsigned physReg) {
-      assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
-             "should be physical register!");
-      assert(regUse_[physReg] != 0);
-      --regUse_[physReg];
-      for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) {
-        assert(regUse_[*as] != 0);
-        --regUse_[*as];
-      }
-    }
-
-    bool isRegAvail(unsigned physReg) const {
-      assert(TargetRegisterInfo::isPhysicalRegister(physReg) &&
-             "should be physical register!");
-      return regUse_[physReg] == 0;
-    }
-
-    void backUpRegUses() {
-      regUseBackUp_ = regUse_;
-    }
-
-    void restoreRegUses() {
-      regUse_ = regUseBackUp_;
-    }
-
-    ///
-    /// Register handling helpers.
-    ///
-
-    /// getFreePhysReg - return a free physical register for this virtual
-    /// register interval if we have one, otherwise return 0.
-    unsigned getFreePhysReg(LiveInterval* cur);
-    unsigned getFreePhysReg(LiveInterval* cur,
-                            const TargetRegisterClass *RC,
-                            unsigned MaxInactiveCount,
-                            SmallVector<unsigned, 256> &inactiveCounts,
-                            bool SkipDGRegs);
-
-    /// getFirstNonReservedPhysReg - return the first non-reserved physical
-    /// register in the register class.
-    unsigned getFirstNonReservedPhysReg(const TargetRegisterClass *RC) {
-      ArrayRef<unsigned> O = RegClassInfo.getOrder(RC);
-      assert(!O.empty() && "All registers reserved?!");
-      return O.front();
-    }
-
-    void ComputeRelatedRegClasses();
-
-    template <typename ItTy>
-    void printIntervals(const char* const str, ItTy i, ItTy e) const {
-      DEBUG({
-          if (str)
-            dbgs() << str << " intervals:\n";
-
-          for (; i != e; ++i) {
-            dbgs() << '\t' << *i->first << " -> ";
-
-            unsigned reg = i->first->reg;
-            if (TargetRegisterInfo::isVirtualRegister(reg))
-              reg = vrm_->getPhys(reg);
-
-            dbgs() << tri_->getName(reg) << '\n';
-          }
-        });
-    }
-  };
-  char RALinScan::ID = 0;
-}
-
-INITIALIZE_PASS_BEGIN(RALinScan, "linearscan-regalloc",
-                      "Linear Scan Register Allocator", false, false)
-INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
-INITIALIZE_PASS_DEPENDENCY(StrongPHIElimination)
-INITIALIZE_PASS_DEPENDENCY(CalculateSpillWeights)
-INITIALIZE_PASS_DEPENDENCY(LiveStacks)
-INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
-INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
-INITIALIZE_PASS_DEPENDENCY(RegisterCoalescer)
-INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
-INITIALIZE_PASS_END(RALinScan, "linearscan-regalloc",
-                    "Linear Scan Register Allocator", false, false)
-
-void RALinScan::ComputeRelatedRegClasses() {
-  // First pass, add all reg classes to the union, and determine at least one
-  // reg class that each register is in.
-  bool HasAliases = false;
-  for (TargetRegisterInfo::regclass_iterator RCI = tri_->regclass_begin(),
-       E = tri_->regclass_end(); RCI != E; ++RCI) {
-    RelatedRegClasses.insert(*RCI);
-    for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
-         I != E; ++I) {
-      HasAliases = HasAliases || *tri_->getAliasSet(*I) != 0;
-
-      const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I];
-      if (PRC) {
-        // Already processed this register.  Just make sure we know that
-        // multiple register classes share a register.
-        RelatedRegClasses.unionSets(PRC, *RCI);
-      } else {
-        PRC = *RCI;
-      }
-    }
-  }
-
-  // Second pass, now that we know conservatively what register classes each reg
-  // belongs to, add info about aliases.  We don't need to do this for targets
-  // without register aliases.
-  if (HasAliases)
-    for (DenseMap<unsigned, const TargetRegisterClass*>::iterator
-         I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
-         I != E; ++I)
-      for (const unsigned *AS = tri_->getAliasSet(I->first); *AS; ++AS) {
-        const TargetRegisterClass *AliasClass = 
-          OneClassForEachPhysReg.lookup(*AS);
-        if (AliasClass)
-          RelatedRegClasses.unionSets(I->second, AliasClass);
-      }
-}
-
-/// attemptTrivialCoalescing - If a simple interval is defined by a copy, try
-/// allocate the definition the same register as the source register if the
-/// register is not defined during live time of the interval. If the interval is
-/// killed by a copy, try to use the destination register. This eliminates a
-/// copy. This is used to coalesce copies which were not coalesced away before
-/// allocation either due to dest and src being in different register classes or
-/// because the coalescer was overly conservative.
-unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
-  unsigned Preference = vrm_->getRegAllocPref(cur.reg);
-  if ((Preference && Preference == Reg) || !cur.containsOneValue())
-    return Reg;
-
-  // We cannot handle complicated live ranges. Simple linear stuff only.
-  if (cur.ranges.size() != 1)
-    return Reg;
-
-  const LiveRange &range = cur.ranges.front();
-
-  VNInfo *vni = range.valno;
-  if (vni->isUnused() || !vni->def.isValid())
-    return Reg;
-
-  unsigned CandReg;
-  {
-    MachineInstr *CopyMI;
-    if ((CopyMI = li_->getInstructionFromIndex(vni->def)) && CopyMI->isCopy())
-      // Defined by a copy, try to extend SrcReg forward
-      CandReg = CopyMI->getOperand(1).getReg();
-    else if (TrivCoalesceEnds &&
-            (CopyMI = li_->getInstructionFromIndex(range.end.getBaseIndex())) &&
-             CopyMI->isCopy() && cur.reg == CopyMI->getOperand(1).getReg())
-      // Only used by a copy, try to extend DstReg backwards
-      CandReg = CopyMI->getOperand(0).getReg();
-    else
-      return Reg;
-
-    // If the target of the copy is a sub-register then don't coalesce.
-    if(CopyMI->getOperand(0).getSubReg())
-      return Reg;
-  }
-
-  if (TargetRegisterInfo::isVirtualRegister(CandReg)) {
-    if (!vrm_->isAssignedReg(CandReg))
-      return Reg;
-    CandReg = vrm_->getPhys(CandReg);
-  }
-  if (Reg == CandReg)
-    return Reg;
-
-  const TargetRegisterClass *RC = mri_->getRegClass(cur.reg);
-  if (!RC->contains(CandReg))
-    return Reg;
-
-  if (li_->conflictsWithPhysReg(cur, *vrm_, CandReg))
-    return Reg;
-
-  // Try to coalesce.
-  DEBUG(dbgs() << "Coalescing: " << cur << " -> " << tri_->getName(CandReg)
-        << '\n');
-  vrm_->clearVirt(cur.reg);
-  vrm_->assignVirt2Phys(cur.reg, CandReg);
-
-  ++NumCoalesce;
-  return CandReg;
-}
-
-bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
-  mf_ = &fn;
-  mri_ = &fn.getRegInfo();
-  tm_ = &fn.getTarget();
-  tri_ = tm_->getRegisterInfo();
-  tii_ = tm_->getInstrInfo();
-  allocatableRegs_ = tri_->getAllocatableSet(fn);
-  reservedRegs_ = tri_->getReservedRegs(fn);
-  li_ = &getAnalysis<LiveIntervals>();
-  loopInfo = &getAnalysis<MachineLoopInfo>();
-  RegClassInfo.runOnMachineFunction(fn);
-
-  // We don't run the coalescer here because we have no reason to
-  // interact with it.  If the coalescer requires interaction, it
-  // won't do anything.  If it doesn't require interaction, we assume
-  // it was run as a separate pass.
-
-  // If this is the first function compiled, compute the related reg classes.
-  if (RelatedRegClasses.empty())
-    ComputeRelatedRegClasses();
-
-  // Also resize register usage trackers.
-  initRegUses();
-
-  vrm_ = &getAnalysis<VirtRegMap>();
-  if (!rewriter_.get()) rewriter_.reset(createVirtRegRewriter());
-
-  spiller_.reset(createSpiller(*this, *mf_, *vrm_));
-
-  initIntervalSets();
-
-  linearScan();
-
-  // Rewrite spill code and update the PhysRegsUsed set.
-  rewriter_->runOnMachineFunction(*mf_, *vrm_, li_);
-
-  // Write out new DBG_VALUE instructions.
-  getAnalysis<LiveDebugVariables>().emitDebugValues(vrm_);
-
-  assert(unhandled_.empty() && "Unhandled live intervals remain!");
-
-  finalizeRegUses();
-
-  fixed_.clear();
-  active_.clear();
-  inactive_.clear();
-  handled_.clear();
-  NextReloadMap.clear();
-  DowngradedRegs.clear();
-  DowngradeMap.clear();
-  spiller_.reset(0);
-
-  return true;
-}
-
-/// initIntervalSets - initialize the interval sets.
-///
-void RALinScan::initIntervalSets()
-{
-  assert(unhandled_.empty() && fixed_.empty() &&
-         active_.empty() && inactive_.empty() &&
-         "interval sets should be empty on initialization");
-
-  handled_.reserve(li_->getNumIntervals());
-
-  for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
-    if (TargetRegisterInfo::isPhysicalRegister(i->second->reg)) {
-      if (!i->second->empty() && allocatableRegs_.test(i->second->reg)) {
-        mri_->setPhysRegUsed(i->second->reg);
-        fixed_.push_back(std::make_pair(i->second, i->second->begin()));
-      }
-    } else {
-      if (i->second->empty()) {
-        assignRegOrStackSlotAtInterval(i->second);
-      }
-      else
-        unhandled_.push(i->second);
-    }
-  }
-}
-
-void RALinScan::linearScan() {
-  // linear scan algorithm
-  DEBUG({
-      dbgs() << "********** LINEAR SCAN **********\n"
-             << "********** Function: "
-             << mf_->getFunction()->getName() << '\n';
-      printIntervals("fixed", fixed_.begin(), fixed_.end());
-    });
-
-  while (!unhandled_.empty()) {
-    // pick the interval with the earliest start point
-    LiveInterval* cur = unhandled_.top();
-    unhandled_.pop();
-    ++NumIters;
-    DEBUG(dbgs() << "\n*** CURRENT ***: " << *cur << '\n');
-
-    assert(!cur->empty() && "Empty interval in unhandled set.");
-
-    processActiveIntervals(cur->beginIndex());
-    processInactiveIntervals(cur->beginIndex());
-
-    assert(TargetRegisterInfo::isVirtualRegister(cur->reg) &&
-           "Can only allocate virtual registers!");
-
-    // Allocating a virtual register. try to find a free
-    // physical register or spill an interval (possibly this one) in order to
-    // assign it one.
-    assignRegOrStackSlotAtInterval(cur);
-
-    DEBUG({
-        printIntervals("active", active_.begin(), active_.end());
-        printIntervals("inactive", inactive_.begin(), inactive_.end());
-      });
-  }
-
-  // Expire any remaining active intervals
-  while (!active_.empty()) {
-    IntervalPtr &IP = active_.back();
-    unsigned reg = IP.first->reg;
-    DEBUG(dbgs() << "\tinterval " << *IP.first << " expired\n");
-    assert(TargetRegisterInfo::isVirtualRegister(reg) &&
-           "Can only allocate virtual registers!");
-    reg = vrm_->getPhys(reg);
-    delRegUse(reg);
-    active_.pop_back();
-  }
-
-  // Expire any remaining inactive intervals
-  DEBUG({
-      for (IntervalPtrs::reverse_iterator
-             i = inactive_.rbegin(); i != inactive_.rend(); ++i)
-        dbgs() << "\tinterval " << *i->first << " expired\n";
-    });
-  inactive_.clear();
-
-  // Add live-ins to every BB except for entry. Also perform trivial coalescing.
-  MachineFunction::iterator EntryMBB = mf_->begin();
-  SmallVector<MachineBasicBlock*, 8> LiveInMBBs;
-  for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
-    LiveInterval &cur = *i->second;
-    unsigned Reg = 0;
-    bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg);
-    if (isPhys)
-      Reg = cur.reg;
-    else if (vrm_->isAssignedReg(cur.reg))
-      Reg = attemptTrivialCoalescing(cur, vrm_->getPhys(cur.reg));
-    if (!Reg)
-      continue;
-    // Ignore splited live intervals.
-    if (!isPhys && vrm_->getPreSplitReg(cur.reg))
-      continue;
-
-    for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end();
-         I != E; ++I) {
-      const LiveRange &LR = *I;
-      if (li_->findLiveInMBBs(LR.start, LR.end, LiveInMBBs)) {
-        for (unsigned i = 0, e = LiveInMBBs.size(); i != e; ++i)
-          if (LiveInMBBs[i] != EntryMBB) {
-            assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
-                   "Adding a virtual register to livein set?");
-            LiveInMBBs[i]->addLiveIn(Reg);
-          }
-        LiveInMBBs.clear();
-      }
-    }
-  }
-
-  DEBUG(dbgs() << *vrm_);
-
-  // Look for physical registers that end up not being allocated even though
-  // register allocator had to spill other registers in its register class.
-  if (!vrm_->FindUnusedRegisters(li_))
-    return;
-}
-
-/// processActiveIntervals - expire old intervals and move non-overlapping ones
-/// to the inactive list.
-void RALinScan::processActiveIntervals(SlotIndex CurPoint)
-{
-  DEBUG(dbgs() << "\tprocessing active intervals:\n");
-
-  for (unsigned i = 0, e = active_.size(); i != e; ++i) {
-    LiveInterval *Interval = active_[i].first;
-    LiveInterval::iterator IntervalPos = active_[i].second;
-    unsigned reg = Interval->reg;
-
-    IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
-
-    if (IntervalPos == Interval->end()) {     // Remove expired intervals.
-      DEBUG(dbgs() << "\t\tinterval " << *Interval << " expired\n");
-      assert(TargetRegisterInfo::isVirtualRegister(reg) &&
-             "Can only allocate virtual registers!");
-      reg = vrm_->getPhys(reg);
-      delRegUse(reg);
-
-      // Pop off the end of the list.
-      active_[i] = active_.back();
-      active_.pop_back();
-      --i; --e;
-
-    } else if (IntervalPos->start > CurPoint) {
-      // Move inactive intervals to inactive list.
-      DEBUG(dbgs() << "\t\tinterval " << *Interval << " inactive\n");
-      assert(TargetRegisterInfo::isVirtualRegister(reg) &&
-             "Can only allocate virtual registers!");
-      reg = vrm_->getPhys(reg);
-      delRegUse(reg);
-      // add to inactive.
-      inactive_.push_back(std::make_pair(Interval, IntervalPos));
-
-      // Pop off the end of the list.
-      active_[i] = active_.back();
-      active_.pop_back();
-      --i; --e;
-    } else {
-      // Otherwise, just update the iterator position.
-      active_[i].second = IntervalPos;
-    }
-  }
-}
-
-/// processInactiveIntervals - expire old intervals and move overlapping
-/// ones to the active list.
-void RALinScan::processInactiveIntervals(SlotIndex CurPoint)
-{
-  DEBUG(dbgs() << "\tprocessing inactive intervals:\n");
-
-  for (unsigned i = 0, e = inactive_.size(); i != e; ++i) {
-    LiveInterval *Interval = inactive_[i].first;
-    LiveInterval::iterator IntervalPos = inactive_[i].second;
-    unsigned reg = Interval->reg;
-
-    IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
-
-    if (IntervalPos == Interval->end()) {       // remove expired intervals.
-      DEBUG(dbgs() << "\t\tinterval " << *Interval << " expired\n");
-
-      // Pop off the end of the list.
-      inactive_[i] = inactive_.back();
-      inactive_.pop_back();
-      --i; --e;
-    } else if (IntervalPos->start <= CurPoint) {
-      // move re-activated intervals in active list
-      DEBUG(dbgs() << "\t\tinterval " << *Interval << " active\n");
-      assert(TargetRegisterInfo::isVirtualRegister(reg) &&
-             "Can only allocate virtual registers!");
-      reg = vrm_->getPhys(reg);
-      addRegUse(reg);
-      // add to active
-      active_.push_back(std::make_pair(Interval, IntervalPos));
-
-      // Pop off the end of the list.
-      inactive_[i] = inactive_.back();
-      inactive_.pop_back();
-      --i; --e;
-    } else {
-      // Otherwise, just update the iterator position.
-      inactive_[i].second = IntervalPos;
-    }
-  }
-}
-
-/// updateSpillWeights - updates the spill weights of the specifed physical
-/// register and its weight.
-void RALinScan::updateSpillWeights(std::vector<float> &Weights,
-                                   unsigned reg, float weight,
-                                   const TargetRegisterClass *RC) {
-  SmallSet<unsigned, 4> Processed;
-  SmallSet<unsigned, 4> SuperAdded;
-  SmallVector<unsigned, 4> Supers;
-  Weights[reg] += weight;
-  Processed.insert(reg);
-  for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) {
-    Weights[*as] += weight;
-    Processed.insert(*as);
-    if (tri_->isSubRegister(*as, reg) &&
-        SuperAdded.insert(*as) &&
-        RC->contains(*as)) {
-      Supers.push_back(*as);
-    }
-  }
-
-  // If the alias is a super-register, and the super-register is in the
-  // register class we are trying to allocate. Then add the weight to all
-  // sub-registers of the super-register even if they are not aliases.
-  // e.g. allocating for GR32, bh is not used, updating bl spill weight.
-  //      bl should get the same spill weight otherwise it will be chosen
-  //      as a spill candidate since spilling bh doesn't make ebx available.
-  for (unsigned i = 0, e = Supers.size(); i != e; ++i) {
-    for (const unsigned *sr = tri_->getSubRegisters(Supers[i]); *sr; ++sr)
-      if (!Processed.count(*sr))
-        Weights[*sr] += weight;
-  }
-}
-
-static
-RALinScan::IntervalPtrs::iterator
-FindIntervalInVector(RALinScan::IntervalPtrs &IP, LiveInterval *LI) {
-  for (RALinScan::IntervalPtrs::iterator I = IP.begin(), E = IP.end();
-       I != E; ++I)
-    if (I->first == LI) return I;
-  return IP.end();
-}
-
-static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V,
-                                    SlotIndex Point){
-  for (unsigned i = 0, e = V.size(); i != e; ++i) {
-    RALinScan::IntervalPtr &IP = V[i];
-    LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
-                                                IP.second, Point);
-    if (I != IP.first->begin()) --I;
-    IP.second = I;
-  }
-}
-
-/// getConflictWeight - Return the number of conflicts between cur
-/// live interval and defs and uses of Reg weighted by loop depthes.
-static
-float getConflictWeight(LiveInterval *cur, unsigned Reg, LiveIntervals *li_,
-                        MachineRegisterInfo *mri_,
-                        MachineLoopInfo *loopInfo) {
-  float Conflicts = 0;
-  for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
-         E = mri_->reg_end(); I != E; ++I) {
-    MachineInstr *MI = &*I;
-    if (cur->liveAt(li_->getInstructionIndex(MI))) {
-      unsigned loopDepth = loopInfo->getLoopDepth(MI->getParent());
-      Conflicts += std::pow(10.0f, (float)loopDepth);
-    }
-  }
-  return Conflicts;
-}
-
-/// findIntervalsToSpill - Determine the intervals to spill for the
-/// specified interval. It's passed the physical registers whose spill
-/// weight is the lowest among all the registers whose live intervals
-/// conflict with the interval.
-void RALinScan::findIntervalsToSpill(LiveInterval *cur,
-                            std::vector<std::pair<unsigned,float> > &Candidates,
-                            unsigned NumCands,
-                            SmallVector<LiveInterval*, 8> &SpillIntervals) {
-  // We have figured out the *best* register to spill. But there are other
-  // registers that are pretty good as well (spill weight within 3%). Spill
-  // the one that has fewest defs and uses that conflict with cur.
-  float Conflicts[3] = { 0.0f, 0.0f, 0.0f };
-  SmallVector<LiveInterval*, 8> SLIs[3];
-
-  DEBUG({
-      dbgs() << "\tConsidering " << NumCands << " candidates: ";
-      for (unsigned i = 0; i != NumCands; ++i)
-        dbgs() << tri_->getName(Candidates[i].first) << " ";
-      dbgs() << "\n";
-    });
-
-  // Calculate the number of conflicts of each candidate.
-  for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
-    unsigned Reg = i->first->reg;
-    unsigned PhysReg = vrm_->getPhys(Reg);
-    if (!cur->overlapsFrom(*i->first, i->second))
-      continue;
-    for (unsigned j = 0; j < NumCands; ++j) {
-      unsigned Candidate = Candidates[j].first;
-      if (tri_->regsOverlap(PhysReg, Candidate)) {
-        if (NumCands > 1)
-          Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
-        SLIs[j].push_back(i->first);
-      }
-    }
-  }
-
-  for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){
-    unsigned Reg = i->first->reg;
-    unsigned PhysReg = vrm_->getPhys(Reg);
-    if (!cur->overlapsFrom(*i->first, i->second-1))
-      continue;
-    for (unsigned j = 0; j < NumCands; ++j) {
-      unsigned Candidate = Candidates[j].first;
-      if (tri_->regsOverlap(PhysReg, Candidate)) {
-        if (NumCands > 1)
-          Conflicts[j] += getConflictWeight(cur, Reg, li_, mri_, loopInfo);
-        SLIs[j].push_back(i->first);
-      }
-    }
-  }
-
-  // Which is the best candidate?
-  unsigned BestCandidate = 0;
-  float MinConflicts = Conflicts[0];
-  for (unsigned i = 1; i != NumCands; ++i) {
-    if (Conflicts[i] < MinConflicts) {
-      BestCandidate = i;
-      MinConflicts = Conflicts[i];
-    }
-  }
-
-  std::copy(SLIs[BestCandidate].begin(), SLIs[BestCandidate].end(),
-            std::back_inserter(SpillIntervals));
-}
-
-namespace {
-  struct WeightCompare {
-  private:
-    const RALinScan &Allocator;
-
-  public:
-    WeightCompare(const RALinScan &Alloc) : Allocator(Alloc) {}
-
-    typedef std::pair<unsigned, float> RegWeightPair;
-    bool operator()(const RegWeightPair &LHS, const RegWeightPair &RHS) const {
-      return LHS.second < RHS.second && !Allocator.isRecentlyUsed(LHS.first);
-    }
-  };
-}
-
-static bool weightsAreClose(float w1, float w2) {
-  if (!NewHeuristic)
-    return false;
-
-  float diff = w1 - w2;
-  if (diff <= 0.02f)  // Within 0.02f
-    return true;
-  return (diff / w2) <= 0.05f;  // Within 5%.
-}
-
-LiveInterval *RALinScan::hasNextReloadInterval(LiveInterval *cur) {
-  DenseMap<unsigned, unsigned>::iterator I = NextReloadMap.find(cur->reg);
-  if (I == NextReloadMap.end())
-    return 0;
-  return &li_->getInterval(I->second);
-}
-
-void RALinScan::DowngradeRegister(LiveInterval *li, unsigned Reg) {
-  for (const unsigned *AS = tri_->getOverlaps(Reg); *AS; ++AS) {
-    bool isNew = DowngradedRegs.insert(*AS);
-    (void)isNew; // Silence compiler warning.
-    assert(isNew && "Multiple reloads holding the same register?");
-    DowngradeMap.insert(std::make_pair(li->reg, *AS));
-  }
-  ++NumDowngrade;
-}
-
-void RALinScan::UpgradeRegister(unsigned Reg) {
-  if (Reg) {
-    DowngradedRegs.erase(Reg);
-    for (const unsigned *AS = tri_->getAliasSet(Reg); *AS; ++AS)
-      DowngradedRegs.erase(*AS);
-  }
-}
-
-namespace {
-  struct LISorter {
-    bool operator()(LiveInterval* A, LiveInterval* B) {
-      return A->beginIndex() < B->beginIndex();
-    }
-  };
-}
-
-/// assignRegOrStackSlotAtInterval - assign a register if one is available, or
-/// spill.
-void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
-  const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
-  DEBUG(dbgs() << "\tallocating current interval from "
-               << RC->getName() << ": ");
-
-  // This is an implicitly defined live interval, just assign any register.
-  if (cur->empty()) {
-    unsigned physReg = vrm_->getRegAllocPref(cur->reg);
-    if (!physReg)
-      physReg = getFirstNonReservedPhysReg(RC);
-    DEBUG(dbgs() <<  tri_->getName(physReg) << '\n');
-    // Note the register is not really in use.
-    vrm_->assignVirt2Phys(cur->reg, physReg);
-    return;
-  }
-
-  backUpRegUses();
-
-  std::vector<std::pair<unsigned, float> > SpillWeightsToAdd;
-  SlotIndex StartPosition = cur->beginIndex();
-  const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
-
-  // If start of this live interval is defined by a move instruction and its
-  // source is assigned a physical register that is compatible with the target
-  // register class, then we should try to assign it the same register.
-  // This can happen when the move is from a larger register class to a smaller
-  // one, e.g. X86::mov32to32_. These move instructions are not coalescable.
-  if (!vrm_->getRegAllocPref(cur->reg) && cur->hasAtLeastOneValue()) {
-    VNInfo *vni = cur->begin()->valno;
-    if (!vni->isUnused() && vni->def.isValid()) {
-      MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
-      if (CopyMI && CopyMI->isCopy()) {
-        unsigned DstSubReg = CopyMI->getOperand(0).getSubReg();
-        unsigned SrcReg = CopyMI->getOperand(1).getReg();
-        unsigned SrcSubReg = CopyMI->getOperand(1).getSubReg();
-        unsigned Reg = 0;
-        if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
-          Reg = SrcReg;
-        else if (vrm_->isAssignedReg(SrcReg))
-          Reg = vrm_->getPhys(SrcReg);
-        if (Reg) {
-          if (SrcSubReg)
-            Reg = tri_->getSubReg(Reg, SrcSubReg);
-          if (DstSubReg)
-            Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC);
-          if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
-            mri_->setRegAllocationHint(cur->reg, 0, Reg);
-        }
-      }
-    }
-  }
-
-  // For every interval in inactive we overlap with, mark the
-  // register as not free and update spill weights.
-  for (IntervalPtrs::const_iterator i = inactive_.begin(),
-         e = inactive_.end(); i != e; ++i) {
-    unsigned Reg = i->first->reg;
-    assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
-           "Can only allocate virtual registers!");
-    const TargetRegisterClass *RegRC = mri_->getRegClass(Reg);
-    // If this is not in a related reg class to the register we're allocating,
-    // don't check it.
-    if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
-        cur->overlapsFrom(*i->first, i->second-1)) {
-      Reg = vrm_->getPhys(Reg);
-      addRegUse(Reg);
-      SpillWeightsToAdd.push_back(std::make_pair(Reg, i->first->weight));
-    }
-  }
-
-  // Speculatively check to see if we can get a register right now.  If not,
-  // we know we won't be able to by adding more constraints.  If so, we can
-  // check to see if it is valid.  Doing an exhaustive search of the fixed_ list
-  // is very bad (it contains all callee clobbered registers for any functions
-  // with a call), so we want to avoid doing that if possible.
-  unsigned physReg = getFreePhysReg(cur);
-  unsigned BestPhysReg = physReg;
-  if (physReg) {
-    // We got a register.  However, if it's in the fixed_ list, we might
-    // conflict with it.  Check to see if we conflict with it or any of its
-    // aliases.
-    SmallSet<unsigned, 8> RegAliases;
-    for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS)
-      RegAliases.insert(*AS);
-
-    bool ConflictsWithFixed = false;
-    for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
-      IntervalPtr &IP = fixed_[i];
-      if (physReg == IP.first->reg || RegAliases.count(IP.first->reg)) {
-        // Okay, this reg is on the fixed list.  Check to see if we actually
-        // conflict.
-        LiveInterval *I = IP.first;
-        if (I->endIndex() > StartPosition) {
-          LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
-          IP.second = II;
-          if (II != I->begin() && II->start > StartPosition)
-            --II;
-          if (cur->overlapsFrom(*I, II)) {
-            ConflictsWithFixed = true;
-            break;
-          }
-        }
-      }
-    }
-
-    // Okay, the register picked by our speculative getFreePhysReg call turned
-    // out to be in use.  Actually add all of the conflicting fixed registers to
-    // regUse_ so we can do an accurate query.
-    if (ConflictsWithFixed) {
-      // For every interval in fixed we overlap with, mark the register as not
-      // free and update spill weights.
-      for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
-        IntervalPtr &IP = fixed_[i];
-        LiveInterval *I = IP.first;
-
-        const TargetRegisterClass *RegRC = OneClassForEachPhysReg[I->reg];
-        if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
-            I->endIndex() > StartPosition) {
-          LiveInterval::iterator II = I->advanceTo(IP.second, StartPosition);
-          IP.second = II;
-          if (II != I->begin() && II->start > StartPosition)
-            --II;
-          if (cur->overlapsFrom(*I, II)) {
-            unsigned reg = I->reg;
-            addRegUse(reg);
-            SpillWeightsToAdd.push_back(std::make_pair(reg, I->weight));
-          }
-        }
-      }
-
-      // Using the newly updated regUse_ object, which includes conflicts in the
-      // future, see if there are any registers available.
-      physReg = getFreePhysReg(cur);
-    }
-  }
-
-  // Restore the physical register tracker, removing information about the
-  // future.
-  restoreRegUses();
-
-  // If we find a free register, we are done: assign this virtual to
-  // the free physical register and add this interval to the active
-  // list.
-  if (physReg) {
-    DEBUG(dbgs() <<  tri_->getName(physReg) << '\n');
-    assert(RC->contains(physReg) && "Invalid candidate");
-    vrm_->assignVirt2Phys(cur->reg, physReg);
-    addRegUse(physReg);
-    active_.push_back(std::make_pair(cur, cur->begin()));
-    handled_.push_back(cur);
-
-    // Remember physReg for avoiding a write-after-write hazard in the next
-    // instruction.
-    if (AvoidWAWHazard &&
-        tri_->avoidWriteAfterWrite(mri_->getRegClass(cur->reg)))
-      avoidWAW_ = physReg;
-
-    // "Upgrade" the physical register since it has been allocated.
-    UpgradeRegister(physReg);
-    if (LiveInterval *NextReloadLI = hasNextReloadInterval(cur)) {
-      // "Downgrade" physReg to try to keep physReg from being allocated until
-      // the next reload from the same SS is allocated.
-      mri_->setRegAllocationHint(NextReloadLI->reg, 0, physReg);
-      DowngradeRegister(cur, physReg);
-    }
-    return;
-  }
-  DEBUG(dbgs() << "no free registers\n");
-
-  // Compile the spill weights into an array that is better for scanning.
-  std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0f);
-  for (std::vector<std::pair<unsigned, float> >::iterator
-       I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I)
-    updateSpillWeights(SpillWeights, I->first, I->second, RC);
-
-  // for each interval in active, update spill weights.
-  for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
-       i != e; ++i) {
-    unsigned reg = i->first->reg;
-    assert(TargetRegisterInfo::isVirtualRegister(reg) &&
-           "Can only allocate virtual registers!");
-    reg = vrm_->getPhys(reg);
-    updateSpillWeights(SpillWeights, reg, i->first->weight, RC);
-  }
-
-  DEBUG(dbgs() << "\tassigning stack slot at interval "<< *cur << ":\n");
-
-  // Find a register to spill.
-  float minWeight = HUGE_VALF;
-  unsigned minReg = 0;
-
-  bool Found = false;
-  std::vector<std::pair<unsigned,float> > RegsWeights;
-  ArrayRef<unsigned> Order = RegClassInfo.getOrder(RC);
-  if (!minReg || SpillWeights[minReg] == HUGE_VALF)
-    for (unsigned i = 0; i != Order.size(); ++i) {
-      unsigned reg = Order[i];
-      float regWeight = SpillWeights[reg];
-      // Skip recently allocated registers and reserved registers.
-      if (minWeight > regWeight && !isRecentlyUsed(reg))
-        Found = true;
-      RegsWeights.push_back(std::make_pair(reg, regWeight));
-    }
-
-  // If we didn't find a register that is spillable, try aliases?
-  if (!Found) {
-    for (unsigned i = 0; i != Order.size(); ++i) {
-      unsigned reg = Order[i];
-      // No need to worry about if the alias register size < regsize of RC.
-      // We are going to spill all registers that alias it anyway.
-      for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as)
-        RegsWeights.push_back(std::make_pair(*as, SpillWeights[*as]));
-    }
-  }
-
-  // Sort all potential spill candidates by weight.
-  std::sort(RegsWeights.begin(), RegsWeights.end(), WeightCompare(*this));
-  minReg = RegsWeights[0].first;
-  minWeight = RegsWeights[0].second;
-  if (minWeight == HUGE_VALF) {
-    // All registers must have inf weight. Just grab one!
-    minReg = BestPhysReg ? BestPhysReg : getFirstNonReservedPhysReg(RC);
-    if (cur->weight == HUGE_VALF ||
-        li_->getApproximateInstructionCount(*cur) == 0) {
-      // Spill a physical register around defs and uses.
-      if (li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_)) {
-        // spillPhysRegAroundRegDefsUses may have invalidated iterator stored
-        // in fixed_. Reset them.
-        for (unsigned i = 0, e = fixed_.size(); i != e; ++i) {
-          IntervalPtr &IP = fixed_[i];
-          LiveInterval *I = IP.first;
-          if (I->reg == minReg || tri_->isSubRegister(minReg, I->reg))
-            IP.second = I->advanceTo(I->begin(), StartPosition);
-        }
-
-        DowngradedRegs.clear();
-        assignRegOrStackSlotAtInterval(cur);
-      } else {
-        assert(false && "Ran out of registers during register allocation!");
-        report_fatal_error("Ran out of registers during register allocation!");
-      }
-      return;
-    }
-  }
-
-  // Find up to 3 registers to consider as spill candidates.
-  unsigned LastCandidate = RegsWeights.size() >= 3 ? 3 : 1;
-  while (LastCandidate > 1) {
-    if (weightsAreClose(RegsWeights[LastCandidate-1].second, minWeight))
-      break;
-    --LastCandidate;
-  }
-
-  DEBUG({
-      dbgs() << "\t\tregister(s) with min weight(s): ";
-
-      for (unsigned i = 0; i != LastCandidate; ++i)
-        dbgs() << tri_->getName(RegsWeights[i].first)
-               << " (" << RegsWeights[i].second << ")\n";
-    });
-
-  // If the current has the minimum weight, we need to spill it and
-  // add any added intervals back to unhandled, and restart
-  // linearscan.
-  if (cur->weight != HUGE_VALF && cur->weight <= minWeight) {
-    DEBUG(dbgs() << "\t\t\tspilling(c): " << *cur << '\n');
-    SmallVector<LiveInterval*, 8> added;
-    LiveRangeEdit LRE(*cur, added);
-    spiller_->spill(LRE);
-
-    std::sort(added.begin(), added.end(), LISorter());
-    if (added.empty())
-      return;  // Early exit if all spills were folded.
-
-    // Merge added with unhandled.  Note that we have already sorted
-    // intervals returned by addIntervalsForSpills by their starting
-    // point.
-    // This also update the NextReloadMap. That is, it adds mapping from a
-    // register defined by a reload from SS to the next reload from SS in the
-    // same basic block.
-    MachineBasicBlock *LastReloadMBB = 0;
-    LiveInterval *LastReload = 0;
-    int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
-    for (unsigned i = 0, e = added.size(); i != e; ++i) {
-      LiveInterval *ReloadLi = added[i];
-      if (ReloadLi->weight == HUGE_VALF &&
-          li_->getApproximateInstructionCount(*ReloadLi) == 0) {
-        SlotIndex ReloadIdx = ReloadLi->beginIndex();
-        MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
-        int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
-        if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
-          // Last reload of same SS is in the same MBB. We want to try to
-          // allocate both reloads the same register and make sure the reg
-          // isn't clobbered in between if at all possible.
-          assert(LastReload->beginIndex() < ReloadIdx);
-          NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
-        }
-        LastReloadMBB = ReloadMBB;
-        LastReload = ReloadLi;
-        LastReloadSS = ReloadSS;
-      }
-      unhandled_.push(ReloadLi);
-    }
-    return;
-  }
-
-  ++NumBacktracks;
-
-  // Push the current interval back to unhandled since we are going
-  // to re-run at least this iteration. Since we didn't modify it it
-  // should go back right in the front of the list
-  unhandled_.push(cur);
-
-  assert(TargetRegisterInfo::isPhysicalRegister(minReg) &&
-         "did not choose a register to spill?");
-
-  // We spill all intervals aliasing the register with
-  // minimum weight, rollback to the interval with the earliest
-  // start point and let the linear scan algorithm run again
-  SmallVector<LiveInterval*, 8> spillIs;
-
-  // Determine which intervals have to be spilled.
-  findIntervalsToSpill(cur, RegsWeights, LastCandidate, spillIs);
-
-  // Set of spilled vregs (used later to rollback properly)
-  SmallSet<unsigned, 8> spilled;
-
-  // The earliest start of a Spilled interval indicates up to where
-  // in handled we need to roll back
-  assert(!spillIs.empty() && "No spill intervals?");
-  SlotIndex earliestStart = spillIs[0]->beginIndex();
-
-  // Spill live intervals of virtual regs mapped to the physical register we
-  // want to clear (and its aliases).  We only spill those that overlap with the
-  // current interval as the rest do not affect its allocation. we also keep
-  // track of the earliest start of all spilled live intervals since this will
-  // mark our rollback point.
-  SmallVector<LiveInterval*, 8> added;
-  while (!spillIs.empty()) {
-    LiveInterval *sli = spillIs.back();
-    spillIs.pop_back();
-    DEBUG(dbgs() << "\t\t\tspilling(a): " << *sli << '\n');
-    if (sli->beginIndex() < earliestStart)
-      earliestStart = sli->beginIndex();
-    LiveRangeEdit LRE(*sli, added, 0, &spillIs);
-    spiller_->spill(LRE);
-    spilled.insert(sli->reg);
-  }
-
-  // Include any added intervals in earliestStart.
-  for (unsigned i = 0, e = added.size(); i != e; ++i) {
-    SlotIndex SI = added[i]->beginIndex();
-    if (SI < earliestStart)
-      earliestStart = SI;
-  }
-
-  DEBUG(dbgs() << "\t\trolling back to: " << earliestStart << '\n');
-
-  // Scan handled in reverse order up to the earliest start of a
-  // spilled live interval and undo each one, restoring the state of
-  // unhandled.
-  while (!handled_.empty()) {
-    LiveInterval* i = handled_.back();
-    // If this interval starts before t we are done.
-    if (!i->empty() && i->beginIndex() < earliestStart)
-      break;
-    DEBUG(dbgs() << "\t\t\tundo changes for: " << *i << '\n');
-    handled_.pop_back();
-
-    // When undoing a live interval allocation we must know if it is active or
-    // inactive to properly update regUse_ and the VirtRegMap.
-    IntervalPtrs::iterator it;
-    if ((it = FindIntervalInVector(active_, i)) != active_.end()) {
-      active_.erase(it);
-      assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
-      if (!spilled.count(i->reg))
-        unhandled_.push(i);
-      delRegUse(vrm_->getPhys(i->reg));
-      vrm_->clearVirt(i->reg);
-    } else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) {
-      inactive_.erase(it);
-      assert(!TargetRegisterInfo::isPhysicalRegister(i->reg));
-      if (!spilled.count(i->reg))
-        unhandled_.push(i);
-      vrm_->clearVirt(i->reg);
-    } else {
-      assert(TargetRegisterInfo::isVirtualRegister(i->reg) &&
-             "Can only allocate virtual registers!");
-      vrm_->clearVirt(i->reg);
-      unhandled_.push(i);
-    }
-
-    DenseMap<unsigned, unsigned>::iterator ii = DowngradeMap.find(i->reg);
-    if (ii == DowngradeMap.end())
-      // It interval has a preference, it must be defined by a copy. Clear the
-      // preference now since the source interval allocation may have been
-      // undone as well.
-      mri_->setRegAllocationHint(i->reg, 0, 0);
-    else {
-      UpgradeRegister(ii->second);
-    }
-  }
-
-  // Rewind the iterators in the active, inactive, and fixed lists back to the
-  // point we reverted to.
-  RevertVectorIteratorsTo(active_, earliestStart);
-  RevertVectorIteratorsTo(inactive_, earliestStart);
-  RevertVectorIteratorsTo(fixed_, earliestStart);
-
-  // Scan the rest and undo each interval that expired after t and
-  // insert it in active (the next iteration of the algorithm will
-  // put it in inactive if required)
-  for (unsigned i = 0, e = handled_.size(); i != e; ++i) {
-    LiveInterval *HI = handled_[i];
-    if (!HI->expiredAt(earliestStart) &&
-        HI->expiredAt(cur->beginIndex())) {
-      DEBUG(dbgs() << "\t\t\tundo changes for: " << *HI << '\n');
-      active_.push_back(std::make_pair(HI, HI->begin()));
-      assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg));
-      addRegUse(vrm_->getPhys(HI->reg));
-    }
-  }
-
-  // Merge added with unhandled.
-  // This also update the NextReloadMap. That is, it adds mapping from a
-  // register defined by a reload from SS to the next reload from SS in the
-  // same basic block.
-  MachineBasicBlock *LastReloadMBB = 0;
-  LiveInterval *LastReload = 0;
-  int LastReloadSS = VirtRegMap::NO_STACK_SLOT;
-  std::sort(added.begin(), added.end(), LISorter());
-  for (unsigned i = 0, e = added.size(); i != e; ++i) {
-    LiveInterval *ReloadLi = added[i];
-    if (ReloadLi->weight == HUGE_VALF &&
-        li_->getApproximateInstructionCount(*ReloadLi) == 0) {
-      SlotIndex ReloadIdx = ReloadLi->beginIndex();
-      MachineBasicBlock *ReloadMBB = li_->getMBBFromIndex(ReloadIdx);
-      int ReloadSS = vrm_->getStackSlot(ReloadLi->reg);
-      if (LastReloadMBB == ReloadMBB && LastReloadSS == ReloadSS) {
-        // Last reload of same SS is in the same MBB. We want to try to
-        // allocate both reloads the same register and make sure the reg
-        // isn't clobbered in between if at all possible.
-        assert(LastReload->beginIndex() < ReloadIdx);
-        NextReloadMap.insert(std::make_pair(LastReload->reg, ReloadLi->reg));
-      }
-      LastReloadMBB = ReloadMBB;
-      LastReload = ReloadLi;
-      LastReloadSS = ReloadSS;
-    }
-    unhandled_.push(ReloadLi);
-  }
-}
-
-unsigned RALinScan::getFreePhysReg(LiveInterval* cur,
-                                   const TargetRegisterClass *RC,
-                                   unsigned MaxInactiveCount,
-                                   SmallVector<unsigned, 256> &inactiveCounts,
-                                   bool SkipDGRegs) {
-  unsigned FreeReg = 0;
-  unsigned FreeRegInactiveCount = 0;
-
-  std::pair<unsigned, unsigned> Hint = mri_->getRegAllocationHint(cur->reg);
-  // Resolve second part of the hint (if possible) given the current allocation.
-  unsigned physReg = Hint.second;
-  if (TargetRegisterInfo::isVirtualRegister(physReg) && vrm_->hasPhys(physReg))
-    physReg = vrm_->getPhys(physReg);
-
-  ArrayRef<unsigned> Order;
-  if (Hint.first)
-    Order = tri_->getRawAllocationOrder(RC, Hint.first, physReg, *mf_);
-  else
-    Order = RegClassInfo.getOrder(RC);
-
-  assert(!Order.empty() && "No allocatable register in this register class!");
-
-  // Scan for the first available register.
-  for (unsigned i = 0; i != Order.size(); ++i) {
-    unsigned Reg = Order[i];
-    // Ignore "downgraded" registers.
-    if (SkipDGRegs && DowngradedRegs.count(Reg))
-      continue;
-    // Skip reserved registers.
-    if (reservedRegs_.test(Reg))
-      continue;
-    // Skip recently allocated registers.
-    if (isRegAvail(Reg) && (!SkipDGRegs || !isRecentlyUsed(Reg))) {
-      FreeReg = Reg;
-      if (FreeReg < inactiveCounts.size())
-        FreeRegInactiveCount = inactiveCounts[FreeReg];
-      else
-        FreeRegInactiveCount = 0;
-      break;
-    }
-  }
-
-  // If there are no free regs, or if this reg has the max inactive count,
-  // return this register.
-  if (FreeReg == 0 || FreeRegInactiveCount == MaxInactiveCount) {
-    // Remember what register we picked so we can skip it next time.
-    if (FreeReg != 0) recordRecentlyUsed(FreeReg);
-    return FreeReg;
-  }
-
-  // Continue scanning the registers, looking for the one with the highest
-  // inactive count.  Alkis found that this reduced register pressure very
-  // slightly on X86 (in rev 1.94 of this file), though this should probably be
-  // reevaluated now.
-  for (unsigned i = 0; i != Order.size(); ++i) {
-    unsigned Reg = Order[i];
-    // Ignore "downgraded" registers.
-    if (SkipDGRegs && DowngradedRegs.count(Reg))
-      continue;
-    // Skip reserved registers.
-    if (reservedRegs_.test(Reg))
-      continue;
-    if (isRegAvail(Reg) && Reg < inactiveCounts.size() &&
-        FreeRegInactiveCount < inactiveCounts[Reg] &&
-        (!SkipDGRegs || !isRecentlyUsed(Reg))) {
-      FreeReg = Reg;
-      FreeRegInactiveCount = inactiveCounts[Reg];
-      if (FreeRegInactiveCount == MaxInactiveCount)
-        break;    // We found the one with the max inactive count.
-    }
-  }
-
-  // Remember what register we picked so we can skip it next time.
-  recordRecentlyUsed(FreeReg);
-
-  return FreeReg;
-}
-
-/// getFreePhysReg - return a free physical register for this virtual register
-/// interval if we have one, otherwise return 0.
-unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
-  SmallVector<unsigned, 256> inactiveCounts;
-  unsigned MaxInactiveCount = 0;
-
-  const TargetRegisterClass *RC = mri_->getRegClass(cur->reg);
-  const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
-
-  for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
-       i != e; ++i) {
-    unsigned reg = i->first->reg;
-    assert(TargetRegisterInfo::isVirtualRegister(reg) &&
-           "Can only allocate virtual registers!");
-
-    // If this is not in a related reg class to the register we're allocating,
-    // don't check it.
-    const TargetRegisterClass *RegRC = mri_->getRegClass(reg);
-    if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
-      reg = vrm_->getPhys(reg);
-      if (inactiveCounts.size() <= reg)
-        inactiveCounts.resize(reg+1);
-      ++inactiveCounts[reg];
-      MaxInactiveCount = std::max(MaxInactiveCount, inactiveCounts[reg]);
-    }
-  }
-
-  // If copy coalescer has assigned a "preferred" register, check if it's
-  // available first.
-  unsigned Preference = vrm_->getRegAllocPref(cur->reg);
-  if (Preference) {
-    DEBUG(dbgs() << "(preferred: " << tri_->getName(Preference) << ") ");
-    if (isRegAvail(Preference) &&
-        RC->contains(Preference))
-      return Preference;
-  }
-
-  unsigned FreeReg = getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts,
-                                    true);
-  if (FreeReg)
-    return FreeReg;
-  return getFreePhysReg(cur, RC, MaxInactiveCount, inactiveCounts, false);
-}
-
-FunctionPass* llvm::createLinearScanRegisterAllocator() {
-  return new RALinScan();
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/CodeGen/ScheduleDAGEmit.cpp
--- a/head/contrib/llvm/lib/CodeGen/ScheduleDAGEmit.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,68 +0,0 @@
-//===---- ScheduleDAGEmit.cpp - Emit routines for the ScheduleDAG class ---===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This implements the Emit routines for the ScheduleDAG class, which creates
-// MachineInstrs according to the computed schedule.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "pre-RA-sched"
-#include "llvm/CodeGen/ScheduleDAG.h"
-#include "llvm/CodeGen/MachineConstantPool.h"
-#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/Target/TargetData.h"
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/ADT/Statistic.h"
-#include "llvm/Support/CommandLine.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/MathExtras.h"
-using namespace llvm;
-
-void ScheduleDAG::EmitNoop() {
-  TII->insertNoop(*BB, InsertPos);
-}
-
-void ScheduleDAG::EmitPhysRegCopy(SUnit *SU,
-                                  DenseMap<SUnit*, unsigned> &VRBaseMap) {
-  for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
-       I != E; ++I) {
-    if (I->isCtrl()) continue;  // ignore chain preds
-    if (I->getSUnit()->CopyDstRC) {
-      // Copy to physical register.
-      DenseMap<SUnit*, unsigned>::iterator VRI = VRBaseMap.find(I->getSUnit());
-      assert(VRI != VRBaseMap.end() && "Node emitted out of order - late");
-      // Find the destination physical register.
-      unsigned Reg = 0;
-      for (SUnit::const_succ_iterator II = SU->Succs.begin(),
-             EE = SU->Succs.end(); II != EE; ++II) {
-        if (II->isCtrl()) continue;  // ignore chain preds
-        if (II->getReg()) {
-          Reg = II->getReg();
-          break;
-        }
-      }
-      BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), Reg)
-        .addReg(VRI->second);
-    } else {
-      // Copy from physical register.
-      assert(I->getReg() && "Unknown physical register!");
-      unsigned VRBase = MRI.createVirtualRegister(SU->CopyDstRC);
-      bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second;
-      (void)isNew; // Silence compiler warning.
-      assert(isNew && "Node emitted out of order - early");
-      BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), VRBase)
-        .addReg(I->getReg());
-    }
-    break;
-  }
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/CodeGen/ScheduleDAGInstrs.h
--- a/head/contrib/llvm/lib/CodeGen/ScheduleDAGInstrs.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,212 +0,0 @@
-//==- ScheduleDAGInstrs.h - MachineInstr Scheduling --------------*- C++ -*-==//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements the ScheduleDAGInstrs class, which implements
-// scheduling for a MachineInstr-based dependency graph.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef SCHEDULEDAGINSTRS_H
-#define SCHEDULEDAGINSTRS_H
-
-#include "llvm/CodeGen/MachineDominators.h"
-#include "llvm/CodeGen/MachineLoopInfo.h"
-#include "llvm/CodeGen/ScheduleDAG.h"
-#include "llvm/Support/Compiler.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/ADT/SmallSet.h"
-#include <map>
-
-namespace llvm {
-  class MachineLoopInfo;
-  class MachineDominatorTree;
-
-  /// LoopDependencies - This class analyzes loop-oriented register
-  /// dependencies, which are used to guide scheduling decisions.
-  /// For example, loop induction variable increments should be
-  /// scheduled as soon as possible after the variable's last use.
-  ///
-  class LLVM_LIBRARY_VISIBILITY LoopDependencies {
-    const MachineLoopInfo &MLI;
-    const MachineDominatorTree &MDT;
-
-  public:
-    typedef std::map<unsigned, std::pair<const MachineOperand *, unsigned> >
-      LoopDeps;
-    LoopDeps Deps;
-
-    LoopDependencies(const MachineLoopInfo &mli,
-                     const MachineDominatorTree &mdt) :
-      MLI(mli), MDT(mdt) {}
-
-    /// VisitLoop - Clear out any previous state and analyze the given loop.
-    ///
-    void VisitLoop(const MachineLoop *Loop) {
-      assert(Deps.empty() && "stale loop dependencies");
-
-      MachineBasicBlock *Header = Loop->getHeader();
-      SmallSet<unsigned, 8> LoopLiveIns;
-      for (MachineBasicBlock::livein_iterator LI = Header->livein_begin(),
-           LE = Header->livein_end(); LI != LE; ++LI)
-        LoopLiveIns.insert(*LI);
-
-      const MachineDomTreeNode *Node = MDT.getNode(Header);
-      const MachineBasicBlock *MBB = Node->getBlock();
-      assert(Loop->contains(MBB) &&
-             "Loop does not contain header!");
-      VisitRegion(Node, MBB, Loop, LoopLiveIns);
-    }
-
-  private:
-    void VisitRegion(const MachineDomTreeNode *Node,
-                     const MachineBasicBlock *MBB,
-                     const MachineLoop *Loop,
-                     const SmallSet<unsigned, 8> &LoopLiveIns) {
-      unsigned Count = 0;
-      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
-           I != E; ++I) {
-        const MachineInstr *MI = I;
-        if (MI->isDebugValue())
-          continue;
-        for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
-          const MachineOperand &MO = MI->getOperand(i);
-          if (!MO.isReg() || !MO.isUse())
-            continue;
-          unsigned MOReg = MO.getReg();
-          if (LoopLiveIns.count(MOReg))
-            Deps.insert(std::make_pair(MOReg, std::make_pair(&MO, Count)));
-        }
-        ++Count; // Not every iteration due to dbg_value above.
-      }
-
-      const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
-      for (std::vector<MachineDomTreeNode*>::const_iterator I =
-           Children.begin(), E = Children.end(); I != E; ++I) {
-        const MachineDomTreeNode *ChildNode = *I;
-        MachineBasicBlock *ChildBlock = ChildNode->getBlock();
-        if (Loop->contains(ChildBlock))
-          VisitRegion(ChildNode, ChildBlock, Loop, LoopLiveIns);
-      }
-    }
-  };
-
-  /// ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of
-  /// MachineInstrs.
-  class LLVM_LIBRARY_VISIBILITY ScheduleDAGInstrs : public ScheduleDAG {
-    const MachineLoopInfo &MLI;
-    const MachineDominatorTree &MDT;
-    const MachineFrameInfo *MFI;
-    const InstrItineraryData *InstrItins;
-
-    /// Defs, Uses - Remember where defs and uses of each physical register
-    /// are as we iterate upward through the instructions. This is allocated
-    /// here instead of inside BuildSchedGraph to avoid the need for it to be
-    /// initialized and destructed for each block.
-    std::vector<std::vector<SUnit *> > Defs;
-    std::vector<std::vector<SUnit *> > Uses;
-
-    /// PendingLoads - Remember where unknown loads are after the most recent
-    /// unknown store, as we iterate. As with Defs and Uses, this is here
-    /// to minimize construction/destruction.
-    std::vector<SUnit *> PendingLoads;
-
-    /// LoopRegs - Track which registers are used for loop-carried dependencies.
-    ///
-    LoopDependencies LoopRegs;
-
-    /// LoopLiveInRegs - Track which regs are live into a loop, to help guide
-    /// back-edge-aware scheduling.
-    ///
-    SmallSet<unsigned, 8> LoopLiveInRegs;
-
-  protected:
-
-    /// DbgValues - Remember instruction that preceeds DBG_VALUE.
-    typedef std::vector<std::pair<MachineInstr *, MachineInstr *> >
-      DbgValueVector;
-    DbgValueVector DbgValues;
-    MachineInstr *FirstDbgValue;
-
-  public:
-    MachineBasicBlock::iterator Begin;    // The beginning of the range to
-                                          // be scheduled. The range extends
-                                          // to InsertPos.
-    unsigned InsertPosIndex;              // The index in BB of InsertPos.
-
-    explicit ScheduleDAGInstrs(MachineFunction &mf,
-                               const MachineLoopInfo &mli,
-                               const MachineDominatorTree &mdt);
-
-    virtual ~ScheduleDAGInstrs() {}
-
-    /// NewSUnit - Creates a new SUnit and return a ptr to it.
-    ///
-    SUnit *NewSUnit(MachineInstr *MI) {
-#ifndef NDEBUG
-      const SUnit *Addr = SUnits.empty() ? 0 : &SUnits[0];
-#endif
-      SUnits.push_back(SUnit(MI, (unsigned)SUnits.size()));
-      assert((Addr == 0 || Addr == &SUnits[0]) &&
-             "SUnits std::vector reallocated on the fly!");
-      SUnits.back().OrigNode = &SUnits.back();
-      return &SUnits.back();
-    }
-
-    /// Run - perform scheduling.
-    ///
-    void Run(MachineBasicBlock *bb,
-             MachineBasicBlock::iterator begin,
-             MachineBasicBlock::iterator end,
-             unsigned endindex);
-
-    /// BuildSchedGraph - Build SUnits from the MachineBasicBlock that we are
-    /// input.
-    virtual void BuildSchedGraph(AliasAnalysis *AA);
-
-    /// AddSchedBarrierDeps - Add dependencies from instructions in the current
-    /// list of instructions being scheduled to scheduling barrier. We want to
-    /// make sure instructions which define registers that are either used by
-    /// the terminator or are live-out are properly scheduled. This is
-    /// especially important when the definition latency of the return value(s)
-    /// are too high to be hidden by the branch or when the liveout registers
-    /// used by instructions in the fallthrough block.
-    void AddSchedBarrierDeps();
-
-    /// ComputeLatency - Compute node latency.
-    ///
-    virtual void ComputeLatency(SUnit *SU);
-
-    /// ComputeOperandLatency - Override dependence edge latency using
-    /// operand use/def information
-    ///
-    virtual void ComputeOperandLatency(SUnit *Def, SUnit *Use,
-                                       SDep& dep) const;
-
-    virtual MachineBasicBlock *EmitSchedule();
-
-    /// StartBlock - Prepare to perform scheduling in the given block.
-    ///
-    virtual void StartBlock(MachineBasicBlock *BB);
-
-    /// Schedule - Order nodes according to selected style, filling
-    /// in the Sequence member.
-    ///
-    virtual void Schedule() = 0;
-
-    /// FinishBlock - Clean up after scheduling in the given block.
-    ///
-    virtual void FinishBlock();
-
-    virtual void dumpNode(const SUnit *SU) const;
-
-    virtual std::string getGraphNodeLabel(const SUnit *SU) const;
-  };
-}
-
-#endif
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
--- a/head/contrib/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,265 +0,0 @@
-//===---- ScheduleDAGList.cpp - Implement a list scheduler for isel DAG ---===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This implements a top-down list scheduler, using standard algorithms.
-// The basic approach uses a priority queue of available nodes to schedule.
-// One at a time, nodes are taken from the priority queue (thus in priority
-// order), checked for legality to schedule, and emitted if legal.
-//
-// Nodes may not be legal to schedule either due to structural hazards (e.g.
-// pipeline or resource constraints) or because an input to the instruction has
-// not completed execution.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "pre-RA-sched"
-#include "ScheduleDAGSDNodes.h"
-#include "llvm/CodeGen/LatencyPriorityQueue.h"
-#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
-#include "llvm/CodeGen/SchedulerRegistry.h"
-#include "llvm/CodeGen/SelectionDAGISel.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetData.h"
-#include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/raw_ostream.h"
-#include "llvm/ADT/Statistic.h"
-#include <climits>
-using namespace llvm;
-
-STATISTIC(NumNoops , "Number of noops inserted");
-STATISTIC(NumStalls, "Number of pipeline stalls");
-
-static RegisterScheduler
-  tdListDAGScheduler("list-td", "Top-down list scheduler",
-                     createTDListDAGScheduler);
-
-namespace {
-//===----------------------------------------------------------------------===//
-/// ScheduleDAGList - The actual list scheduler implementation.  This supports
-/// top-down scheduling.
-///
-class ScheduleDAGList : public ScheduleDAGSDNodes {
-private:
-  /// AvailableQueue - The priority queue to use for the available SUnits.
-  ///
-  SchedulingPriorityQueue *AvailableQueue;
-
-  /// PendingQueue - This contains all of the instructions whose operands have
-  /// been issued, but their results are not ready yet (due to the latency of
-  /// the operation).  Once the operands become available, the instruction is
-  /// added to the AvailableQueue.
-  std::vector<SUnit*> PendingQueue;
-
-  /// HazardRec - The hazard recognizer to use.
-  ScheduleHazardRecognizer *HazardRec;
-
-public:
-  ScheduleDAGList(MachineFunction &mf,
-                  SchedulingPriorityQueue *availqueue)
-    : ScheduleDAGSDNodes(mf), AvailableQueue(availqueue) {
-
-    const TargetMachine &tm = mf.getTarget();
-    HazardRec = tm.getInstrInfo()->CreateTargetHazardRecognizer(&tm, this);
-  }
-
-  ~ScheduleDAGList() {
-    delete HazardRec;
-    delete AvailableQueue;
-  }
-
-  void Schedule();
-
-private:
-  void ReleaseSucc(SUnit *SU, const SDep &D);
-  void ReleaseSuccessors(SUnit *SU);
-  void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
-  void ListScheduleTopDown();
-};
-}  // end anonymous namespace
-
-/// Schedule - Schedule the DAG using list scheduling.
-void ScheduleDAGList::Schedule() {
-  DEBUG(dbgs() << "********** List Scheduling **********\n");
-
-  // Build the scheduling graph.
-  BuildSchedGraph(NULL);
-
-  AvailableQueue->initNodes(SUnits);
-
-  ListScheduleTopDown();
-
-  AvailableQueue->releaseState();
-}
-
-//===----------------------------------------------------------------------===//
-//  Top-Down Scheduling
-//===----------------------------------------------------------------------===//
-
-/// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
-/// the PendingQueue if the count reaches zero. Also update its cycle bound.
-void ScheduleDAGList::ReleaseSucc(SUnit *SU, const SDep &D) {
-  SUnit *SuccSU = D.getSUnit();
-
-#ifndef NDEBUG
-  if (SuccSU->NumPredsLeft == 0) {
-    dbgs() << "*** Scheduling failed! ***\n";
-    SuccSU->dump(this);
-    dbgs() << " has been released too many times!\n";
-    llvm_unreachable(0);
-  }
-#endif
-  --SuccSU->NumPredsLeft;
-
-  SuccSU->setDepthToAtLeast(SU->getDepth() + D.getLatency());
-
-  // If all the node's predecessors are scheduled, this node is ready
-  // to be scheduled. Ignore the special ExitSU node.
-  if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
-    PendingQueue.push_back(SuccSU);
-}
-
-void ScheduleDAGList::ReleaseSuccessors(SUnit *SU) {
-  // Top down: release successors.
-  for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
-       I != E; ++I) {
-    assert(!I->isAssignedRegDep() &&
-           "The list-td scheduler doesn't yet support physreg dependencies!");
-
-    ReleaseSucc(SU, *I);
-  }
-}
-
-/// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
-/// count of its successors. If a successor pending count is zero, add it to
-/// the Available queue.
-void ScheduleDAGList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
-  DEBUG(dbgs() << "*** Scheduling [" << CurCycle << "]: ");
-  DEBUG(SU->dump(this));
-
-  Sequence.push_back(SU);
-  assert(CurCycle >= SU->getDepth() && "Node scheduled above its depth!");
-  SU->setDepthToAtLeast(CurCycle);
-
-  ReleaseSuccessors(SU);
-  SU->isScheduled = true;
-  AvailableQueue->ScheduledNode(SU);
-}
-
-/// ListScheduleTopDown - The main loop of list scheduling for top-down
-/// schedulers.
-void ScheduleDAGList::ListScheduleTopDown() {
-  unsigned CurCycle = 0;
-
-  // Release any successors of the special Entry node.
-  ReleaseSuccessors(&EntrySU);
-
-  // All leaves to Available queue.
-  for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
-    // It is available if it has no predecessors.
-    if (SUnits[i].Preds.empty()) {
-      AvailableQueue->push(&SUnits[i]);
-      SUnits[i].isAvailable = true;
-    }
-  }
-
-  // While Available queue is not empty, grab the node with the highest
-  // priority. If it is not ready put it back.  Schedule the node.
-  std::vector<SUnit*> NotReady;
-  Sequence.reserve(SUnits.size());
-  while (!AvailableQueue->empty() || !PendingQueue.empty()) {
-    // Check to see if any of the pending instructions are ready to issue.  If
-    // so, add them to the available queue.
-    for (unsigned i = 0, e = PendingQueue.size(); i != e; ++i) {
-      if (PendingQueue[i]->getDepth() == CurCycle) {
-        AvailableQueue->push(PendingQueue[i]);
-        PendingQueue[i]->isAvailable = true;
-        PendingQueue[i] = PendingQueue.back();
-        PendingQueue.pop_back();
-        --i; --e;
-      } else {
-        assert(PendingQueue[i]->getDepth() > CurCycle && "Negative latency?");
-      }
-    }
-
-    // If there are no instructions available, don't try to issue anything, and
-    // don't advance the hazard recognizer.
-    if (AvailableQueue->empty()) {
-      ++CurCycle;
-      continue;
-    }
-
-    SUnit *FoundSUnit = 0;
-
-    bool HasNoopHazards = false;
-    while (!AvailableQueue->empty()) {
-      SUnit *CurSUnit = AvailableQueue->pop();
-
-      ScheduleHazardRecognizer::HazardType HT =
-        HazardRec->getHazardType(CurSUnit, 0/*no stalls*/);
-      if (HT == ScheduleHazardRecognizer::NoHazard) {
-        FoundSUnit = CurSUnit;
-        break;
-      }
-
-      // Remember if this is a noop hazard.
-      HasNoopHazards |= HT == ScheduleHazardRecognizer::NoopHazard;
-
-      NotReady.push_back(CurSUnit);
-    }
-
-    // Add the nodes that aren't ready back onto the available list.
-    if (!NotReady.empty()) {
-      AvailableQueue->push_all(NotReady);
-      NotReady.clear();
-    }
-
-    // If we found a node to schedule, do it now.
-    if (FoundSUnit) {
-      ScheduleNodeTopDown(FoundSUnit, CurCycle);
-      HazardRec->EmitInstruction(FoundSUnit);
-
-      // If this is a pseudo-op node, we don't want to increment the current
-      // cycle.
-      if (FoundSUnit->Latency)  // Don't increment CurCycle for pseudo-ops!
-        ++CurCycle;
-    } else if (!HasNoopHazards) {
-      // Otherwise, we have a pipeline stall, but no other problem, just advance
-      // the current cycle and try again.
-      DEBUG(dbgs() << "*** Advancing cycle, no work to do\n");
-      HazardRec->AdvanceCycle();
-      ++NumStalls;
-      ++CurCycle;
-    } else {
-      // Otherwise, we have no instructions to issue and we have instructions
-      // that will fault if we don't do this right.  This is the case for
-      // processors without pipeline interlocks and other cases.
-      DEBUG(dbgs() << "*** Emitting noop\n");
-      HazardRec->EmitNoop();
-      Sequence.push_back(0);   // NULL here means noop
-      ++NumNoops;
-      ++CurCycle;
-    }
-  }
-
-#ifndef NDEBUG
-  VerifySchedule(/*isBottomUp=*/false);
-#endif
-}
-
-//===----------------------------------------------------------------------===//
-//                         Public Constructor Functions
-//===----------------------------------------------------------------------===//
-
-/// createTDListDAGScheduler - This creates a top-down list scheduler.
-ScheduleDAGSDNodes *
-llvm::createTDListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
-  return new ScheduleDAGList(*IS->MF, new LatencyPriorityQueue());
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/CodeGen/Splitter.cpp
--- a/head/contrib/llvm/lib/CodeGen/Splitter.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,827 +0,0 @@
-//===-- llvm/CodeGen/Splitter.cpp -  Splitter -----------------------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "loopsplitter"
-
-#include "Splitter.h"
-
-#include "llvm/Module.h"
-#include "llvm/CodeGen/CalcSpillWeights.h"
-#include "llvm/CodeGen/LiveIntervalAnalysis.h"
-#include "llvm/CodeGen/LiveStackAnalysis.h"
-#include "llvm/CodeGen/MachineDominators.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/Passes.h"
-#include "llvm/CodeGen/SlotIndexes.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetInstrInfo.h"
-
-using namespace llvm;
-
-char LoopSplitter::ID = 0;
-INITIALIZE_PASS_BEGIN(LoopSplitter, "loop-splitting",
-                "Split virtual regists across loop boundaries.", false, false)
-INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
-INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
-INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
-INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
-INITIALIZE_PASS_END(LoopSplitter, "loop-splitting",
-                "Split virtual regists across loop boundaries.", false, false)
-
-namespace llvm {
-
-  class StartSlotComparator {
-  public:
-    StartSlotComparator(LiveIntervals &lis) : lis(lis) {}
-    bool operator()(const MachineBasicBlock *mbb1,
-                    const MachineBasicBlock *mbb2) const {
-      return lis.getMBBStartIdx(mbb1) < lis.getMBBStartIdx(mbb2);
-    }
-  private:
-    LiveIntervals &lis;
-  };
-
-  class LoopSplit {
-  public:
-    LoopSplit(LoopSplitter &ls, LiveInterval &li, MachineLoop &loop)
-      : ls(ls), li(li), loop(loop), valid(true), inSplit(false), newLI(0) {
-      assert(TargetRegisterInfo::isVirtualRegister(li.reg) &&
-             "Cannot split physical registers.");
-    }
-
-    LiveInterval& getLI() const { return li; }
-
-    MachineLoop& getLoop() const { return loop; }
-
-    bool isValid() const { return valid; }
-
-    bool isWorthwhile() const { return valid && (inSplit || !outSplits.empty()); }
-
-    void invalidate() { valid = false; }
-
-    void splitIncoming() { inSplit = true; }
-
-    void splitOutgoing(MachineLoop::Edge &edge) { outSplits.insert(edge); }
-
-    void addLoopInstr(MachineInstr *i) { loopInstrs.push_back(i); }
-
-    void apply() {
-      assert(valid && "Attempt to apply invalid split.");
-      applyIncoming();
-      applyOutgoing();
-      copyRanges();
-      renameInside();
-    }
-
-  private:
-    LoopSplitter &ls;
-    LiveInterval &li;
-    MachineLoop &loop;
-    bool valid, inSplit;
-    std::set<MachineLoop::Edge> outSplits;
-    std::vector<MachineInstr*> loopInstrs;
-
-    LiveInterval *newLI;
-    std::map<VNInfo*, VNInfo*> vniMap;
-
-    LiveInterval* getNewLI() {
-      if (newLI == 0) {
-        const TargetRegisterClass *trc = ls.mri->getRegClass(li.reg);
-        unsigned vreg = ls.mri->createVirtualRegister(trc);
-        newLI = &ls.lis->getOrCreateInterval(vreg);
-      }
-      return newLI;
-    }
-
-    VNInfo* getNewVNI(VNInfo *oldVNI) {
-      VNInfo *newVNI = vniMap[oldVNI];
-
-      if (newVNI == 0) {
-        newVNI = getNewLI()->createValueCopy(oldVNI,
-                                             ls.lis->getVNInfoAllocator());
-        vniMap[oldVNI] = newVNI;
-      }
-
-      return newVNI;
-    }
-
-    void applyIncoming() {
-      if (!inSplit) {
-        return;
-      }
-
-      MachineBasicBlock *preHeader = loop.getLoopPreheader();
-      if (preHeader == 0) {
-        assert(ls.canInsertPreHeader(loop) &&
-               "Can't insert required preheader.");
-        preHeader = &ls.insertPreHeader(loop);
-      }
-
-      LiveRange *preHeaderRange =
-        ls.lis->findExitingRange(li, preHeader);
-      assert(preHeaderRange != 0 && "Range not live into preheader.");
-
-      // Insert the new copy.
-      MachineInstr *copy = BuildMI(*preHeader,
-                                   preHeader->getFirstTerminator(),
-                                   DebugLoc(),
-                                   ls.tii->get(TargetOpcode::COPY))
-        .addReg(getNewLI()->reg, RegState::Define)
-        .addReg(li.reg, RegState::Kill);
-
-      ls.lis->InsertMachineInstrInMaps(copy);
-
-      SlotIndex copyDefIdx = ls.lis->getInstructionIndex(copy).getDefIndex();
-
-      VNInfo *newVal = getNewVNI(preHeaderRange->valno);
-      newVal->def = copyDefIdx;
-      newVal->setCopy(copy);
-      li.removeRange(copyDefIdx, ls.lis->getMBBEndIdx(preHeader), true);
-
-      getNewLI()->addRange(LiveRange(copyDefIdx,
-                                     ls.lis->getMBBEndIdx(preHeader),
-                                     newVal));
-    }
-
-    void applyOutgoing() {
-
-      for (std::set<MachineLoop::Edge>::iterator osItr = outSplits.begin(),
-                                                 osEnd = outSplits.end();
-           osItr != osEnd; ++osItr) {
-        MachineLoop::Edge edge = *osItr;
-        MachineBasicBlock *outBlock = edge.second;
-        if (ls.isCriticalEdge(edge)) {
-          assert(ls.canSplitEdge(edge) && "Unsplitable critical edge.");
-          outBlock = &ls.splitEdge(edge, loop);
-        }
-        LiveRange *outRange = ls.lis->findEnteringRange(li, outBlock);
-        assert(outRange != 0 && "No exiting range?");
-
-        MachineInstr *copy = BuildMI(*outBlock, outBlock->begin(),
-                                     DebugLoc(),
-                                     ls.tii->get(TargetOpcode::COPY))
-          .addReg(li.reg, RegState::Define)
-          .addReg(getNewLI()->reg, RegState::Kill);
-
-        ls.lis->InsertMachineInstrInMaps(copy);
-
-        SlotIndex copyDefIdx = ls.lis->getInstructionIndex(copy).getDefIndex();
-        
-        // Blow away output range definition.
-        outRange->valno->def = ls.lis->getInvalidIndex();
-        li.removeRange(ls.lis->getMBBStartIdx(outBlock), copyDefIdx);
-
-        SlotIndex newDefIdx = ls.lis->getMBBStartIdx(outBlock);
-        assert(ls.lis->getInstructionFromIndex(newDefIdx) == 0 &&
-               "PHI def index points at actual instruction.");
-        VNInfo *newVal =
-          getNewLI()->getNextValue(newDefIdx, 0, ls.lis->getVNInfoAllocator());
-
-        getNewLI()->addRange(LiveRange(ls.lis->getMBBStartIdx(outBlock),
-                                       copyDefIdx, newVal));
-                                       
-      }
-    }
-
-    void copyRange(LiveRange &lr) {
-      std::pair<bool, LoopSplitter::SlotPair> lsr =
-        ls.getLoopSubRange(lr, loop);
-      
-      if (!lsr.first)
-        return;
-
-      LiveRange loopRange(lsr.second.first, lsr.second.second,
-                          getNewVNI(lr.valno));
-
-      li.removeRange(loopRange.start, loopRange.end, true);
-
-      getNewLI()->addRange(loopRange);
-    }
-
-    void copyRanges() {
-      for (std::vector<MachineInstr*>::iterator iItr = loopInstrs.begin(),
-                                                iEnd = loopInstrs.end();
-           iItr != iEnd; ++iItr) {
-        MachineInstr &instr = **iItr;
-        SlotIndex instrIdx = ls.lis->getInstructionIndex(&instr);
-        if (instr.modifiesRegister(li.reg, 0)) {
-          LiveRange *defRange =
-            li.getLiveRangeContaining(instrIdx.getDefIndex());
-          if (defRange != 0) // May have caught this already.
-            copyRange(*defRange);
-        }
-        if (instr.readsRegister(li.reg, 0)) {
-          LiveRange *useRange =
-            li.getLiveRangeContaining(instrIdx.getUseIndex());
-          if (useRange != 0) { // May have caught this already.
-            copyRange(*useRange);
-          }
-        }
-      }
-
-      for (MachineLoop::block_iterator bbItr = loop.block_begin(),
-                                       bbEnd = loop.block_end();
-           bbItr != bbEnd; ++bbItr) {
-        MachineBasicBlock &loopBlock = **bbItr;
-        LiveRange *enteringRange =
-          ls.lis->findEnteringRange(li, &loopBlock);
-        if (enteringRange != 0) {
-          copyRange(*enteringRange);
-        }
-      }
-    } 
-
-    void renameInside() {
-      for (std::vector<MachineInstr*>::iterator iItr = loopInstrs.begin(),
-                                                iEnd = loopInstrs.end();
-           iItr != iEnd; ++iItr) {
-        MachineInstr &instr = **iItr;
-        for (unsigned i = 0; i < instr.getNumOperands(); ++i) {
-          MachineOperand &mop = instr.getOperand(i);
-          if (mop.isReg() && mop.getReg() == li.reg) {
-            mop.setReg(getNewLI()->reg);
-          }
-        }
-      }
-    }
-
-  };
-
-  void LoopSplitter::getAnalysisUsage(AnalysisUsage &au) const {
-    au.addRequired<MachineDominatorTree>();
-    au.addPreserved<MachineDominatorTree>();
-    au.addRequired<MachineLoopInfo>();
-    au.addPreserved<MachineLoopInfo>();
-    au.addPreservedID(RegisterCoalescerPassID);
-    au.addPreserved<CalculateSpillWeights>();
-    au.addPreserved<LiveStacks>();
-    au.addRequired<SlotIndexes>();
-    au.addPreserved<SlotIndexes>();
-    au.addRequired<LiveIntervals>();
-    au.addPreserved<LiveIntervals>();
-    MachineFunctionPass::getAnalysisUsage(au);
-  }
-
-  bool LoopSplitter::runOnMachineFunction(MachineFunction &fn) {
-
-    mf = &fn;
-    mri = &mf->getRegInfo();
-    tii = mf->getTarget().getInstrInfo();
-    tri = mf->getTarget().getRegisterInfo();
-    sis = &getAnalysis<SlotIndexes>();
-    lis = &getAnalysis<LiveIntervals>();
-    mli = &getAnalysis<MachineLoopInfo>();
-    mdt = &getAnalysis<MachineDominatorTree>();
-
-    fqn = mf->getFunction()->getParent()->getModuleIdentifier() + "." +
-      mf->getFunction()->getName().str();
-
-    dbgs() << "Splitting " << mf->getFunction()->getName() << ".";
-
-    dumpOddTerminators();
-
-//      dbgs() << "----------------------------------------\n";
-//      lis->dump();
-//      dbgs() << "----------------------------------------\n";
-       
-//     std::deque<MachineLoop*> loops;
-//     std::copy(mli->begin(), mli->end(), std::back_inserter(loops));
-//     dbgs() << "Loops:\n";
-//     while (!loops.empty()) {
-//       MachineLoop &loop = *loops.front();
-//       loops.pop_front();
-//       std::copy(loop.begin(), loop.end(), std::back_inserter(loops));
-
-//       dumpLoopInfo(loop);
-//     }
-    
-    //lis->dump();
-    //exit(0);
-
-    // Setup initial intervals.
-    for (LiveIntervals::iterator liItr = lis->begin(), liEnd = lis->end();
-         liItr != liEnd; ++liItr) {
-      LiveInterval *li = liItr->second;
-
-      if (TargetRegisterInfo::isVirtualRegister(li->reg) &&
-          !lis->intervalIsInOneMBB(*li)) {
-        intervals.push_back(li);
-      }
-    }
-
-    processIntervals();
-
-    intervals.clear();
-
-//     dbgs() << "----------------------------------------\n";
-//     lis->dump();
-//     dbgs() << "----------------------------------------\n";
-
-    dumpOddTerminators();
-
-    //exit(1);
-
-    return false;
-  }
-
-  void LoopSplitter::releaseMemory() {
-    fqn.clear();
-    intervals.clear();
-    loopRangeMap.clear();
-  }
-
-  void LoopSplitter::dumpOddTerminators() {
-    for (MachineFunction::iterator bbItr = mf->begin(), bbEnd = mf->end();
-         bbItr != bbEnd; ++bbItr) {
-      MachineBasicBlock *mbb = &*bbItr;
-      MachineBasicBlock *a = 0, *b = 0;
-      SmallVector<MachineOperand, 4> c;
-      if (tii->AnalyzeBranch(*mbb, a, b, c)) {
-        dbgs() << "MBB#" << mbb->getNumber() << " has multiway terminator.\n";
-        dbgs() << "  Terminators:\n";
-        for (MachineBasicBlock::iterator iItr = mbb->begin(), iEnd = mbb->end();
-             iItr != iEnd; ++iItr) {
-          MachineInstr *instr= &*iItr;
-          dbgs() << "    " << *instr << "";
-        }
-        dbgs() << "\n  Listed successors: [ ";
-        for (MachineBasicBlock::succ_iterator sItr = mbb->succ_begin(), sEnd = mbb->succ_end();
-             sItr != sEnd; ++sItr) {
-          MachineBasicBlock *succMBB = *sItr;
-          dbgs() << succMBB->getNumber() << " ";
-        }
-        dbgs() << "]\n\n";
-      }
-    }
-  }
-
-  void LoopSplitter::dumpLoopInfo(MachineLoop &loop) {
-    MachineBasicBlock &headerBlock = *loop.getHeader();
-    typedef SmallVector<MachineLoop::Edge, 8> ExitEdgesList;
-    ExitEdgesList exitEdges;
-    loop.getExitEdges(exitEdges);
-
-    dbgs() << "  Header: BB#" << headerBlock.getNumber() << ", Contains: [ ";
-    for (std::vector<MachineBasicBlock*>::const_iterator
-           subBlockItr = loop.getBlocks().begin(),
-           subBlockEnd = loop.getBlocks().end();
-         subBlockItr != subBlockEnd; ++subBlockItr) {
-      MachineBasicBlock &subBlock = **subBlockItr;
-      dbgs() << "BB#" << subBlock.getNumber() << " ";
-    }
-    dbgs() << "], Exit edges: [ ";
-    for (ExitEdgesList::iterator exitEdgeItr = exitEdges.begin(),
-                                 exitEdgeEnd = exitEdges.end();
-         exitEdgeItr != exitEdgeEnd; ++exitEdgeItr) {
-      MachineLoop::Edge &exitEdge = *exitEdgeItr;
-      dbgs() << "(MBB#" << exitEdge.first->getNumber()
-             << ", MBB#" << exitEdge.second->getNumber() << ") ";
-    }
-    dbgs() << "], Sub-Loop Headers: [ ";
-    for (MachineLoop::iterator subLoopItr = loop.begin(),
-                               subLoopEnd = loop.end();
-         subLoopItr != subLoopEnd; ++subLoopItr) {
-      MachineLoop &subLoop = **subLoopItr;
-      MachineBasicBlock &subLoopBlock = *subLoop.getHeader();
-      dbgs() << "BB#" << subLoopBlock.getNumber() << " ";
-    }
-    dbgs() << "]\n";
-  }
-
-  void LoopSplitter::updateTerminators(MachineBasicBlock &mbb) {
-    mbb.updateTerminator();
-
-    for (MachineBasicBlock::iterator miItr = mbb.begin(), miEnd = mbb.end();
-         miItr != miEnd; ++miItr) {
-      if (lis->isNotInMIMap(miItr)) {
-        lis->InsertMachineInstrInMaps(miItr);
-      }
-    }
-  }
-
-  bool LoopSplitter::canInsertPreHeader(MachineLoop &loop) {
-    MachineBasicBlock *header = loop.getHeader();
-    MachineBasicBlock *a = 0, *b = 0;
-    SmallVector<MachineOperand, 4> c;
-
-    for (MachineBasicBlock::pred_iterator pbItr = header->pred_begin(),
-                                          pbEnd = header->pred_end();
-         pbItr != pbEnd; ++pbItr) {
-      MachineBasicBlock *predBlock = *pbItr;
-      if (!!tii->AnalyzeBranch(*predBlock, a, b, c)) {
-        return false;
-      }
-    }
-
-    MachineFunction::iterator headerItr(header);
-    if (headerItr == mf->begin())
-      return true;
-    MachineBasicBlock *headerLayoutPred = llvm::prior(headerItr);
-    assert(headerLayoutPred != 0 && "Header should have layout pred.");
-
-    return (!tii->AnalyzeBranch(*headerLayoutPred, a, b, c));
-  }
-
-  MachineBasicBlock& LoopSplitter::insertPreHeader(MachineLoop &loop) {
-    assert(loop.getLoopPreheader() == 0 && "Loop already has preheader.");
-
-    MachineBasicBlock &header = *loop.getHeader();
-
-    // Save the preds - we'll need to update them once we insert the preheader.
-    typedef std::set<MachineBasicBlock*> HeaderPreds;
-    HeaderPreds headerPreds;
-
-    for (MachineBasicBlock::pred_iterator predItr = header.pred_begin(),
-                                          predEnd = header.pred_end();
-         predItr != predEnd; ++predItr) {
-      if (!loop.contains(*predItr))
-        headerPreds.insert(*predItr);
-    }
-
-    assert(!headerPreds.empty() && "No predecessors for header?");
-
-    //dbgs() << fqn << " MBB#" << header.getNumber() << " inserting preheader...";
-
-    MachineBasicBlock *preHeader =
-      mf->CreateMachineBasicBlock(header.getBasicBlock());
-
-    assert(preHeader != 0 && "Failed to create pre-header.");
-
-    mf->insert(header, preHeader);
-
-    for (HeaderPreds::iterator hpItr = headerPreds.begin(),
-                               hpEnd = headerPreds.end(); 
-         hpItr != hpEnd; ++hpItr) {
-      assert(*hpItr != 0 && "How'd a null predecessor get into this set?");
-      MachineBasicBlock &hp = **hpItr;
-      hp.ReplaceUsesOfBlockWith(&header, preHeader);
-    }
-    preHeader->addSuccessor(&header);
-
-    MachineBasicBlock *oldLayoutPred =
-      llvm::prior(MachineFunction::iterator(preHeader));
-    if (oldLayoutPred != 0) {
-      updateTerminators(*oldLayoutPred);
-    }
-
-    lis->InsertMBBInMaps(preHeader);
-
-    if (MachineLoop *parentLoop = loop.getParentLoop()) {
-      assert(parentLoop->getHeader() != loop.getHeader() &&
-             "Parent loop has same header?");
-      parentLoop->addBasicBlockToLoop(preHeader, mli->getBase());
-
-      // Invalidate all parent loop ranges.
-      while (parentLoop != 0) {
-        loopRangeMap.erase(parentLoop);
-        parentLoop = parentLoop->getParentLoop();
-      }
-    }
-
-    for (LiveIntervals::iterator liItr = lis->begin(),
-                                 liEnd = lis->end();
-         liItr != liEnd; ++liItr) {
-      LiveInterval &li = *liItr->second;
-
-      // Is this safe for physregs?
-      // TargetRegisterInfo::isPhysicalRegister(li.reg) ||
-      if (!lis->isLiveInToMBB(li, &header))
-        continue;
-
-      if (lis->isLiveInToMBB(li, preHeader)) {
-        assert(lis->isLiveOutOfMBB(li, preHeader) &&
-               "Range terminates in newly added preheader?");
-        continue;
-      }
-
-      bool insertRange = false;
-
-      for (MachineBasicBlock::pred_iterator predItr = preHeader->pred_begin(),
-                                            predEnd = preHeader->pred_end();
-           predItr != predEnd; ++predItr) {
-        MachineBasicBlock *predMBB = *predItr;
-        if (lis->isLiveOutOfMBB(li, predMBB)) {
-          insertRange = true;
-          break;
-        }
-      }
-
-      if (!insertRange)
-        continue;
-
-      SlotIndex newDefIdx = lis->getMBBStartIdx(preHeader);
-      assert(lis->getInstructionFromIndex(newDefIdx) == 0 &&
-             "PHI def index points at actual instruction.");
-      VNInfo *newVal = li.getNextValue(newDefIdx, 0, lis->getVNInfoAllocator());
-      li.addRange(LiveRange(lis->getMBBStartIdx(preHeader),
-                            lis->getMBBEndIdx(preHeader),
-                            newVal));
-    }
-
-
-    //dbgs() << "Dumping SlotIndexes:\n";
-    //sis->dump();
-
-    //dbgs() << "done. (Added MBB#" << preHeader->getNumber() << ")\n";
-
-    return *preHeader;
-  }
-
-  bool LoopSplitter::isCriticalEdge(MachineLoop::Edge &edge) {
-    assert(edge.first->succ_size() > 1 && "Non-sensical edge.");
-    if (edge.second->pred_size() > 1)
-      return true;
-    return false;
-  }
-
-  bool LoopSplitter::canSplitEdge(MachineLoop::Edge &edge) {
-    MachineFunction::iterator outBlockItr(edge.second);
-    if (outBlockItr == mf->begin())
-      return true;
-    MachineBasicBlock *outBlockLayoutPred = llvm::prior(outBlockItr);
-    assert(outBlockLayoutPred != 0 && "Should have a layout pred if out!=begin.");
-    MachineBasicBlock *a = 0, *b = 0;
-    SmallVector<MachineOperand, 4> c;
-    return (!tii->AnalyzeBranch(*outBlockLayoutPred, a, b, c) &&
-            !tii->AnalyzeBranch(*edge.first, a, b, c));
-  }
-
-  MachineBasicBlock& LoopSplitter::splitEdge(MachineLoop::Edge &edge,
-                                             MachineLoop &loop) {
-
-    MachineBasicBlock &inBlock = *edge.first;
-    MachineBasicBlock &outBlock = *edge.second;
-
-    assert((inBlock.succ_size() > 1) && (outBlock.pred_size() > 1) &&
-           "Splitting non-critical edge?");
-
-    //dbgs() << fqn << " Splitting edge (MBB#" << inBlock.getNumber()
-    //       << " -> MBB#" << outBlock.getNumber() << ")...";
-
-    MachineBasicBlock *splitBlock =
-      mf->CreateMachineBasicBlock();
-
-    assert(splitBlock != 0 && "Failed to create split block.");
-
-    mf->insert(&outBlock, splitBlock);
-
-    inBlock.ReplaceUsesOfBlockWith(&outBlock, splitBlock);
-    splitBlock->addSuccessor(&outBlock);
-
-    MachineBasicBlock *oldLayoutPred =
-      llvm::prior(MachineFunction::iterator(splitBlock));
-    if (oldLayoutPred != 0) {
-      updateTerminators(*oldLayoutPred);
-    }
-
-    lis->InsertMBBInMaps(splitBlock);
-
-    loopRangeMap.erase(&loop);
-
-    MachineLoop *splitParentLoop = loop.getParentLoop();
-    while (splitParentLoop != 0 &&
-           !splitParentLoop->contains(&outBlock)) {
-      splitParentLoop = splitParentLoop->getParentLoop();
-    }
-
-    if (splitParentLoop != 0) {
-      assert(splitParentLoop->contains(&loop) &&
-             "Split-block parent doesn't contain original loop?");
-      splitParentLoop->addBasicBlockToLoop(splitBlock, mli->getBase());
-      
-      // Invalidate all parent loop ranges.
-      while (splitParentLoop != 0) {
-        loopRangeMap.erase(splitParentLoop);
-        splitParentLoop = splitParentLoop->getParentLoop();
-      }
-    }
-
-
-    for (LiveIntervals::iterator liItr = lis->begin(),
-                                 liEnd = lis->end();
-         liItr != liEnd; ++liItr) {
-      LiveInterval &li = *liItr->second;
-      bool intersects = lis->isLiveOutOfMBB(li, &inBlock) &&
-                       lis->isLiveInToMBB(li, &outBlock);
-      if (lis->isLiveInToMBB(li, splitBlock)) {
-        if (!intersects) {
-          li.removeRange(lis->getMBBStartIdx(splitBlock),
-                         lis->getMBBEndIdx(splitBlock), true);
-        }
-      } else if (intersects) {
-        SlotIndex newDefIdx = lis->getMBBStartIdx(splitBlock);
-        assert(lis->getInstructionFromIndex(newDefIdx) == 0 &&
-               "PHI def index points at actual instruction.");
-        VNInfo *newVal = li.getNextValue(newDefIdx, 0,
-                                         lis->getVNInfoAllocator());
-        li.addRange(LiveRange(lis->getMBBStartIdx(splitBlock),
-                              lis->getMBBEndIdx(splitBlock),
-                              newVal));
-      }
-    }
-
-    //dbgs() << "done. (Added MBB#" << splitBlock->getNumber() << ")\n";
-
-    return *splitBlock;
-  }
-
-  LoopSplitter::LoopRanges& LoopSplitter::getLoopRanges(MachineLoop &loop) {
-    typedef std::set<MachineBasicBlock*, StartSlotComparator> LoopMBBSet;
-    LoopRangeMap::iterator lrItr = loopRangeMap.find(&loop);
-    if (lrItr == loopRangeMap.end()) {
-      LoopMBBSet loopMBBs((StartSlotComparator(*lis))); 
-      std::copy(loop.block_begin(), loop.block_end(),
-                std::inserter(loopMBBs, loopMBBs.begin()));
-
-      assert(!loopMBBs.empty() && "No blocks in loop?");
-
-      LoopRanges &loopRanges = loopRangeMap[&loop];
-      assert(loopRanges.empty() && "Loop encountered but not processed?");
-      SlotIndex oldEnd = lis->getMBBEndIdx(*loopMBBs.begin());
-      loopRanges.push_back(
-        std::make_pair(lis->getMBBStartIdx(*loopMBBs.begin()),
-                       lis->getInvalidIndex()));
-      for (LoopMBBSet::iterator curBlockItr = llvm::next(loopMBBs.begin()),
-                                curBlockEnd = loopMBBs.end();
-           curBlockItr != curBlockEnd; ++curBlockItr) {
-        SlotIndex newStart = lis->getMBBStartIdx(*curBlockItr);
-        if (newStart != oldEnd) {
-          loopRanges.back().second = oldEnd;
-          loopRanges.push_back(std::make_pair(newStart,
-                                              lis->getInvalidIndex()));
-        }
-        oldEnd = lis->getMBBEndIdx(*curBlockItr);
-      }
-
-      loopRanges.back().second =
-        lis->getMBBEndIdx(*llvm::prior(loopMBBs.end()));
-
-      return loopRanges;
-    }
-    return lrItr->second;
-  }
-
-  std::pair<bool, LoopSplitter::SlotPair> LoopSplitter::getLoopSubRange(
-                                                           const LiveRange &lr,
-                                                           MachineLoop &loop) {
-    LoopRanges &loopRanges = getLoopRanges(loop);
-    LoopRanges::iterator lrItr = loopRanges.begin(),
-                         lrEnd = loopRanges.end();
-    while (lrItr != lrEnd && lr.start >= lrItr->second) {
-      ++lrItr;
-    }
-
-    if (lrItr == lrEnd) {
-      SlotIndex invalid = lis->getInvalidIndex();
-      return std::make_pair(false, SlotPair(invalid, invalid));
-    }
-
-    SlotIndex srStart(lr.start < lrItr->first ? lrItr->first : lr.start);
-    SlotIndex srEnd(lr.end > lrItr->second ? lrItr->second : lr.end);
-
-    return std::make_pair(true, SlotPair(srStart, srEnd));      
-  }
-
-  void LoopSplitter::dumpLoopRanges(MachineLoop &loop) {
-    LoopRanges &loopRanges = getLoopRanges(loop);
-    dbgs() << "For loop MBB#" << loop.getHeader()->getNumber() << ", subranges are: [ ";
-    for (LoopRanges::iterator lrItr = loopRanges.begin(), lrEnd = loopRanges.end();
-         lrItr != lrEnd; ++lrItr) {
-      dbgs() << "[" << lrItr->first << ", " << lrItr->second << ") ";
-    }
-    dbgs() << "]\n";
-  }
-
-  void LoopSplitter::processHeader(LoopSplit &split) {
-    MachineBasicBlock &header = *split.getLoop().getHeader();
-    //dbgs() << "  Processing loop header BB#" << header.getNumber() << "\n";
-
-    if (!lis->isLiveInToMBB(split.getLI(), &header))
-      return; // Not live in, but nothing wrong so far.
-
-    MachineBasicBlock *preHeader = split.getLoop().getLoopPreheader();
-    if (!preHeader) {
-
-      if (!canInsertPreHeader(split.getLoop())) {
-        split.invalidate();
-        return; // Couldn't insert a pre-header. Bail on this interval.
-      }
-
-      for (MachineBasicBlock::pred_iterator predItr = header.pred_begin(),
-                                            predEnd = header.pred_end();
-           predItr != predEnd; ++predItr) {
-        if (lis->isLiveOutOfMBB(split.getLI(), *predItr)) {
-          split.splitIncoming();
-          break;
-        }
-      }
-    } else if (lis->isLiveOutOfMBB(split.getLI(), preHeader)) {
-      split.splitIncoming();
-    }
-  }
-
-  void LoopSplitter::processLoopExits(LoopSplit &split) {
-    typedef SmallVector<MachineLoop::Edge, 8> ExitEdgesList;
-    ExitEdgesList exitEdges;
-    split.getLoop().getExitEdges(exitEdges);
-
-    //dbgs() << "  Processing loop exits:\n";
-
-    for (ExitEdgesList::iterator exitEdgeItr = exitEdges.begin(),
-                                 exitEdgeEnd = exitEdges.end();
-         exitEdgeItr != exitEdgeEnd; ++exitEdgeItr) {
-      MachineLoop::Edge exitEdge = *exitEdgeItr;
-
-      LiveRange *outRange =
-        split.getLI().getLiveRangeContaining(lis->getMBBStartIdx(exitEdge.second));
-
-      if (outRange != 0) {
-        if (isCriticalEdge(exitEdge) && !canSplitEdge(exitEdge)) {
-          split.invalidate();
-          return;
-        }
-
-        split.splitOutgoing(exitEdge);
-      }
-    }
-  }
-
-  void LoopSplitter::processLoopUses(LoopSplit &split) {
-    std::set<MachineInstr*> processed;
-
-    for (MachineRegisterInfo::reg_iterator
-           rItr = mri->reg_begin(split.getLI().reg),
-           rEnd = mri->reg_end();
-      rItr != rEnd; ++rItr) {
-      MachineInstr &instr = *rItr;
-      if (split.getLoop().contains(&instr) && processed.count(&instr) == 0) {
-        split.addLoopInstr(&instr);
-        processed.insert(&instr);
-      }
-    }
-
-    //dbgs() << "  Rewriting reg" << li.reg << " to reg" << newLI->reg
-    //       << " in blocks [ ";
-    //dbgs() << "]\n";
-  }
-
-  bool LoopSplitter::splitOverLoop(LiveInterval &li, MachineLoop &loop) {
-    assert(TargetRegisterInfo::isVirtualRegister(li.reg) &&
-           "Attempt to split physical register.");
-
-    LoopSplit split(*this, li, loop);
-    processHeader(split);
-    if (split.isValid())
-      processLoopExits(split);
-    if (split.isValid())
-      processLoopUses(split);
-    if (split.isValid() /* && split.isWorthwhile() */) {
-      split.apply();
-      DEBUG(dbgs() << "Success.\n");
-      return true;
-    }
-    DEBUG(dbgs() << "Failed.\n");
-    return false;
-  }
-
-  void LoopSplitter::processInterval(LiveInterval &li) {
-    std::deque<MachineLoop*> loops;
-    std::copy(mli->begin(), mli->end(), std::back_inserter(loops));
-
-    while (!loops.empty()) {
-      MachineLoop &loop = *loops.front();
-      loops.pop_front();
-      DEBUG(
-        dbgs() << fqn << " reg" << li.reg << " " << li.weight << " BB#"
-               << loop.getHeader()->getNumber() << " ";
-      );
-      if (!splitOverLoop(li, loop)) {
-        // Couldn't split over outer loop, schedule sub-loops to be checked.
-	std::copy(loop.begin(), loop.end(), std::back_inserter(loops));
-      }
-    }
-  }
-
-  void LoopSplitter::processIntervals() {
-    while (!intervals.empty()) {
-      LiveInterval &li = *intervals.front();
-      intervals.pop_front();
-
-      assert(!lis->intervalIsInOneMBB(li) &&
-             "Single interval in process worklist.");
-
-      processInterval(li);      
-    }
-  }
-
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/CodeGen/Splitter.h
--- a/head/contrib/llvm/lib/CodeGen/Splitter.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,101 +0,0 @@
-//===-- llvm/CodeGen/Splitter.h - Splitter -*- C++ -*----------------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_CODEGEN_SPLITTER_H
-#define LLVM_CODEGEN_SPLITTER_H
-
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineLoopInfo.h"
-#include "llvm/CodeGen/SlotIndexes.h"
-
-#include <deque>
-#include <map>
-#include <string>
-#include <vector>
-
-namespace llvm {
-
-  class LiveInterval;
-  class LiveIntervals;
-  struct LiveRange;
-  class LoopSplit;
-  class MachineDominatorTree;
-  class MachineRegisterInfo;
-  class SlotIndexes;
-  class TargetInstrInfo;
-  class VNInfo;
-
-  class LoopSplitter : public MachineFunctionPass {
-    friend class LoopSplit;
-  public:
-    static char ID;
-
-    LoopSplitter() : MachineFunctionPass(ID) {
-      initializeLoopSplitterPass(*PassRegistry::getPassRegistry());
-    }
-
-    virtual void getAnalysisUsage(AnalysisUsage &au) const;
-
-    virtual bool runOnMachineFunction(MachineFunction &fn);
-
-    virtual void releaseMemory();
-
-
-  private:
-
-    MachineFunction *mf;
-    LiveIntervals *lis;
-    MachineLoopInfo *mli;
-    MachineRegisterInfo *mri;
-    MachineDominatorTree *mdt;
-    SlotIndexes *sis;
-    const TargetInstrInfo *tii;
-    const TargetRegisterInfo *tri;
-
-    std::string fqn;
-    std::deque<LiveInterval*> intervals;
-
-    typedef std::pair<SlotIndex, SlotIndex> SlotPair;
-    typedef std::vector<SlotPair> LoopRanges;
-    typedef std::map<MachineLoop*, LoopRanges> LoopRangeMap;
-    LoopRangeMap loopRangeMap;
-
-    void dumpLoopInfo(MachineLoop &loop);
-
-    void dumpOddTerminators();
-
-    void updateTerminators(MachineBasicBlock &mbb);
-
-    bool canInsertPreHeader(MachineLoop &loop);
-    MachineBasicBlock& insertPreHeader(MachineLoop &loop);
-
-    bool isCriticalEdge(MachineLoop::Edge &edge);
-    bool canSplitEdge(MachineLoop::Edge &edge);
-    MachineBasicBlock& splitEdge(MachineLoop::Edge &edge, MachineLoop &loop);
-
-    LoopRanges& getLoopRanges(MachineLoop &loop);
-    std::pair<bool, SlotPair> getLoopSubRange(const LiveRange &lr,
-                                              MachineLoop &loop);
-
-    void dumpLoopRanges(MachineLoop &loop);
-
-    void processHeader(LoopSplit &split);
-    void processLoopExits(LoopSplit &split);
-    void processLoopUses(LoopSplit &split);
-
-    bool splitOverLoop(LiveInterval &li, MachineLoop &loop);
-
-    void processInterval(LiveInterval &li);
-
-    void processIntervals();
-  };
-
-}
-
-#endif
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/CodeGen/VirtRegRewriter.cpp
--- a/head/contrib/llvm/lib/CodeGen/VirtRegRewriter.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,2633 +0,0 @@
-//===-- llvm/CodeGen/Rewriter.cpp -  Rewriter -----------------------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "virtregrewriter"
-#include "VirtRegRewriter.h"
-#include "VirtRegMap.h"
-#include "llvm/Function.h"
-#include "llvm/CodeGen/LiveIntervalAnalysis.h"
-#include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/Support/CommandLine.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/ADT/DepthFirstIterator.h"
-#include "llvm/ADT/SmallSet.h"
-#include "llvm/ADT/Statistic.h"
-using namespace llvm;
-
-STATISTIC(NumDSE     , "Number of dead stores elided");
-STATISTIC(NumDSS     , "Number of dead spill slots removed");
-STATISTIC(NumCommutes, "Number of instructions commuted");
-STATISTIC(NumDRM     , "Number of re-materializable defs elided");
-STATISTIC(NumStores  , "Number of stores added");
-STATISTIC(NumPSpills , "Number of physical register spills");
-STATISTIC(NumOmitted , "Number of reloads omitted");
-STATISTIC(NumAvoided , "Number of reloads deemed unnecessary");
-STATISTIC(NumCopified, "Number of available reloads turned into copies");
-STATISTIC(NumReMats  , "Number of re-materialization");
-STATISTIC(NumLoads   , "Number of loads added");
-STATISTIC(NumReused  , "Number of values reused");
-STATISTIC(NumDCE     , "Number of copies elided");
-STATISTIC(NumSUnfold , "Number of stores unfolded");
-STATISTIC(NumModRefUnfold, "Number of modref unfolded");
-
-namespace {
-  enum RewriterName { local, trivial };
-}
-
-static cl::opt<RewriterName>
-RewriterOpt("rewriter",
-            cl::desc("Rewriter to use (default=local)"),
-            cl::Prefix,
-            cl::values(clEnumVal(local,   "local rewriter"),
-                       clEnumVal(trivial, "trivial rewriter"),
-                       clEnumValEnd),
-            cl::init(local));
-
-static cl::opt<bool>
-ScheduleSpills("schedule-spills",
-               cl::desc("Schedule spill code"),
-               cl::init(false));
-
-VirtRegRewriter::~VirtRegRewriter() {}
-
-/// substitutePhysReg - Replace virtual register in MachineOperand with a
-/// physical register. Do the right thing with the sub-register index.
-/// Note that operands may be added, so the MO reference is no longer valid.
-static void substitutePhysReg(MachineOperand &MO, unsigned Reg,
-                              const TargetRegisterInfo &TRI) {
-  if (MO.getSubReg()) {
-    MO.substPhysReg(Reg, TRI);
-
-    // Any kill flags apply to the full virtual register, so they also apply to
-    // the full physical register.
-    // We assume that partial defs have already been decorated with a super-reg
-    // <imp-def> operand by LiveIntervals.
-    MachineInstr &MI = *MO.getParent();
-    if (MO.isUse() && !MO.isUndef() &&
-        (MO.isKill() || MI.isRegTiedToDefOperand(&MO-&MI.getOperand(0))))
-      MI.addRegisterKilled(Reg, &TRI, /*AddIfNotFound=*/ true);
-  } else {
-    MO.setReg(Reg);
-  }
-}
-
-namespace {
-
-/// This class is intended for use with the new spilling framework only. It
-/// rewrites vreg def/uses to use the assigned preg, but does not insert any
-/// spill code.
-struct TrivialRewriter : public VirtRegRewriter {
-
-  bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM,
-                            LiveIntervals* LIs) {
-    DEBUG(dbgs() << "********** REWRITE MACHINE CODE **********\n");
-    DEBUG(dbgs() << "********** Function: "
-          << MF.getFunction()->getName() << '\n');
-    DEBUG(dbgs() << "**** Machine Instrs"
-          << "(NOTE! Does not include spills and reloads!) ****\n");
-    DEBUG(MF.dump());
-
-    MachineRegisterInfo *mri = &MF.getRegInfo();
-    const TargetRegisterInfo *tri = MF.getTarget().getRegisterInfo();
-
-    bool changed = false;
-
-    for (LiveIntervals::iterator liItr = LIs->begin(), liEnd = LIs->end();
-         liItr != liEnd; ++liItr) {
-
-      const LiveInterval *li = liItr->second;
-      unsigned reg = li->reg;
-
-      if (TargetRegisterInfo::isPhysicalRegister(reg)) {
-        if (!li->empty())
-          mri->setPhysRegUsed(reg);
-      }
-      else {
-        if (!VRM.hasPhys(reg))
-          continue;
-        unsigned pReg = VRM.getPhys(reg);
-        mri->setPhysRegUsed(pReg);
-        // Copy the register use-list before traversing it.
-        SmallVector<std::pair<MachineInstr*, unsigned>, 32> reglist;
-        for (MachineRegisterInfo::reg_iterator I = mri->reg_begin(reg),
-               E = mri->reg_end(); I != E; ++I)
-          reglist.push_back(std::make_pair(&*I, I.getOperandNo()));
-        for (unsigned N=0; N != reglist.size(); ++N)
-          substitutePhysReg(reglist[N].first->getOperand(reglist[N].second),
-                            pReg, *tri);
-        changed |= !reglist.empty();
-      }
-    }
-
-    DEBUG(dbgs() << "**** Post Machine Instrs ****\n");
-    DEBUG(MF.dump());
-
-    return changed;
-  }
-
-};
-
-}
-
-// ************************************************************************ //
-
-namespace {
-
-/// AvailableSpills - As the local rewriter is scanning and rewriting an MBB
-/// from top down, keep track of which spill slots or remat are available in
-/// each register.
-///
-/// Note that not all physregs are created equal here.  In particular, some
-/// physregs are reloads that we are allowed to clobber or ignore at any time.
-/// Other physregs are values that the register allocated program is using
-/// that we cannot CHANGE, but we can read if we like.  We keep track of this
-/// on a per-stack-slot / remat id basis as the low bit in the value of the
-/// SpillSlotsAvailable entries.  The predicate 'canClobberPhysReg()' checks
-/// this bit and addAvailable sets it if.
-class AvailableSpills {
-  const TargetRegisterInfo *TRI;
-  const TargetInstrInfo *TII;
-
-  // SpillSlotsOrReMatsAvailable - This map keeps track of all of the spilled
-  // or remat'ed virtual register values that are still available, due to
-  // being loaded or stored to, but not invalidated yet.
-  std::map<int, unsigned> SpillSlotsOrReMatsAvailable;
-
-  // PhysRegsAvailable - This is the inverse of SpillSlotsOrReMatsAvailable,
-  // indicating which stack slot values are currently held by a physreg.  This
-  // is used to invalidate entries in SpillSlotsOrReMatsAvailable when a
-  // physreg is modified.
-  std::multimap<unsigned, int> PhysRegsAvailable;
-
-  void disallowClobberPhysRegOnly(unsigned PhysReg);
-
-  void ClobberPhysRegOnly(unsigned PhysReg);
-public:
-  AvailableSpills(const TargetRegisterInfo *tri, const TargetInstrInfo *tii)
-    : TRI(tri), TII(tii) {
-  }
-
-  /// clear - Reset the state.
-  void clear() {
-    SpillSlotsOrReMatsAvailable.clear();
-    PhysRegsAvailable.clear();
-  }
-
-  const TargetRegisterInfo *getRegInfo() const { return TRI; }
-
-  /// getSpillSlotOrReMatPhysReg - If the specified stack slot or remat is
-  /// available in a physical register, return that PhysReg, otherwise
-  /// return 0.
-  unsigned getSpillSlotOrReMatPhysReg(int Slot) const {
-    std::map<int, unsigned>::const_iterator I =
-      SpillSlotsOrReMatsAvailable.find(Slot);
-    if (I != SpillSlotsOrReMatsAvailable.end()) {
-      return I->second >> 1;  // Remove the CanClobber bit.
-    }
-    return 0;
-  }
-
-  /// addAvailable - Mark that the specified stack slot / remat is available
-  /// in the specified physreg.  If CanClobber is true, the physreg can be
-  /// modified at any time without changing the semantics of the program.
-  void addAvailable(int SlotOrReMat, unsigned Reg, bool CanClobber = true) {
-    // If this stack slot is thought to be available in some other physreg,
-    // remove its record.
-    ModifyStackSlotOrReMat(SlotOrReMat);
-
-    PhysRegsAvailable.insert(std::make_pair(Reg, SlotOrReMat));
-    SpillSlotsOrReMatsAvailable[SlotOrReMat]= (Reg << 1) |
-                                              (unsigned)CanClobber;
-
-    if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
-      DEBUG(dbgs() << "Remembering RM#"
-                   << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1);
-    else
-      DEBUG(dbgs() << "Remembering SS#" << SlotOrReMat);
-    DEBUG(dbgs() << " in physreg " << TRI->getName(Reg)
-          << (CanClobber ? " canclobber" : "") << "\n");
-  }
-
-  /// canClobberPhysRegForSS - Return true if the spiller is allowed to change
-  /// the value of the specified stackslot register if it desires. The
-  /// specified stack slot must be available in a physreg for this query to
-  /// make sense.
-  bool canClobberPhysRegForSS(int SlotOrReMat) const {
-    assert(SpillSlotsOrReMatsAvailable.count(SlotOrReMat) &&
-           "Value not available!");
-    return SpillSlotsOrReMatsAvailable.find(SlotOrReMat)->second & 1;
-  }
-
-  /// canClobberPhysReg - Return true if the spiller is allowed to clobber the
-  /// physical register where values for some stack slot(s) might be
-  /// available.
-  bool canClobberPhysReg(unsigned PhysReg) const {
-    std::multimap<unsigned, int>::const_iterator I =
-      PhysRegsAvailable.lower_bound(PhysReg);
-    while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
-      int SlotOrReMat = I->second;
-      I++;
-      if (!canClobberPhysRegForSS(SlotOrReMat))
-        return false;
-    }
-    return true;
-  }
-
-  /// disallowClobberPhysReg - Unset the CanClobber bit of the specified
-  /// stackslot register. The register is still available but is no longer
-  /// allowed to be modifed.
-  void disallowClobberPhysReg(unsigned PhysReg);
-
-  /// ClobberPhysReg - This is called when the specified physreg changes
-  /// value.  We use this to invalidate any info about stuff that lives in
-  /// it and any of its aliases.
-  void ClobberPhysReg(unsigned PhysReg);
-
-  /// ModifyStackSlotOrReMat - This method is called when the value in a stack
-  /// slot changes.  This removes information about which register the
-  /// previous value for this slot lives in (as the previous value is dead
-  /// now).
-  void ModifyStackSlotOrReMat(int SlotOrReMat);
-
-  /// ClobberSharingStackSlots - When a register mapped to a stack slot changes,
-  /// other stack slots sharing the same register are no longer valid.
-  void ClobberSharingStackSlots(int StackSlot);
-
-  /// AddAvailableRegsToLiveIn - Availability information is being kept coming
-  /// into the specified MBB. Add available physical registers as potential
-  /// live-in's. If they are reused in the MBB, they will be added to the
-  /// live-in set to make register scavenger and post-allocation scheduler.
-  void AddAvailableRegsToLiveIn(MachineBasicBlock &MBB, BitVector &RegKills,
-                                std::vector<MachineOperand*> &KillOps);
-};
-
-}
-
-// ************************************************************************ //
-
-// Given a location where a reload of a spilled register or a remat of
-// a constant is to be inserted, attempt to find a safe location to
-// insert the load at an earlier point in the basic-block, to hide
-// latency of the load and to avoid address-generation interlock
-// issues.
-static MachineBasicBlock::iterator
-ComputeReloadLoc(MachineBasicBlock::iterator const InsertLoc,
-                 MachineBasicBlock::iterator const Begin,
-                 unsigned PhysReg,
-                 const TargetRegisterInfo *TRI,
-                 bool DoReMat,
-                 int SSorRMId,
-                 const TargetInstrInfo *TII,
-                 const MachineFunction &MF)
-{
-  if (!ScheduleSpills)
-    return InsertLoc;
-
-  // Spill backscheduling is of primary interest to addresses, so
-  // don't do anything if the register isn't in the register class
-  // used for pointers.
-
-  const TargetLowering *TL = MF.getTarget().getTargetLowering();
-
-  if (!TL->isTypeLegal(TL->getPointerTy()))
-    // Believe it or not, this is true on 16-bit targets like PIC16.
-    return InsertLoc;
-
-  const TargetRegisterClass *ptrRegClass =
-    TL->getRegClassFor(TL->getPointerTy());
-  if (!ptrRegClass->contains(PhysReg))
-    return InsertLoc;
-
-  // Scan upwards through the preceding instructions. If an instruction doesn't
-  // reference the stack slot or the register we're loading, we can
-  // backschedule the reload up past it.
-  MachineBasicBlock::iterator NewInsertLoc = InsertLoc;
-  while (NewInsertLoc != Begin) {
-    MachineBasicBlock::iterator Prev = prior(NewInsertLoc);
-    for (unsigned i = 0; i < Prev->getNumOperands(); ++i) {
-      MachineOperand &Op = Prev->getOperand(i);
-      if (!DoReMat && Op.isFI() && Op.getIndex() == SSorRMId)
-        goto stop;
-    }
-    if (Prev->findRegisterUseOperandIdx(PhysReg) != -1 ||
-        Prev->findRegisterDefOperand(PhysReg))
-      goto stop;
-    for (const unsigned *Alias = TRI->getAliasSet(PhysReg); *Alias; ++Alias)
-      if (Prev->findRegisterUseOperandIdx(*Alias) != -1 ||
-          Prev->findRegisterDefOperand(*Alias))
-        goto stop;
-    NewInsertLoc = Prev;
-  }
-stop:;
-
-  // If we made it to the beginning of the block, turn around and move back
-  // down just past any existing reloads. They're likely to be reloads/remats
-  // for instructions earlier than what our current reload/remat is for, so
-  // they should be scheduled earlier.
-  if (NewInsertLoc == Begin) {
-    int FrameIdx;
-    while (InsertLoc != NewInsertLoc &&
-           (TII->isLoadFromStackSlot(NewInsertLoc, FrameIdx) ||
-            TII->isTriviallyReMaterializable(NewInsertLoc)))
-      ++NewInsertLoc;
-  }
-
-  return NewInsertLoc;
-}
-
-namespace {
-
-// ReusedOp - For each reused operand, we keep track of a bit of information,
-// in case we need to rollback upon processing a new operand.  See comments
-// below.
-struct ReusedOp {
-  // The MachineInstr operand that reused an available value.
-  unsigned Operand;
-
-  // StackSlotOrReMat - The spill slot or remat id of the value being reused.
-  unsigned StackSlotOrReMat;
-
-  // PhysRegReused - The physical register the value was available in.
-  unsigned PhysRegReused;
-
-  // AssignedPhysReg - The physreg that was assigned for use by the reload.
-  unsigned AssignedPhysReg;
-
-  // VirtReg - The virtual register itself.
-  unsigned VirtReg;
-
-  ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
-           unsigned vreg)
-    : Operand(o), StackSlotOrReMat(ss), PhysRegReused(prr),
-      AssignedPhysReg(apr), VirtReg(vreg) {}
-};
-
-/// ReuseInfo - This maintains a collection of ReuseOp's for each operand that
-/// is reused instead of reloaded.
-class ReuseInfo {
-  MachineInstr &MI;
-  std::vector<ReusedOp> Reuses;
-  BitVector PhysRegsClobbered;
-public:
-  ReuseInfo(MachineInstr &mi, const TargetRegisterInfo *tri) : MI(mi) {
-    PhysRegsClobbered.resize(tri->getNumRegs());
-  }
-
-  bool hasReuses() const {
-    return !Reuses.empty();
-  }
-
-  /// addReuse - If we choose to reuse a virtual register that is already
-  /// available instead of reloading it, remember that we did so.
-  void addReuse(unsigned OpNo, unsigned StackSlotOrReMat,
-                unsigned PhysRegReused, unsigned AssignedPhysReg,
-                unsigned VirtReg) {
-    // If the reload is to the assigned register anyway, no undo will be
-    // required.
-    if (PhysRegReused == AssignedPhysReg) return;
-
-    // Otherwise, remember this.
-    Reuses.push_back(ReusedOp(OpNo, StackSlotOrReMat, PhysRegReused,
-                              AssignedPhysReg, VirtReg));
-  }
-
-  void markClobbered(unsigned PhysReg) {
-    PhysRegsClobbered.set(PhysReg);
-  }
-
-  bool isClobbered(unsigned PhysReg) const {
-    return PhysRegsClobbered.test(PhysReg);
-  }
-
-  /// GetRegForReload - We are about to emit a reload into PhysReg.  If there
-  /// is some other operand that is using the specified register, either pick
-  /// a new register to use, or evict the previous reload and use this reg.
-  unsigned GetRegForReload(const TargetRegisterClass *RC, unsigned PhysReg,
-                           MachineFunction &MF, MachineInstr *MI,
-                           AvailableSpills &Spills,
-                           std::vector<MachineInstr*> &MaybeDeadStores,
-                           SmallSet<unsigned, 8> &Rejected,
-                           BitVector &RegKills,
-                           std::vector<MachineOperand*> &KillOps,
-                           VirtRegMap &VRM);
-
-  /// GetRegForReload - Helper for the above GetRegForReload(). Add a
-  /// 'Rejected' set to remember which registers have been considered and
-  /// rejected for the reload. This avoids infinite looping in case like
-  /// this:
-  /// t1 := op t2, t3
-  /// t2 <- assigned r0 for use by the reload but ended up reuse r1
-  /// t3 <- assigned r1 for use by the reload but ended up reuse r0
-  /// t1 <- desires r1
-  ///       sees r1 is taken by t2, tries t2's reload register r0
-  ///       sees r0 is taken by t3, tries t3's reload register r1
-  ///       sees r1 is taken by t2, tries t2's reload register r0 ...
-  unsigned GetRegForReload(unsigned VirtReg, unsigned PhysReg, MachineInstr *MI,
-                           AvailableSpills &Spills,
-                           std::vector<MachineInstr*> &MaybeDeadStores,
-                           BitVector &RegKills,
-                           std::vector<MachineOperand*> &KillOps,
-                           VirtRegMap &VRM) {
-    SmallSet<unsigned, 8> Rejected;
-    MachineFunction &MF = *MI->getParent()->getParent();
-    const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(VirtReg);
-    return GetRegForReload(RC, PhysReg, MF, MI, Spills, MaybeDeadStores,
-                           Rejected, RegKills, KillOps, VRM);
-  }
-};
-
-}
-
-// ****************** //
-// Utility Functions  //
-// ****************** //
-
-/// findSinglePredSuccessor - Return via reference a vector of machine basic
-/// blocks each of which is a successor of the specified BB and has no other
-/// predecessor.
-static void findSinglePredSuccessor(MachineBasicBlock *MBB,
-                                   SmallVectorImpl<MachineBasicBlock *> &Succs){
-  for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
-         SE = MBB->succ_end(); SI != SE; ++SI) {
-    MachineBasicBlock *SuccMBB = *SI;
-    if (SuccMBB->pred_size() == 1)
-      Succs.push_back(SuccMBB);
-  }
-}
-
-/// ResurrectConfirmedKill - Helper for ResurrectKill. This register is killed
-/// but not re-defined and it's being reused. Remove the kill flag for the
-/// register and unset the kill's marker and last kill operand.
-static void ResurrectConfirmedKill(unsigned Reg, const TargetRegisterInfo* TRI,
-                                   BitVector &RegKills,
-                                   std::vector<MachineOperand*> &KillOps) {
-  DEBUG(dbgs() << "Resurrect " << TRI->getName(Reg) << "\n");
-
-  MachineOperand *KillOp = KillOps[Reg];
-  KillOp->setIsKill(false);
-  // KillOps[Reg] might be a def of a super-register.
-  unsigned KReg = KillOp->getReg();
-  if (!RegKills[KReg])
-    return;
-
-  assert(KillOps[KReg]->getParent() == KillOp->getParent() &&
-         "invalid superreg kill flags");
-  KillOps[KReg] = NULL;
-  RegKills.reset(KReg);
-
-  // If it's a def of a super-register. Its other sub-regsters are no
-  // longer killed as well.
-  for (const unsigned *SR = TRI->getSubRegisters(KReg); *SR; ++SR) {
-    DEBUG(dbgs() << "  Resurrect subreg " << TRI->getName(*SR) << "\n");
-
-    assert(KillOps[*SR]->getParent() == KillOp->getParent() &&
-           "invalid subreg kill flags");
-    KillOps[*SR] = NULL;
-    RegKills.reset(*SR);
-  }
-}
-
-/// ResurrectKill - Invalidate kill info associated with a previous MI. An
-/// optimization may have decided that it's safe to reuse a previously killed
-/// register. If we fail to erase the invalid kill flags, then the register
-/// scavenger may later clobber the register used by this MI. Note that this
-/// must be done even if this MI is being deleted! Consider:
-///
-/// USE $r1 (vreg1) <kill>
-/// ...
-/// $r1(vreg3) = COPY $r1 (vreg2)
-///
-/// RegAlloc has smartly assigned all three vregs to the same physreg. Initially
-/// vreg1's only use is a kill. The rewriter doesn't know it should be live
-/// until it rewrites vreg2. At that points it sees that the copy is dead and
-/// deletes it. However, deleting the copy implicitly forwards liveness of $r1
-/// (it's copy coalescing). We must resurrect $r1 by removing the kill flag at
-/// vreg1 before deleting the copy.
-static void ResurrectKill(MachineInstr &MI, unsigned Reg,
-                          const TargetRegisterInfo* TRI, BitVector &RegKills,
-                          std::vector<MachineOperand*> &KillOps) {
-  if (RegKills[Reg] && KillOps[Reg]->getParent() != &MI) {
-    ResurrectConfirmedKill(Reg, TRI, RegKills, KillOps);
-    return;
-  }
-  // No previous kill for this reg. Check for subreg kills as well.
-  // d4 =
-  // store d4, fi#0
-  // ...
-  //    = s8<kill>
-  // ...
-  //    = d4  <avoiding reload>
-  for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR) {
-    unsigned SReg = *SR;
-    if (RegKills[SReg] && KillOps[SReg]->getParent() != &MI)
-      ResurrectConfirmedKill(SReg, TRI, RegKills, KillOps);
-  }
-}
-
-/// InvalidateKills - MI is going to be deleted. If any of its operands are
-/// marked kill, then invalidate the information.
-static void InvalidateKills(MachineInstr &MI,
-                            const TargetRegisterInfo* TRI,
-                            BitVector &RegKills,
-                            std::vector<MachineOperand*> &KillOps,
-                            SmallVector<unsigned, 2> *KillRegs = NULL) {
-  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
-    MachineOperand &MO = MI.getOperand(i);
-    if (!MO.isReg() || !MO.isUse() || !MO.isKill() || MO.isUndef())
-      continue;
-    unsigned Reg = MO.getReg();
-    if (TargetRegisterInfo::isVirtualRegister(Reg))
-      continue;
-    if (KillRegs)
-      KillRegs->push_back(Reg);
-    assert(Reg < KillOps.size());
-    if (KillOps[Reg] == &MO) {
-      // This operand was the kill, now no longer.
-      KillOps[Reg] = NULL;
-      RegKills.reset(Reg);
-      for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR) {
-        if (RegKills[*SR]) {
-          assert(KillOps[*SR] == &MO && "bad subreg kill flags");
-          KillOps[*SR] = NULL;
-          RegKills.reset(*SR);
-        }
-      }
-    }
-    else {
-      // This operand may have reused a previously killed reg. Keep it live in
-      // case it continues to be used after erasing this instruction.
-      ResurrectKill(MI, Reg, TRI, RegKills, KillOps);
-    }
-  }
-}
-
-/// InvalidateRegDef - If the def operand of the specified def MI is now dead
-/// (since its spill instruction is removed), mark it isDead. Also checks if
-/// the def MI has other definition operands that are not dead. Returns it by
-/// reference.
-static bool InvalidateRegDef(MachineBasicBlock::iterator I,
-                             MachineInstr &NewDef, unsigned Reg,
-                             bool &HasLiveDef,
-                             const TargetRegisterInfo *TRI) {
-  // Due to remat, it's possible this reg isn't being reused. That is,
-  // the def of this reg (by prev MI) is now dead.
-  MachineInstr *DefMI = I;
-  MachineOperand *DefOp = NULL;
-  for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) {
-    MachineOperand &MO = DefMI->getOperand(i);
-    if (!MO.isReg() || !MO.isDef() || !MO.isKill() || MO.isUndef())
-      continue;
-    if (MO.getReg() == Reg)
-      DefOp = &MO;
-    else if (!MO.isDead())
-      HasLiveDef = true;
-  }
-  if (!DefOp)
-    return false;
-
-  bool FoundUse = false, Done = false;
-  MachineBasicBlock::iterator E = &NewDef;
-  ++I; ++E;
-  for (; !Done && I != E; ++I) {
-    MachineInstr *NMI = I;
-    for (unsigned j = 0, ee = NMI->getNumOperands(); j != ee; ++j) {
-      MachineOperand &MO = NMI->getOperand(j);
-      if (!MO.isReg() || MO.getReg() == 0 ||
-          (MO.getReg() != Reg && !TRI->isSubRegister(Reg, MO.getReg())))
-        continue;
-      if (MO.isUse())
-        FoundUse = true;
-      Done = true; // Stop after scanning all the operands of this MI.
-    }
-  }
-  if (!FoundUse) {
-    // Def is dead!
-    DefOp->setIsDead();
-    return true;
-  }
-  return false;
-}
-
-/// UpdateKills - Track and update kill info. If a MI reads a register that is
-/// marked kill, then it must be due to register reuse. Transfer the kill info
-/// over.
-static void UpdateKills(MachineInstr &MI, const TargetRegisterInfo* TRI,
-                        BitVector &RegKills,
-                        std::vector<MachineOperand*> &KillOps) {
-  // These do not affect kill info at all.
-  if (MI.isDebugValue())
-    return;
-  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
-    MachineOperand &MO = MI.getOperand(i);
-    if (!MO.isReg() || !MO.isUse() || MO.isUndef())
-      continue;
-    unsigned Reg = MO.getReg();
-    if (Reg == 0)
-      continue;
-
-    // This operand may have reused a previously killed reg. Keep it live.
-    ResurrectKill(MI, Reg, TRI, RegKills, KillOps);
-
-    if (MO.isKill()) {
-      RegKills.set(Reg);
-      KillOps[Reg] = &MO;
-      for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR) {
-        RegKills.set(*SR);
-        KillOps[*SR] = &MO;
-      }
-    }
-  }
-
-  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
-    const MachineOperand &MO = MI.getOperand(i);
-    if (!MO.isReg() || !MO.getReg() || !MO.isDef())
-      continue;
-    unsigned Reg = MO.getReg();
-    RegKills.reset(Reg);
-    KillOps[Reg] = NULL;
-    // It also defines (or partially define) aliases.
-    for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR) {
-      RegKills.reset(*SR);
-      KillOps[*SR] = NULL;
-    }
-    for (const unsigned *SR = TRI->getSuperRegisters(Reg); *SR; ++SR) {
-      RegKills.reset(*SR);
-      KillOps[*SR] = NULL;
-    }
-  }
-}
-
-/// ReMaterialize - Re-materialize definition for Reg targeting DestReg.
-///
-static void ReMaterialize(MachineBasicBlock &MBB,
-                          MachineBasicBlock::iterator &MII,
-                          unsigned DestReg, unsigned Reg,
-                          const TargetInstrInfo *TII,
-                          const TargetRegisterInfo *TRI,
-                          VirtRegMap &VRM) {
-  MachineInstr *ReMatDefMI = VRM.getReMaterializedMI(Reg);
-#ifndef NDEBUG
-  const MCInstrDesc &MCID = ReMatDefMI->getDesc();
-  assert(MCID.getNumDefs() == 1 &&
-         "Don't know how to remat instructions that define > 1 values!");
-#endif
-  TII->reMaterialize(MBB, MII, DestReg, 0, ReMatDefMI, *TRI);
-  MachineInstr *NewMI = prior(MII);
-  for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) {
-    MachineOperand &MO = NewMI->getOperand(i);
-    if (!MO.isReg() || MO.getReg() == 0)
-      continue;
-    unsigned VirtReg = MO.getReg();
-    if (TargetRegisterInfo::isPhysicalRegister(VirtReg))
-      continue;
-    assert(MO.isUse());
-    unsigned Phys = VRM.getPhys(VirtReg);
-    assert(Phys && "Virtual register is not assigned a register?");
-    substitutePhysReg(MO, Phys, *TRI);
-  }
-  ++NumReMats;
-}
-
-/// findSuperReg - Find the SubReg's super-register of given register class
-/// where its SubIdx sub-register is SubReg.
-static unsigned findSuperReg(const TargetRegisterClass *RC, unsigned SubReg,
-                             unsigned SubIdx, const TargetRegisterInfo *TRI) {
-  for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
-       I != E; ++I) {
-    unsigned Reg = *I;
-    if (TRI->getSubReg(Reg, SubIdx) == SubReg)
-      return Reg;
-  }
-  return 0;
-}
-
-// ******************************** //
-// Available Spills Implementation  //
-// ******************************** //
-
-/// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified
-/// stackslot register. The register is still available but is no longer
-/// allowed to be modifed.
-void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) {
-  std::multimap<unsigned, int>::iterator I =
-    PhysRegsAvailable.lower_bound(PhysReg);
-  while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
-    int SlotOrReMat = I->second;
-    I++;
-    assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
-           "Bidirectional map mismatch!");
-    SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1;
-    DEBUG(dbgs() << "PhysReg " << TRI->getName(PhysReg)
-         << " copied, it is available for use but can no longer be modified\n");
-  }
-}
-
-/// disallowClobberPhysReg - Unset the CanClobber bit of the specified
-/// stackslot register and its aliases. The register and its aliases may
-/// still available but is no longer allowed to be modifed.
-void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) {
-  for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS)
-    disallowClobberPhysRegOnly(*AS);
-  disallowClobberPhysRegOnly(PhysReg);
-}
-
-/// ClobberPhysRegOnly - This is called when the specified physreg changes
-/// value.  We use this to invalidate any info about stuff we thing lives in it.
-void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
-  std::multimap<unsigned, int>::iterator I =
-    PhysRegsAvailable.lower_bound(PhysReg);
-  while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
-    int SlotOrReMat = I->second;
-    PhysRegsAvailable.erase(I++);
-    assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
-           "Bidirectional map mismatch!");
-    SpillSlotsOrReMatsAvailable.erase(SlotOrReMat);
-    DEBUG(dbgs() << "PhysReg " << TRI->getName(PhysReg)
-          << " clobbered, invalidating ");
-    if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
-      DEBUG(dbgs() << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 <<"\n");
-    else
-      DEBUG(dbgs() << "SS#" << SlotOrReMat << "\n");
-  }
-}
-
-/// ClobberPhysReg - This is called when the specified physreg changes
-/// value.  We use this to invalidate any info about stuff we thing lives in
-/// it and any of its aliases.
-void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
-  for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS)
-    ClobberPhysRegOnly(*AS);
-  ClobberPhysRegOnly(PhysReg);
-}
-
-/// AddAvailableRegsToLiveIn - Availability information is being kept coming
-/// into the specified MBB. Add available physical registers as potential
-/// live-in's. If they are reused in the MBB, they will be added to the
-/// live-in set to make register scavenger and post-allocation scheduler.
-void AvailableSpills::AddAvailableRegsToLiveIn(MachineBasicBlock &MBB,
-                                        BitVector &RegKills,
-                                        std::vector<MachineOperand*> &KillOps) {
-  std::set<unsigned> NotAvailable;
-  for (std::multimap<unsigned, int>::iterator
-         I = PhysRegsAvailable.begin(), E = PhysRegsAvailable.end();
-       I != E; ++I) {
-    unsigned Reg = I->first;
-    const TargetRegisterClass* RC = TRI->getMinimalPhysRegClass(Reg);
-    // FIXME: A temporary workaround. We can't reuse available value if it's
-    // not safe to move the def of the virtual register's class. e.g.
-    // X86::RFP* register classes. Do not add it as a live-in.
-    if (!TII->isSafeToMoveRegClassDefs(RC))
-      // This is no longer available.
-      NotAvailable.insert(Reg);
-    else {
-      MBB.addLiveIn(Reg);
-      if (RegKills[Reg])
-        ResurrectConfirmedKill(Reg, TRI, RegKills, KillOps);
-    }
-
-    // Skip over the same register.
-    std::multimap<unsigned, int>::iterator NI = llvm::next(I);
-    while (NI != E && NI->first == Reg) {
-      ++I;
-      ++NI;
-    }
-  }
-
-  for (std::set<unsigned>::iterator I = NotAvailable.begin(),
-         E = NotAvailable.end(); I != E; ++I) {
-    ClobberPhysReg(*I);
-    for (const unsigned *SubRegs = TRI->getSubRegisters(*I);
-       *SubRegs; ++SubRegs)
-      ClobberPhysReg(*SubRegs);
-  }
-}
-
-/// ModifyStackSlotOrReMat - This method is called when the value in a stack
-/// slot changes.  This removes information about which register the previous
-/// value for this slot lives in (as the previous value is dead now).
-void AvailableSpills::ModifyStackSlotOrReMat(int SlotOrReMat) {
-  std::map<int, unsigned>::iterator It =
-    SpillSlotsOrReMatsAvailable.find(SlotOrReMat);
-  if (It == SpillSlotsOrReMatsAvailable.end()) return;
-  unsigned Reg = It->second >> 1;
-  SpillSlotsOrReMatsAvailable.erase(It);
-
-  // This register may hold the value of multiple stack slots, only remove this
-  // stack slot from the set of values the register contains.
-  std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
-  for (; ; ++I) {
-    assert(I != PhysRegsAvailable.end() && I->first == Reg &&
-           "Map inverse broken!");
-    if (I->second == SlotOrReMat) break;
-  }
-  PhysRegsAvailable.erase(I);
-}
-
-void AvailableSpills::ClobberSharingStackSlots(int StackSlot) {
-  std::map<int, unsigned>::iterator It =
-    SpillSlotsOrReMatsAvailable.find(StackSlot);
-  if (It == SpillSlotsOrReMatsAvailable.end()) return;
-  unsigned Reg = It->second >> 1;
-
-  // Erase entries in PhysRegsAvailable for other stack slots.
-  std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
-  while (I != PhysRegsAvailable.end() && I->first == Reg) {
-    std::multimap<unsigned, int>::iterator NextI = llvm::next(I);
-    if (I->second != StackSlot) {
-      DEBUG(dbgs() << "Clobbered sharing SS#" << I->second << " in "
-                   << PrintReg(Reg, TRI) << '\n');
-      SpillSlotsOrReMatsAvailable.erase(I->second);
-      PhysRegsAvailable.erase(I);
-    }
-    I = NextI;
-  }
-}
-
-// ************************** //
-// Reuse Info Implementation  //
-// ************************** //
-
-/// GetRegForReload - We are about to emit a reload into PhysReg.  If there
-/// is some other operand that is using the specified register, either pick
-/// a new register to use, or evict the previous reload and use this reg.
-unsigned ReuseInfo::GetRegForReload(const TargetRegisterClass *RC,
-                         unsigned PhysReg,
-                         MachineFunction &MF,
-                         MachineInstr *MI, AvailableSpills &Spills,
-                         std::vector<MachineInstr*> &MaybeDeadStores,
-                         SmallSet<unsigned, 8> &Rejected,
-                         BitVector &RegKills,
-                         std::vector<MachineOperand*> &KillOps,
-                         VirtRegMap &VRM) {
-  const TargetInstrInfo* TII = MF.getTarget().getInstrInfo();
-  const TargetRegisterInfo *TRI = Spills.getRegInfo();
-
-  if (Reuses.empty()) return PhysReg;  // This is most often empty.
-
-  for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
-    ReusedOp &Op = Reuses[ro];
-    // If we find some other reuse that was supposed to use this register
-    // exactly for its reload, we can change this reload to use ITS reload
-    // register. That is, unless its reload register has already been
-    // considered and subsequently rejected because it has also been reused
-    // by another operand.
-    if (Op.PhysRegReused == PhysReg &&
-        Rejected.count(Op.AssignedPhysReg) == 0 &&
-        RC->contains(Op.AssignedPhysReg)) {
-      // Yup, use the reload register that we didn't use before.
-      unsigned NewReg = Op.AssignedPhysReg;
-      Rejected.insert(PhysReg);
-      return GetRegForReload(RC, NewReg, MF, MI, Spills, MaybeDeadStores,
-                             Rejected, RegKills, KillOps, VRM);
-    } else {
-      // Otherwise, we might also have a problem if a previously reused
-      // value aliases the new register. If so, codegen the previous reload
-      // and use this one.
-      unsigned PRRU = Op.PhysRegReused;
-      if (TRI->regsOverlap(PRRU, PhysReg)) {
-        // Okay, we found out that an alias of a reused register
-        // was used.  This isn't good because it means we have
-        // to undo a previous reuse.
-        MachineBasicBlock *MBB = MI->getParent();
-        const TargetRegisterClass *AliasRC =
-          MBB->getParent()->getRegInfo().getRegClass(Op.VirtReg);
-
-        // Copy Op out of the vector and remove it, we're going to insert an
-        // explicit load for it.
-        ReusedOp NewOp = Op;
-        Reuses.erase(Reuses.begin()+ro);
-
-        // MI may be using only a sub-register of PhysRegUsed.
-        unsigned RealPhysRegUsed = MI->getOperand(NewOp.Operand).getReg();
-        unsigned SubIdx = 0;
-        assert(TargetRegisterInfo::isPhysicalRegister(RealPhysRegUsed) &&
-               "A reuse cannot be a virtual register");
-        if (PRRU != RealPhysRegUsed) {
-          // What was the sub-register index?
-          SubIdx = TRI->getSubRegIndex(PRRU, RealPhysRegUsed);
-          assert(SubIdx &&
-                 "Operand physreg is not a sub-register of PhysRegUsed");
-        }
-
-        // Ok, we're going to try to reload the assigned physreg into the
-        // slot that we were supposed to in the first place.  However, that
-        // register could hold a reuse.  Check to see if it conflicts or
-        // would prefer us to use a different register.
-        unsigned NewPhysReg = GetRegForReload(RC, NewOp.AssignedPhysReg,
-                                              MF, MI, Spills, MaybeDeadStores,
-                                              Rejected, RegKills, KillOps, VRM);
-
-        bool DoReMat = NewOp.StackSlotOrReMat > VirtRegMap::MAX_STACK_SLOT;
-        int SSorRMId = DoReMat
-          ? VRM.getReMatId(NewOp.VirtReg) : (int) NewOp.StackSlotOrReMat;
-
-        // Back-schedule reloads and remats.
-        MachineBasicBlock::iterator InsertLoc =
-          ComputeReloadLoc(MI, MBB->begin(), PhysReg, TRI,
-                           DoReMat, SSorRMId, TII, MF);
-
-        if (DoReMat) {
-          ReMaterialize(*MBB, InsertLoc, NewPhysReg, NewOp.VirtReg, TII,
-                        TRI, VRM);
-        } else {
-          TII->loadRegFromStackSlot(*MBB, InsertLoc, NewPhysReg,
-                                    NewOp.StackSlotOrReMat, AliasRC, TRI);
-          MachineInstr *LoadMI = prior(InsertLoc);
-          VRM.addSpillSlotUse(NewOp.StackSlotOrReMat, LoadMI);
-          // Any stores to this stack slot are not dead anymore.
-          MaybeDeadStores[NewOp.StackSlotOrReMat] = NULL;
-          ++NumLoads;
-        }
-        Spills.ClobberPhysReg(NewPhysReg);
-        Spills.ClobberPhysReg(NewOp.PhysRegReused);
-
-        unsigned RReg = SubIdx ? TRI->getSubReg(NewPhysReg, SubIdx) :NewPhysReg;
-        MI->getOperand(NewOp.Operand).setReg(RReg);
-        MI->getOperand(NewOp.Operand).setSubReg(0);
-
-        Spills.addAvailable(NewOp.StackSlotOrReMat, NewPhysReg);
-        UpdateKills(*prior(InsertLoc), TRI, RegKills, KillOps);
-        DEBUG(dbgs() << '\t' << *prior(InsertLoc));
-
-        DEBUG(dbgs() << "Reuse undone!\n");
-        --NumReused;
-
-        // Finally, PhysReg is now available, go ahead and use it.
-        return PhysReg;
-      }
-    }
-  }
-  return PhysReg;
-}
-
-// ************************************************************************ //
-
-/// FoldsStackSlotModRef - Return true if the specified MI folds the specified
-/// stack slot mod/ref. It also checks if it's possible to unfold the
-/// instruction by having it define a specified physical register instead.
-static bool FoldsStackSlotModRef(MachineInstr &MI, int SS, unsigned PhysReg,
-                                 const TargetInstrInfo *TII,
-                                 const TargetRegisterInfo *TRI,
-                                 VirtRegMap &VRM) {
-  if (VRM.hasEmergencySpills(&MI) || VRM.isSpillPt(&MI))
-    return false;
-
-  bool Found = false;
-  VirtRegMap::MI2VirtMapTy::const_iterator I, End;
-  for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
-    unsigned VirtReg = I->second.first;
-    VirtRegMap::ModRef MR = I->second.second;
-    if (MR & VirtRegMap::isModRef)
-      if (VRM.getStackSlot(VirtReg) == SS) {
-        Found= TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(), true, true) != 0;
-        break;
-      }
-  }
-  if (!Found)
-    return false;
-
-  // Does the instruction uses a register that overlaps the scratch register?
-  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
-    MachineOperand &MO = MI.getOperand(i);
-    if (!MO.isReg() || MO.getReg() == 0)
-      continue;
-    unsigned Reg = MO.getReg();
-    if (TargetRegisterInfo::isVirtualRegister(Reg)) {
-      if (!VRM.hasPhys(Reg))
-        continue;
-      Reg = VRM.getPhys(Reg);
-    }
-    if (TRI->regsOverlap(PhysReg, Reg))
-      return false;
-  }
-  return true;
-}
-
-/// FindFreeRegister - Find a free register of a given register class by looking
-/// at (at most) the last two machine instructions.
-static unsigned FindFreeRegister(MachineBasicBlock::iterator MII,
-                                 MachineBasicBlock &MBB,
-                                 const TargetRegisterClass *RC,
-                                 const TargetRegisterInfo *TRI,
-                                 BitVector &AllocatableRegs) {
-  BitVector Defs(TRI->getNumRegs());
-  BitVector Uses(TRI->getNumRegs());
-  SmallVector<unsigned, 4> LocalUses;
-  SmallVector<unsigned, 4> Kills;
-
-  // Take a look at 2 instructions at most.
-  unsigned Count = 0;
-  while (Count < 2) {
-    if (MII == MBB.begin())
-      break;
-    MachineInstr *PrevMI = prior(MII);
-    MII = PrevMI;
-
-    if (PrevMI->isDebugValue())
-      continue; // Skip over dbg_value instructions.
-    ++Count;
-
-    for (unsigned i = 0, e = PrevMI->getNumOperands(); i != e; ++i) {
-      MachineOperand &MO = PrevMI->getOperand(i);
-      if (!MO.isReg() || MO.getReg() == 0)
-        continue;
-      unsigned Reg = MO.getReg();
-      if (MO.isDef()) {
-        Defs.set(Reg);
-        for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
-          Defs.set(*AS);
-      } else  {
-        LocalUses.push_back(Reg);
-        if (MO.isKill() && AllocatableRegs[Reg])
-          Kills.push_back(Reg);
-      }
-    }
-
-    for (unsigned i = 0, e = Kills.size(); i != e; ++i) {
-      unsigned Kill = Kills[i];
-      if (!Defs[Kill] && !Uses[Kill] &&
-          RC->contains(Kill))
-        return Kill;
-    }
-    for (unsigned i = 0, e = LocalUses.size(); i != e; ++i) {
-      unsigned Reg = LocalUses[i];
-      Uses.set(Reg);
-      for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
-        Uses.set(*AS);
-    }
-  }
-
-  return 0;
-}
-
-static
-void AssignPhysToVirtReg(MachineInstr *MI, unsigned VirtReg, unsigned PhysReg,
-                         const TargetRegisterInfo &TRI) {
-  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
-    MachineOperand &MO = MI->getOperand(i);
-    if (MO.isReg() && MO.getReg() == VirtReg)
-      substitutePhysReg(MO, PhysReg, TRI);
-  }
-}
-
-namespace {
-
-struct RefSorter {
-  bool operator()(const std::pair<MachineInstr*, int> &A,
-                  const std::pair<MachineInstr*, int> &B) {
-    return A.second < B.second;
-  }
-};
-
-// ***************************** //
-// Local Spiller Implementation  //
-// ***************************** //
-
-class LocalRewriter : public VirtRegRewriter {
-  MachineRegisterInfo *MRI;
-  const TargetRegisterInfo *TRI;
-  const TargetInstrInfo *TII;
-  VirtRegMap *VRM;
-  LiveIntervals *LIs;
-  BitVector AllocatableRegs;
-  DenseMap<MachineInstr*, unsigned> DistanceMap;
-  DenseMap<int, SmallVector<MachineInstr*,4> > Slot2DbgValues;
-
-  MachineBasicBlock *MBB;       // Basic block currently being processed.
-
-public:
-
-  bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM,
-                            LiveIntervals* LIs);
-
-private:
-  void EraseInstr(MachineInstr *MI) {
-    VRM->RemoveMachineInstrFromMaps(MI);
-    LIs->RemoveMachineInstrFromMaps(MI);
-    MI->eraseFromParent();
-  }
-
-  bool OptimizeByUnfold2(unsigned VirtReg, int SS,
-                         MachineBasicBlock::iterator &MII,
-                         std::vector<MachineInstr*> &MaybeDeadStores,
-                         AvailableSpills &Spills,
-                         BitVector &RegKills,
-                         std::vector<MachineOperand*> &KillOps);
-
-  bool OptimizeByUnfold(MachineBasicBlock::iterator &MII,
-                        std::vector<MachineInstr*> &MaybeDeadStores,
-                        AvailableSpills &Spills,
-                        BitVector &RegKills,
-                        std::vector<MachineOperand*> &KillOps);
-
-  bool CommuteToFoldReload(MachineBasicBlock::iterator &MII,
-                           unsigned VirtReg, unsigned SrcReg, int SS,
-                           AvailableSpills &Spills,
-                           BitVector &RegKills,
-                           std::vector<MachineOperand*> &KillOps,
-                           const TargetRegisterInfo *TRI);
-
-  void SpillRegToStackSlot(MachineBasicBlock::iterator &MII,
-                           int Idx, unsigned PhysReg, int StackSlot,
-                           const TargetRegisterClass *RC,
-                           bool isAvailable, MachineInstr *&LastStore,
-                           AvailableSpills &Spills,
-                           SmallSet<MachineInstr*, 4> &ReMatDefs,
-                           BitVector &RegKills,
-                           std::vector<MachineOperand*> &KillOps);
-
-  void TransferDeadness(unsigned Reg, BitVector &RegKills,
-                        std::vector<MachineOperand*> &KillOps);
-
-  bool InsertEmergencySpills(MachineInstr *MI);
-
-  bool InsertRestores(MachineInstr *MI,
-                      AvailableSpills &Spills,
-                      BitVector &RegKills,
-                      std::vector<MachineOperand*> &KillOps);
-
-  bool InsertSpills(MachineInstr *MI);
-
-  void ProcessUses(MachineInstr &MI, AvailableSpills &Spills,
-                   std::vector<MachineInstr*> &MaybeDeadStores,
-                   BitVector &RegKills,
-                   ReuseInfo &ReusedOperands,
-                   std::vector<MachineOperand*> &KillOps);
-
-  void RewriteMBB(LiveIntervals *LIs,
-                  AvailableSpills &Spills, BitVector &RegKills,
-                  std::vector<MachineOperand*> &KillOps);
-};
-}
-
-bool LocalRewriter::runOnMachineFunction(MachineFunction &MF, VirtRegMap &vrm,
-                                         LiveIntervals* lis) {
-  MRI = &MF.getRegInfo();
-  TRI = MF.getTarget().getRegisterInfo();
-  TII = MF.getTarget().getInstrInfo();
-  VRM = &vrm;
-  LIs = lis;
-  AllocatableRegs = TRI->getAllocatableSet(MF);
-  DEBUG(dbgs() << "\n**** Local spiller rewriting function '"
-        << MF.getFunction()->getName() << "':\n");
-  DEBUG(dbgs() << "**** Machine Instrs (NOTE! Does not include spills and"
-        " reloads!) ****\n");
-  DEBUG(MF.print(dbgs(), LIs->getSlotIndexes()));
-
-  // Spills - Keep track of which spilled values are available in physregs
-  // so that we can choose to reuse the physregs instead of emitting
-  // reloads. This is usually refreshed per basic block.
-  AvailableSpills Spills(TRI, TII);
-
-  // Keep track of kill information.
-  BitVector RegKills(TRI->getNumRegs());
-  std::vector<MachineOperand*> KillOps;
-  KillOps.resize(TRI->getNumRegs(), NULL);
-
-  // SingleEntrySuccs - Successor blocks which have a single predecessor.
-  SmallVector<MachineBasicBlock*, 4> SinglePredSuccs;
-  SmallPtrSet<MachineBasicBlock*,16> EarlyVisited;
-
-  // Traverse the basic blocks depth first.
-  MachineBasicBlock *Entry = MF.begin();
-  SmallPtrSet<MachineBasicBlock*,16> Visited;
-  for (df_ext_iterator<MachineBasicBlock*,
-         SmallPtrSet<MachineBasicBlock*,16> >
-         DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
-       DFI != E; ++DFI) {
-    MBB = *DFI;
-    if (!EarlyVisited.count(MBB))
-      RewriteMBB(LIs, Spills, RegKills, KillOps);
-
-    // If this MBB is the only predecessor of a successor. Keep the
-    // availability information and visit it next.
-    do {
-      // Keep visiting single predecessor successor as long as possible.
-      SinglePredSuccs.clear();
-      findSinglePredSuccessor(MBB, SinglePredSuccs);
-      if (SinglePredSuccs.empty())
-        MBB = 0;
-      else {
-        // FIXME: More than one successors, each of which has MBB has
-        // the only predecessor.
-        MBB = SinglePredSuccs[0];
-        if (!Visited.count(MBB) && EarlyVisited.insert(MBB)) {
-          Spills.AddAvailableRegsToLiveIn(*MBB, RegKills, KillOps);
-          RewriteMBB(LIs, Spills, RegKills, KillOps);
-        }
-      }
-    } while (MBB);
-
-    // Clear the availability info.
-    Spills.clear();
-  }
-
-  DEBUG(dbgs() << "**** Post Machine Instrs ****\n");
-  DEBUG(MF.print(dbgs(), LIs->getSlotIndexes()));
-
-  // Mark unused spill slots.
-  MachineFrameInfo *MFI = MF.getFrameInfo();
-  int SS = VRM->getLowSpillSlot();
-  if (SS != VirtRegMap::NO_STACK_SLOT) {
-    for (int e = VRM->getHighSpillSlot(); SS <= e; ++SS) {
-      SmallVector<MachineInstr*, 4> &DbgValues = Slot2DbgValues[SS];
-      if (!VRM->isSpillSlotUsed(SS)) {
-        MFI->RemoveStackObject(SS);
-        for (unsigned j = 0, ee = DbgValues.size(); j != ee; ++j) {
-          MachineInstr *DVMI = DbgValues[j];
-          DEBUG(dbgs() << "Removing debug info referencing FI#" << SS << '\n');
-          EraseInstr(DVMI);
-        }
-        ++NumDSS;
-      }
-      DbgValues.clear();
-    }
-  }
-  Slot2DbgValues.clear();
-
-  return true;
-}
-
-/// OptimizeByUnfold2 - Unfold a series of load / store folding instructions if
-/// a scratch register is available.
-///     xorq  %r12<kill>, %r13
-///     addq  %rax, -184(%rbp)
-///     addq  %r13, -184(%rbp)
-/// ==>
-///     xorq  %r12<kill>, %r13
-///     movq  -184(%rbp), %r12
-///     addq  %rax, %r12
-///     addq  %r13, %r12
-///     movq  %r12, -184(%rbp)
-bool LocalRewriter::
-OptimizeByUnfold2(unsigned VirtReg, int SS,
-                  MachineBasicBlock::iterator &MII,
-                  std::vector<MachineInstr*> &MaybeDeadStores,
-                  AvailableSpills &Spills,
-                  BitVector &RegKills,
-                  std::vector<MachineOperand*> &KillOps) {
-
-  MachineBasicBlock::iterator NextMII = llvm::next(MII);
-  // Skip over dbg_value instructions.
-  while (NextMII != MBB->end() && NextMII->isDebugValue())
-    NextMII = llvm::next(NextMII);
-  if (NextMII == MBB->end())
-    return false;
-
-  if (TII->getOpcodeAfterMemoryUnfold(MII->getOpcode(), true, true) == 0)
-    return false;
-
-  // Now let's see if the last couple of instructions happens to have freed up
-  // a register.
-  const TargetRegisterClass* RC = MRI->getRegClass(VirtReg);
-  unsigned PhysReg = FindFreeRegister(MII, *MBB, RC, TRI, AllocatableRegs);
-  if (!PhysReg)
-    return false;
-
-  MachineFunction &MF = *MBB->getParent();
-  TRI = MF.getTarget().getRegisterInfo();
-  MachineInstr &MI = *MII;
-  if (!FoldsStackSlotModRef(MI, SS, PhysReg, TII, TRI, *VRM))
-    return false;
-
-  // If the next instruction also folds the same SS modref and can be unfoled,
-  // then it's worthwhile to issue a load from SS into the free register and
-  // then unfold these instructions.
-  if (!FoldsStackSlotModRef(*NextMII, SS, PhysReg, TII, TRI, *VRM))
-    return false;
-
-  // Back-schedule reloads and remats.
-  ComputeReloadLoc(MII, MBB->begin(), PhysReg, TRI, false, SS, TII, MF);
-
-  // Load from SS to the spare physical register.
-  TII->loadRegFromStackSlot(*MBB, MII, PhysReg, SS, RC, TRI);
-  // This invalidates Phys.
-  Spills.ClobberPhysReg(PhysReg);
-  // Remember it's available.
-  Spills.addAvailable(SS, PhysReg);
-  MaybeDeadStores[SS] = NULL;
-
-  // Unfold current MI.
-  SmallVector<MachineInstr*, 4> NewMIs;
-  if (!TII->unfoldMemoryOperand(MF, &MI, VirtReg, false, false, NewMIs))
-    llvm_unreachable("Unable unfold the load / store folding instruction!");
-  assert(NewMIs.size() == 1);
-  AssignPhysToVirtReg(NewMIs[0], VirtReg, PhysReg, *TRI);
-  VRM->transferRestorePts(&MI, NewMIs[0]);
-  MII = MBB->insert(MII, NewMIs[0]);
-  InvalidateKills(MI, TRI, RegKills, KillOps);
-  EraseInstr(&MI);
-  ++NumModRefUnfold;
-
-  // Unfold next instructions that fold the same SS.
-  do {
-    MachineInstr &NextMI = *NextMII;
-    NextMII = llvm::next(NextMII);
-    NewMIs.clear();
-    if (!TII->unfoldMemoryOperand(MF, &NextMI, VirtReg, false, false, NewMIs))
-      llvm_unreachable("Unable unfold the load / store folding instruction!");
-    assert(NewMIs.size() == 1);
-    AssignPhysToVirtReg(NewMIs[0], VirtReg, PhysReg, *TRI);
-    VRM->transferRestorePts(&NextMI, NewMIs[0]);
-    MBB->insert(NextMII, NewMIs[0]);
-    InvalidateKills(NextMI, TRI, RegKills, KillOps);
-    EraseInstr(&NextMI);
-    ++NumModRefUnfold;
-    // Skip over dbg_value instructions.
-    while (NextMII != MBB->end() && NextMII->isDebugValue())
-      NextMII = llvm::next(NextMII);
-    if (NextMII == MBB->end())
-      break;
-  } while (FoldsStackSlotModRef(*NextMII, SS, PhysReg, TII, TRI, *VRM));
-
-  // Store the value back into SS.
-  TII->storeRegToStackSlot(*MBB, NextMII, PhysReg, true, SS, RC, TRI);
-  MachineInstr *StoreMI = prior(NextMII);
-  VRM->addSpillSlotUse(SS, StoreMI);
-  VRM->virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
-
-  return true;
-}
-
-/// OptimizeByUnfold - Turn a store folding instruction into a load folding
-/// instruction. e.g.
-///     xorl  %edi, %eax
-///     movl  %eax, -32(%ebp)
-///     movl  -36(%ebp), %eax
-///     orl   %eax, -32(%ebp)
-/// ==>
-///     xorl  %edi, %eax
-///     orl   -36(%ebp), %eax
-///     mov   %eax, -32(%ebp)
-/// This enables unfolding optimization for a subsequent instruction which will
-/// also eliminate the newly introduced store instruction.
-bool LocalRewriter::
-OptimizeByUnfold(MachineBasicBlock::iterator &MII,
-                 std::vector<MachineInstr*> &MaybeDeadStores,
-                 AvailableSpills &Spills,
-                 BitVector &RegKills,
-                 std::vector<MachineOperand*> &KillOps) {
-  MachineFunction &MF = *MBB->getParent();
-  MachineInstr &MI = *MII;
-  unsigned UnfoldedOpc = 0;
-  unsigned UnfoldPR = 0;
-  unsigned UnfoldVR = 0;
-  int FoldedSS = VirtRegMap::NO_STACK_SLOT;
-  VirtRegMap::MI2VirtMapTy::const_iterator I, End;
-  for (tie(I, End) = VRM->getFoldedVirts(&MI); I != End; ) {
-    // Only transform a MI that folds a single register.
-    if (UnfoldedOpc)
-      return false;
-    UnfoldVR = I->second.first;
-    VirtRegMap::ModRef MR = I->second.second;
-    // MI2VirtMap be can updated which invalidate the iterator.
-    // Increment the iterator first.
-    ++I;
-    if (VRM->isAssignedReg(UnfoldVR))
-      continue;
-    // If this reference is not a use, any previous store is now dead.
-    // Otherwise, the store to this stack slot is not dead anymore.
-    FoldedSS = VRM->getStackSlot(UnfoldVR);
-    MachineInstr* DeadStore = MaybeDeadStores[FoldedSS];
-    if (DeadStore && (MR & VirtRegMap::isModRef)) {
-      unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(FoldedSS);
-      if (!PhysReg || !DeadStore->readsRegister(PhysReg))
-        continue;
-      UnfoldPR = PhysReg;
-      UnfoldedOpc = TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
-                                                    false, true);
-    }
-  }
-
-  if (!UnfoldedOpc) {
-    if (!UnfoldVR)
-      return false;
-
-    // Look for other unfolding opportunities.
-    return OptimizeByUnfold2(UnfoldVR, FoldedSS, MII, MaybeDeadStores, Spills,
-                             RegKills, KillOps);
-  }
-
-  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
-    MachineOperand &MO = MI.getOperand(i);
-    if (!MO.isReg() || MO.getReg() == 0 || !MO.isUse())
-      continue;
-    unsigned VirtReg = MO.getReg();
-    if (TargetRegisterInfo::isPhysicalRegister(VirtReg) || MO.getSubReg())
-      continue;
-    if (VRM->isAssignedReg(VirtReg)) {
-      unsigned PhysReg = VRM->getPhys(VirtReg);
-      if (PhysReg && TRI->regsOverlap(PhysReg, UnfoldPR))
-        return false;
-    } else if (VRM->isReMaterialized(VirtReg))
-      continue;
-    int SS = VRM->getStackSlot(VirtReg);
-    unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
-    if (PhysReg) {
-      if (TRI->regsOverlap(PhysReg, UnfoldPR))
-        return false;
-      continue;
-    }
-    if (VRM->hasPhys(VirtReg)) {
-      PhysReg = VRM->getPhys(VirtReg);
-      if (!TRI->regsOverlap(PhysReg, UnfoldPR))
-        continue;
-    }
-
-    // Ok, we'll need to reload the value into a register which makes
-    // it impossible to perform the store unfolding optimization later.
-    // Let's see if it is possible to fold the load if the store is
-    // unfolded. This allows us to perform the store unfolding
-    // optimization.
-    SmallVector<MachineInstr*, 4> NewMIs;
-    if (TII->unfoldMemoryOperand(MF, &MI, UnfoldVR, false, false, NewMIs)) {
-      assert(NewMIs.size() == 1);
-      MachineInstr *NewMI = NewMIs.back();
-      MBB->insert(MII, NewMI);
-      NewMIs.clear();
-      int Idx = NewMI->findRegisterUseOperandIdx(VirtReg, false);
-      assert(Idx != -1);
-      SmallVector<unsigned, 1> Ops;
-      Ops.push_back(Idx);
-      MachineInstr *FoldedMI = TII->foldMemoryOperand(NewMI, Ops, SS);
-      NewMI->eraseFromParent();
-      if (FoldedMI) {
-        VRM->addSpillSlotUse(SS, FoldedMI);
-        if (!VRM->hasPhys(UnfoldVR))
-          VRM->assignVirt2Phys(UnfoldVR, UnfoldPR);
-        VRM->virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef);
-        MII = FoldedMI;
-        InvalidateKills(MI, TRI, RegKills, KillOps);
-        EraseInstr(&MI);
-        return true;
-      }
-    }
-  }
-
-  return false;
-}
-
-/// CommuteChangesDestination - We are looking for r0 = op r1, r2 and
-/// where SrcReg is r1 and it is tied to r0. Return true if after
-/// commuting this instruction it will be r0 = op r2, r1.
-static bool CommuteChangesDestination(MachineInstr *DefMI,
-                                      const MCInstrDesc &MCID,
-                                      unsigned SrcReg,
-                                      const TargetInstrInfo *TII,
-                                      unsigned &DstIdx) {
-  if (MCID.getNumDefs() != 1 && MCID.getNumOperands() != 3)
-    return false;
-  if (!DefMI->getOperand(1).isReg() ||
-      DefMI->getOperand(1).getReg() != SrcReg)
-    return false;
-  unsigned DefIdx;
-  if (!DefMI->isRegTiedToDefOperand(1, &DefIdx) || DefIdx != 0)
-    return false;
-  unsigned SrcIdx1, SrcIdx2;
-  if (!TII->findCommutedOpIndices(DefMI, SrcIdx1, SrcIdx2))
-    return false;
-  if (SrcIdx1 == 1 && SrcIdx2 == 2) {
-    DstIdx = 2;
-    return true;
-  }
-  return false;
-}
-
-/// CommuteToFoldReload -
-/// Look for
-/// r1 = load fi#1
-/// r1 = op r1, r2<kill>
-/// store r1, fi#1
-///
-/// If op is commutable and r2 is killed, then we can xform these to
-/// r2 = op r2, fi#1
-/// store r2, fi#1
-bool LocalRewriter::
-CommuteToFoldReload(MachineBasicBlock::iterator &MII,
-                    unsigned VirtReg, unsigned SrcReg, int SS,
-                    AvailableSpills &Spills,
-                    BitVector &RegKills,
-                    std::vector<MachineOperand*> &KillOps,
-                    const TargetRegisterInfo *TRI) {
-  if (MII == MBB->begin() || !MII->killsRegister(SrcReg))
-    return false;
-
-  MachineInstr &MI = *MII;
-  MachineBasicBlock::iterator DefMII = prior(MII);
-  MachineInstr *DefMI = DefMII;
-  const MCInstrDesc &MCID = DefMI->getDesc();
-  unsigned NewDstIdx;
-  if (DefMII != MBB->begin() &&
-      MCID.isCommutable() &&
-      CommuteChangesDestination(DefMI, MCID, SrcReg, TII, NewDstIdx)) {
-    MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
-    unsigned NewReg = NewDstMO.getReg();
-    if (!NewDstMO.isKill() || TRI->regsOverlap(NewReg, SrcReg))
-      return false;
-    MachineInstr *ReloadMI = prior(DefMII);
-    int FrameIdx;
-    unsigned DestReg = TII->isLoadFromStackSlot(ReloadMI, FrameIdx);
-    if (DestReg != SrcReg || FrameIdx != SS)
-      return false;
-    int UseIdx = DefMI->findRegisterUseOperandIdx(DestReg, false);
-    if (UseIdx == -1)
-      return false;
-    unsigned DefIdx;
-    if (!MI.isRegTiedToDefOperand(UseIdx, &DefIdx))
-      return false;
-    assert(DefMI->getOperand(DefIdx).isReg() &&
-           DefMI->getOperand(DefIdx).getReg() == SrcReg);
-
-    // Now commute def instruction.
-    MachineInstr *CommutedMI = TII->commuteInstruction(DefMI, true);
-    if (!CommutedMI)
-      return false;
-    MBB->insert(MII, CommutedMI);
-    SmallVector<unsigned, 1> Ops;
-    Ops.push_back(NewDstIdx);
-    MachineInstr *FoldedMI = TII->foldMemoryOperand(CommutedMI, Ops, SS);
-    // Not needed since foldMemoryOperand returns new MI.
-    CommutedMI->eraseFromParent();
-    if (!FoldedMI)
-      return false;
-
-    VRM->addSpillSlotUse(SS, FoldedMI);
-    VRM->virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef);
-    // Insert new def MI and spill MI.
-    const TargetRegisterClass* RC = MRI->getRegClass(VirtReg);
-    TII->storeRegToStackSlot(*MBB, &MI, NewReg, true, SS, RC, TRI);
-    MII = prior(MII);
-    MachineInstr *StoreMI = MII;
-    VRM->addSpillSlotUse(SS, StoreMI);
-    VRM->virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
-    MII = FoldedMI;  // Update MII to backtrack.
-
-    // Delete all 3 old instructions.
-    InvalidateKills(*ReloadMI, TRI, RegKills, KillOps);
-    EraseInstr(ReloadMI);
-    InvalidateKills(*DefMI, TRI, RegKills, KillOps);
-    EraseInstr(DefMI);
-    InvalidateKills(MI, TRI, RegKills, KillOps);
-    EraseInstr(&MI);
-
-    // If NewReg was previously holding value of some SS, it's now clobbered.
-    // This has to be done now because it's a physical register. When this
-    // instruction is re-visited, it's ignored.
-    Spills.ClobberPhysReg(NewReg);
-
-    ++NumCommutes;
-    return true;
-  }
-
-  return false;
-}
-
-/// SpillRegToStackSlot - Spill a register to a specified stack slot. Check if
-/// the last store to the same slot is now dead. If so, remove the last store.
-void LocalRewriter::
-SpillRegToStackSlot(MachineBasicBlock::iterator &MII,
-                    int Idx, unsigned PhysReg, int StackSlot,
-                    const TargetRegisterClass *RC,
-                    bool isAvailable, MachineInstr *&LastStore,
-                    AvailableSpills &Spills,
-                    SmallSet<MachineInstr*, 4> &ReMatDefs,
-                    BitVector &RegKills,
-                    std::vector<MachineOperand*> &KillOps) {
-
-  MachineBasicBlock::iterator oldNextMII = llvm::next(MII);
-  TII->storeRegToStackSlot(*MBB, llvm::next(MII), PhysReg, true, StackSlot, RC,
-                           TRI);
-  MachineInstr *StoreMI = prior(oldNextMII);
-  VRM->addSpillSlotUse(StackSlot, StoreMI);
-  DEBUG(dbgs() << "Store:\t" << *StoreMI);
-
-  // If there is a dead store to this stack slot, nuke it now.
-  if (LastStore) {
-    DEBUG(dbgs() << "Removed dead store:\t" << *LastStore);
-    ++NumDSE;
-    SmallVector<unsigned, 2> KillRegs;
-    InvalidateKills(*LastStore, TRI, RegKills, KillOps, &KillRegs);
-    MachineBasicBlock::iterator PrevMII = LastStore;
-    bool CheckDef = PrevMII != MBB->begin();
-    if (CheckDef)
-      --PrevMII;
-    EraseInstr(LastStore);
-    if (CheckDef) {
-      // Look at defs of killed registers on the store. Mark the defs
-      // as dead since the store has been deleted and they aren't
-      // being reused.
-      for (unsigned j = 0, ee = KillRegs.size(); j != ee; ++j) {
-        bool HasOtherDef = false;
-        if (InvalidateRegDef(PrevMII, *MII, KillRegs[j], HasOtherDef, TRI)) {
-          MachineInstr *DeadDef = PrevMII;
-          if (ReMatDefs.count(DeadDef) && !HasOtherDef) {
-            // FIXME: This assumes a remat def does not have side effects.
-            EraseInstr(DeadDef);
-            ++NumDRM;
-          }
-        }
-      }
-    }
-  }
-
-  // Allow for multi-instruction spill sequences, as on PPC Altivec.  Presume
-  // the last of multiple instructions is the actual store.
-  LastStore = prior(oldNextMII);
-
-  // If the stack slot value was previously available in some other
-  // register, change it now.  Otherwise, make the register available,
-  // in PhysReg.
-  Spills.ModifyStackSlotOrReMat(StackSlot);
-  Spills.ClobberPhysReg(PhysReg);
-  Spills.addAvailable(StackSlot, PhysReg, isAvailable);
-  ++NumStores;
-}
-
-/// isSafeToDelete - Return true if this instruction doesn't produce any side
-/// effect and all of its defs are dead.
-static bool isSafeToDelete(MachineInstr &MI) {
-  const MCInstrDesc &MCID = MI.getDesc();
-  if (MCID.mayLoad() || MCID.mayStore() || MCID.isTerminator() ||
-      MCID.isCall() || MCID.isBarrier() || MCID.isReturn() ||
-      MI.isLabel() || MI.isDebugValue() ||
-      MI.hasUnmodeledSideEffects())
-    return false;
-
-  // Technically speaking inline asm without side effects and no defs can still
-  // be deleted. But there is so much bad inline asm code out there, we should
-  // let them be.
-  if (MI.isInlineAsm())
-    return false;
-
-  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
-    MachineOperand &MO = MI.getOperand(i);
-    if (!MO.isReg() || !MO.getReg())
-      continue;
-    if (MO.isDef() && !MO.isDead())
-      return false;
-    if (MO.isUse() && MO.isKill())
-      // FIXME: We can't remove kill markers or else the scavenger will assert.
-      // An alternative is to add a ADD pseudo instruction to replace kill
-      // markers.
-      return false;
-  }
-  return true;
-}
-
-/// TransferDeadness - A identity copy definition is dead and it's being
-/// removed. Find the last def or use and mark it as dead / kill.
-void LocalRewriter::
-TransferDeadness(unsigned Reg, BitVector &RegKills,
-                 std::vector<MachineOperand*> &KillOps) {
-  SmallPtrSet<MachineInstr*, 4> Seens;
-  SmallVector<std::pair<MachineInstr*, int>,8> Refs;
-  for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(Reg),
-         RE = MRI->reg_end(); RI != RE; ++RI) {
-    MachineInstr *UDMI = &*RI;
-    if (UDMI->isDebugValue() || UDMI->getParent() != MBB)
-      continue;
-    DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UDMI);
-    if (DI == DistanceMap.end())
-      continue;
-    if (Seens.insert(UDMI))
-      Refs.push_back(std::make_pair(UDMI, DI->second));
-  }
-
-  if (Refs.empty())
-    return;
-  std::sort(Refs.begin(), Refs.end(), RefSorter());
-
-  while (!Refs.empty()) {
-    MachineInstr *LastUDMI = Refs.back().first;
-    Refs.pop_back();
-
-    MachineOperand *LastUD = NULL;
-    for (unsigned i = 0, e = LastUDMI->getNumOperands(); i != e; ++i) {
-      MachineOperand &MO = LastUDMI->getOperand(i);
-      if (!MO.isReg() || MO.getReg() != Reg)
-        continue;
-      if (!LastUD || (LastUD->isUse() && MO.isDef()))
-        LastUD = &MO;
-      if (LastUDMI->isRegTiedToDefOperand(i))
-        break;
-    }
-    if (LastUD->isDef()) {
-      // If the instruction has no side effect, delete it and propagate
-      // backward further. Otherwise, mark is dead and we are done.
-      if (!isSafeToDelete(*LastUDMI)) {
-        LastUD->setIsDead();
-        break;
-      }
-      EraseInstr(LastUDMI);
-    } else {
-      LastUD->setIsKill();
-      RegKills.set(Reg);
-      KillOps[Reg] = LastUD;
-      break;
-    }
-  }
-}
-
-/// InsertEmergencySpills - Insert emergency spills before MI if requested by
-/// VRM. Return true if spills were inserted.
-bool LocalRewriter::InsertEmergencySpills(MachineInstr *MI) {
-  if (!VRM->hasEmergencySpills(MI))
-    return false;
-  MachineBasicBlock::iterator MII = MI;
-  SmallSet<int, 4> UsedSS;
-  std::vector<unsigned> &EmSpills = VRM->getEmergencySpills(MI);
-  for (unsigned i = 0, e = EmSpills.size(); i != e; ++i) {
-    unsigned PhysReg = EmSpills[i];
-    const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysReg);
-    assert(RC && "Unable to determine register class!");
-    int SS = VRM->getEmergencySpillSlot(RC);
-    if (UsedSS.count(SS))
-      llvm_unreachable("Need to spill more than one physical registers!");
-    UsedSS.insert(SS);
-    TII->storeRegToStackSlot(*MBB, MII, PhysReg, true, SS, RC, TRI);
-    MachineInstr *StoreMI = prior(MII);
-    VRM->addSpillSlotUse(SS, StoreMI);
-
-    // Back-schedule reloads and remats.
-    MachineBasicBlock::iterator InsertLoc =
-      ComputeReloadLoc(llvm::next(MII), MBB->begin(), PhysReg, TRI, false, SS,
-                       TII, *MBB->getParent());
-
-    TII->loadRegFromStackSlot(*MBB, InsertLoc, PhysReg, SS, RC, TRI);
-
-    MachineInstr *LoadMI = prior(InsertLoc);
-    VRM->addSpillSlotUse(SS, LoadMI);
-    ++NumPSpills;
-    DistanceMap.insert(std::make_pair(LoadMI, DistanceMap.size()));
-  }
-  return true;
-}
-
-/// InsertRestores - Restore registers before MI is requested by VRM. Return
-/// true is any instructions were inserted.
-bool LocalRewriter::InsertRestores(MachineInstr *MI,
-                                   AvailableSpills &Spills,
-                                   BitVector &RegKills,
-                                   std::vector<MachineOperand*> &KillOps) {
-  if (!VRM->isRestorePt(MI))
-    return false;
-  MachineBasicBlock::iterator MII = MI;
-  std::vector<unsigned> &RestoreRegs = VRM->getRestorePtRestores(MI);
-  for (unsigned i = 0, e = RestoreRegs.size(); i != e; ++i) {
-    unsigned VirtReg = RestoreRegs[e-i-1];  // Reverse order.
-    if (!VRM->getPreSplitReg(VirtReg))
-      continue; // Split interval spilled again.
-    unsigned Phys = VRM->getPhys(VirtReg);
-    MRI->setPhysRegUsed(Phys);
-
-    // Check if the value being restored if available. If so, it must be
-    // from a predecessor BB that fallthrough into this BB. We do not
-    // expect:
-    // BB1:
-    // r1 = load fi#1
-    // ...
-    //    = r1<kill>
-    // ... # r1 not clobbered
-    // ...
-    //    = load fi#1
-    bool DoReMat = VRM->isReMaterialized(VirtReg);
-    int SSorRMId = DoReMat
-      ? VRM->getReMatId(VirtReg) : VRM->getStackSlot(VirtReg);
-    unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId);
-    if (InReg == Phys) {
-      // If the value is already available in the expected register, save
-      // a reload / remat.
-      if (SSorRMId)
-        DEBUG(dbgs() << "Reusing RM#"
-                     << SSorRMId-VirtRegMap::MAX_STACK_SLOT-1);
-      else
-        DEBUG(dbgs() << "Reusing SS#" << SSorRMId);
-      DEBUG(dbgs() << " from physreg "
-                   << TRI->getName(InReg) << " for " << PrintReg(VirtReg)
-                   <<" instead of reloading into physreg "
-                   << TRI->getName(Phys) << '\n');
-
-      // Reusing a physreg may resurrect it. But we expect ProcessUses to update
-      // the kill flags for the current instruction after processing it.
-
-      ++NumOmitted;
-      continue;
-    } else if (InReg && InReg != Phys) {
-      if (SSorRMId)
-        DEBUG(dbgs() << "Reusing RM#"
-                     << SSorRMId-VirtRegMap::MAX_STACK_SLOT-1);
-      else
-        DEBUG(dbgs() << "Reusing SS#" << SSorRMId);
-      DEBUG(dbgs() << " from physreg "
-                   << TRI->getName(InReg) << " for " << PrintReg(VirtReg)
-                   <<" by copying it into physreg "
-                   << TRI->getName(Phys) << '\n');
-
-      // If the reloaded / remat value is available in another register,
-      // copy it to the desired register.
-
-      // Back-schedule reloads and remats.
-      MachineBasicBlock::iterator InsertLoc =
-        ComputeReloadLoc(MII, MBB->begin(), Phys, TRI, DoReMat, SSorRMId, TII,
-                         *MBB->getParent());
-      MachineInstr *CopyMI = BuildMI(*MBB, InsertLoc, MI->getDebugLoc(),
-                                     TII->get(TargetOpcode::COPY), Phys)
-                               .addReg(InReg, RegState::Kill);
-
-      // This invalidates Phys.
-      Spills.ClobberPhysReg(Phys);
-      // Remember it's available.
-      Spills.addAvailable(SSorRMId, Phys);
-
-      CopyMI->setAsmPrinterFlag(MachineInstr::ReloadReuse);
-      UpdateKills(*CopyMI, TRI, RegKills, KillOps);
-
-      DEBUG(dbgs() << '\t' << *CopyMI);
-      ++NumCopified;
-      continue;
-    }
-
-    // Back-schedule reloads and remats.
-    MachineBasicBlock::iterator InsertLoc =
-      ComputeReloadLoc(MII, MBB->begin(), Phys, TRI, DoReMat, SSorRMId, TII,
-                       *MBB->getParent());
-
-    if (VRM->isReMaterialized(VirtReg)) {
-      ReMaterialize(*MBB, InsertLoc, Phys, VirtReg, TII, TRI, *VRM);
-    } else {
-      const TargetRegisterClass* RC = MRI->getRegClass(VirtReg);
-      TII->loadRegFromStackSlot(*MBB, InsertLoc, Phys, SSorRMId, RC, TRI);
-      MachineInstr *LoadMI = prior(InsertLoc);
-      VRM->addSpillSlotUse(SSorRMId, LoadMI);
-      ++NumLoads;
-      DistanceMap.insert(std::make_pair(LoadMI, DistanceMap.size()));
-    }
-
-    // This invalidates Phys.
-    Spills.ClobberPhysReg(Phys);
-    // Remember it's available.
-    Spills.addAvailable(SSorRMId, Phys);
-
-    UpdateKills(*prior(InsertLoc), TRI, RegKills, KillOps);
-    DEBUG(dbgs() << '\t' << *prior(MII));
-  }
-  return true;
-}
-
-/// InsertSpills - Insert spills after MI if requested by VRM. Return
-/// true if spills were inserted.
-bool LocalRewriter::InsertSpills(MachineInstr *MI) {
-  if (!VRM->isSpillPt(MI))
-    return false;
-  MachineBasicBlock::iterator MII = MI;
-  std::vector<std::pair<unsigned,bool> > &SpillRegs =
-    VRM->getSpillPtSpills(MI);
-  for (unsigned i = 0, e = SpillRegs.size(); i != e; ++i) {
-    unsigned VirtReg = SpillRegs[i].first;
-    bool isKill = SpillRegs[i].second;
-    if (!VRM->getPreSplitReg(VirtReg))
-      continue; // Split interval spilled again.
-    const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
-    unsigned Phys = VRM->getPhys(VirtReg);
-    int StackSlot = VRM->getStackSlot(VirtReg);
-    MachineBasicBlock::iterator oldNextMII = llvm::next(MII);
-    TII->storeRegToStackSlot(*MBB, llvm::next(MII), Phys, isKill, StackSlot,
-                             RC, TRI);
-    MachineInstr *StoreMI = prior(oldNextMII);
-    VRM->addSpillSlotUse(StackSlot, StoreMI);
-    DEBUG(dbgs() << "Store:\t" << *StoreMI);
-    VRM->virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
-  }
-  return true;
-}
-
-
-/// ProcessUses - Process all of MI's spilled operands and all available
-/// operands.
-void LocalRewriter::ProcessUses(MachineInstr &MI, AvailableSpills &Spills,
-                                std::vector<MachineInstr*> &MaybeDeadStores,
-                                BitVector &RegKills,
-                                ReuseInfo &ReusedOperands,
-                                std::vector<MachineOperand*> &KillOps) {
-  // Clear kill info.
-  SmallSet<unsigned, 2> KilledMIRegs;
-  SmallVector<unsigned, 4> VirtUseOps;
-  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
-    MachineOperand &MO = MI.getOperand(i);
-    if (!MO.isReg() || MO.getReg() == 0)
-      continue;   // Ignore non-register operands.
-
-    unsigned VirtReg = MO.getReg();
-
-    if (TargetRegisterInfo::isPhysicalRegister(VirtReg)) {
-      // Ignore physregs for spilling, but remember that it is used by this
-      // function.
-      MRI->setPhysRegUsed(VirtReg);
-      continue;
-    }
-
-    // We want to process implicit virtual register uses first.
-    if (MO.isImplicit())
-      // If the virtual register is implicitly defined, emit a implicit_def
-      // before so scavenger knows it's "defined".
-      // FIXME: This is a horrible hack done the by register allocator to
-      // remat a definition with virtual register operand.
-      VirtUseOps.insert(VirtUseOps.begin(), i);
-    else
-      VirtUseOps.push_back(i);
-
-    // A partial def causes problems because the same operand both reads and
-    // writes the register. This rewriter is designed to rewrite uses and defs
-    // separately, so a partial def would already have been rewritten to a
-    // physreg by the time we get to processing defs.
-    // Add an implicit use operand to model the partial def.
-    if (MO.isDef() && MO.getSubReg() && MI.readsVirtualRegister(VirtReg) &&
-        MI.findRegisterUseOperandIdx(VirtReg) == -1) {
-      VirtUseOps.insert(VirtUseOps.begin(), MI.getNumOperands());
-      MI.addOperand(MachineOperand::CreateReg(VirtReg,
-                                              false,  // isDef
-                                              true)); // isImplicit
-      DEBUG(dbgs() << "Partial redef: " << MI);
-    }
-  }
-
-  // Process all of the spilled uses and all non spilled reg references.
-  SmallVector<int, 2> PotentialDeadStoreSlots;
-  KilledMIRegs.clear();
-  for (unsigned j = 0, e = VirtUseOps.size(); j != e; ++j) {
-    unsigned i = VirtUseOps[j];
-    unsigned VirtReg = MI.getOperand(i).getReg();
-    assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
-           "Not a virtual register?");
-
-    unsigned SubIdx = MI.getOperand(i).getSubReg();
-    if (VRM->isAssignedReg(VirtReg)) {
-      // This virtual register was assigned a physreg!
-      unsigned Phys = VRM->getPhys(VirtReg);
-      MRI->setPhysRegUsed(Phys);
-      if (MI.getOperand(i).isDef())
-        ReusedOperands.markClobbered(Phys);
-      substitutePhysReg(MI.getOperand(i), Phys, *TRI);
-      if (VRM->isImplicitlyDefined(VirtReg))
-        // FIXME: Is this needed?
-        BuildMI(*MBB, &MI, MI.getDebugLoc(),
-                TII->get(TargetOpcode::IMPLICIT_DEF), Phys);
-      continue;
-    }
-
-    // This virtual register is now known to be a spilled value.
-    if (!MI.getOperand(i).isUse())
-      continue;  // Handle defs in the loop below (handle use&def here though)
-
-    bool AvoidReload = MI.getOperand(i).isUndef();
-    // Check if it is defined by an implicit def. It should not be spilled.
-    // Note, this is for correctness reason. e.g.
-    // 8   %reg1024<def> = IMPLICIT_DEF
-    // 12  %reg1024<def> = INSERT_SUBREG %reg1024<kill>, %reg1025, 2
-    // The live range [12, 14) are not part of the r1024 live interval since
-    // it's defined by an implicit def. It will not conflicts with live
-    // interval of r1025. Now suppose both registers are spilled, you can
-    // easily see a situation where both registers are reloaded before
-    // the INSERT_SUBREG and both target registers that would overlap.
-    bool DoReMat = VRM->isReMaterialized(VirtReg);
-    int SSorRMId = DoReMat
-      ? VRM->getReMatId(VirtReg) : VRM->getStackSlot(VirtReg);
-    int ReuseSlot = SSorRMId;
-
-    // Check to see if this stack slot is available.
-    unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId);
-
-    // If this is a sub-register use, make sure the reuse register is in the
-    // right register class. For example, for x86 not all of the 32-bit
-    // registers have accessible sub-registers.
-    // Similarly so for EXTRACT_SUBREG. Consider this:
-    // EDI = op
-    // MOV32_mr fi#1, EDI
-    // ...
-    //       = EXTRACT_SUBREG fi#1
-    // fi#1 is available in EDI, but it cannot be reused because it's not in
-    // the right register file.
-    if (PhysReg && !AvoidReload && SubIdx) {
-      const TargetRegisterClass* RC = MRI->getRegClass(VirtReg);
-      if (!RC->contains(PhysReg))
-        PhysReg = 0;
-    }
-
-    if (PhysReg && !AvoidReload) {
-      // This spilled operand might be part of a two-address operand.  If this
-      // is the case, then changing it will necessarily require changing the
-      // def part of the instruction as well.  However, in some cases, we
-      // aren't allowed to modify the reused register.  If none of these cases
-      // apply, reuse it.
-      bool CanReuse = true;
-      bool isTied = MI.isRegTiedToDefOperand(i);
-      if (isTied) {
-        // Okay, we have a two address operand.  We can reuse this physreg as
-        // long as we are allowed to clobber the value and there isn't an
-        // earlier def that has already clobbered the physreg.
-        CanReuse = !ReusedOperands.isClobbered(PhysReg) &&
-          Spills.canClobberPhysReg(PhysReg);
-      }
-      // If this is an asm, and a PhysReg alias is used elsewhere as an
-      // earlyclobber operand, we can't also use it as an input.
-      if (MI.isInlineAsm()) {
-        for (unsigned k = 0, e = MI.getNumOperands(); k != e; ++k) {
-          MachineOperand &MOk = MI.getOperand(k);
-          if (MOk.isReg() && MOk.isEarlyClobber() &&
-              TRI->regsOverlap(MOk.getReg(), PhysReg)) {
-            CanReuse = false;
-            DEBUG(dbgs() << "Not reusing physreg " << TRI->getName(PhysReg)
-                         << " for " << PrintReg(VirtReg) << ": " << MOk
-                         << '\n');
-            break;
-          }
-        }
-      }
-
-      if (CanReuse) {
-        // If this stack slot value is already available, reuse it!
-        if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
-          DEBUG(dbgs() << "Reusing RM#"
-                << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1);
-        else
-          DEBUG(dbgs() << "Reusing SS#" << ReuseSlot);
-        DEBUG(dbgs() << " from physreg "
-              << TRI->getName(PhysReg) << " for " << PrintReg(VirtReg)
-              << " instead of reloading into "
-              << PrintReg(VRM->getPhys(VirtReg), TRI) << '\n');
-        unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
-        MI.getOperand(i).setReg(RReg);
-        MI.getOperand(i).setSubReg(0);
-
-        // Reusing a physreg may resurrect it. But we expect ProcessUses to
-        // update the kill flags for the current instr after processing it.
-
-        // The only technical detail we have is that we don't know that
-        // PhysReg won't be clobbered by a reloaded stack slot that occurs
-        // later in the instruction.  In particular, consider 'op V1, V2'.
-        // If V1 is available in physreg R0, we would choose to reuse it
-        // here, instead of reloading it into the register the allocator
-        // indicated (say R1).  However, V2 might have to be reloaded
-        // later, and it might indicate that it needs to live in R0.  When
-        // this occurs, we need to have information available that
-        // indicates it is safe to use R1 for the reload instead of R0.
-        //
-        // To further complicate matters, we might conflict with an alias,
-        // or R0 and R1 might not be compatible with each other.  In this
-        // case, we actually insert a reload for V1 in R1, ensuring that
-        // we can get at R0 or its alias.
-        ReusedOperands.addReuse(i, ReuseSlot, PhysReg,
-                                VRM->getPhys(VirtReg), VirtReg);
-        if (isTied)
-          // Only mark it clobbered if this is a use&def operand.
-          ReusedOperands.markClobbered(PhysReg);
-        ++NumReused;
-
-        if (MI.getOperand(i).isKill() &&
-            ReuseSlot <= VirtRegMap::MAX_STACK_SLOT) {
-
-          // The store of this spilled value is potentially dead, but we
-          // won't know for certain until we've confirmed that the re-use
-          // above is valid, which means waiting until the other operands
-          // are processed. For now we just track the spill slot, we'll
-          // remove it after the other operands are processed if valid.
-
-          PotentialDeadStoreSlots.push_back(ReuseSlot);
-        }
-
-        // Mark is isKill if it's there no other uses of the same virtual
-        // register and it's not a two-address operand. IsKill will be
-        // unset if reg is reused.
-        if (!isTied && KilledMIRegs.count(VirtReg) == 0) {
-          MI.getOperand(i).setIsKill();
-          KilledMIRegs.insert(VirtReg);
-        }
-        continue;
-      }  // CanReuse
-
-      // Otherwise we have a situation where we have a two-address instruction
-      // whose mod/ref operand needs to be reloaded.  This reload is already
-      // available in some register "PhysReg", but if we used PhysReg as the
-      // operand to our 2-addr instruction, the instruction would modify
-      // PhysReg.  This isn't cool if something later uses PhysReg and expects
-      // to get its initial value.
-      //
-      // To avoid this problem, and to avoid doing a load right after a store,
-      // we emit a copy from PhysReg into the designated register for this
-      // operand.
-      //
-      // This case also applies to an earlyclobber'd PhysReg.
-      unsigned DesignatedReg = VRM->getPhys(VirtReg);
-      assert(DesignatedReg && "Must map virtreg to physreg!");
-
-      // Note that, if we reused a register for a previous operand, the
-      // register we want to reload into might not actually be
-      // available.  If this occurs, use the register indicated by the
-      // reuser.
-      if (ReusedOperands.hasReuses())
-        DesignatedReg = ReusedOperands.
-          GetRegForReload(VirtReg, DesignatedReg, &MI, Spills,
-                          MaybeDeadStores, RegKills, KillOps, *VRM);
-
-      // If the mapped designated register is actually the physreg we have
-      // incoming, we don't need to inserted a dead copy.
-      if (DesignatedReg == PhysReg) {
-        // If this stack slot value is already available, reuse it!
-        if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
-          DEBUG(dbgs() << "Reusing RM#"
-                << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1);
-        else
-          DEBUG(dbgs() << "Reusing SS#" << ReuseSlot);
-        DEBUG(dbgs() << " from physreg " << TRI->getName(PhysReg)
-              << " for " << PrintReg(VirtReg)
-              << " instead of reloading into same physreg.\n");
-        unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
-        MI.getOperand(i).setReg(RReg);
-        MI.getOperand(i).setSubReg(0);
-        ReusedOperands.markClobbered(RReg);
-        ++NumReused;
-        continue;
-      }
-
-      MRI->setPhysRegUsed(DesignatedReg);
-      ReusedOperands.markClobbered(DesignatedReg);
-
-      // Back-schedule reloads and remats.
-      MachineBasicBlock::iterator InsertLoc =
-        ComputeReloadLoc(&MI, MBB->begin(), PhysReg, TRI, DoReMat,
-                         SSorRMId, TII, *MBB->getParent());
-      MachineInstr *CopyMI = BuildMI(*MBB, InsertLoc, MI.getDebugLoc(),
-                                     TII->get(TargetOpcode::COPY),
-                                     DesignatedReg).addReg(PhysReg);
-      CopyMI->setAsmPrinterFlag(MachineInstr::ReloadReuse);
-      UpdateKills(*CopyMI, TRI, RegKills, KillOps);
-
-      // This invalidates DesignatedReg.
-      Spills.ClobberPhysReg(DesignatedReg);
-
-      Spills.addAvailable(ReuseSlot, DesignatedReg);
-      unsigned RReg =
-        SubIdx ? TRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg;
-      MI.getOperand(i).setReg(RReg);
-      MI.getOperand(i).setSubReg(0);
-      DEBUG(dbgs() << '\t' << *prior(InsertLoc));
-      ++NumReused;
-      continue;
-    } // if (PhysReg)
-
-    // Otherwise, reload it and remember that we have it.
-    PhysReg = VRM->getPhys(VirtReg);
-    assert(PhysReg && "Must map virtreg to physreg!");
-
-    // Note that, if we reused a register for a previous operand, the
-    // register we want to reload into might not actually be
-    // available.  If this occurs, use the register indicated by the
-    // reuser.
-    if (ReusedOperands.hasReuses())
-      PhysReg = ReusedOperands.GetRegForReload(VirtReg, PhysReg, &MI,
-                  Spills, MaybeDeadStores, RegKills, KillOps, *VRM);
-
-    MRI->setPhysRegUsed(PhysReg);
-    ReusedOperands.markClobbered(PhysReg);
-    if (AvoidReload)
-      ++NumAvoided;
-    else {
-      // Back-schedule reloads and remats.
-      MachineBasicBlock::iterator InsertLoc =
-        ComputeReloadLoc(MI, MBB->begin(), PhysReg, TRI, DoReMat,
-                         SSorRMId, TII, *MBB->getParent());
-
-      if (DoReMat) {
-        ReMaterialize(*MBB, InsertLoc, PhysReg, VirtReg, TII, TRI, *VRM);
-      } else {
-        const TargetRegisterClass* RC = MRI->getRegClass(VirtReg);
-        TII->loadRegFromStackSlot(*MBB, InsertLoc, PhysReg, SSorRMId, RC,TRI);
-        MachineInstr *LoadMI = prior(InsertLoc);
-        VRM->addSpillSlotUse(SSorRMId, LoadMI);
-        ++NumLoads;
-        DistanceMap.insert(std::make_pair(LoadMI, DistanceMap.size()));
-      }
-      // This invalidates PhysReg.
-      Spills.ClobberPhysReg(PhysReg);
-
-      // Any stores to this stack slot are not dead anymore.
-      if (!DoReMat)
-        MaybeDeadStores[SSorRMId] = NULL;
-      Spills.addAvailable(SSorRMId, PhysReg);
-      // Assumes this is the last use. IsKill will be unset if reg is reused
-      // unless it's a two-address operand.
-      if (!MI.isRegTiedToDefOperand(i) &&
-          KilledMIRegs.count(VirtReg) == 0) {
-        MI.getOperand(i).setIsKill();
-        KilledMIRegs.insert(VirtReg);
-      }
-
-      UpdateKills(*prior(InsertLoc), TRI, RegKills, KillOps);
-      DEBUG(dbgs() << '\t' << *prior(InsertLoc));
-    }
-    unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
-    MI.getOperand(i).setReg(RReg);
-    MI.getOperand(i).setSubReg(0);
-  }
-
-  // Ok - now we can remove stores that have been confirmed dead.
-  for (unsigned j = 0, e = PotentialDeadStoreSlots.size(); j != e; ++j) {
-    // This was the last use and the spilled value is still available
-    // for reuse. That means the spill was unnecessary!
-    int PDSSlot = PotentialDeadStoreSlots[j];
-    MachineInstr* DeadStore = MaybeDeadStores[PDSSlot];
-    if (DeadStore) {
-      DEBUG(dbgs() << "Removed dead store:\t" << *DeadStore);
-      InvalidateKills(*DeadStore, TRI, RegKills, KillOps);
-      EraseInstr(DeadStore);
-      MaybeDeadStores[PDSSlot] = NULL;
-      ++NumDSE;
-    }
-  }
-}
-
-/// rewriteMBB - Keep track of which spills are available even after the
-/// register allocator is done with them.  If possible, avoid reloading vregs.
-void
-LocalRewriter::RewriteMBB(LiveIntervals *LIs,
-                          AvailableSpills &Spills, BitVector &RegKills,
-                          std::vector<MachineOperand*> &KillOps) {
-
-  DEBUG(dbgs() << "\n**** Local spiller rewriting MBB '"
-               << MBB->getName() << "':\n");
-
-  MachineFunction &MF = *MBB->getParent();
-
-  // MaybeDeadStores - When we need to write a value back into a stack slot,
-  // keep track of the inserted store.  If the stack slot value is never read
-  // (because the value was used from some available register, for example), and
-  // subsequently stored to, the original store is dead.  This map keeps track
-  // of inserted stores that are not used.  If we see a subsequent store to the
-  // same stack slot, the original store is deleted.
-  std::vector<MachineInstr*> MaybeDeadStores;
-  MaybeDeadStores.resize(MF.getFrameInfo()->getObjectIndexEnd(), NULL);
-
-  // ReMatDefs - These are rematerializable def MIs which are not deleted.
-  SmallSet<MachineInstr*, 4> ReMatDefs;
-
-  // Keep track of the registers we have already spilled in case there are
-  // multiple defs of the same register in MI.
-  SmallSet<unsigned, 8> SpilledMIRegs;
-
-  RegKills.reset();
-  KillOps.clear();
-  KillOps.resize(TRI->getNumRegs(), NULL);
-
-  DistanceMap.clear();
-  for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
-       MII != E; ) {
-    MachineBasicBlock::iterator NextMII = llvm::next(MII);
-
-    if (OptimizeByUnfold(MII, MaybeDeadStores, Spills, RegKills, KillOps))
-      NextMII = llvm::next(MII);
-
-    if (InsertEmergencySpills(MII))
-      NextMII = llvm::next(MII);
-
-    InsertRestores(MII, Spills, RegKills, KillOps);
-
-    if (InsertSpills(MII))
-      NextMII = llvm::next(MII);
-
-    bool Erased = false;
-    bool BackTracked = false;
-    MachineInstr &MI = *MII;
-
-    // Remember DbgValue's which reference stack slots.
-    if (MI.isDebugValue() && MI.getOperand(0).isFI())
-      Slot2DbgValues[MI.getOperand(0).getIndex()].push_back(&MI);
-
-    /// ReusedOperands - Keep track of operand reuse in case we need to undo
-    /// reuse.
-    ReuseInfo ReusedOperands(MI, TRI);
-
-    ProcessUses(MI, Spills, MaybeDeadStores, RegKills, ReusedOperands, KillOps);
-
-    DEBUG(dbgs() << '\t' << MI);
-
-
-    // If we have folded references to memory operands, make sure we clear all
-    // physical registers that may contain the value of the spilled virtual
-    // register
-
-    // Copy the folded virts to a small vector, we may change MI2VirtMap.
-    SmallVector<std::pair<unsigned, VirtRegMap::ModRef>, 4> FoldedVirts;
-    // C++0x FTW!
-    for (std::pair<VirtRegMap::MI2VirtMapTy::const_iterator,
-                   VirtRegMap::MI2VirtMapTy::const_iterator> FVRange =
-           VRM->getFoldedVirts(&MI);
-         FVRange.first != FVRange.second; ++FVRange.first)
-      FoldedVirts.push_back(FVRange.first->second);
-
-    SmallSet<int, 2> FoldedSS;
-    for (unsigned FVI = 0, FVE = FoldedVirts.size(); FVI != FVE; ++FVI) {
-      unsigned VirtReg = FoldedVirts[FVI].first;
-      VirtRegMap::ModRef MR = FoldedVirts[FVI].second;
-      DEBUG(dbgs() << "Folded " << PrintReg(VirtReg) << "  MR: " << MR);
-
-      int SS = VRM->getStackSlot(VirtReg);
-      if (SS == VirtRegMap::NO_STACK_SLOT)
-        continue;
-      FoldedSS.insert(SS);
-      DEBUG(dbgs() << " - StackSlot: " << SS << "\n");
-
-      // If this folded instruction is just a use, check to see if it's a
-      // straight load from the virt reg slot.
-      if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
-        int FrameIdx;
-        unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx);
-        if (DestReg && FrameIdx == SS) {
-          // If this spill slot is available, turn it into a copy (or nothing)
-          // instead of leaving it as a load!
-          if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) {
-            DEBUG(dbgs() << "Promoted Load To Copy: " << MI);
-            if (DestReg != InReg) {
-              MachineOperand *DefMO = MI.findRegisterDefOperand(DestReg);
-              MachineInstr *CopyMI = BuildMI(*MBB, &MI, MI.getDebugLoc(),
-                                             TII->get(TargetOpcode::COPY))
-                .addReg(DestReg, RegState::Define, DefMO->getSubReg())
-                .addReg(InReg, RegState::Kill);
-              // Revisit the copy so we make sure to notice the effects of the
-              // operation on the destreg (either needing to RA it if it's
-              // virtual or needing to clobber any values if it's physical).
-              NextMII = CopyMI;
-              NextMII->setAsmPrinterFlag(MachineInstr::ReloadReuse);
-              BackTracked = true;
-            } else {
-              DEBUG(dbgs() << "Removing now-noop copy: " << MI);
-              // InvalidateKills resurrects any prior kill of the copy's source
-              // allowing the source reg to be reused in place of the copy.
-              Spills.disallowClobberPhysReg(InReg);
-            }
-
-            InvalidateKills(MI, TRI, RegKills, KillOps);
-            EraseInstr(&MI);
-            Erased = true;
-            goto ProcessNextInst;
-          }
-        } else {
-          unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
-          SmallVector<MachineInstr*, 4> NewMIs;
-          if (PhysReg &&
-              TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, false, NewMIs)){
-            MBB->insert(MII, NewMIs[0]);
-            InvalidateKills(MI, TRI, RegKills, KillOps);
-            EraseInstr(&MI);
-            Erased = true;
-            --NextMII;  // backtrack to the unfolded instruction.
-            BackTracked = true;
-            goto ProcessNextInst;
-          }
-        }
-      }
-
-      // If this reference is not a use, any previous store is now dead.
-      // Otherwise, the store to this stack slot is not dead anymore.
-      MachineInstr* DeadStore = MaybeDeadStores[SS];
-      if (DeadStore) {
-        bool isDead = !(MR & VirtRegMap::isRef);
-        MachineInstr *NewStore = NULL;
-        if (MR & VirtRegMap::isModRef) {
-          unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
-          SmallVector<MachineInstr*, 4> NewMIs;
-          // We can reuse this physreg as long as we are allowed to clobber
-          // the value and there isn't an earlier def that has already clobbered
-          // the physreg.
-          if (PhysReg &&
-              !ReusedOperands.isClobbered(PhysReg) &&
-              Spills.canClobberPhysReg(PhysReg) &&
-              !TII->isStoreToStackSlot(&MI, SS)) { // Not profitable!
-            MachineOperand *KillOpnd =
-              DeadStore->findRegisterUseOperand(PhysReg, true);
-            // Note, if the store is storing a sub-register, it's possible the
-            // super-register is needed below.
-            if (KillOpnd && !KillOpnd->getSubReg() &&
-                TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, true,NewMIs)){
-              MBB->insert(MII, NewMIs[0]);
-              NewStore = NewMIs[1];
-              MBB->insert(MII, NewStore);
-              VRM->addSpillSlotUse(SS, NewStore);
-              InvalidateKills(MI, TRI, RegKills, KillOps);
-              EraseInstr(&MI);
-              Erased = true;
-              --NextMII;
-              --NextMII;  // backtrack to the unfolded instruction.
-              BackTracked = true;
-              isDead = true;
-              ++NumSUnfold;
-            }
-          }
-        }
-
-        if (isDead) {  // Previous store is dead.
-          // If we get here, the store is dead, nuke it now.
-          DEBUG(dbgs() << "Removed dead store:\t" << *DeadStore);
-          InvalidateKills(*DeadStore, TRI, RegKills, KillOps);
-          EraseInstr(DeadStore);
-          if (!NewStore)
-            ++NumDSE;
-        }
-
-        MaybeDeadStores[SS] = NULL;
-        if (NewStore) {
-          // Treat this store as a spill merged into a copy. That makes the
-          // stack slot value available.
-          VRM->virtFolded(VirtReg, NewStore, VirtRegMap::isMod);
-          goto ProcessNextInst;
-        }
-      }
-
-      // If the spill slot value is available, and this is a new definition of
-      // the value, the value is not available anymore.
-      if (MR & VirtRegMap::isMod) {
-        // Notice that the value in this stack slot has been modified.
-        Spills.ModifyStackSlotOrReMat(SS);
-
-        // If this is *just* a mod of the value, check to see if this is just a
-        // store to the spill slot (i.e. the spill got merged into the copy). If
-        // so, realize that the vreg is available now, and add the store to the
-        // MaybeDeadStore info.
-        int StackSlot;
-        if (!(MR & VirtRegMap::isRef)) {
-          if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
-            assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
-                   "Src hasn't been allocated yet?");
-
-            if (CommuteToFoldReload(MII, VirtReg, SrcReg, StackSlot,
-                                    Spills, RegKills, KillOps, TRI)) {
-              NextMII = llvm::next(MII);
-              BackTracked = true;
-              goto ProcessNextInst;
-            }
-
-            // Okay, this is certainly a store of SrcReg to [StackSlot].  Mark
-            // this as a potentially dead store in case there is a subsequent
-            // store into the stack slot without a read from it.
-            MaybeDeadStores[StackSlot] = &MI;
-
-            // If the stack slot value was previously available in some other
-            // register, change it now.  Otherwise, make the register
-            // available in PhysReg.
-            Spills.addAvailable(StackSlot, SrcReg, MI.killsRegister(SrcReg));
-          }
-        }
-      }
-    }
-
-    // Process all of the spilled defs.
-    SpilledMIRegs.clear();
-    for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
-      MachineOperand &MO = MI.getOperand(i);
-      if (!(MO.isReg() && MO.getReg() && MO.isDef()))
-        continue;
-
-      unsigned VirtReg = MO.getReg();
-      if (!TargetRegisterInfo::isVirtualRegister(VirtReg)) {
-        // Check to see if this is a noop copy.  If so, eliminate the
-        // instruction before considering the dest reg to be changed.
-        // Also check if it's copying from an "undef", if so, we can't
-        // eliminate this or else the undef marker is lost and it will
-        // confuses the scavenger. This is extremely rare.
-        if (MI.isIdentityCopy() && !MI.getOperand(1).isUndef() &&
-            MI.getNumOperands() == 2) {
-          ++NumDCE;
-          DEBUG(dbgs() << "Removing now-noop copy: " << MI);
-          SmallVector<unsigned, 2> KillRegs;
-          InvalidateKills(MI, TRI, RegKills, KillOps, &KillRegs);
-          if (MO.isDead() && !KillRegs.empty()) {
-            // Source register or an implicit super/sub-register use is killed.
-            assert(TRI->regsOverlap(KillRegs[0], MI.getOperand(0).getReg()));
-            // Last def is now dead.
-            TransferDeadness(MI.getOperand(1).getReg(), RegKills, KillOps);
-          }
-          EraseInstr(&MI);
-          Erased = true;
-          Spills.disallowClobberPhysReg(VirtReg);
-          goto ProcessNextInst;
-        }
-
-        // If it's not a no-op copy, it clobbers the value in the destreg.
-        Spills.ClobberPhysReg(VirtReg);
-        ReusedOperands.markClobbered(VirtReg);
-
-        // Check to see if this instruction is a load from a stack slot into
-        // a register.  If so, this provides the stack slot value in the reg.
-        int FrameIdx;
-        if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
-          assert(DestReg == VirtReg && "Unknown load situation!");
-
-          // If it is a folded reference, then it's not safe to clobber.
-          bool Folded = FoldedSS.count(FrameIdx);
-          // Otherwise, if it wasn't available, remember that it is now!
-          Spills.addAvailable(FrameIdx, DestReg, !Folded);
-          goto ProcessNextInst;
-        }
-
-        continue;
-      }
-
-      unsigned SubIdx = MO.getSubReg();
-      bool DoReMat = VRM->isReMaterialized(VirtReg);
-      if (DoReMat)
-        ReMatDefs.insert(&MI);
-
-      // The only vregs left are stack slot definitions.
-      int StackSlot = VRM->getStackSlot(VirtReg);
-      const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
-
-      // If this def is part of a two-address operand, make sure to execute
-      // the store from the correct physical register.
-      unsigned PhysReg;
-      unsigned TiedOp;
-      if (MI.isRegTiedToUseOperand(i, &TiedOp)) {
-        PhysReg = MI.getOperand(TiedOp).getReg();
-        if (SubIdx) {
-          unsigned SuperReg = findSuperReg(RC, PhysReg, SubIdx, TRI);
-          assert(SuperReg && TRI->getSubReg(SuperReg, SubIdx) == PhysReg &&
-                 "Can't find corresponding super-register!");
-          PhysReg = SuperReg;
-        }
-      } else {
-        PhysReg = VRM->getPhys(VirtReg);
-        if (ReusedOperands.isClobbered(PhysReg)) {
-          // Another def has taken the assigned physreg. It must have been a
-          // use&def which got it due to reuse. Undo the reuse!
-          PhysReg = ReusedOperands.GetRegForReload(VirtReg, PhysReg, &MI,
-                      Spills, MaybeDeadStores, RegKills, KillOps, *VRM);
-        }
-      }
-
-      // If StackSlot is available in a register that also holds other stack
-      // slots, clobber those stack slots now.
-      Spills.ClobberSharingStackSlots(StackSlot);
-
-      assert(PhysReg && "VR not assigned a physical register?");
-      MRI->setPhysRegUsed(PhysReg);
-      unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
-      ReusedOperands.markClobbered(RReg);
-      MI.getOperand(i).setReg(RReg);
-      MI.getOperand(i).setSubReg(0);
-
-      if (!MO.isDead() && SpilledMIRegs.insert(VirtReg)) {
-        MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
-        SpillRegToStackSlot(MII, -1, PhysReg, StackSlot, RC, true,
-          LastStore, Spills, ReMatDefs, RegKills, KillOps);
-        NextMII = llvm::next(MII);
-
-        // Check to see if this is a noop copy.  If so, eliminate the
-        // instruction before considering the dest reg to be changed.
-        if (MI.isIdentityCopy()) {
-          ++NumDCE;
-          DEBUG(dbgs() << "Removing now-noop copy: " << MI);
-          InvalidateKills(MI, TRI, RegKills, KillOps);
-          EraseInstr(&MI);
-          Erased = true;
-          UpdateKills(*LastStore, TRI, RegKills, KillOps);
-          goto ProcessNextInst;
-        }
-      }
-    }
-    ProcessNextInst:
-    // Delete dead instructions without side effects.
-    if (!Erased && !BackTracked && isSafeToDelete(MI)) {
-      InvalidateKills(MI, TRI, RegKills, KillOps);
-      EraseInstr(&MI);
-      Erased = true;
-    }
-    if (!Erased)
-      DistanceMap.insert(std::make_pair(&MI, DistanceMap.size()));
-    if (!Erased && !BackTracked) {
-      for (MachineBasicBlock::iterator II = &MI; II != NextMII; ++II)
-        UpdateKills(*II, TRI, RegKills, KillOps);
-    }
-    MII = NextMII;
-  }
-
-}
-
-llvm::VirtRegRewriter* llvm::createVirtRegRewriter() {
-  switch (RewriterOpt) {
-  default: llvm_unreachable("Unreachable!");
-  case local:
-    return new LocalRewriter();
-  case trivial:
-    return new TrivialRewriter();
-  }
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/CodeGen/VirtRegRewriter.h
--- a/head/contrib/llvm/lib/CodeGen/VirtRegRewriter.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,32 +0,0 @@
-//===-- llvm/CodeGen/VirtRegRewriter.h - VirtRegRewriter -*- C++ -*--------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_CODEGEN_VIRTREGREWRITER_H
-#define LLVM_CODEGEN_VIRTREGREWRITER_H
-
-namespace llvm {
-  class LiveIntervals;
-  class MachineFunction;
-  class VirtRegMap;
-  
-  /// VirtRegRewriter interface: Implementations of this interface assign
-  /// spilled virtual registers to stack slots, rewriting the code.
-  struct VirtRegRewriter {
-    virtual ~VirtRegRewriter();
-    virtual bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM,
-                                      LiveIntervals* LIs) = 0;
-  };
-
-  /// createVirtRegRewriter - Create an return a rewriter object, as specified
-  /// on the command line.
-  VirtRegRewriter* createVirtRegRewriter();
-
-}
-
-#endif
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/ExecutionEngine/JIT/Intercept.cpp
--- a/head/contrib/llvm/lib/ExecutionEngine/JIT/Intercept.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,162 +0,0 @@
-//===-- Intercept.cpp - System function interception routines -------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// If a function call occurs to an external function, the JIT is designed to use
-// the dynamic loader interface to find a function to call.  This is useful for
-// calling system calls and library functions that are not available in LLVM.
-// Some system calls, however, need to be handled specially.  For this reason,
-// we intercept some of them here and use our own stubs to handle them.
-//
-//===----------------------------------------------------------------------===//
-
-#include "JIT.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/DynamicLibrary.h"
-#include "llvm/Config/config.h"
-using namespace llvm;
-
-// AtExitHandlers - List of functions to call when the program exits,
-// registered with the atexit() library function.
-static std::vector<void (*)()> AtExitHandlers;
-
-/// runAtExitHandlers - Run any functions registered by the program's
-/// calls to atexit(3), which we intercept and store in
-/// AtExitHandlers.
-///
-static void runAtExitHandlers() {
-  while (!AtExitHandlers.empty()) {
-    void (*Fn)() = AtExitHandlers.back();
-    AtExitHandlers.pop_back();
-    Fn();
-  }
-}
-
-//===----------------------------------------------------------------------===//
-// Function stubs that are invoked instead of certain library calls
-//===----------------------------------------------------------------------===//
-
-// Force the following functions to be linked in to anything that uses the
-// JIT. This is a hack designed to work around the all-too-clever Glibc
-// strategy of making these functions work differently when inlined vs. when
-// not inlined, and hiding their real definitions in a separate archive file
-// that the dynamic linker can't see. For more info, search for
-// 'libc_nonshared.a' on Google, or read http://llvm.org/PR274.
-#if defined(__linux__)
-#if defined(HAVE_SYS_STAT_H)
-#include <sys/stat.h>
-#endif
-#include <fcntl.h>
-#include <unistd.h>
-/* stat functions are redirecting to __xstat with a version number.  On x86-64
- * linking with libc_nonshared.a and -Wl,--export-dynamic doesn't make 'stat'
- * available as an exported symbol, so we have to add it explicitly.
- */
-namespace {
-class StatSymbols {
-public:
-  StatSymbols() {
-    sys::DynamicLibrary::AddSymbol("stat", (void*)(intptr_t)stat);
-    sys::DynamicLibrary::AddSymbol("fstat", (void*)(intptr_t)fstat);
-    sys::DynamicLibrary::AddSymbol("lstat", (void*)(intptr_t)lstat);
-    sys::DynamicLibrary::AddSymbol("stat64", (void*)(intptr_t)stat64);
-    sys::DynamicLibrary::AddSymbol("\x1stat64", (void*)(intptr_t)stat64);
-    sys::DynamicLibrary::AddSymbol("\x1open64", (void*)(intptr_t)open64);
-    sys::DynamicLibrary::AddSymbol("\x1lseek64", (void*)(intptr_t)lseek64);
-    sys::DynamicLibrary::AddSymbol("fstat64", (void*)(intptr_t)fstat64);
-    sys::DynamicLibrary::AddSymbol("lstat64", (void*)(intptr_t)lstat64);
-    sys::DynamicLibrary::AddSymbol("atexit", (void*)(intptr_t)atexit);
-    sys::DynamicLibrary::AddSymbol("mknod", (void*)(intptr_t)mknod);
-  }
-};
-}
-static StatSymbols initStatSymbols;
-#endif // __linux__
-
-// jit_exit - Used to intercept the "exit" library call.
-static void jit_exit(int Status) {
-  runAtExitHandlers();   // Run atexit handlers...
-  exit(Status);
-}
-
-// jit_atexit - Used to intercept the "atexit" library call.
-static int jit_atexit(void (*Fn)()) {
-  AtExitHandlers.push_back(Fn);    // Take note of atexit handler...
-  return 0;  // Always successful
-}
-
-static int jit_noop() {
-  return 0;
-}
-
-//===----------------------------------------------------------------------===//
-//
-/// getPointerToNamedFunction - This method returns the address of the specified
-/// function by using the dynamic loader interface.  As such it is only useful
-/// for resolving library symbols, not code generated symbols.
-///
-void *JIT::getPointerToNamedFunction(const std::string &Name,
-                                     bool AbortOnFailure) {
-  if (!isSymbolSearchingDisabled()) {
-    // Check to see if this is one of the functions we want to intercept.  Note,
-    // we cast to intptr_t here to silence a -pedantic warning that complains
-    // about casting a function pointer to a normal pointer.
-    if (Name == "exit") return (void*)(intptr_t)&jit_exit;
-    if (Name == "atexit") return (void*)(intptr_t)&jit_atexit;
-
-    // We should not invoke parent's ctors/dtors from generated main()!
-    // On Mingw and Cygwin, the symbol __main is resolved to
-    // callee's(eg. tools/lli) one, to invoke wrong duplicated ctors
-    // (and register wrong callee's dtors with atexit(3)).
-    // We expect ExecutionEngine::runStaticConstructorsDestructors()
-    // is called before ExecutionEngine::runFunctionAsMain() is called.
-    if (Name == "__main") return (void*)(intptr_t)&jit_noop;
-
-    const char *NameStr = Name.c_str();
-    // If this is an asm specifier, skip the sentinal.
-    if (NameStr[0] == 1) ++NameStr;
-
-    // If it's an external function, look it up in the process image...
-    void *Ptr = sys::DynamicLibrary::SearchForAddressOfSymbol(NameStr);
-    if (Ptr) return Ptr;
-
-    // If it wasn't found and if it starts with an underscore ('_') character,
-    // and has an asm specifier, try again without the underscore.
-    if (Name[0] == 1 && NameStr[0] == '_') {
-      Ptr = sys::DynamicLibrary::SearchForAddressOfSymbol(NameStr+1);
-      if (Ptr) return Ptr;
-    }
-
-    // Darwin/PPC adds $LDBLStub suffixes to various symbols like printf.  These
-    // are references to hidden visibility symbols that dlsym cannot resolve.
-    // If we have one of these, strip off $LDBLStub and try again.
-#if defined(__APPLE__) && defined(__ppc__)
-    if (Name.size() > 9 && Name[Name.size()-9] == '$' &&
-        memcmp(&Name[Name.size()-8], "LDBLStub", 8) == 0) {
-      // First try turning $LDBLStub into $LDBL128. If that fails, strip it off.
-      // This mirrors logic in libSystemStubs.a.
-      std::string Prefix = std::string(Name.begin(), Name.end()-9);
-      if (void *Ptr = getPointerToNamedFunction(Prefix+"$LDBL128", false))
-        return Ptr;
-      if (void *Ptr = getPointerToNamedFunction(Prefix, false))
-        return Ptr;
-    }
-#endif
-  }
-
-  /// If a LazyFunctionCreator is installed, use it to get/create the function.
-  if (LazyFunctionCreator)
-    if (void *RP = LazyFunctionCreator(Name))
-      return RP;
-
-  if (AbortOnFailure) {
-    report_fatal_error("Program used external function '"+Name+
-                      "' which could not be resolved!");
-  }
-  return 0;
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/ExecutionEngine/JIT/JITDebugRegisterer.cpp
--- a/head/contrib/llvm/lib/ExecutionEngine/JIT/JITDebugRegisterer.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,211 +0,0 @@
-//===-- JITDebugRegisterer.cpp - Register debug symbols for JIT -----------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines a JITDebugRegisterer object that is used by the JIT to
-// register debug info with debuggers like GDB.
-//
-//===----------------------------------------------------------------------===//
-
-#include "JITDebugRegisterer.h"
-#include "../../CodeGen/ELF.h"
-#include "../../CodeGen/ELFWriter.h"
-#include "llvm/LLVMContext.h"
-#include "llvm/Function.h"
-#include "llvm/Module.h"
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetOptions.h"
-#include "llvm/ADT/DenseMap.h"
-#include "llvm/ADT/OwningPtr.h"
-#include "llvm/Support/Compiler.h"
-#include "llvm/Support/MutexGuard.h"
-#include "llvm/Support/raw_ostream.h"
-#include "llvm/Support/Mutex.h"
-#include <string>
-
-namespace llvm {
-
-// This must be kept in sync with gdb/gdb/jit.h .
-extern "C" {
-
-  // Debuggers puts a breakpoint in this function.
-  LLVM_ATTRIBUTE_NOINLINE void __jit_debug_register_code() { }
-
-  // We put information about the JITed function in this global, which the
-  // debugger reads.  Make sure to specify the version statically, because the
-  // debugger checks the version before we can set it during runtime.
-  struct jit_descriptor __jit_debug_descriptor = { 1, 0, 0, 0 };
-
-}
-
-namespace {
-
-  /// JITDebugLock - Used to serialize all code registration events, since they
-  /// modify global variables.
-  sys::Mutex JITDebugLock;
-
-}
-
-JITDebugRegisterer::JITDebugRegisterer(TargetMachine &tm) : TM(tm), FnMap() { }
-
-JITDebugRegisterer::~JITDebugRegisterer() {
-  // Free all ELF memory.
-  for (RegisteredFunctionsMap::iterator I = FnMap.begin(), E = FnMap.end();
-       I != E; ++I) {
-    // Call the private method that doesn't update the map so our iterator
-    // doesn't break.
-    UnregisterFunctionInternal(I);
-  }
-  FnMap.clear();
-}
-
-std::string JITDebugRegisterer::MakeELF(const Function *F, DebugInfo &I) {
-  // Stack allocate an empty module with an empty LLVMContext for the ELFWriter
-  // API.  We don't use the real module because then the ELFWriter would write
-  // out unnecessary GlobalValues during finalization.
-  LLVMContext Context;
-  Module M("", Context);
-
-  // Make a buffer for the ELF in memory.
-  std::string Buffer;
-  raw_string_ostream O(Buffer);
-  ELFWriter EW(O, TM);
-  EW.doInitialization(M);
-
-  // Copy the binary into the .text section.  This isn't necessary, but it's
-  // useful to be able to disassemble the ELF by hand.
-  ELFSection &Text = EW.getTextSection(const_cast<Function *>(F));
-  Text.Addr = (uint64_t)I.FnStart;
-  // TODO: We could eliminate this copy if we somehow used a pointer/size pair
-  // instead of a vector.
-  Text.getData().assign(I.FnStart, I.FnEnd);
-
-  // Copy the exception handling call frame information into the .eh_frame
-  // section.  This allows GDB to get a good stack trace, particularly on
-  // linux x86_64.  Mark this as a PROGBITS section that needs to be loaded
-  // into memory at runtime.
-  ELFSection &EH = EW.getSection(".eh_frame", ELF::SHT_PROGBITS,
-                                 ELF::SHF_ALLOC);
-  // Pointers in the DWARF EH info are all relative to the EH frame start,
-  // which is stored here.
-  EH.Addr = (uint64_t)I.EhStart;
-  // TODO: We could eliminate this copy if we somehow used a pointer/size pair
-  // instead of a vector.
-  EH.getData().assign(I.EhStart, I.EhEnd);
-
-  // Add this single function to the symbol table, so the debugger prints the
-  // name instead of '???'.  We give the symbol default global visibility.
-  ELFSym *FnSym = ELFSym::getGV(F,
-                                ELF::STB_GLOBAL,
-                                ELF::STT_FUNC,
-                                ELF::STV_DEFAULT);
-  FnSym->SectionIdx = Text.SectionIdx;
-  FnSym->Size = I.FnEnd - I.FnStart;
-  FnSym->Value = 0;  // Offset from start of section.
-  EW.SymbolList.push_back(FnSym);
-
-  EW.doFinalization(M);
-  O.flush();
-
-  // When trying to debug why GDB isn't getting the debug info right, it's
-  // awfully helpful to write the object file to disk so that it can be
-  // inspected with readelf and objdump.
-  if (JITEmitDebugInfoToDisk) {
-    std::string Filename;
-    raw_string_ostream O2(Filename);
-    O2 << "/tmp/llvm_function_" << I.FnStart << "_" << F->getNameStr() << ".o";
-    O2.flush();
-    std::string Errors;
-    raw_fd_ostream O3(Filename.c_str(), Errors);
-    O3 << Buffer;
-    O3.close();
-  }
-
-  return Buffer;
-}
-
-void JITDebugRegisterer::RegisterFunction(const Function *F, DebugInfo &I) {
-  // TODO: Support non-ELF platforms.
-  if (!TM.getELFWriterInfo())
-    return;
-
-  std::string Buffer = MakeELF(F, I);
-
-  jit_code_entry *JITCodeEntry = new jit_code_entry();
-  JITCodeEntry->symfile_addr = Buffer.c_str();
-  JITCodeEntry->symfile_size = Buffer.size();
-
-  // Add a mapping from F to the entry and buffer, so we can delete this
-  // info later.
-  FnMap[F] = std::make_pair(Buffer, JITCodeEntry);
-
-  // Acquire the lock and do the registration.
-  {
-    MutexGuard locked(JITDebugLock);
-    __jit_debug_descriptor.action_flag = JIT_REGISTER_FN;
-
-    // Insert this entry at the head of the list.
-    JITCodeEntry->prev_entry = NULL;
-    jit_code_entry *NextEntry = __jit_debug_descriptor.first_entry;
-    JITCodeEntry->next_entry = NextEntry;
-    if (NextEntry != NULL) {
-      NextEntry->prev_entry = JITCodeEntry;
-    }
-    __jit_debug_descriptor.first_entry = JITCodeEntry;
-    __jit_debug_descriptor.relevant_entry = JITCodeEntry;
-    __jit_debug_register_code();
-  }
-}
-
-void JITDebugRegisterer::UnregisterFunctionInternal(
-    RegisteredFunctionsMap::iterator I) {
-  jit_code_entry *&JITCodeEntry = I->second.second;
-
-  // Acquire the lock and do the unregistration.
-  {
-    MutexGuard locked(JITDebugLock);
-    __jit_debug_descriptor.action_flag = JIT_UNREGISTER_FN;
-
-    // Remove the jit_code_entry from the linked list.
-    jit_code_entry *PrevEntry = JITCodeEntry->prev_entry;
-    jit_code_entry *NextEntry = JITCodeEntry->next_entry;
-    if (NextEntry) {
-      NextEntry->prev_entry = PrevEntry;
-    }
-    if (PrevEntry) {
-      PrevEntry->next_entry = NextEntry;
-    } else {
-      assert(__jit_debug_descriptor.first_entry == JITCodeEntry);
-      __jit_debug_descriptor.first_entry = NextEntry;
-    }
-
-    // Tell GDB which entry we removed, and unregister the code.
-    __jit_debug_descriptor.relevant_entry = JITCodeEntry;
-    __jit_debug_register_code();
-  }
-
-  delete JITCodeEntry;
-  JITCodeEntry = NULL;
-
-  // Free the ELF file in memory.
-  std::string &Buffer = I->second.first;
-  Buffer.clear();
-}
-
-void JITDebugRegisterer::UnregisterFunction(const Function *F) {
-  // TODO: Support non-ELF platforms.
-  if (!TM.getELFWriterInfo())
-    return;
-
-  RegisteredFunctionsMap::iterator I = FnMap.find(F);
-  if (I == FnMap.end()) return;
-  UnregisterFunctionInternal(I);
-  FnMap.erase(I);
-}
-
-} // end namespace llvm
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/ExecutionEngine/JIT/JITDebugRegisterer.h
--- a/head/contrib/llvm/lib/ExecutionEngine/JIT/JITDebugRegisterer.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,116 +0,0 @@
-//===-- JITDebugRegisterer.h - Register debug symbols for JIT -------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines a JITDebugRegisterer object that is used by the JIT to
-// register debug info with debuggers like GDB.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_EXECUTION_ENGINE_JIT_DEBUGREGISTERER_H
-#define LLVM_EXECUTION_ENGINE_JIT_DEBUGREGISTERER_H
-
-#include "llvm/ADT/DenseMap.h"
-#include "llvm/Support/DataTypes.h"
-#include <string>
-
-// This must be kept in sync with gdb/gdb/jit.h .
-extern "C" {
-
-  typedef enum {
-    JIT_NOACTION = 0,
-    JIT_REGISTER_FN,
-    JIT_UNREGISTER_FN
-  } jit_actions_t;
-
-  struct jit_code_entry {
-    struct jit_code_entry *next_entry;
-    struct jit_code_entry *prev_entry;
-    const char *symfile_addr;
-    uint64_t symfile_size;
-  };
-
-  struct jit_descriptor {
-    uint32_t version;
-    // This should be jit_actions_t, but we want to be specific about the
-    // bit-width.
-    uint32_t action_flag;
-    struct jit_code_entry *relevant_entry;
-    struct jit_code_entry *first_entry;
-  };
-
-}
-
-namespace llvm {
-
-class ELFSection;
-class Function;
-class TargetMachine;
-
-
-/// This class encapsulates information we want to send to the debugger.
-///
-struct DebugInfo {
-  uint8_t *FnStart;
-  uint8_t *FnEnd;
-  uint8_t *EhStart;
-  uint8_t *EhEnd;
-
-  DebugInfo() : FnStart(0), FnEnd(0), EhStart(0), EhEnd(0) {}
-};
-
-typedef DenseMap< const Function*, std::pair<std::string, jit_code_entry*> >
-  RegisteredFunctionsMap;
-
-/// This class registers debug info for JITed code with an attached debugger.
-/// Without proper debug info, GDB can't do things like source level debugging
-/// or even produce a proper stack trace on linux-x86_64.  To use this class,
-/// whenever a function is JITed, create a DebugInfo struct and pass it to the
-/// RegisterFunction method.  The method will then do whatever is necessary to
-/// inform the debugger about the JITed function.
-class JITDebugRegisterer {
-
-  TargetMachine &TM;
-
-  /// FnMap - A map of functions that have been registered to the associated
-  /// temporary files.  Used for cleanup.
-  RegisteredFunctionsMap FnMap;
-
-  /// MakeELF - Builds the ELF file in memory and returns a std::string that
-  /// contains the ELF.
-  std::string MakeELF(const Function *F, DebugInfo &I);
-
-public:
-  JITDebugRegisterer(TargetMachine &tm);
-
-  /// ~JITDebugRegisterer - Unregisters all code and frees symbol files.
-  ///
-  ~JITDebugRegisterer();
-
-  /// RegisterFunction - Register debug info for the given function with an
-  /// attached debugger.  Clients must call UnregisterFunction on all
-  /// registered functions before deleting them to free the associated symbol
-  /// file and unregister it from the debugger.
-  void RegisterFunction(const Function *F, DebugInfo &I);
-
-  /// UnregisterFunction - Unregister the debug info for the given function
-  /// from the debugger and free associated memory.
-  void UnregisterFunction(const Function *F);
-
-private:
-  /// UnregisterFunctionInternal - Unregister the debug info for the given
-  /// function from the debugger and delete any temporary files.  The private
-  /// version of this method does not remove the function from FnMap so that it
-  /// can be called while iterating over FnMap.
-  void UnregisterFunctionInternal(RegisteredFunctionsMap::iterator I);
-
-};
-
-} // end namespace llvm
-
-#endif // LLVM_EXECUTION_ENGINE_JIT_DEBUGREGISTERER_H
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/ExecutionEngine/JIT/OProfileJITEventListener.cpp
--- a/head/contrib/llvm/lib/ExecutionEngine/JIT/OProfileJITEventListener.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,192 +0,0 @@
-//===-- OProfileJITEventListener.cpp - Tell OProfile about JITted code ----===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines a JITEventListener object that calls into OProfile to tell
-// it about JITted functions.  For now, we only record function names and sizes,
-// but eventually we'll also record line number information.
-//
-// See http://oprofile.sourceforge.net/doc/devel/jit-interface.html for the
-// definition of the interface we're using.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "oprofile-jit-event-listener"
-#include "llvm/Function.h"
-#include "llvm/Metadata.h"
-#include "llvm/ADT/DenseMap.h"
-#include "llvm/Analysis/DebugInfo.h"
-#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/ExecutionEngine/JITEventListener.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/ValueHandle.h"
-#include "llvm/Support/raw_ostream.h"
-#include "llvm/Support/Errno.h"
-#include "llvm/Config/config.h"
-#include <stddef.h>
-using namespace llvm;
-
-#if USE_OPROFILE
-
-#include <opagent.h>
-
-namespace {
-
-class OProfileJITEventListener : public JITEventListener {
-  op_agent_t Agent;
-public:
-  OProfileJITEventListener();
-  ~OProfileJITEventListener();
-
-  virtual void NotifyFunctionEmitted(const Function &F,
-                                     void *FnStart, size_t FnSize,
-                                     const EmittedFunctionDetails &Details);
-  virtual void NotifyFreeingMachineCode(void *OldPtr);
-};
-
-OProfileJITEventListener::OProfileJITEventListener()
-    : Agent(op_open_agent()) {
-  if (Agent == NULL) {
-    const std::string err_str = sys::StrError();
-    DEBUG(dbgs() << "Failed to connect to OProfile agent: " << err_str << "\n");
-  } else {
-    DEBUG(dbgs() << "Connected to OProfile agent.\n");
-  }
-}
-
-OProfileJITEventListener::~OProfileJITEventListener() {
-  if (Agent != NULL) {
-    if (op_close_agent(Agent) == -1) {
-      const std::string err_str = sys::StrError();
-      DEBUG(dbgs() << "Failed to disconnect from OProfile agent: "
-                   << err_str << "\n");
-    } else {
-      DEBUG(dbgs() << "Disconnected from OProfile agent.\n");
-    }
-  }
-}
-
-class FilenameCache {
-  // Holds the filename of each Scope, so that we can pass a null-terminated
-  // string into oprofile.  Use an AssertingVH rather than a ValueMap because we
-  // shouldn't be modifying any MDNodes while this map is alive.
-  DenseMap<AssertingVH<MDNode>, std::string> Filenames;
-
- public:
-  const char *getFilename(MDNode *Scope) {
-    std::string &Filename = Filenames[Scope];
-    if (Filename.empty()) {
-      Filename = DIScope(Scope).getFilename();
-    }
-    return Filename.c_str();
-  }
-};
-
-static debug_line_info LineStartToOProfileFormat(
-    const MachineFunction &MF, FilenameCache &Filenames,
-    uintptr_t Address, DebugLoc Loc) {
-  debug_line_info Result;
-  Result.vma = Address;
-  Result.lineno = Loc.getLine();
-  Result.filename = Filenames.getFilename(
-    Loc.getScope(MF.getFunction()->getContext()));
-  DEBUG(dbgs() << "Mapping " << reinterpret_cast<void*>(Result.vma) << " to "
-               << Result.filename << ":" << Result.lineno << "\n");
-  return Result;
-}
-
-// Adds the just-emitted function to the symbol table.
-void OProfileJITEventListener::NotifyFunctionEmitted(
-    const Function &F, void *FnStart, size_t FnSize,
-    const EmittedFunctionDetails &Details) {
-  assert(F.hasName() && FnStart != 0 && "Bad symbol to add");
-  if (op_write_native_code(Agent, F.getName().data(),
-                           reinterpret_cast<uint64_t>(FnStart),
-                           FnStart, FnSize) == -1) {
-    DEBUG(dbgs() << "Failed to tell OProfile about native function "
-          << F.getName() << " at ["
-          << FnStart << "-" << ((char*)FnStart + FnSize) << "]\n");
-    return;
-  }
-
-  if (!Details.LineStarts.empty()) {
-    // Now we convert the line number information from the address/DebugLoc
-    // format in Details to the address/filename/lineno format that OProfile
-    // expects.  Note that OProfile 0.9.4 has a bug that causes it to ignore
-    // line numbers for addresses above 4G.
-    FilenameCache Filenames;
-    std::vector<debug_line_info> LineInfo;
-    LineInfo.reserve(1 + Details.LineStarts.size());
-
-    DebugLoc FirstLoc = Details.LineStarts[0].Loc;
-    assert(!FirstLoc.isUnknown()
-           && "LineStarts should not contain unknown DebugLocs");
-    MDNode *FirstLocScope = FirstLoc.getScope(F.getContext());
-    DISubprogram FunctionDI = getDISubprogram(FirstLocScope);
-    if (FunctionDI.Verify()) {
-      // If we have debug info for the function itself, use that as the line
-      // number of the first several instructions.  Otherwise, after filling
-      // LineInfo, we'll adjust the address of the first line number to point at
-      // the start of the function.
-      debug_line_info line_info;
-      line_info.vma = reinterpret_cast<uintptr_t>(FnStart);
-      line_info.lineno = FunctionDI.getLineNumber();
-      line_info.filename = Filenames.getFilename(FirstLocScope);
-      LineInfo.push_back(line_info);
-    }
-
-    for (std::vector<EmittedFunctionDetails::LineStart>::const_iterator
-           I = Details.LineStarts.begin(), E = Details.LineStarts.end();
-         I != E; ++I) {
-      LineInfo.push_back(LineStartToOProfileFormat(
-                           *Details.MF, Filenames, I->Address, I->Loc));
-    }
-
-    // In case the function didn't have line info of its own, adjust the first
-    // line info's address to include the start of the function.
-    LineInfo[0].vma = reinterpret_cast<uintptr_t>(FnStart);
-
-    if (op_write_debug_line_info(Agent, FnStart,
-                                 LineInfo.size(), &*LineInfo.begin()) == -1) {
-      DEBUG(dbgs()
-            << "Failed to tell OProfile about line numbers for native function "
-            << F.getName() << " at ["
-            << FnStart << "-" << ((char*)FnStart + FnSize) << "]\n");
-    }
-  }
-}
-
-// Removes the being-deleted function from the symbol table.
-void OProfileJITEventListener::NotifyFreeingMachineCode(void *FnStart) {
-  assert(FnStart && "Invalid function pointer");
-  if (op_unload_native_code(Agent, reinterpret_cast<uint64_t>(FnStart)) == -1) {
-    DEBUG(dbgs()
-          << "Failed to tell OProfile about unload of native function at "
-          << FnStart << "\n");
-  }
-}
-
-}  // anonymous namespace.
-
-namespace llvm {
-JITEventListener *createOProfileJITEventListener() {
-  return new OProfileJITEventListener;
-}
-}
-
-#else  // USE_OPROFILE
-
-namespace llvm {
-// By defining this to return NULL, we can let clients call it unconditionally,
-// even if they haven't configured with the OProfile libraries.
-JITEventListener *createOProfileJITEventListener() {
-  return NULL;
-}
-}  // namespace llvm
-
-#endif  // USE_OPROFILE
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/ExecutionEngine/MCJIT/Intercept.cpp
--- a/head/contrib/llvm/lib/ExecutionEngine/MCJIT/Intercept.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,162 +0,0 @@
-//===-- Intercept.cpp - System function interception routines -------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// If a function call occurs to an external function, the JIT is designed to use
-// the dynamic loader interface to find a function to call.  This is useful for
-// calling system calls and library functions that are not available in LLVM.
-// Some system calls, however, need to be handled specially.  For this reason,
-// we intercept some of them here and use our own stubs to handle them.
-//
-//===----------------------------------------------------------------------===//
-
-#include "MCJIT.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/DynamicLibrary.h"
-#include "llvm/Config/config.h"
-using namespace llvm;
-
-// AtExitHandlers - List of functions to call when the program exits,
-// registered with the atexit() library function.
-static std::vector<void (*)()> AtExitHandlers;
-
-/// runAtExitHandlers - Run any functions registered by the program's
-/// calls to atexit(3), which we intercept and store in
-/// AtExitHandlers.
-///
-static void runAtExitHandlers() {
-  while (!AtExitHandlers.empty()) {
-    void (*Fn)() = AtExitHandlers.back();
-    AtExitHandlers.pop_back();
-    Fn();
-  }
-}
-
-//===----------------------------------------------------------------------===//
-// Function stubs that are invoked instead of certain library calls
-//===----------------------------------------------------------------------===//
-
-// Force the following functions to be linked in to anything that uses the
-// JIT. This is a hack designed to work around the all-too-clever Glibc
-// strategy of making these functions work differently when inlined vs. when
-// not inlined, and hiding their real definitions in a separate archive file
-// that the dynamic linker can't see. For more info, search for
-// 'libc_nonshared.a' on Google, or read http://llvm.org/PR274.
-#if defined(__linux__)
-#if defined(HAVE_SYS_STAT_H)
-#include <sys/stat.h>
-#endif
-#include <fcntl.h>
-#include <unistd.h>
-/* stat functions are redirecting to __xstat with a version number.  On x86-64
- * linking with libc_nonshared.a and -Wl,--export-dynamic doesn't make 'stat'
- * available as an exported symbol, so we have to add it explicitly.
- */
-namespace {
-class StatSymbols {
-public:
-  StatSymbols() {
-    sys::DynamicLibrary::AddSymbol("stat", (void*)(intptr_t)stat);
-    sys::DynamicLibrary::AddSymbol("fstat", (void*)(intptr_t)fstat);
-    sys::DynamicLibrary::AddSymbol("lstat", (void*)(intptr_t)lstat);
-    sys::DynamicLibrary::AddSymbol("stat64", (void*)(intptr_t)stat64);
-    sys::DynamicLibrary::AddSymbol("\x1stat64", (void*)(intptr_t)stat64);
-    sys::DynamicLibrary::AddSymbol("\x1open64", (void*)(intptr_t)open64);
-    sys::DynamicLibrary::AddSymbol("\x1lseek64", (void*)(intptr_t)lseek64);
-    sys::DynamicLibrary::AddSymbol("fstat64", (void*)(intptr_t)fstat64);
-    sys::DynamicLibrary::AddSymbol("lstat64", (void*)(intptr_t)lstat64);
-    sys::DynamicLibrary::AddSymbol("atexit", (void*)(intptr_t)atexit);
-    sys::DynamicLibrary::AddSymbol("mknod", (void*)(intptr_t)mknod);
-  }
-};
-}
-static StatSymbols initStatSymbols;
-#endif // __linux__
-
-// jit_exit - Used to intercept the "exit" library call.
-static void jit_exit(int Status) {
-  runAtExitHandlers();   // Run atexit handlers...
-  exit(Status);
-}
-
-// jit_atexit - Used to intercept the "atexit" library call.
-static int jit_atexit(void (*Fn)()) {
-  AtExitHandlers.push_back(Fn);    // Take note of atexit handler...
-  return 0;  // Always successful
-}
-
-static int jit_noop() {
-  return 0;
-}
-
-//===----------------------------------------------------------------------===//
-//
-/// getPointerToNamedFunction - This method returns the address of the specified
-/// function by using the dynamic loader interface.  As such it is only useful
-/// for resolving library symbols, not code generated symbols.
-///
-void *MCJIT::getPointerToNamedFunction(const std::string &Name,
-                                       bool AbortOnFailure) {
-  if (!isSymbolSearchingDisabled()) {
-    // Check to see if this is one of the functions we want to intercept.  Note,
-    // we cast to intptr_t here to silence a -pedantic warning that complains
-    // about casting a function pointer to a normal pointer.
-    if (Name == "exit") return (void*)(intptr_t)&jit_exit;
-    if (Name == "atexit") return (void*)(intptr_t)&jit_atexit;
-
-    // We should not invoke parent's ctors/dtors from generated main()!
-    // On Mingw and Cygwin, the symbol __main is resolved to
-    // callee's(eg. tools/lli) one, to invoke wrong duplicated ctors
-    // (and register wrong callee's dtors with atexit(3)).
-    // We expect ExecutionEngine::runStaticConstructorsDestructors()
-    // is called before ExecutionEngine::runFunctionAsMain() is called.
-    if (Name == "__main") return (void*)(intptr_t)&jit_noop;
-
-    const char *NameStr = Name.c_str();
-    // If this is an asm specifier, skip the sentinal.
-    if (NameStr[0] == 1) ++NameStr;
-
-    // If it's an external function, look it up in the process image...
-    void *Ptr = sys::DynamicLibrary::SearchForAddressOfSymbol(NameStr);
-    if (Ptr) return Ptr;
-
-    // If it wasn't found and if it starts with an underscore ('_') character,
-    // and has an asm specifier, try again without the underscore.
-    if (Name[0] == 1 && NameStr[0] == '_') {
-      Ptr = sys::DynamicLibrary::SearchForAddressOfSymbol(NameStr+1);
-      if (Ptr) return Ptr;
-    }
-
-    // Darwin/PPC adds $LDBLStub suffixes to various symbols like printf.  These
-    // are references to hidden visibility symbols that dlsym cannot resolve.
-    // If we have one of these, strip off $LDBLStub and try again.
-#if defined(__APPLE__) && defined(__ppc__)
-    if (Name.size() > 9 && Name[Name.size()-9] == '$' &&
-        memcmp(&Name[Name.size()-8], "LDBLStub", 8) == 0) {
-      // First try turning $LDBLStub into $LDBL128. If that fails, strip it off.
-      // This mirrors logic in libSystemStubs.a.
-      std::string Prefix = std::string(Name.begin(), Name.end()-9);
-      if (void *Ptr = getPointerToNamedFunction(Prefix+"$LDBL128", false))
-        return Ptr;
-      if (void *Ptr = getPointerToNamedFunction(Prefix, false))
-        return Ptr;
-    }
-#endif
-  }
-
-  /// If a LazyFunctionCreator is installed, use it to get/create the function.
-  if (LazyFunctionCreator)
-    if (void *RP = LazyFunctionCreator(Name))
-      return RP;
-
-  if (AbortOnFailure) {
-    report_fatal_error("Program used external function '"+Name+
-                      "' which could not be resolved!");
-  }
-  return 0;
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/MC/ELFObjectWriter.h
--- a/head/contrib/llvm/lib/MC/ELFObjectWriter.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,446 +0,0 @@
-//===- lib/MC/ELFObjectWriter.h - ELF File Writer -------------------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements ELF object file writer information.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_MC_ELFOBJECTWRITER_H
-#define LLVM_MC_ELFOBJECTWRITER_H
-
-#include "MCELF.h"
-#include "llvm/ADT/OwningPtr.h"
-#include "llvm/ADT/SmallPtrSet.h"
-#include "llvm/ADT/SmallString.h"
-#include "llvm/ADT/STLExtras.h"
-#include "llvm/MC/MCAssembler.h"
-#include "llvm/MC/MCELFObjectWriter.h"
-#include "llvm/MC/MCELFSymbolFlags.h"
-#include "llvm/MC/MCObjectWriter.h"
-#include "llvm/MC/MCExpr.h"
-#include "llvm/MC/MCSymbol.h"
-
-#include <vector>
-
-namespace llvm {
-
-class MCSection;
-class MCDataFragment;
-class MCSectionELF;
-
-class ELFObjectWriter : public MCObjectWriter {
-  protected:
-
-    static bool isFixupKindPCRel(const MCAssembler &Asm, unsigned Kind);
-    static bool RelocNeedsGOT(MCSymbolRefExpr::VariantKind Variant);
-    static uint64_t SymbolValue(MCSymbolData &Data, const MCAsmLayout &Layout);
-    static bool isInSymtab(const MCAssembler &Asm, const MCSymbolData &Data,
-                           bool Used, bool Renamed);
-    static bool isLocal(const MCSymbolData &Data, bool isSignature,
-                        bool isUsedInReloc);
-    static bool IsELFMetaDataSection(const MCSectionData &SD);
-    static uint64_t DataSectionSize(const MCSectionData &SD);
-    static uint64_t GetSectionFileSize(const MCAsmLayout &Layout,
-                                       const MCSectionData &SD);
-    static uint64_t GetSectionAddressSize(const MCAsmLayout &Layout,
-                                          const MCSectionData &SD);
-
-    void WriteDataSectionData(MCAssembler &Asm,
-                              const MCAsmLayout &Layout,
-                              const MCSectionELF &Section);
-
-    /*static bool isFixupKindX86RIPRel(unsigned Kind) {
-      return Kind == X86::reloc_riprel_4byte ||
-        Kind == X86::reloc_riprel_4byte_movq_load;
-    }*/
-
-    /// ELFSymbolData - Helper struct for containing some precomputed
-    /// information on symbols.
-    struct ELFSymbolData {
-      MCSymbolData *SymbolData;
-      uint64_t StringIndex;
-      uint32_t SectionIndex;
-
-      // Support lexicographic sorting.
-      bool operator<(const ELFSymbolData &RHS) const {
-        if (MCELF::GetType(*SymbolData) == ELF::STT_FILE)
-          return true;
-        if (MCELF::GetType(*RHS.SymbolData) == ELF::STT_FILE)
-          return false;
-        return SymbolData->getSymbol().getName() <
-               RHS.SymbolData->getSymbol().getName();
-      }
-    };
-
-    /// @name Relocation Data
-    /// @{
-
-    struct ELFRelocationEntry {
-      // Make these big enough for both 32-bit and 64-bit
-      uint64_t r_offset;
-      int Index;
-      unsigned Type;
-      const MCSymbol *Symbol;
-      uint64_t r_addend;
-
-      ELFRelocationEntry()
-        : r_offset(0), Index(0), Type(0), Symbol(0), r_addend(0) {}
-
-      ELFRelocationEntry(uint64_t RelocOffset, int Idx,
-                         unsigned RelType, const MCSymbol *Sym,
-                         uint64_t Addend)
-        : r_offset(RelocOffset), Index(Idx), Type(RelType),
-          Symbol(Sym), r_addend(Addend) {}
-
-      // Support lexicographic sorting.
-      bool operator<(const ELFRelocationEntry &RE) const {
-        return RE.r_offset < r_offset;
-      }
-    };
-
-    /// The target specific ELF writer instance.
-    llvm::OwningPtr<MCELFObjectTargetWriter> TargetObjectWriter;
-
-    SmallPtrSet<const MCSymbol *, 16> UsedInReloc;
-    SmallPtrSet<const MCSymbol *, 16> WeakrefUsedInReloc;
-    DenseMap<const MCSymbol *, const MCSymbol *> Renames;
-
-    llvm::DenseMap<const MCSectionData*,
-                   std::vector<ELFRelocationEntry> > Relocations;
-    DenseMap<const MCSection*, uint64_t> SectionStringTableIndex;
-
-    /// @}
-    /// @name Symbol Table Data
-    /// @{
-
-    SmallString<256> StringTable;
-    std::vector<ELFSymbolData> LocalSymbolData;
-    std::vector<ELFSymbolData> ExternalSymbolData;
-    std::vector<ELFSymbolData> UndefinedSymbolData;
-
-    /// @}
-
-    bool NeedsGOT;
-
-    bool NeedsSymtabShndx;
-
-    // This holds the symbol table index of the last local symbol.
-    unsigned LastLocalSymbolIndex;
-    // This holds the .strtab section index.
-    unsigned StringTableIndex;
-    // This holds the .symtab section index.
-    unsigned SymbolTableIndex;
-
-    unsigned ShstrtabIndex;
-
-
-    virtual const MCSymbol *SymbolToReloc(const MCAssembler &Asm,
-                                          const MCValue &Target,
-                                          const MCFragment &F,
-                                          const MCFixup &Fixup,
-                                          bool IsPCRel) const;
-
-    // For arch-specific emission of explicit reloc symbol
-    virtual const MCSymbol *ExplicitRelSym(const MCAssembler &Asm,
-                                           const MCValue &Target,
-                                           const MCFragment &F,
-                                           const MCFixup &Fixup,
-                                           bool IsPCRel) const {
-      return NULL;
-    }
-
-    bool is64Bit() const { return TargetObjectWriter->is64Bit(); }
-    bool hasRelocationAddend() const {
-      return TargetObjectWriter->hasRelocationAddend();
-    }
-
-  public:
-    ELFObjectWriter(MCELFObjectTargetWriter *MOTW,
-                    raw_ostream &_OS, bool IsLittleEndian)
-      : MCObjectWriter(_OS, IsLittleEndian),
-        TargetObjectWriter(MOTW),
-        NeedsGOT(false), NeedsSymtabShndx(false){
-    }
-
-    virtual ~ELFObjectWriter();
-
-    void WriteWord(uint64_t W) {
-      if (is64Bit())
-        Write64(W);
-      else
-        Write32(W);
-    }
-
-    void StringLE16(char *buf, uint16_t Value) {
-      buf[0] = char(Value >> 0);
-      buf[1] = char(Value >> 8);
-    }
-
-    void StringLE32(char *buf, uint32_t Value) {
-      StringLE16(buf, uint16_t(Value >> 0));
-      StringLE16(buf + 2, uint16_t(Value >> 16));
-    }
-
-    void StringLE64(char *buf, uint64_t Value) {
-      StringLE32(buf, uint32_t(Value >> 0));
-      StringLE32(buf + 4, uint32_t(Value >> 32));
-    }
-
-    void StringBE16(char *buf ,uint16_t Value) {
-      buf[0] = char(Value >> 8);
-      buf[1] = char(Value >> 0);
-    }
-
-    void StringBE32(char *buf, uint32_t Value) {
-      StringBE16(buf, uint16_t(Value >> 16));
-      StringBE16(buf + 2, uint16_t(Value >> 0));
-    }
-
-    void StringBE64(char *buf, uint64_t Value) {
-      StringBE32(buf, uint32_t(Value >> 32));
-      StringBE32(buf + 4, uint32_t(Value >> 0));
-    }
-
-    void String8(MCDataFragment &F, uint8_t Value) {
-      char buf[1];
-      buf[0] = Value;
-      F.getContents() += StringRef(buf, 1);
-    }
-
-    void String16(MCDataFragment &F, uint16_t Value) {
-      char buf[2];
-      if (isLittleEndian())
-        StringLE16(buf, Value);
-      else
-        StringBE16(buf, Value);
-      F.getContents() += StringRef(buf, 2);
-    }
-
-    void String32(MCDataFragment &F, uint32_t Value) {
-      char buf[4];
-      if (isLittleEndian())
-        StringLE32(buf, Value);
-      else
-        StringBE32(buf, Value);
-      F.getContents() += StringRef(buf, 4);
-    }
-
-    void String64(MCDataFragment &F, uint64_t Value) {
-      char buf[8];
-      if (isLittleEndian())
-        StringLE64(buf, Value);
-      else
-        StringBE64(buf, Value);
-      F.getContents() += StringRef(buf, 8);
-    }
-
-    virtual void WriteHeader(uint64_t SectionDataSize, unsigned NumberOfSections);
-
-    /// Default e_flags = 0
-    virtual void WriteEFlags() { Write32(0); }
-
-    virtual void WriteSymbolEntry(MCDataFragment *SymtabF, MCDataFragment *ShndxF,
-                          uint64_t name, uint8_t info,
-                          uint64_t value, uint64_t size,
-                          uint8_t other, uint32_t shndx,
-                          bool Reserved);
-
-    virtual void WriteSymbol(MCDataFragment *SymtabF,  MCDataFragment *ShndxF,
-                     ELFSymbolData &MSD,
-                     const MCAsmLayout &Layout);
-
-    typedef DenseMap<const MCSectionELF*, uint32_t> SectionIndexMapTy;
-    virtual void WriteSymbolTable(MCDataFragment *SymtabF, MCDataFragment *ShndxF,
-                          const MCAssembler &Asm,
-                          const MCAsmLayout &Layout,
-                          const SectionIndexMapTy &SectionIndexMap);
-
-    virtual void RecordRelocation(const MCAssembler &Asm, const MCAsmLayout &Layout,
-                                  const MCFragment *Fragment, const MCFixup &Fixup,
-                                  MCValue Target, uint64_t &FixedValue);
-
-    virtual uint64_t getSymbolIndexInSymbolTable(const MCAssembler &Asm,
-                                         const MCSymbol *S);
-
-    // Map from a group section to the signature symbol
-    typedef DenseMap<const MCSectionELF*, const MCSymbol*> GroupMapTy;
-    // Map from a signature symbol to the group section
-    typedef DenseMap<const MCSymbol*, const MCSectionELF*> RevGroupMapTy;
-    // Map from a section to the section with the relocations
-    typedef DenseMap<const MCSectionELF*, const MCSectionELF*> RelMapTy;
-    // Map from a section to its offset
-    typedef DenseMap<const MCSectionELF*, uint64_t> SectionOffsetMapTy;
-
-    /// ComputeSymbolTable - Compute the symbol table data
-    ///
-    /// \param StringTable [out] - The string table data.
-    /// \param StringIndexMap [out] - Map from symbol names to offsets in the
-    /// string table.
-    virtual void ComputeSymbolTable(MCAssembler &Asm,
-                            const SectionIndexMapTy &SectionIndexMap,
-                                    RevGroupMapTy RevGroupMap,
-                                    unsigned NumRegularSections);
-
-    virtual void ComputeIndexMap(MCAssembler &Asm,
-                                 SectionIndexMapTy &SectionIndexMap,
-                                 const RelMapTy &RelMap);
-
-    void CreateRelocationSections(MCAssembler &Asm, MCAsmLayout &Layout,
-                                  RelMapTy &RelMap);
-
-    void WriteRelocations(MCAssembler &Asm, MCAsmLayout &Layout,
-                          const RelMapTy &RelMap);
-
-    virtual void CreateMetadataSections(MCAssembler &Asm, MCAsmLayout &Layout,
-                                        SectionIndexMapTy &SectionIndexMap,
-                                        const RelMapTy &RelMap);
-
-    // Create the sections that show up in the symbol table. Currently
-    // those are the .note.GNU-stack section and the group sections.
-    virtual void CreateIndexedSections(MCAssembler &Asm, MCAsmLayout &Layout,
-                                       GroupMapTy &GroupMap,
-                                       RevGroupMapTy &RevGroupMap,
-                                       SectionIndexMapTy &SectionIndexMap,
-                                       const RelMapTy &RelMap);
-
-    virtual void ExecutePostLayoutBinding(MCAssembler &Asm,
-                                          const MCAsmLayout &Layout);
-
-    void WriteSectionHeader(MCAssembler &Asm, const GroupMapTy &GroupMap,
-                            const MCAsmLayout &Layout,
-                            const SectionIndexMapTy &SectionIndexMap,
-                            const SectionOffsetMapTy &SectionOffsetMap);
-
-    void ComputeSectionOrder(MCAssembler &Asm,
-                             std::vector<const MCSectionELF*> &Sections);
-
-    virtual void WriteSecHdrEntry(uint32_t Name, uint32_t Type, uint64_t Flags,
-                          uint64_t Address, uint64_t Offset,
-                          uint64_t Size, uint32_t Link, uint32_t Info,
-                          uint64_t Alignment, uint64_t EntrySize);
-
-    virtual void WriteRelocationsFragment(const MCAssembler &Asm,
-                                          MCDataFragment *F,
-                                          const MCSectionData *SD);
-
-    virtual bool
-    IsSymbolRefDifferenceFullyResolvedImpl(const MCAssembler &Asm,
-                                           const MCSymbolData &DataA,
-                                           const MCFragment &FB,
-                                           bool InSet,
-                                           bool IsPCRel) const;
-
-    virtual void WriteObject(MCAssembler &Asm, const MCAsmLayout &Layout);
-    virtual void WriteSection(MCAssembler &Asm,
-                      const SectionIndexMapTy &SectionIndexMap,
-                      uint32_t GroupSymbolIndex,
-                      uint64_t Offset, uint64_t Size, uint64_t Alignment,
-                      const MCSectionELF &Section);
-
-  protected:
-    virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
-                                  bool IsPCRel, bool IsRelocWithSymbol,
-                                  int64_t Addend) = 0;
-    virtual void adjustFixupOffset(const MCFixup &Fixup, uint64_t &RelocOffset) { }
-  };
-
-  //===- X86ELFObjectWriter -------------------------------------------===//
-
-  class X86ELFObjectWriter : public ELFObjectWriter {
-  public:
-    X86ELFObjectWriter(MCELFObjectTargetWriter *MOTW,
-                       raw_ostream &_OS,
-                       bool IsLittleEndian);
-
-    virtual ~X86ELFObjectWriter();
-  protected:
-    virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
-                                  bool IsPCRel, bool IsRelocWithSymbol,
-                                  int64_t Addend);
-  };
-
-
-  //===- ARMELFObjectWriter -------------------------------------------===//
-
-  class ARMELFObjectWriter : public ELFObjectWriter {
-  public:
-    // FIXME: MCAssembler can't yet return the Subtarget,
-    enum { DefaultEABIVersion = 0x05000000U };
-
-    ARMELFObjectWriter(MCELFObjectTargetWriter *MOTW,
-                       raw_ostream &_OS,
-                       bool IsLittleEndian);
-
-    virtual ~ARMELFObjectWriter();
-
-    virtual void WriteEFlags();
-  protected:
-    virtual const MCSymbol *ExplicitRelSym(const MCAssembler &Asm,
-                                           const MCValue &Target,
-                                           const MCFragment &F,
-                                           const MCFixup &Fixup,
-                                           bool IsPCRel) const;
-
-    virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
-                                  bool IsPCRel, bool IsRelocWithSymbol,
-                                  int64_t Addend);
-  private:
-    unsigned GetRelocTypeInner(const MCValue &Target,
-                               const MCFixup &Fixup, bool IsPCRel) const;
-    
-  };
-
-  //===- PPCELFObjectWriter -------------------------------------------===//
-
-  class PPCELFObjectWriter : public ELFObjectWriter {
-  public:
-    PPCELFObjectWriter(MCELFObjectTargetWriter *MOTW,
-                          raw_ostream &_OS,
-                          bool IsLittleEndian);
-
-    virtual ~PPCELFObjectWriter();
-  protected:
-    virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
-                                  bool IsPCRel, bool IsRelocWithSymbol,
-                                  int64_t Addend);
-    virtual void adjustFixupOffset(const MCFixup &Fixup, uint64_t &RelocOffset);
-  };
-
-  //===- MBlazeELFObjectWriter -------------------------------------------===//
-
-  class MBlazeELFObjectWriter : public ELFObjectWriter {
-  public:
-    MBlazeELFObjectWriter(MCELFObjectTargetWriter *MOTW,
-                          raw_ostream &_OS,
-                          bool IsLittleEndian);
-
-    virtual ~MBlazeELFObjectWriter();
-  protected:
-    virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
-                                  bool IsPCRel, bool IsRelocWithSymbol,
-                                  int64_t Addend);
-  };
-
-  //===- MipsELFObjectWriter -------------------------------------------===//
-
-  class MipsELFObjectWriter : public ELFObjectWriter {
-  public:
-    MipsELFObjectWriter(MCELFObjectTargetWriter *MOTW,
-                        raw_ostream &_OS,
-                        bool IsLittleEndian);
-
-    virtual ~MipsELFObjectWriter();
-  protected:
-    virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
-                                  bool IsPCRel, bool IsRelocWithSymbol,
-                                  int64_t Addend);
-  };
-}
-
-#endif
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/MC/MCELFStreamer.h
--- a/head/contrib/llvm/lib/MC/MCELFStreamer.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,141 +0,0 @@
-//===- lib/MC/MCELFStreamer.h - ELF Object Output -------------------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file assembles .s files and emits ELF .o object files.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_MC_MCELFSTREAMER_H
-#define LLVM_MC_MCELFSTREAMER_H
-
-#include "llvm/ADT/SmallPtrSet.h"
-#include "llvm/ADT/DenseMap.h"
-#include "llvm/MC/MCAssembler.h"
-#include "llvm/MC/MCContext.h"
-#include "llvm/MC/MCObjectStreamer.h"
-#include "llvm/MC/MCSectionELF.h"
-
-namespace llvm {
-
-class MCELFStreamer : public MCObjectStreamer {
-public:
-  MCELFStreamer(MCContext &Context, MCAsmBackend &TAB,
-                  raw_ostream &OS, MCCodeEmitter *Emitter)
-    : MCObjectStreamer(Context, TAB, OS, Emitter) {}
-
-  MCELFStreamer(MCContext &Context, MCAsmBackend &TAB,
-                raw_ostream &OS, MCCodeEmitter *Emitter,
-                MCAssembler *Assembler)
-    : MCObjectStreamer(Context, TAB, OS, Emitter, Assembler) {}
-
-
-  ~MCELFStreamer() {}
-
-  /// @name MCStreamer Interface
-  /// @{
-
-  virtual void InitSections();
-  virtual void ChangeSection(const MCSection *Section);
-  virtual void EmitLabel(MCSymbol *Symbol);
-  virtual void EmitAssemblerFlag(MCAssemblerFlag Flag);
-  virtual void EmitThumbFunc(MCSymbol *Func);
-  virtual void EmitAssignment(MCSymbol *Symbol, const MCExpr *Value);
-  virtual void EmitWeakReference(MCSymbol *Alias, const MCSymbol *Symbol);
-  virtual void EmitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute);
-  virtual void EmitSymbolDesc(MCSymbol *Symbol, unsigned DescValue) {
-    assert(0 && "ELF doesn't support this directive");
-  }
-  virtual void EmitCommonSymbol(MCSymbol *Symbol, uint64_t Size,
-                                unsigned ByteAlignment);
-  virtual void BeginCOFFSymbolDef(const MCSymbol *Symbol) {
-    assert(0 && "ELF doesn't support this directive");
-  }
-
-  virtual void EmitCOFFSymbolStorageClass(int StorageClass) {
-    assert(0 && "ELF doesn't support this directive");
-  }
-
-  virtual void EmitCOFFSymbolType(int Type) {
-    assert(0 && "ELF doesn't support this directive");
-  }
-
-  virtual void EndCOFFSymbolDef() {
-    assert(0 && "ELF doesn't support this directive");
-  }
-
-  virtual void EmitELFSize(MCSymbol *Symbol, const MCExpr *Value) {
-     MCSymbolData &SD = getAssembler().getOrCreateSymbolData(*Symbol);
-     SD.setSize(Value);
-  }
-
-  virtual void EmitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size,
-                                     unsigned ByteAlignment);
-
-  virtual void EmitZerofill(const MCSection *Section, MCSymbol *Symbol = 0,
-                            unsigned Size = 0, unsigned ByteAlignment = 0) {
-    assert(0 && "ELF doesn't support this directive");
-  }
-  virtual void EmitTBSSSymbol(const MCSection *Section, MCSymbol *Symbol,
-                              uint64_t Size, unsigned ByteAlignment = 0) {
-    assert(0 && "ELF doesn't support this directive");
-  }
-  virtual void EmitBytes(StringRef Data, unsigned AddrSpace);
-  virtual void EmitValueToAlignment(unsigned ByteAlignment, int64_t Value = 0,
-                                    unsigned ValueSize = 1,
-                                    unsigned MaxBytesToEmit = 0);
-  virtual void EmitCodeAlignment(unsigned ByteAlignment,
-                                 unsigned MaxBytesToEmit = 0);
-
-  virtual void EmitFileDirective(StringRef Filename);
-
-  virtual void Finish();
-
-private:
-  virtual void EmitInstToFragment(const MCInst &Inst);
-  virtual void EmitInstToData(const MCInst &Inst);
-
-  void fixSymbolsInTLSFixups(const MCExpr *expr);
-
-  struct LocalCommon {
-    MCSymbolData *SD;
-    uint64_t Size;
-    unsigned ByteAlignment;
-  };
-  std::vector<LocalCommon> LocalCommons;
-
-  SmallPtrSet<MCSymbol *, 16> BindingExplicitlySet;
-  /// @}
-  void SetSection(StringRef Section, unsigned Type, unsigned Flags,
-                  SectionKind Kind) {
-    SwitchSection(getContext().getELFSection(Section, Type, Flags, Kind));
-  }
-
-  void SetSectionData() {
-    SetSection(".data", ELF::SHT_PROGBITS,
-               ELF::SHF_WRITE |ELF::SHF_ALLOC,
-               SectionKind::getDataRel());
-    EmitCodeAlignment(4, 0);
-  }
-  void SetSectionText() {
-    SetSection(".text", ELF::SHT_PROGBITS,
-               ELF::SHF_EXECINSTR |
-               ELF::SHF_ALLOC, SectionKind::getText());
-    EmitCodeAlignment(4, 0);
-  }
-  void SetSectionBss() {
-    SetSection(".bss", ELF::SHT_NOBITS,
-               ELF::SHF_WRITE |
-               ELF::SHF_ALLOC, SectionKind::getBSS());
-    EmitCodeAlignment(4, 0);
-  }
-};
-
-} // end llvm namespace
-
-#endif
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/MC/MCLoggingStreamer.cpp
--- a/head/contrib/llvm/lib/MC/MCLoggingStreamer.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,250 +0,0 @@
-//===- lib/MC/MCLoggingStreamer.cpp - API Logging Streamer ----------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#include "llvm/MC/MCStreamer.h"
-#include "llvm/ADT/OwningPtr.h"
-#include "llvm/ADT/Twine.h"
-#include "llvm/Support/raw_ostream.h"
-using namespace llvm;
-
-namespace {
-
-class MCLoggingStreamer : public MCStreamer {
-  llvm::OwningPtr<MCStreamer> Child;
-  
-  raw_ostream &OS;
-
-public:
-  MCLoggingStreamer(MCStreamer *_Child, raw_ostream &_OS)
-    : MCStreamer(_Child->getContext()), Child(_Child), OS(_OS) {}
-
-  void LogCall(const char *Function) {
-    OS << Function << "\n";
-  }
-
-  void LogCall(const char *Function, const Twine &Message) {
-    OS << Function << ": " << Message << "\n";
-  }
-
-  virtual bool isVerboseAsm() const { return Child->isVerboseAsm(); }
-  
-  virtual bool hasRawTextSupport() const { return Child->hasRawTextSupport(); }
-
-  virtual raw_ostream &GetCommentOS() { return Child->GetCommentOS(); }
-
-  virtual void AddComment(const Twine &T) {
-    LogCall("AddComment", T);
-    return Child->AddComment(T);
-  }
-
-  virtual void AddBlankLine() {
-    LogCall("AddBlankLine");
-    return Child->AddBlankLine();
-  }
-
-  virtual void ChangeSection(const MCSection *Section) {
-    LogCall("ChangeSection");
-    return Child->ChangeSection(Section);
-  }
-
-  virtual void InitSections() {
-    LogCall("InitSections");
-    return Child->InitSections();
-  }
-
-  virtual void EmitLabel(MCSymbol *Symbol) {
-    LogCall("EmitLabel");
-    return Child->EmitLabel(Symbol);
-  }
-
-  virtual void EmitAssemblerFlag(MCAssemblerFlag Flag) {
-    LogCall("EmitAssemblerFlag");
-    return Child->EmitAssemblerFlag(Flag);
-  }
-
-  virtual void EmitThumbFunc(MCSymbol *Func) {
-    LogCall("EmitThumbFunc");
-    return Child->EmitThumbFunc(Func);
-  }
-
-  virtual void EmitAssignment(MCSymbol *Symbol, const MCExpr *Value) {
-    LogCall("EmitAssignment");
-    return Child->EmitAssignment(Symbol, Value);
-  }
-
-  virtual void EmitWeakReference(MCSymbol *Alias, const MCSymbol *Symbol) {
-    LogCall("EmitWeakReference");
-    return Child->EmitWeakReference(Alias, Symbol);
-  }
-
-  virtual void EmitDwarfAdvanceLineAddr(int64_t LineDelta,
-                                        const MCSymbol *LastLabel,
-                                        const MCSymbol *Label,
-                                        unsigned PointerSize) {
-    LogCall("EmitDwarfAdvanceLineAddr");
-    return Child->EmitDwarfAdvanceLineAddr(LineDelta, LastLabel, Label,
-                                           PointerSize);
-  }
-
-  virtual void EmitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute) {
-    LogCall("EmitSymbolAttribute");
-    return Child->EmitSymbolAttribute(Symbol, Attribute);
-  }
-
-  virtual void EmitSymbolDesc(MCSymbol *Symbol, unsigned DescValue) {
-    LogCall("EmitSymbolDesc");
-    return Child->EmitSymbolDesc(Symbol, DescValue);
-  }
-
-  virtual void BeginCOFFSymbolDef(const MCSymbol *Symbol) {
-    LogCall("BeginCOFFSymbolDef");
-    return Child->BeginCOFFSymbolDef(Symbol);
-  }
-
-  virtual void EmitCOFFSymbolStorageClass(int StorageClass) {
-    LogCall("EmitCOFFSymbolStorageClass");
-    return Child->EmitCOFFSymbolStorageClass(StorageClass);
-  }
-
-  virtual void EmitCOFFSymbolType(int Type) {
-    LogCall("EmitCOFFSymbolType");
-    return Child->EmitCOFFSymbolType(Type);
-  }
-
-  virtual void EndCOFFSymbolDef() {
-    LogCall("EndCOFFSymbolDef");
-    return Child->EndCOFFSymbolDef();
-  }
-
-  virtual void EmitELFSize(MCSymbol *Symbol, const MCExpr *Value) {
-    LogCall("EmitELFSize");
-    return Child->EmitELFSize(Symbol, Value);
-  }
-
-  virtual void EmitCommonSymbol(MCSymbol *Symbol, uint64_t Size,
-                                unsigned ByteAlignment) {
-    LogCall("EmitCommonSymbol");
-    return Child->EmitCommonSymbol(Symbol, Size, ByteAlignment);
-  }
-
-  virtual void EmitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size,
-                                     unsigned ByteAlignment) {
-    LogCall("EmitLocalCommonSymbol");
-    return Child->EmitLocalCommonSymbol(Symbol, Size, ByteAlignment);
-  }
-  
-  virtual void EmitZerofill(const MCSection *Section, MCSymbol *Symbol = 0,
-                            unsigned Size = 0, unsigned ByteAlignment = 0) {
-    LogCall("EmitZerofill");
-    return Child->EmitZerofill(Section, Symbol, Size, ByteAlignment);
-  }
-
-  virtual void EmitTBSSSymbol (const MCSection *Section, MCSymbol *Symbol,
-                               uint64_t Size, unsigned ByteAlignment = 0) {
-    LogCall("EmitTBSSSymbol");
-    return Child->EmitTBSSSymbol(Section, Symbol, Size, ByteAlignment);
-  }
-
-  virtual void EmitBytes(StringRef Data, unsigned AddrSpace) {
-    LogCall("EmitBytes");
-    return Child->EmitBytes(Data, AddrSpace);
-  }
-
-  virtual void EmitValueImpl(const MCExpr *Value, unsigned Size,
-                             unsigned AddrSpace){
-    LogCall("EmitValue");
-    return Child->EmitValueImpl(Value, Size, AddrSpace);
-  }
-
-  virtual void EmitULEB128Value(const MCExpr *Value) {
-    LogCall("EmitULEB128Value");
-    return Child->EmitULEB128Value(Value);
-  }
-
-  virtual void EmitSLEB128Value(const MCExpr *Value) {
-    LogCall("EmitSLEB128Value");
-    return Child->EmitSLEB128Value(Value);
-  }
-
-  virtual void EmitGPRel32Value(const MCExpr *Value) {
-    LogCall("EmitGPRel32Value");
-    return Child->EmitGPRel32Value(Value);
-  }
-
-  virtual void EmitFill(uint64_t NumBytes, uint8_t FillValue,
-                        unsigned AddrSpace) {
-    LogCall("EmitFill");
-    return Child->EmitFill(NumBytes, FillValue, AddrSpace);
-  }
-
-  virtual void EmitValueToAlignment(unsigned ByteAlignment, int64_t Value = 0,
-                                    unsigned ValueSize = 1,
-                                    unsigned MaxBytesToEmit = 0) {
-    LogCall("EmitValueToAlignment");
-    return Child->EmitValueToAlignment(ByteAlignment, Value,
-                                       ValueSize, MaxBytesToEmit);
-  }
-
-  virtual void EmitCodeAlignment(unsigned ByteAlignment,
-                                 unsigned MaxBytesToEmit = 0) {
-    LogCall("EmitCodeAlignment");
-    return Child->EmitCodeAlignment(ByteAlignment, MaxBytesToEmit);
-  }
-
-  virtual void EmitValueToOffset(const MCExpr *Offset,
-                                 unsigned char Value = 0) {
-    LogCall("EmitValueToOffset");
-    return Child->EmitValueToOffset(Offset, Value);
-  }
-
-  virtual void EmitFileDirective(StringRef Filename) {
-    LogCall("EmitFileDirective", "FileName:" + Filename);
-    return Child->EmitFileDirective(Filename);
-  }
-
-  virtual bool EmitDwarfFileDirective(unsigned FileNo, StringRef Filename) {
-    LogCall("EmitDwarfFileDirective",
-            "FileNo:" + Twine(FileNo) + " Filename:" + Filename);
-    return Child->EmitDwarfFileDirective(FileNo, Filename);
-  }
-
-  virtual void EmitDwarfLocDirective(unsigned FileNo, unsigned Line,
-                                     unsigned Column, unsigned Flags,
-                                     unsigned Isa, unsigned Discriminator,
-                                     StringRef FileName) {
-    LogCall("EmitDwarfLocDirective",
-            "FileNo:" + Twine(FileNo) + " Line:" + Twine(Line) +
-            " Column:" + Twine(Column) + " Flags:" + Twine(Flags) +
-            " Isa:" + Twine(Isa) + " Discriminator:" + Twine(Discriminator));
-            return Child->EmitDwarfLocDirective(FileNo, Line, Column, Flags,
-                                                Isa, Discriminator, FileName);
-  }
-
-  virtual void EmitInstruction(const MCInst &Inst) {
-    LogCall("EmitInstruction");
-    return Child->EmitInstruction(Inst);
-  }
-
-  virtual void EmitRawText(StringRef String) {
-    LogCall("EmitRawText", "\"" + String + "\"");
-    return Child->EmitRawText(String);
-  }
-
-  virtual void Finish() {
-    LogCall("Finish");
-    return Child->Finish();
-  }
-
-};
-
-} // end anonymous namespace.
-
-MCStreamer *llvm::createLoggingStreamer(MCStreamer *Child, raw_ostream &OS) {
-  return new MCLoggingStreamer(Child, OS);
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/ARM/ARMGlobalMerge.cpp
--- a/head/contrib/llvm/lib/Target/ARM/ARMGlobalMerge.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,219 +0,0 @@
-//===-- ARMGlobalMerge.cpp - Internal globals merging  --------------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-// This pass merges globals with internal linkage into one. This way all the
-// globals which were merged into a biggest one can be addressed using offsets
-// from the same base pointer (no need for separate base pointer for each of the
-// global). Such a transformation can significantly reduce the register pressure
-// when many globals are involved.
-//
-// For example, consider the code which touches several global variables at 
-// once:
-//
-// static int foo[N], bar[N], baz[N];
-//
-// for (i = 0; i < N; ++i) {
-//    foo[i] = bar[i] * baz[i];
-// }
-//
-//  On ARM the addresses of 3 arrays should be kept in the registers, thus
-//  this code has quite large register pressure (loop body):
-//
-//  ldr     r1, [r5], #4
-//  ldr     r2, [r6], #4
-//  mul     r1, r2, r1
-//  str     r1, [r0], #4
-//
-//  Pass converts the code to something like:
-//
-//  static struct {
-//    int foo[N];
-//    int bar[N];
-//    int baz[N];
-//  } merged;
-//
-//  for (i = 0; i < N; ++i) {
-//    merged.foo[i] = merged.bar[i] * merged.baz[i];
-//  }
-//
-//  and in ARM code this becomes:
-//
-//  ldr     r0, [r5, #40]
-//  ldr     r1, [r5, #80]
-//  mul     r0, r1, r0
-//  str     r0, [r5], #4
-//
-//  note that we saved 2 registers here almostly "for free".
-// ===---------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "arm-global-merge"
-#include "ARM.h"
-#include "llvm/CodeGen/Passes.h"
-#include "llvm/Attributes.h"
-#include "llvm/Constants.h"
-#include "llvm/DerivedTypes.h"
-#include "llvm/Function.h"
-#include "llvm/GlobalVariable.h"
-#include "llvm/Instructions.h"
-#include "llvm/Intrinsics.h"
-#include "llvm/Module.h"
-#include "llvm/Pass.h"
-#include "llvm/Target/TargetData.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
-using namespace llvm;
-
-namespace {
-  class ARMGlobalMerge : public FunctionPass {
-    /// TLI - Keep a pointer of a TargetLowering to consult for determining
-    /// target type sizes.
-    const TargetLowering *TLI;
-
-    bool doMerge(SmallVectorImpl<GlobalVariable*> &Globals,
-                 Module &M, bool isConst) const;
-
-  public:
-    static char ID;             // Pass identification, replacement for typeid.
-    explicit ARMGlobalMerge(const TargetLowering *tli)
-      : FunctionPass(ID), TLI(tli) {}
-
-    virtual bool doInitialization(Module &M);
-    virtual bool runOnFunction(Function &F);
-
-    const char *getPassName() const {
-      return "Merge internal globals";
-    }
-
-    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
-      AU.setPreservesCFG();
-      FunctionPass::getAnalysisUsage(AU);
-    }
-
-    struct GlobalCmp {
-      const TargetData *TD;
-
-      GlobalCmp(const TargetData *td) : TD(td) { }
-
-      bool operator()(const GlobalVariable *GV1, const GlobalVariable *GV2) {
-        Type *Ty1 = cast<PointerType>(GV1->getType())->getElementType();
-        Type *Ty2 = cast<PointerType>(GV2->getType())->getElementType();
-
-        return (TD->getTypeAllocSize(Ty1) < TD->getTypeAllocSize(Ty2));
-      }
-    };
-  };
-} // end anonymous namespace
-
-char ARMGlobalMerge::ID = 0;
-
-bool ARMGlobalMerge::doMerge(SmallVectorImpl<GlobalVariable*> &Globals,
-                             Module &M, bool isConst) const {
-  const TargetData *TD = TLI->getTargetData();
-
-  // FIXME: Infer the maximum possible offset depending on the actual users
-  // (these max offsets are different for the users inside Thumb or ARM
-  // functions)
-  unsigned MaxOffset = TLI->getMaximalGlobalOffset();
-
-  // FIXME: Find better heuristics
-  std::stable_sort(Globals.begin(), Globals.end(), GlobalCmp(TD));
-
-  Type *Int32Ty = Type::getInt32Ty(M.getContext());
-
-  for (size_t i = 0, e = Globals.size(); i != e; ) {
-    size_t j = 0;
-    uint64_t MergedSize = 0;
-    std::vector<Type*> Tys;
-    std::vector<Constant*> Inits;
-    for (j = i; j != e; ++j) {
-      Type *Ty = Globals[j]->getType()->getElementType();
-      MergedSize += TD->getTypeAllocSize(Ty);
-      if (MergedSize > MaxOffset) {
-        break;
-      }
-      Tys.push_back(Ty);
-      Inits.push_back(Globals[j]->getInitializer());
-    }
-
-    StructType *MergedTy = StructType::get(M.getContext(), Tys);
-    Constant *MergedInit = ConstantStruct::get(MergedTy, Inits);
-    GlobalVariable *MergedGV = new GlobalVariable(M, MergedTy, isConst,
-                                                  GlobalValue::InternalLinkage,
-                                                  MergedInit, "_MergedGlobals");
-    for (size_t k = i; k < j; ++k) {
-      Constant *Idx[2] = {
-        ConstantInt::get(Int32Ty, 0),
-        ConstantInt::get(Int32Ty, k-i)
-      };
-      Constant *GEP = ConstantExpr::getInBoundsGetElementPtr(MergedGV, Idx);
-      Globals[k]->replaceAllUsesWith(GEP);
-      Globals[k]->eraseFromParent();
-    }
-    i = j;
-  }
-
-  return true;
-}
-
-
-bool ARMGlobalMerge::doInitialization(Module &M) {
-  SmallVector<GlobalVariable*, 16> Globals, ConstGlobals, BSSGlobals;
-  const TargetData *TD = TLI->getTargetData();
-  unsigned MaxOffset = TLI->getMaximalGlobalOffset();
-  bool Changed = false;
-
-  // Grab all non-const globals.
-  for (Module::global_iterator I = M.global_begin(),
-         E = M.global_end(); I != E; ++I) {
-    // Merge is safe for "normal" internal globals only
-    if (!I->hasLocalLinkage() || I->isThreadLocal() || I->hasSection())
-      continue;
-
-    // Ignore fancy-aligned globals for now.
-    unsigned Alignment = I->getAlignment();
-    Type *Ty = I->getType()->getElementType();
-    if (Alignment > TD->getABITypeAlignment(Ty))
-      continue;
-
-    // Ignore all 'special' globals.
-    if (I->getName().startswith("llvm.") ||
-        I->getName().startswith(".llvm."))
-      continue;
-
-    if (TD->getTypeAllocSize(Ty) < MaxOffset) {
-      const TargetLoweringObjectFile &TLOF = TLI->getObjFileLowering();
-      if (TLOF.getKindForGlobal(I, TLI->getTargetMachine()).isBSSLocal())
-        BSSGlobals.push_back(I);
-      else if (I->isConstant())
-        ConstGlobals.push_back(I);
-      else
-        Globals.push_back(I);
-    }
-  }
-
-  if (Globals.size() > 1)
-    Changed |= doMerge(Globals, M, false);
-  if (BSSGlobals.size() > 1)
-    Changed |= doMerge(BSSGlobals, M, false);
-
-  // FIXME: This currently breaks the EH processing due to way how the 
-  // typeinfo detection works. We might want to detect the TIs and ignore 
-  // them in the future.
-  // if (ConstGlobals.size() > 1)
-  //  Changed |= doMerge(ConstGlobals, M, true);
-
-  return Changed;
-}
-
-bool ARMGlobalMerge::runOnFunction(Function &F) {
-  return false;
-}
-
-FunctionPass *llvm::createARMGlobalMergePass(const TargetLowering *tli) {
-  return new ARMGlobalMerge(tli);
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/Alpha.h
--- a/head/contrib/llvm/lib/Target/Alpha/Alpha.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,43 +0,0 @@
-//===-- Alpha.h - Top-level interface for Alpha representation --*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains the entry points for global functions defined in the LLVM
-// Alpha back-end.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef TARGET_ALPHA_H
-#define TARGET_ALPHA_H
-
-#include "MCTargetDesc/AlphaMCTargetDesc.h"
-#include "llvm/Target/TargetMachine.h"
-
-namespace llvm {
-  namespace Alpha {
-    // These describe LDAx
-
-    static const int IMM_LOW  = -32768;
-    static const int IMM_HIGH = 32767;
-    static const int IMM_MULT = 65536;
-  }
-
-  class AlphaTargetMachine;
-  class FunctionPass;
-  class formatted_raw_ostream;
-
-  FunctionPass *createAlphaISelDag(AlphaTargetMachine &TM);
-  FunctionPass *createAlphaPatternInstructionSelector(TargetMachine &TM);
-  FunctionPass *createAlphaJITCodeEmitterPass(AlphaTargetMachine &TM,
-                                              JITCodeEmitter &JCE);
-  FunctionPass *createAlphaLLRPPass(AlphaTargetMachine &tm);
-  FunctionPass *createAlphaBranchSelectionPass();
-
-} // end namespace llvm;
-
-#endif
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/Alpha.td
--- a/head/contrib/llvm/lib/Target/Alpha/Alpha.td	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,68 +0,0 @@
-//===- Alpha.td - Describe the Alpha Target Machine --------*- tablegen -*-===//
-// 
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-// 
-//===----------------------------------------------------------------------===//
-//
-//
-//===----------------------------------------------------------------------===//
-
-// Get the target-independent interfaces which we are implementing...
-//
-include "llvm/Target/Target.td"
-
-//Alpha is little endian
-
-//===----------------------------------------------------------------------===//
-// Subtarget Features
-//===----------------------------------------------------------------------===//
-
-def FeatureCIX : SubtargetFeature<"cix", "HasCT", "true",
-                                  "Enable CIX extensions">;
-
-//===----------------------------------------------------------------------===//
-// Register File Description
-//===----------------------------------------------------------------------===//
-
-include "AlphaRegisterInfo.td"
-
-//===----------------------------------------------------------------------===//
-// Calling Convention Description
-//===----------------------------------------------------------------------===//
-
-include "AlphaCallingConv.td"
-
-//===----------------------------------------------------------------------===//
-// Schedule Description
-//===----------------------------------------------------------------------===//
-
-include "AlphaSchedule.td"
-
-//===----------------------------------------------------------------------===//
-// Instruction Descriptions
-//===----------------------------------------------------------------------===//
-
-include "AlphaInstrInfo.td"
-
-def AlphaInstrInfo : InstrInfo;
-
-//===----------------------------------------------------------------------===//
-// Alpha Processor Definitions
-//===----------------------------------------------------------------------===//
-
-def : Processor<"generic", Alpha21264Itineraries, []>;
-def : Processor<"ev6"    , Alpha21264Itineraries, []>;
-def : Processor<"ev67"   , Alpha21264Itineraries, [FeatureCIX]>;
-
-//===----------------------------------------------------------------------===//
-// The Alpha Target
-//===----------------------------------------------------------------------===//
-
-
-def Alpha : Target {
-  // Pull in Instruction Info:
-  let InstructionSet = AlphaInstrInfo;
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp
--- a/head/contrib/llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,166 +0,0 @@
-//===-- AlphaAsmPrinter.cpp - Alpha LLVM assembly writer ------------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains a printer that converts from our internal representation
-// of machine-dependent LLVM code to GAS-format Alpha assembly language.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "asm-printer"
-#include "Alpha.h"
-#include "AlphaInstrInfo.h"
-#include "AlphaTargetMachine.h"
-#include "llvm/Module.h"
-#include "llvm/Type.h"
-#include "llvm/Assembly/Writer.h"
-#include "llvm/CodeGen/AsmPrinter.h"
-#include "llvm/MC/MCStreamer.h"
-#include "llvm/MC/MCAsmInfo.h"
-#include "llvm/MC/MCSymbol.h"
-#include "llvm/Target/Mangler.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/ADT/SmallString.h"
-#include "llvm/Support/TargetRegistry.h"
-#include "llvm/Support/raw_ostream.h"
-using namespace llvm;
-
-namespace {
-  struct AlphaAsmPrinter : public AsmPrinter {
-    /// Unique incrementer for label values for referencing Global values.
-    ///
-
-    explicit AlphaAsmPrinter(TargetMachine &tm, MCStreamer &Streamer)
-      : AsmPrinter(tm, Streamer) {}
-
-    virtual const char *getPassName() const {
-      return "Alpha Assembly Printer";
-    }
-    void printInstruction(const MachineInstr *MI, raw_ostream &O);
-    void EmitInstruction(const MachineInstr *MI) {
-      SmallString<128> Str;
-      raw_svector_ostream OS(Str);
-      printInstruction(MI, OS);
-      OutStreamer.EmitRawText(OS.str());
-    }
-    static const char *getRegisterName(unsigned RegNo);
-
-    void printOp(const MachineOperand &MO, raw_ostream &O);
-    void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
-    virtual void EmitFunctionBodyStart();
-    virtual void EmitFunctionBodyEnd(); 
-    void EmitStartOfAsmFile(Module &M);
-
-    bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
-                         unsigned AsmVariant, const char *ExtraCode,
-                         raw_ostream &O);
-    bool PrintAsmMemoryOperand(const MachineInstr *MI,
-                               unsigned OpNo, unsigned AsmVariant,
-                               const char *ExtraCode, raw_ostream &O);
-  };
-} // end of anonymous namespace
-
-#include "AlphaGenAsmWriter.inc"
-
-void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
-                                   raw_ostream &O) {
-  const MachineOperand &MO = MI->getOperand(opNum);
-  if (MO.isReg()) {
-    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
-           "Not physreg??");
-    O << getRegisterName(MO.getReg());
-  } else if (MO.isImm()) {
-    O << MO.getImm();
-    assert(MO.getImm() < (1 << 30));
-  } else {
-    printOp(MO, O);
-  }
-}
-
-
-void AlphaAsmPrinter::printOp(const MachineOperand &MO, raw_ostream &O) {
-  switch (MO.getType()) {
-  case MachineOperand::MO_Register:
-    O << getRegisterName(MO.getReg());
-    return;
-
-  case MachineOperand::MO_Immediate:
-    assert(0 && "printOp() does not handle immediate values");
-    return;
-
-  case MachineOperand::MO_MachineBasicBlock:
-    O << *MO.getMBB()->getSymbol();
-    return;
-
-  case MachineOperand::MO_ConstantPoolIndex:
-    O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << "_"
-      << MO.getIndex();
-    return;
-
-  case MachineOperand::MO_ExternalSymbol:
-    O << MO.getSymbolName();
-    return;
-
-  case MachineOperand::MO_GlobalAddress:
-    O << *Mang->getSymbol(MO.getGlobal());
-    return;
-
-  case MachineOperand::MO_JumpTableIndex:
-    O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
-      << '_' << MO.getIndex();
-    return;
-
-  default:
-    O << "<unknown operand type: " << MO.getType() << ">";
-    return;
-  }
-}
-
-/// EmitFunctionBodyStart - Targets can override this to emit stuff before
-/// the first basic block in the function.
-void AlphaAsmPrinter::EmitFunctionBodyStart() {
-  OutStreamer.EmitRawText("\t.ent " + Twine(CurrentFnSym->getName()));
-}
-
-/// EmitFunctionBodyEnd - Targets can override this to emit stuff after
-/// the last basic block in the function.
-void AlphaAsmPrinter::EmitFunctionBodyEnd() {
-  OutStreamer.EmitRawText("\t.end " + Twine(CurrentFnSym->getName()));
-}
-
-void AlphaAsmPrinter::EmitStartOfAsmFile(Module &M) {
-  OutStreamer.EmitRawText(StringRef("\t.arch ev6"));
-  OutStreamer.EmitRawText(StringRef("\t.set noat"));
-}
-
-/// PrintAsmOperand - Print out an operand for an inline asm expression.
-///
-bool AlphaAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
-                                      unsigned AsmVariant,
-                                      const char *ExtraCode, raw_ostream &O) {
-  printOperand(MI, OpNo, O);
-  return false;
-}
-
-bool AlphaAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
-                                            unsigned OpNo, unsigned AsmVariant,
-                                            const char *ExtraCode,
-                                            raw_ostream &O) {
-  if (ExtraCode && ExtraCode[0])
-    return true; // Unknown modifier.
-  O << "0(";
-  printOperand(MI, OpNo, O);
-  O << ")";
-  return false;
-}
-
-// Force static initialization.
-extern "C" void LLVMInitializeAlphaAsmPrinter() { 
-  RegisterAsmPrinter<AlphaAsmPrinter> X(TheAlphaTarget);
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/AlphaBranchSelector.cpp
--- a/head/contrib/llvm/lib/Target/Alpha/AlphaBranchSelector.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,66 +0,0 @@
-//===-- AlphaBranchSelector.cpp - Convert Pseudo branchs ----------*- C++ -*-=//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// Replace Pseudo COND_BRANCH_* with their appropriate real branch
-// Simplified version of the PPC Branch Selector
-//
-//===----------------------------------------------------------------------===//
-
-#include "Alpha.h"
-#include "AlphaInstrInfo.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/MC/MCAsmInfo.h"
-using namespace llvm;
-
-namespace {
-  struct AlphaBSel : public MachineFunctionPass {
-    static char ID;
-    AlphaBSel() : MachineFunctionPass(ID) {}
-
-    virtual bool runOnMachineFunction(MachineFunction &Fn);
-
-    virtual const char *getPassName() const {
-      return "Alpha Branch Selection";
-    }
-  };
-  char AlphaBSel::ID = 0;
-}
-
-/// createAlphaBranchSelectionPass - returns an instance of the Branch Selection
-/// Pass
-///
-FunctionPass *llvm::createAlphaBranchSelectionPass() {
-  return new AlphaBSel();
-}
-
-bool AlphaBSel::runOnMachineFunction(MachineFunction &Fn) {
-
-  for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
-       ++MFI) {
-    MachineBasicBlock *MBB = MFI;
-    
-    for (MachineBasicBlock::iterator MBBI = MBB->begin(), EE = MBB->end();
-         MBBI != EE; ++MBBI) {
-      if (MBBI->getOpcode() == Alpha::COND_BRANCH_I ||
-          MBBI->getOpcode() == Alpha::COND_BRANCH_F) {
-        
-        // condbranch operands:
-        // 0. bc opcode
-        // 1. reg
-        // 2. target MBB
-        const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
-        MBBI->setDesc(TII->get(MBBI->getOperand(0).getImm()));
-      }
-    }
-  }
-  
-  return true;
-}
-
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/AlphaCallingConv.td
--- a/head/contrib/llvm/lib/Target/Alpha/AlphaCallingConv.td	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,38 +0,0 @@
-//===- AlphaCallingConv.td - Calling Conventions for Alpha -*- tablegen -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-// This describes the calling conventions for Alpha architecture.
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// Alpha Return Value Calling Convention
-//===----------------------------------------------------------------------===//
-def RetCC_Alpha : CallingConv<[
-  // i64 is returned in register R0
-  // R1 is an llvm extension, I don't know what gcc does
-  CCIfType<[i64], CCAssignToReg<[R0,R1]>>,
-
-  // f32 / f64 are returned in F0/F1
-  CCIfType<[f32, f64], CCAssignToReg<[F0, F1]>>
-]>;
-
-//===----------------------------------------------------------------------===//
-// Alpha Argument Calling Conventions
-//===----------------------------------------------------------------------===//
-def CC_Alpha : CallingConv<[
-  // The first 6 arguments are passed in registers, whether integer or
-  // floating-point
-  CCIfType<[i64], CCAssignToRegWithShadow<[R16, R17, R18, R19, R20, R21],
-                                          [F16, F17, F18, F19, F20, F21]>>,
-
-  CCIfType<[f32, f64], CCAssignToRegWithShadow<[F16, F17, F18, F19, F20, F21],
-                                               [R16, R17, R18, R19, R20, R21]>>,
-
-  // Stack slots are 8 bytes in size and 8-byte aligned.
-  CCIfType<[i64, f32, f64], CCAssignToStack<8, 8>>
-]>;
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/AlphaFrameLowering.cpp
--- a/head/contrib/llvm/lib/Target/Alpha/AlphaFrameLowering.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,143 +0,0 @@
-//=====- AlphaFrameLowering.cpp - Alpha Frame Information ------*- C++ -*-====//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains the Alpha implementation of TargetFrameLowering class.
-//
-//===----------------------------------------------------------------------===//
-
-#include "AlphaFrameLowering.h"
-#include "AlphaInstrInfo.h"
-#include "AlphaMachineFunctionInfo.h"
-#include "llvm/Function.h"
-#include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/ADT/Twine.h"
-
-using namespace llvm;
-
-static long getUpper16(long l) {
-  long y = l / Alpha::IMM_MULT;
-  if (l % Alpha::IMM_MULT > Alpha::IMM_HIGH)
-    ++y;
-  return y;
-}
-
-static long getLower16(long l) {
-  long h = getUpper16(l);
-  return l - h * Alpha::IMM_MULT;
-}
-
-// hasFP - Return true if the specified function should have a dedicated frame
-// pointer register.  This is true if the function has variable sized allocas or
-// if frame pointer elimination is disabled.
-//
-bool AlphaFrameLowering::hasFP(const MachineFunction &MF) const {
-  const MachineFrameInfo *MFI = MF.getFrameInfo();
-  return MFI->hasVarSizedObjects();
-}
-
-void AlphaFrameLowering::emitPrologue(MachineFunction &MF) const {
-  MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
-  MachineBasicBlock::iterator MBBI = MBB.begin();
-  MachineFrameInfo *MFI = MF.getFrameInfo();
-  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
-
-  DebugLoc dl = (MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc());
-  bool FP = hasFP(MF);
-
-  // Handle GOP offset
-  BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAHg), Alpha::R29)
-    .addGlobalAddress(MF.getFunction()).addReg(Alpha::R27).addImm(++curgpdist);
-  BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAg), Alpha::R29)
-    .addGlobalAddress(MF.getFunction()).addReg(Alpha::R29).addImm(curgpdist);
-
-  BuildMI(MBB, MBBI, dl, TII.get(Alpha::ALTENT))
-    .addGlobalAddress(MF.getFunction());
-
-  // Get the number of bytes to allocate from the FrameInfo
-  long NumBytes = MFI->getStackSize();
-
-  if (FP)
-    NumBytes += 8; //reserve space for the old FP
-
-  // Do we need to allocate space on the stack?
-  if (NumBytes == 0) return;
-
-  unsigned Align = getStackAlignment();
-  NumBytes = (NumBytes+Align-1)/Align*Align;
-
-  // Update frame info to pretend that this is part of the stack...
-  MFI->setStackSize(NumBytes);
-
-  // adjust stack pointer: r30 -= numbytes
-  NumBytes = -NumBytes;
-  if (NumBytes >= Alpha::IMM_LOW) {
-    BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
-      .addReg(Alpha::R30);
-  } else if (getUpper16(NumBytes) >= Alpha::IMM_LOW) {
-    BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAH), Alpha::R30)
-      .addImm(getUpper16(NumBytes)).addReg(Alpha::R30);
-    BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30)
-      .addImm(getLower16(NumBytes)).addReg(Alpha::R30);
-  } else {
-    report_fatal_error("Too big a stack frame at " + Twine(NumBytes));
-  }
-
-  // Now if we need to, save the old FP and set the new
-  if (FP) {
-    BuildMI(MBB, MBBI, dl, TII.get(Alpha::STQ))
-      .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
-    // This must be the last instr in the prolog
-    BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R15)
-      .addReg(Alpha::R30).addReg(Alpha::R30);
-  }
-
-}
-
-void AlphaFrameLowering::emitEpilogue(MachineFunction &MF,
-                                  MachineBasicBlock &MBB) const {
-  const MachineFrameInfo *MFI = MF.getFrameInfo();
-  MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
-  const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
-
-  assert((MBBI->getOpcode() == Alpha::RETDAG ||
-          MBBI->getOpcode() == Alpha::RETDAGp)
-         && "Can only insert epilog into returning blocks");
-  DebugLoc dl = MBBI->getDebugLoc();
-
-  bool FP = hasFP(MF);
-
-  // Get the number of bytes allocated from the FrameInfo...
-  long NumBytes = MFI->getStackSize();
-
-  //now if we need to, restore the old FP
-  if (FP) {
-    //copy the FP into the SP (discards allocas)
-    BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15)
-      .addReg(Alpha::R15);
-    //restore the FP
-    BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDQ), Alpha::R15)
-      .addImm(0).addReg(Alpha::R15);
-  }
-
-  if (NumBytes != 0) {
-    if (NumBytes <= Alpha::IMM_HIGH) {
-      BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
-        .addReg(Alpha::R30);
-    } else if (getUpper16(NumBytes) <= Alpha::IMM_HIGH) {
-      BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAH), Alpha::R30)
-        .addImm(getUpper16(NumBytes)).addReg(Alpha::R30);
-      BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30)
-        .addImm(getLower16(NumBytes)).addReg(Alpha::R30);
-    } else {
-      report_fatal_error("Too big a stack frame at " + Twine(NumBytes));
-    }
-  }
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/AlphaFrameLowering.h
--- a/head/contrib/llvm/lib/Target/Alpha/AlphaFrameLowering.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,43 +0,0 @@
-//==-- AlphaFrameLowering.h - Define frame lowering for Alpha --*- C++ -*---==//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-//
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef ALPHA_FRAMEINFO_H
-#define ALPHA_FRAMEINFO_H
-
-#include "Alpha.h"
-#include "AlphaSubtarget.h"
-#include "llvm/Target/TargetFrameLowering.h"
-
-namespace llvm {
-  class AlphaSubtarget;
-
-class AlphaFrameLowering : public TargetFrameLowering {
-  const AlphaSubtarget &STI;
-  // FIXME: This should end in MachineFunctionInfo, not here!
-  mutable int curgpdist;
-public:
-  explicit AlphaFrameLowering(const AlphaSubtarget &sti)
-    : TargetFrameLowering(StackGrowsDown, 16, 0), STI(sti), curgpdist(0) {
-  }
-
-  /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
-  /// the function.
-  void emitPrologue(MachineFunction &MF) const;
-  void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
-
-  bool hasFP(const MachineFunction &MF) const;
-};
-
-} // End llvm namespace
-
-#endif
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
--- a/head/contrib/llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,425 +0,0 @@
-//===-- AlphaISelDAGToDAG.cpp - Alpha pattern matching inst selector ------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines a pattern matching instruction selector for Alpha,
-// converting from a legalized dag to a Alpha dag.
-//
-//===----------------------------------------------------------------------===//
-
-#include "Alpha.h"
-#include "AlphaTargetMachine.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/CodeGen/SelectionDAGISel.h"
-#include "llvm/Target/TargetOptions.h"
-#include "llvm/Constants.h"
-#include "llvm/DerivedTypes.h"
-#include "llvm/GlobalValue.h"
-#include "llvm/Intrinsics.h"
-#include "llvm/LLVMContext.h"
-#include "llvm/Support/Compiler.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/MathExtras.h"
-#include "llvm/Support/raw_ostream.h"
-#include <algorithm>
-using namespace llvm;
-
-namespace {
-
-  //===--------------------------------------------------------------------===//
-  /// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
-  /// instructions for SelectionDAG operations.
-  class AlphaDAGToDAGISel : public SelectionDAGISel {
-    static const int64_t IMM_LOW  = -32768;
-    static const int64_t IMM_HIGH = 32767;
-    static const int64_t IMM_MULT = 65536;
-    static const int64_t IMM_FULLHIGH = IMM_HIGH + IMM_HIGH * IMM_MULT;
-    static const int64_t IMM_FULLLOW = IMM_LOW + IMM_LOW  * IMM_MULT;
-
-    static int64_t get_ldah16(int64_t x) {
-      int64_t y = x / IMM_MULT;
-      if (x % IMM_MULT > IMM_HIGH)
-        ++y;
-      return y;
-    }
-
-    static int64_t get_lda16(int64_t x) {
-      return x - get_ldah16(x) * IMM_MULT;
-    }
-
-    /// get_zapImm - Return a zap mask if X is a valid immediate for a zapnot
-    /// instruction (if not, return 0).  Note that this code accepts partial
-    /// zap masks.  For example (and LHS, 1) is a valid zap, as long we know
-    /// that the bits 1-7 of LHS are already zero.  If LHS is non-null, we are
-    /// in checking mode.  If LHS is null, we assume that the mask has already
-    /// been validated before.
-    uint64_t get_zapImm(SDValue LHS, uint64_t Constant) const {
-      uint64_t BitsToCheck = 0;
-      unsigned Result = 0;
-      for (unsigned i = 0; i != 8; ++i) {
-        if (((Constant >> 8*i) & 0xFF) == 0) {
-          // nothing to do.
-        } else {
-          Result |= 1 << i;
-          if (((Constant >> 8*i) & 0xFF) == 0xFF) {
-            // If the entire byte is set, zapnot the byte.
-          } else if (LHS.getNode() == 0) {
-            // Otherwise, if the mask was previously validated, we know its okay
-            // to zapnot this entire byte even though all the bits aren't set.
-          } else {
-            // Otherwise we don't know that the it's okay to zapnot this entire
-            // byte.  Only do this iff we can prove that the missing bits are
-            // already null, so the bytezap doesn't need to really null them.
-            BitsToCheck |= ~Constant & (0xFFULL << 8*i);
-          }
-        }
-      }
-      
-      // If there are missing bits in a byte (for example, X & 0xEF00), check to
-      // see if the missing bits (0x1000) are already known zero if not, the zap
-      // isn't okay to do, as it won't clear all the required bits.
-      if (BitsToCheck &&
-          !CurDAG->MaskedValueIsZero(LHS,
-                                     APInt(LHS.getValueSizeInBits(),
-                                           BitsToCheck)))
-        return 0;
-      
-      return Result;
-    }
-    
-    static uint64_t get_zapImm(uint64_t x) {
-      unsigned build = 0;
-      for(int i = 0; i != 8; ++i) {
-        if ((x & 0x00FF) == 0x00FF)
-          build |= 1 << i;
-        else if ((x & 0x00FF) != 0)
-          return 0;
-        x >>= 8;
-      }
-      return build;
-    }
-      
-    
-    static uint64_t getNearPower2(uint64_t x) {
-      if (!x) return 0;
-      unsigned at = CountLeadingZeros_64(x);
-      uint64_t complow = 1ULL << (63 - at);
-      uint64_t comphigh = complow << 1;
-      if (x - complow <= comphigh - x)
-        return complow;
-      else
-        return comphigh;
-    }
-
-    static bool chkRemNearPower2(uint64_t x, uint64_t r, bool swap) {
-      uint64_t y = getNearPower2(x);
-      if (swap)
-        return (y - x) == r;
-      else
-        return (x - y) == r;
-    }
-
-  public:
-    explicit AlphaDAGToDAGISel(AlphaTargetMachine &TM)
-      : SelectionDAGISel(TM)
-    {}
-
-    /// getI64Imm - Return a target constant with the specified value, of type
-    /// i64.
-    inline SDValue getI64Imm(int64_t Imm) {
-      return CurDAG->getTargetConstant(Imm, MVT::i64);
-    }
-
-    // Select - Convert the specified operand from a target-independent to a
-    // target-specific node if it hasn't already been changed.
-    SDNode *Select(SDNode *N);
-    
-    virtual const char *getPassName() const {
-      return "Alpha DAG->DAG Pattern Instruction Selection";
-    } 
-
-    /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
-    /// inline asm expressions.
-    virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
-                                              char ConstraintCode,
-                                              std::vector<SDValue> &OutOps) {
-      SDValue Op0;
-      switch (ConstraintCode) {
-      default: return true;
-      case 'm':   // memory
-        Op0 = Op;
-        break;
-      }
-      
-      OutOps.push_back(Op0);
-      return false;
-    }
-    
-// Include the pieces autogenerated from the target description.
-#include "AlphaGenDAGISel.inc"
-    
-private:
-    /// getTargetMachine - Return a reference to the TargetMachine, casted
-    /// to the target-specific type.
-    const AlphaTargetMachine &getTargetMachine() {
-      return static_cast<const AlphaTargetMachine &>(TM);
-    }
-
-    /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
-    /// to the target-specific type.
-    const AlphaInstrInfo *getInstrInfo() {
-      return getTargetMachine().getInstrInfo();
-    }
-
-    SDNode *getGlobalBaseReg();
-    SDNode *getGlobalRetAddr();
-    void SelectCALL(SDNode *Op);
-
-  };
-}
-
-/// getGlobalBaseReg - Output the instructions required to put the
-/// GOT address into a register.
-///
-SDNode *AlphaDAGToDAGISel::getGlobalBaseReg() {
-  unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
-  return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
-}
-
-/// getGlobalRetAddr - Grab the return address.
-///
-SDNode *AlphaDAGToDAGISel::getGlobalRetAddr() {
-  unsigned GlobalRetAddr = getInstrInfo()->getGlobalRetAddr(MF);
-  return CurDAG->getRegister(GlobalRetAddr, TLI.getPointerTy()).getNode();
-}
-
-// Select - Convert the specified operand from a target-independent to a
-// target-specific node if it hasn't already been changed.
-SDNode *AlphaDAGToDAGISel::Select(SDNode *N) {
-  if (N->isMachineOpcode())
-    return NULL;   // Already selected.
-  DebugLoc dl = N->getDebugLoc();
-
-  switch (N->getOpcode()) {
-  default: break;
-  case AlphaISD::CALL:
-    SelectCALL(N);
-    return NULL;
-
-  case ISD::FrameIndex: {
-    int FI = cast<FrameIndexSDNode>(N)->getIndex();
-    return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
-                                CurDAG->getTargetFrameIndex(FI, MVT::i32),
-                                getI64Imm(0));
-  }
-  case ISD::GLOBAL_OFFSET_TABLE:
-    return getGlobalBaseReg();
-  case AlphaISD::GlobalRetAddr:
-    return getGlobalRetAddr();
-  
-  case AlphaISD::DivCall: {
-    SDValue Chain = CurDAG->getEntryNode();
-    SDValue N0 = N->getOperand(0);
-    SDValue N1 = N->getOperand(1);
-    SDValue N2 = N->getOperand(2);
-    Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R24, N1, 
-                                 SDValue(0,0));
-    Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R25, N2, 
-                                 Chain.getValue(1));
-    Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, N0, 
-                                 Chain.getValue(1));
-    SDNode *CNode =
-      CurDAG->getMachineNode(Alpha::JSRs, dl, MVT::Other, MVT::Glue, 
-                             Chain, Chain.getValue(1));
-    Chain = CurDAG->getCopyFromReg(Chain, dl, Alpha::R27, MVT::i64, 
-                                   SDValue(CNode, 1));
-    return CurDAG->SelectNodeTo(N, Alpha::BISr, MVT::i64, Chain, Chain);
-  }
-
-  case ISD::READCYCLECOUNTER: {
-    SDValue Chain = N->getOperand(0);
-    return CurDAG->getMachineNode(Alpha::RPCC, dl, MVT::i64, MVT::Other,
-                                  Chain);
-  }
-
-  case ISD::Constant: {
-    uint64_t uval = cast<ConstantSDNode>(N)->getZExtValue();
-    
-    if (uval == 0) {
-      SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
-                                                Alpha::R31, MVT::i64);
-      ReplaceUses(SDValue(N, 0), Result);
-      return NULL;
-    }
-
-    int64_t val = (int64_t)uval;
-    int32_t val32 = (int32_t)val;
-    if (val <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
-        val >= IMM_LOW  + IMM_LOW  * IMM_MULT)
-      break; //(LDAH (LDA))
-    if ((uval >> 32) == 0 && //empty upper bits
-        val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT)
-      // val32 >= IMM_LOW  + IMM_LOW  * IMM_MULT) //always true
-      break; //(zext (LDAH (LDA)))
-    //Else use the constant pool
-    ConstantInt *C = ConstantInt::get(
-                                Type::getInt64Ty(*CurDAG->getContext()), uval);
-    SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
-    SDNode *Tmp = CurDAG->getMachineNode(Alpha::LDAHr, dl, MVT::i64, CPI,
-                                         SDValue(getGlobalBaseReg(), 0));
-    return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other, 
-                                CPI, SDValue(Tmp, 0), CurDAG->getEntryNode());
-  }
-  case ISD::TargetConstantFP:
-  case ISD::ConstantFP: {
-    ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
-    bool isDouble = N->getValueType(0) == MVT::f64;
-    EVT T = isDouble ? MVT::f64 : MVT::f32;
-    if (CN->getValueAPF().isPosZero()) {
-      return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
-                                  T, CurDAG->getRegister(Alpha::F31, T),
-                                  CurDAG->getRegister(Alpha::F31, T));
-    } else if (CN->getValueAPF().isNegZero()) {
-      return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
-                                  T, CurDAG->getRegister(Alpha::F31, T),
-                                  CurDAG->getRegister(Alpha::F31, T));
-    } else {
-      report_fatal_error("Unhandled FP constant type");
-    }
-    break;
-  }
-
-  case ISD::SETCC:
-    if (N->getOperand(0).getNode()->getValueType(0).isFloatingPoint()) {
-      ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
-
-      unsigned Opc = Alpha::WTF;
-      bool rev = false;
-      bool inv = false;
-      switch(CC) {
-      default: DEBUG(N->dump(CurDAG)); llvm_unreachable("Unknown FP comparison!");
-      case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ:
-        Opc = Alpha::CMPTEQ; break;
-      case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT: 
-        Opc = Alpha::CMPTLT; break;
-      case ISD::SETLE: case ISD::SETOLE: case ISD::SETULE: 
-        Opc = Alpha::CMPTLE; break;
-      case ISD::SETGT: case ISD::SETOGT: case ISD::SETUGT: 
-        Opc = Alpha::CMPTLT; rev = true; break;
-      case ISD::SETGE: case ISD::SETOGE: case ISD::SETUGE: 
-        Opc = Alpha::CMPTLE; rev = true; break;
-      case ISD::SETNE: case ISD::SETONE: case ISD::SETUNE:
-        Opc = Alpha::CMPTEQ; inv = true; break;
-      case ISD::SETO:
-        Opc = Alpha::CMPTUN; inv = true; break;
-      case ISD::SETUO:
-        Opc = Alpha::CMPTUN; break;
-      };
-      SDValue tmp1 = N->getOperand(rev?1:0);
-      SDValue tmp2 = N->getOperand(rev?0:1);
-      SDNode *cmp = CurDAG->getMachineNode(Opc, dl, MVT::f64, tmp1, tmp2);
-      if (inv) 
-        cmp = CurDAG->getMachineNode(Alpha::CMPTEQ, dl, 
-                                     MVT::f64, SDValue(cmp, 0), 
-                                     CurDAG->getRegister(Alpha::F31, MVT::f64));
-      switch(CC) {
-      case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE:
-      case ISD::SETUNE: case ISD::SETUGT: case ISD::SETUGE:
-       {
-         SDNode* cmp2 = CurDAG->getMachineNode(Alpha::CMPTUN, dl, MVT::f64,
-                                               tmp1, tmp2);
-         cmp = CurDAG->getMachineNode(Alpha::ADDT, dl, MVT::f64, 
-                                      SDValue(cmp2, 0), SDValue(cmp, 0));
-         break;
-       }
-      default: break;
-      }
-
-      SDNode* LD = CurDAG->getMachineNode(Alpha::FTOIT, dl,
-                                          MVT::i64, SDValue(cmp, 0));
-      return CurDAG->getMachineNode(Alpha::CMPULT, dl, MVT::i64, 
-                                    CurDAG->getRegister(Alpha::R31, MVT::i64),
-                                    SDValue(LD,0));
-    }
-    break;
-
-  case ISD::AND: {
-    ConstantSDNode* SC = NULL;
-    ConstantSDNode* MC = NULL;
-    if (N->getOperand(0).getOpcode() == ISD::SRL &&
-        (MC = dyn_cast<ConstantSDNode>(N->getOperand(1))) &&
-        (SC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1)))) {
-      uint64_t sval = SC->getZExtValue();
-      uint64_t mval = MC->getZExtValue();
-      // If the result is a zap, let the autogened stuff handle it.
-      if (get_zapImm(N->getOperand(0), mval))
-        break;
-      // given mask X, and shift S, we want to see if there is any zap in the
-      // mask if we play around with the botton S bits
-      uint64_t dontcare = (~0ULL) >> (64 - sval);
-      uint64_t mask = mval << sval;
-      
-      if (get_zapImm(mask | dontcare))
-        mask = mask | dontcare;
-      
-      if (get_zapImm(mask)) {
-        SDValue Z = 
-          SDValue(CurDAG->getMachineNode(Alpha::ZAPNOTi, dl, MVT::i64,
-                                         N->getOperand(0).getOperand(0),
-                                         getI64Imm(get_zapImm(mask))), 0);
-        return CurDAG->getMachineNode(Alpha::SRLr, dl, MVT::i64, Z, 
-                                      getI64Imm(sval));
-      }
-    }
-    break;
-  }
-
-  }
-
-  return SelectCode(N);
-}
-
-void AlphaDAGToDAGISel::SelectCALL(SDNode *N) {
-  //TODO: add flag stuff to prevent nondeturministic breakage!
-
-  SDValue Chain = N->getOperand(0);
-  SDValue Addr = N->getOperand(1);
-  SDValue InFlag = N->getOperand(N->getNumOperands() - 1);
-  DebugLoc dl = N->getDebugLoc();
-
-   if (Addr.getOpcode() == AlphaISD::GPRelLo) {
-     SDValue GOT = SDValue(getGlobalBaseReg(), 0);
-     Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R29, GOT, InFlag);
-     InFlag = Chain.getValue(1);
-     Chain = SDValue(CurDAG->getMachineNode(Alpha::BSR, dl, MVT::Other, 
-                                            MVT::Glue, Addr.getOperand(0),
-                                            Chain, InFlag), 0);
-   } else {
-     Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, Addr, InFlag);
-     InFlag = Chain.getValue(1);
-     Chain = SDValue(CurDAG->getMachineNode(Alpha::JSR, dl, MVT::Other,
-                                            MVT::Glue, Chain, InFlag), 0);
-   }
-   InFlag = Chain.getValue(1);
-
-  ReplaceUses(SDValue(N, 0), Chain);
-  ReplaceUses(SDValue(N, 1), InFlag);
-}
-
-
-/// createAlphaISelDag - This pass converts a legalized DAG into a 
-/// Alpha-specific DAG, ready for instruction scheduling.
-///
-FunctionPass *llvm::createAlphaISelDag(AlphaTargetMachine &TM) {
-  return new AlphaDAGToDAGISel(TM);
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/AlphaISelLowering.cpp
--- a/head/contrib/llvm/lib/Target/Alpha/AlphaISelLowering.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,962 +0,0 @@
-//===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements the AlphaISelLowering class.
-//
-//===----------------------------------------------------------------------===//
-
-#include "AlphaISelLowering.h"
-#include "AlphaTargetMachine.h"
-#include "AlphaMachineFunctionInfo.h"
-#include "llvm/CodeGen/CallingConvLower.h"
-#include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/PseudoSourceValue.h"
-#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
-#include "llvm/Constants.h"
-#include "llvm/Function.h"
-#include "llvm/Module.h"
-#include "llvm/Intrinsics.h"
-#include "llvm/Type.h"
-#include "llvm/Support/CommandLine.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/raw_ostream.h"
-using namespace llvm;
-
-/// AddLiveIn - This helper function adds the specified physical register to the
-/// MachineFunction as a live in value.  It also creates a corresponding virtual
-/// register for it.
-static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
-                          TargetRegisterClass *RC) {
-  assert(RC->contains(PReg) && "Not the correct regclass!");
-  unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
-  MF.getRegInfo().addLiveIn(PReg, VReg);
-  return VReg;
-}
-
-AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM)
-  : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
-  // Set up the TargetLowering object.
-  //I am having problems with shr n i8 1
-  setBooleanContents(ZeroOrOneBooleanContent);
-  setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
-
-  addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
-  addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
-  addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
-
-  // We want to custom lower some of our intrinsics.
-  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
-
-  setLoadExtAction(ISD::EXTLOAD, MVT::i1,  Promote);
-  setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
-
-  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
-  setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Expand);
-
-  setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);
-  setLoadExtAction(ISD::SEXTLOAD, MVT::i8,  Expand);
-  setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
-
-  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
-
-  //  setOperationAction(ISD::BRIND,        MVT::Other,   Expand);
-  setOperationAction(ISD::BR_JT,        MVT::Other, Expand);
-  setOperationAction(ISD::BR_CC,        MVT::Other, Expand);
-  setOperationAction(ISD::SELECT_CC,    MVT::Other, Expand);
-
-  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
-
-  setOperationAction(ISD::FREM, MVT::f32, Expand);
-  setOperationAction(ISD::FREM, MVT::f64, Expand);
-
-  setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
-  setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
-  setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
-  setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
-
-  if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
-    setOperationAction(ISD::CTPOP    , MVT::i64  , Expand);
-    setOperationAction(ISD::CTTZ     , MVT::i64  , Expand);
-    setOperationAction(ISD::CTLZ     , MVT::i64  , Expand);
-  }
-  setOperationAction(ISD::BSWAP    , MVT::i64, Expand);
-  setOperationAction(ISD::ROTL     , MVT::i64, Expand);
-  setOperationAction(ISD::ROTR     , MVT::i64, Expand);
-
-  setOperationAction(ISD::SREM     , MVT::i64, Custom);
-  setOperationAction(ISD::UREM     , MVT::i64, Custom);
-  setOperationAction(ISD::SDIV     , MVT::i64, Custom);
-  setOperationAction(ISD::UDIV     , MVT::i64, Custom);
-
-  setOperationAction(ISD::ADDC     , MVT::i64, Expand);
-  setOperationAction(ISD::ADDE     , MVT::i64, Expand);
-  setOperationAction(ISD::SUBC     , MVT::i64, Expand);
-  setOperationAction(ISD::SUBE     , MVT::i64, Expand);
-
-  setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
-  setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
-
-  setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
-  setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
-  setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
-
-  // We don't support sin/cos/sqrt/pow
-  setOperationAction(ISD::FSIN , MVT::f64, Expand);
-  setOperationAction(ISD::FCOS , MVT::f64, Expand);
-  setOperationAction(ISD::FSIN , MVT::f32, Expand);
-  setOperationAction(ISD::FCOS , MVT::f32, Expand);
-
-  setOperationAction(ISD::FSQRT, MVT::f64, Expand);
-  setOperationAction(ISD::FSQRT, MVT::f32, Expand);
-
-  setOperationAction(ISD::FPOW , MVT::f32, Expand);
-  setOperationAction(ISD::FPOW , MVT::f64, Expand);
-
-  setOperationAction(ISD::FMA, MVT::f64, Expand);
-  setOperationAction(ISD::FMA, MVT::f32, Expand);
-
-  setOperationAction(ISD::SETCC, MVT::f32, Promote);
-
-  setOperationAction(ISD::BITCAST, MVT::f32, Promote);
-
-  setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
-
-  // Not implemented yet.
-  setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
-  setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
-  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
-
-  // We want to legalize GlobalAddress and ConstantPool and
-  // ExternalSymbols nodes into the appropriate instructions to
-  // materialize the address.
-  setOperationAction(ISD::GlobalAddress,  MVT::i64, Custom);
-  setOperationAction(ISD::ConstantPool,   MVT::i64, Custom);
-  setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
-  setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
-
-  setOperationAction(ISD::VASTART, MVT::Other, Custom);
-  setOperationAction(ISD::VAEND,   MVT::Other, Expand);
-  setOperationAction(ISD::VACOPY,  MVT::Other, Custom);
-  setOperationAction(ISD::VAARG,   MVT::Other, Custom);
-  setOperationAction(ISD::VAARG,   MVT::i32,   Custom);
-
-  setOperationAction(ISD::JumpTable, MVT::i64, Custom);
-  setOperationAction(ISD::JumpTable, MVT::i32, Custom);
-
-  setOperationAction(ISD::ATOMIC_LOAD,  MVT::i32, Expand);
-  setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
-
-  setStackPointerRegisterToSaveRestore(Alpha::R30);
-
-  setJumpBufSize(272);
-  setJumpBufAlignment(16);
-
-  setMinFunctionAlignment(4);
-
-  setInsertFencesForAtomic(true);
-
-  computeRegisterProperties();
-}
-
-EVT AlphaTargetLowering::getSetCCResultType(EVT VT) const {
-  return MVT::i64;
-}
-
-const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
-  switch (Opcode) {
-  default: return 0;
-  case AlphaISD::CVTQT_: return "Alpha::CVTQT_";
-  case AlphaISD::CVTQS_: return "Alpha::CVTQS_";
-  case AlphaISD::CVTTQ_: return "Alpha::CVTTQ_";
-  case AlphaISD::GPRelHi: return "Alpha::GPRelHi";
-  case AlphaISD::GPRelLo: return "Alpha::GPRelLo";
-  case AlphaISD::RelLit: return "Alpha::RelLit";
-  case AlphaISD::GlobalRetAddr: return "Alpha::GlobalRetAddr";
-  case AlphaISD::CALL:   return "Alpha::CALL";
-  case AlphaISD::DivCall: return "Alpha::DivCall";
-  case AlphaISD::RET_FLAG: return "Alpha::RET_FLAG";
-  case AlphaISD::COND_BRANCH_I: return "Alpha::COND_BRANCH_I";
-  case AlphaISD::COND_BRANCH_F: return "Alpha::COND_BRANCH_F";
-  }
-}
-
-static SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
-  EVT PtrVT = Op.getValueType();
-  JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
-  SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
-  // FIXME there isn't really any debug info here
-  DebugLoc dl = Op.getDebugLoc();
-
-  SDValue Hi = DAG.getNode(AlphaISD::GPRelHi,  dl, MVT::i64, JTI,
-                             DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
-  SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, JTI, Hi);
-  return Lo;
-}
-
-//http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/
-//AA-PY8AC-TET1_html/callCH3.html#BLOCK21
-
-//For now, just use variable size stack frame format
-
-//In a standard call, the first six items are passed in registers $16
-//- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
-//of argument-to-register correspondence.) The remaining items are
-//collected in a memory argument list that is a naturally aligned
-//array of quadwords. In a standard call, this list, if present, must
-//be passed at 0(SP).
-//7 ... n         0(SP) ... (n-7)*8(SP)
-
-// //#define FP    $15
-// //#define RA    $26
-// //#define PV    $27
-// //#define GP    $29
-// //#define SP    $30
-
-#include "AlphaGenCallingConv.inc"
-
-SDValue
-AlphaTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
-                               CallingConv::ID CallConv, bool isVarArg,
-                               bool &isTailCall,
-                               const SmallVectorImpl<ISD::OutputArg> &Outs,
-                               const SmallVectorImpl<SDValue> &OutVals,
-                               const SmallVectorImpl<ISD::InputArg> &Ins,
-                               DebugLoc dl, SelectionDAG &DAG,
-                               SmallVectorImpl<SDValue> &InVals) const {
-  // Alpha target does not yet support tail call optimization.
-  isTailCall = false;
-
-  // Analyze operands of the call, assigning locations to each operand.
-  SmallVector<CCValAssign, 16> ArgLocs;
-  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
-		 getTargetMachine(), ArgLocs, *DAG.getContext());
-
-  CCInfo.AnalyzeCallOperands(Outs, CC_Alpha);
-
-    // Get a count of how many bytes are to be pushed on the stack.
-  unsigned NumBytes = CCInfo.getNextStackOffset();
-
-  Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes,
-                                                      getPointerTy(), true));
-
-  SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
-  SmallVector<SDValue, 12> MemOpChains;
-  SDValue StackPtr;
-
-  // Walk the register/memloc assignments, inserting copies/loads.
-  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
-    CCValAssign &VA = ArgLocs[i];
-
-    SDValue Arg = OutVals[i];
-
-    // Promote the value if needed.
-    switch (VA.getLocInfo()) {
-      default: assert(0 && "Unknown loc info!");
-      case CCValAssign::Full: break;
-      case CCValAssign::SExt:
-        Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
-        break;
-      case CCValAssign::ZExt:
-        Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
-        break;
-      case CCValAssign::AExt:
-        Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
-        break;
-    }
-
-    // Arguments that can be passed on register must be kept at RegsToPass
-    // vector
-    if (VA.isRegLoc()) {
-      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
-    } else {
-      assert(VA.isMemLoc());
-
-      if (StackPtr.getNode() == 0)
-        StackPtr = DAG.getCopyFromReg(Chain, dl, Alpha::R30, MVT::i64);
-
-      SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
-                                   StackPtr,
-                                   DAG.getIntPtrConstant(VA.getLocMemOffset()));
-
-      MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
-                                         MachinePointerInfo(),false, false, 0));
-    }
-  }
-
-  // Transform all store nodes into one single node because all store nodes are
-  // independent of each other.
-  if (!MemOpChains.empty())
-    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
-                        &MemOpChains[0], MemOpChains.size());
-
-  // Build a sequence of copy-to-reg nodes chained together with token chain and
-  // flag operands which copy the outgoing args into registers.  The InFlag in
-  // necessary since all emitted instructions must be stuck together.
-  SDValue InFlag;
-  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
-    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
-                             RegsToPass[i].second, InFlag);
-    InFlag = Chain.getValue(1);
-  }
-
-  // Returns a chain & a flag for retval copy to use.
-  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
-  SmallVector<SDValue, 8> Ops;
-  Ops.push_back(Chain);
-  Ops.push_back(Callee);
-
-  // Add argument registers to the end of the list so that they are
-  // known live into the call.
-  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
-    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
-                                  RegsToPass[i].second.getValueType()));
-
-  if (InFlag.getNode())
-    Ops.push_back(InFlag);
-
-  Chain = DAG.getNode(AlphaISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
-  InFlag = Chain.getValue(1);
-
-  // Create the CALLSEQ_END node.
-  Chain = DAG.getCALLSEQ_END(Chain,
-                             DAG.getConstant(NumBytes, getPointerTy(), true),
-                             DAG.getConstant(0, getPointerTy(), true),
-                             InFlag);
-  InFlag = Chain.getValue(1);
-
-  // Handle result values, copying them out of physregs into vregs that we
-  // return.
-  return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
-                         Ins, dl, DAG, InVals);
-}
-
-/// LowerCallResult - Lower the result values of a call into the
-/// appropriate copies out of appropriate physical registers.
-///
-SDValue
-AlphaTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
-                                     CallingConv::ID CallConv, bool isVarArg,
-                                     const SmallVectorImpl<ISD::InputArg> &Ins,
-                                     DebugLoc dl, SelectionDAG &DAG,
-                                     SmallVectorImpl<SDValue> &InVals) const {
-
-  // Assign locations to each value returned by this call.
-  SmallVector<CCValAssign, 16> RVLocs;
-  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
-		 getTargetMachine(), RVLocs, *DAG.getContext());
-
-  CCInfo.AnalyzeCallResult(Ins, RetCC_Alpha);
-
-  // Copy all of the result registers out of their specified physreg.
-  for (unsigned i = 0; i != RVLocs.size(); ++i) {
-    CCValAssign &VA = RVLocs[i];
-
-    Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
-                               VA.getLocVT(), InFlag).getValue(1);
-    SDValue RetValue = Chain.getValue(0);
-    InFlag = Chain.getValue(2);
-
-    // If this is an 8/16/32-bit value, it is really passed promoted to 64
-    // bits. Insert an assert[sz]ext to capture this, then truncate to the
-    // right size.
-    if (VA.getLocInfo() == CCValAssign::SExt)
-      RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue,
-                             DAG.getValueType(VA.getValVT()));
-    else if (VA.getLocInfo() == CCValAssign::ZExt)
-      RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue,
-                             DAG.getValueType(VA.getValVT()));
-
-    if (VA.getLocInfo() != CCValAssign::Full)
-      RetValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), RetValue);
-
-    InVals.push_back(RetValue);
-  }
-
-  return Chain;
-}
-
-SDValue
-AlphaTargetLowering::LowerFormalArguments(SDValue Chain,
-                                          CallingConv::ID CallConv, bool isVarArg,
-                                          const SmallVectorImpl<ISD::InputArg>
-                                            &Ins,
-                                          DebugLoc dl, SelectionDAG &DAG,
-                                          SmallVectorImpl<SDValue> &InVals)
-                                            const {
-
-  MachineFunction &MF = DAG.getMachineFunction();
-  MachineFrameInfo *MFI = MF.getFrameInfo();
-  AlphaMachineFunctionInfo *FuncInfo = MF.getInfo<AlphaMachineFunctionInfo>();
-
-  unsigned args_int[] = {
-    Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
-  unsigned args_float[] = {
-    Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
-
-  for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
-    SDValue argt;
-    EVT ObjectVT = Ins[ArgNo].VT;
-    SDValue ArgVal;
-
-    if (ArgNo  < 6) {
-      switch (ObjectVT.getSimpleVT().SimpleTy) {
-      default:
-        assert(false && "Invalid value type!");
-      case MVT::f64:
-        args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
-                                      &Alpha::F8RCRegClass);
-        ArgVal = DAG.getCopyFromReg(Chain, dl, args_float[ArgNo], ObjectVT);
-        break;
-      case MVT::f32:
-        args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
-                                      &Alpha::F4RCRegClass);
-        ArgVal = DAG.getCopyFromReg(Chain, dl, args_float[ArgNo], ObjectVT);
-        break;
-      case MVT::i64:
-        args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo],
-                                    &Alpha::GPRCRegClass);
-        ArgVal = DAG.getCopyFromReg(Chain, dl, args_int[ArgNo], MVT::i64);
-        break;
-      }
-    } else { //more args
-      // Create the frame index object for this incoming parameter...
-      int FI = MFI->CreateFixedObject(8, 8 * (ArgNo - 6), true);
-
-      // Create the SelectionDAG nodes corresponding to a load
-      //from this parameter
-      SDValue FIN = DAG.getFrameIndex(FI, MVT::i64);
-      ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
-                           false, false, 0);
-    }
-    InVals.push_back(ArgVal);
-  }
-
-  // If the functions takes variable number of arguments, copy all regs to stack
-  if (isVarArg) {
-    FuncInfo->setVarArgsOffset(Ins.size() * 8);
-    std::vector<SDValue> LS;
-    for (int i = 0; i < 6; ++i) {
-      if (TargetRegisterInfo::isPhysicalRegister(args_int[i]))
-        args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass);
-      SDValue argt = DAG.getCopyFromReg(Chain, dl, args_int[i], MVT::i64);
-      int FI = MFI->CreateFixedObject(8, -8 * (6 - i), true);
-      if (i == 0) FuncInfo->setVarArgsBase(FI);
-      SDValue SDFI = DAG.getFrameIndex(FI, MVT::i64);
-      LS.push_back(DAG.getStore(Chain, dl, argt, SDFI, MachinePointerInfo(),
-                                false, false, 0));
-
-      if (TargetRegisterInfo::isPhysicalRegister(args_float[i]))
-        args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass);
-      argt = DAG.getCopyFromReg(Chain, dl, args_float[i], MVT::f64);
-      FI = MFI->CreateFixedObject(8, - 8 * (12 - i), true);
-      SDFI = DAG.getFrameIndex(FI, MVT::i64);
-      LS.push_back(DAG.getStore(Chain, dl, argt, SDFI, MachinePointerInfo(),
-                                false, false, 0));
-    }
-
-    //Set up a token factor with all the stack traffic
-    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &LS[0], LS.size());
-  }
-
-  return Chain;
-}
-
-SDValue
-AlphaTargetLowering::LowerReturn(SDValue Chain,
-                                 CallingConv::ID CallConv, bool isVarArg,
-                                 const SmallVectorImpl<ISD::OutputArg> &Outs,
-                                 const SmallVectorImpl<SDValue> &OutVals,
-                                 DebugLoc dl, SelectionDAG &DAG) const {
-
-  SDValue Copy = DAG.getCopyToReg(Chain, dl, Alpha::R26,
-                                  DAG.getNode(AlphaISD::GlobalRetAddr,
-                                              DebugLoc(), MVT::i64),
-                                  SDValue());
-  switch (Outs.size()) {
-  default:
-    llvm_unreachable("Do not know how to return this many arguments!");
-  case 0:
-    break;
-    //return SDValue(); // ret void is legal
-  case 1: {
-    EVT ArgVT = Outs[0].VT;
-    unsigned ArgReg;
-    if (ArgVT.isInteger())
-      ArgReg = Alpha::R0;
-    else {
-      assert(ArgVT.isFloatingPoint());
-      ArgReg = Alpha::F0;
-    }
-    Copy = DAG.getCopyToReg(Copy, dl, ArgReg,
-                            OutVals[0], Copy.getValue(1));
-    if (DAG.getMachineFunction().getRegInfo().liveout_empty())
-      DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg);
-    break;
-  }
-  case 2: {
-    EVT ArgVT = Outs[0].VT;
-    unsigned ArgReg1, ArgReg2;
-    if (ArgVT.isInteger()) {
-      ArgReg1 = Alpha::R0;
-      ArgReg2 = Alpha::R1;
-    } else {
-      assert(ArgVT.isFloatingPoint());
-      ArgReg1 = Alpha::F0;
-      ArgReg2 = Alpha::F1;
-    }
-    Copy = DAG.getCopyToReg(Copy, dl, ArgReg1,
-                            OutVals[0], Copy.getValue(1));
-    if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
-                  DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg1)
-        == DAG.getMachineFunction().getRegInfo().liveout_end())
-      DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg1);
-    Copy = DAG.getCopyToReg(Copy, dl, ArgReg2,
-                            OutVals[1], Copy.getValue(1));
-    if (std::find(DAG.getMachineFunction().getRegInfo().liveout_begin(),
-                   DAG.getMachineFunction().getRegInfo().liveout_end(), ArgReg2)
-        == DAG.getMachineFunction().getRegInfo().liveout_end())
-      DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg2);
-    break;
-  }
-  }
-  return DAG.getNode(AlphaISD::RET_FLAG, dl,
-                     MVT::Other, Copy, Copy.getValue(1));
-}
-
-void AlphaTargetLowering::LowerVAARG(SDNode *N, SDValue &Chain,
-                                     SDValue &DataPtr,
-                                     SelectionDAG &DAG) const {
-  Chain = N->getOperand(0);
-  SDValue VAListP = N->getOperand(1);
-  const Value *VAListS = cast<SrcValueSDNode>(N->getOperand(2))->getValue();
-  DebugLoc dl = N->getDebugLoc();
-
-  SDValue Base = DAG.getLoad(MVT::i64, dl, Chain, VAListP,
-                             MachinePointerInfo(VAListS),
-                             false, false, 0);
-  SDValue Tmp = DAG.getNode(ISD::ADD, dl, MVT::i64, VAListP,
-                              DAG.getConstant(8, MVT::i64));
-  SDValue Offset = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Base.getValue(1),
-                                  Tmp, MachinePointerInfo(),
-                                  MVT::i32, false, false, 0);
-  DataPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Base, Offset);
-  if (N->getValueType(0).isFloatingPoint())
-  {
-    //if fp && Offset < 6*8, then subtract 6*8 from DataPtr
-    SDValue FPDataPtr = DAG.getNode(ISD::SUB, dl, MVT::i64, DataPtr,
-                                      DAG.getConstant(8*6, MVT::i64));
-    SDValue CC = DAG.getSetCC(dl, MVT::i64, Offset,
-                                DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
-    DataPtr = DAG.getNode(ISD::SELECT, dl, MVT::i64, CC, FPDataPtr, DataPtr);
-  }
-
-  SDValue NewOffset = DAG.getNode(ISD::ADD, dl, MVT::i64, Offset,
-                                    DAG.getConstant(8, MVT::i64));
-  Chain = DAG.getTruncStore(Offset.getValue(1), dl, NewOffset, Tmp,
-                            MachinePointerInfo(),
-                            MVT::i32, false, false, 0);
-}
-
-/// LowerOperation - Provide custom lowering hooks for some operations.
-///
-SDValue AlphaTargetLowering::LowerOperation(SDValue Op,
-                                            SelectionDAG &DAG) const {
-  DebugLoc dl = Op.getDebugLoc();
-  switch (Op.getOpcode()) {
-  default: llvm_unreachable("Wasn't expecting to be able to lower this!");
-  case ISD::JumpTable: return LowerJumpTable(Op, DAG);
-
-  case ISD::INTRINSIC_WO_CHAIN: {
-    unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
-    switch (IntNo) {
-    default: break;    // Don't custom lower most intrinsics.
-    case Intrinsic::alpha_umulh:
-      return DAG.getNode(ISD::MULHU, dl, MVT::i64,
-                         Op.getOperand(1), Op.getOperand(2));
-    }
-  }
-
-  case ISD::SRL_PARTS: {
-    SDValue ShOpLo = Op.getOperand(0);
-    SDValue ShOpHi = Op.getOperand(1);
-    SDValue ShAmt  = Op.getOperand(2);
-    SDValue bm = DAG.getNode(ISD::SUB, dl, MVT::i64,
-                             DAG.getConstant(64, MVT::i64), ShAmt);
-    SDValue BMCC = DAG.getSetCC(dl, MVT::i64, bm,
-                                DAG.getConstant(0, MVT::i64), ISD::SETLE);
-    // if 64 - shAmt <= 0
-    SDValue Hi_Neg = DAG.getConstant(0, MVT::i64);
-    SDValue ShAmt_Neg = DAG.getNode(ISD::SUB, dl, MVT::i64,
-                                    DAG.getConstant(0, MVT::i64), bm);
-    SDValue Lo_Neg = DAG.getNode(ISD::SRL, dl, MVT::i64, ShOpHi, ShAmt_Neg);
-    // else
-    SDValue carries = DAG.getNode(ISD::SHL, dl, MVT::i64, ShOpHi, bm);
-    SDValue Hi_Pos =  DAG.getNode(ISD::SRL, dl, MVT::i64, ShOpHi, ShAmt);
-    SDValue Lo_Pos = DAG.getNode(ISD::SRL, dl, MVT::i64, ShOpLo, ShAmt);
-    Lo_Pos = DAG.getNode(ISD::OR, dl, MVT::i64, Lo_Pos, carries);
-    // Merge
-    SDValue Hi = DAG.getNode(ISD::SELECT, dl, MVT::i64, BMCC, Hi_Neg, Hi_Pos);
-    SDValue Lo = DAG.getNode(ISD::SELECT, dl, MVT::i64, BMCC, Lo_Neg, Lo_Pos);
-    SDValue Ops[2] = { Lo, Hi };
-    return DAG.getMergeValues(Ops, 2, dl);
-  }
-    //  case ISD::SRA_PARTS:
-
-    //  case ISD::SHL_PARTS:
-
-
-  case ISD::SINT_TO_FP: {
-    assert(Op.getOperand(0).getValueType() == MVT::i64 &&
-           "Unhandled SINT_TO_FP type in custom expander!");
-    SDValue LD;
-    bool isDouble = Op.getValueType() == MVT::f64;
-    LD = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op.getOperand(0));
-    SDValue FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_, dl,
-                               isDouble?MVT::f64:MVT::f32, LD);
-    return FP;
-  }
-  case ISD::FP_TO_SINT: {
-    bool isDouble = Op.getOperand(0).getValueType() == MVT::f64;
-    SDValue src = Op.getOperand(0);
-
-    if (!isDouble) //Promote
-      src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, src);
-
-    src = DAG.getNode(AlphaISD::CVTTQ_, dl, MVT::f64, src);
-
-    return DAG.getNode(ISD::BITCAST, dl, MVT::i64, src);
-  }
-  case ISD::ConstantPool: {
-    ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
-    const Constant *C = CP->getConstVal();
-    SDValue CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
-    // FIXME there isn't really any debug info here
-
-    SDValue Hi = DAG.getNode(AlphaISD::GPRelHi,  dl, MVT::i64, CPI,
-                               DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
-    SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, CPI, Hi);
-    return Lo;
-  }
-  case ISD::GlobalTLSAddress:
-    llvm_unreachable("TLS not implemented for Alpha.");
-  case ISD::GlobalAddress: {
-    GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
-    const GlobalValue *GV = GSDN->getGlobal();
-    SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i64,
-                                            GSDN->getOffset());
-    // FIXME there isn't really any debug info here
-
-    //    if (!GV->hasWeakLinkage() && !GV->isDeclaration()
-    //        && !GV->hasLinkOnceLinkage()) {
-    if (GV->hasLocalLinkage()) {
-      SDValue Hi = DAG.getNode(AlphaISD::GPRelHi,  dl, MVT::i64, GA,
-                                DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
-      SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, GA, Hi);
-      return Lo;
-    } else
-      return DAG.getNode(AlphaISD::RelLit, dl, MVT::i64, GA,
-                         DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
-  }
-  case ISD::ExternalSymbol: {
-    return DAG.getNode(AlphaISD::RelLit, dl, MVT::i64,
-                       DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)
-                                                   ->getSymbol(), MVT::i64),
-                       DAG.getGLOBAL_OFFSET_TABLE(MVT::i64));
-  }
-
-  case ISD::UREM:
-  case ISD::SREM:
-    //Expand only on constant case
-    if (Op.getOperand(1).getOpcode() == ISD::Constant) {
-      EVT VT = Op.getNode()->getValueType(0);
-      SDValue Tmp1 = Op.getNode()->getOpcode() == ISD::UREM ?
-        BuildUDIV(Op.getNode(), DAG, NULL) :
-        BuildSDIV(Op.getNode(), DAG, NULL);
-      Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Op.getOperand(1));
-      Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Op.getOperand(0), Tmp1);
-      return Tmp1;
-    }
-    //fall through
-  case ISD::SDIV:
-  case ISD::UDIV:
-    if (Op.getValueType().isInteger()) {
-      if (Op.getOperand(1).getOpcode() == ISD::Constant)
-        return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.getNode(), DAG, NULL)
-          : BuildUDIV(Op.getNode(), DAG, NULL);
-      const char* opstr = 0;
-      switch (Op.getOpcode()) {
-      case ISD::UREM: opstr = "__remqu"; break;
-      case ISD::SREM: opstr = "__remq";  break;
-      case ISD::UDIV: opstr = "__divqu"; break;
-      case ISD::SDIV: opstr = "__divq";  break;
-      }
-      SDValue Tmp1 = Op.getOperand(0),
-        Tmp2 = Op.getOperand(1),
-        Addr = DAG.getExternalSymbol(opstr, MVT::i64);
-      return DAG.getNode(AlphaISD::DivCall, dl, MVT::i64, Addr, Tmp1, Tmp2);
-    }
-    break;
-
-  case ISD::VAARG: {
-    SDValue Chain, DataPtr;
-    LowerVAARG(Op.getNode(), Chain, DataPtr, DAG);
-
-    SDValue Result;
-    if (Op.getValueType() == MVT::i32)
-      Result = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Chain, DataPtr,
-                              MachinePointerInfo(), MVT::i32, false, false, 0);
-    else
-      Result = DAG.getLoad(Op.getValueType(), dl, Chain, DataPtr,
-                           MachinePointerInfo(),
-                           false, false, 0);
-    return Result;
-  }
-  case ISD::VACOPY: {
-    SDValue Chain = Op.getOperand(0);
-    SDValue DestP = Op.getOperand(1);
-    SDValue SrcP = Op.getOperand(2);
-    const Value *DestS = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
-    const Value *SrcS = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
-
-    SDValue Val = DAG.getLoad(getPointerTy(), dl, Chain, SrcP,
-                              MachinePointerInfo(SrcS),
-                              false, false, 0);
-    SDValue Result = DAG.getStore(Val.getValue(1), dl, Val, DestP,
-                                  MachinePointerInfo(DestS),
-                                  false, false, 0);
-    SDValue NP = DAG.getNode(ISD::ADD, dl, MVT::i64, SrcP,
-                               DAG.getConstant(8, MVT::i64));
-    Val = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Result,
-                         NP, MachinePointerInfo(), MVT::i32, false, false, 0);
-    SDValue NPD = DAG.getNode(ISD::ADD, dl, MVT::i64, DestP,
-                                DAG.getConstant(8, MVT::i64));
-    return DAG.getTruncStore(Val.getValue(1), dl, Val, NPD,
-                             MachinePointerInfo(), MVT::i32,
-                             false, false, 0);
-  }
-  case ISD::VASTART: {
-    MachineFunction &MF = DAG.getMachineFunction();
-    AlphaMachineFunctionInfo *FuncInfo = MF.getInfo<AlphaMachineFunctionInfo>();
-
-    SDValue Chain = Op.getOperand(0);
-    SDValue VAListP = Op.getOperand(1);
-    const Value *VAListS = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
-
-    // vastart stores the address of the VarArgsBase and VarArgsOffset
-    SDValue FR  = DAG.getFrameIndex(FuncInfo->getVarArgsBase(), MVT::i64);
-    SDValue S1  = DAG.getStore(Chain, dl, FR, VAListP,
-                               MachinePointerInfo(VAListS), false, false, 0);
-    SDValue SA2 = DAG.getNode(ISD::ADD, dl, MVT::i64, VAListP,
-                                DAG.getConstant(8, MVT::i64));
-    return DAG.getTruncStore(S1, dl,
-                             DAG.getConstant(FuncInfo->getVarArgsOffset(),
-                                             MVT::i64),
-                             SA2, MachinePointerInfo(),
-                             MVT::i32, false, false, 0);
-  }
-  case ISD::RETURNADDR:
-    return DAG.getNode(AlphaISD::GlobalRetAddr, DebugLoc(), MVT::i64);
-      //FIXME: implement
-  case ISD::FRAMEADDR:          break;
-  }
-
-  return SDValue();
-}
-
-void AlphaTargetLowering::ReplaceNodeResults(SDNode *N,
-                                             SmallVectorImpl<SDValue>&Results,
-                                             SelectionDAG &DAG) const {
-  DebugLoc dl = N->getDebugLoc();
-  assert(N->getValueType(0) == MVT::i32 &&
-         N->getOpcode() == ISD::VAARG &&
-         "Unknown node to custom promote!");
-
-  SDValue Chain, DataPtr;
-  LowerVAARG(N, Chain, DataPtr, DAG);
-  SDValue Res = DAG.getLoad(N->getValueType(0), dl, Chain, DataPtr,
-                            MachinePointerInfo(),
-                            false, false, 0);
-  Results.push_back(Res);
-  Results.push_back(SDValue(Res.getNode(), 1));
-}
-
-
-//Inline Asm
-
-/// getConstraintType - Given a constraint letter, return the type of
-/// constraint it is for this target.
-AlphaTargetLowering::ConstraintType
-AlphaTargetLowering::getConstraintType(const std::string &Constraint) const {
-  if (Constraint.size() == 1) {
-    switch (Constraint[0]) {
-    default: break;
-    case 'f':
-    case 'r':
-      return C_RegisterClass;
-    }
-  }
-  return TargetLowering::getConstraintType(Constraint);
-}
-
-/// Examine constraint type and operand type and determine a weight value.
-/// This object must already have been set up with the operand type
-/// and the current alternative constraint selected.
-TargetLowering::ConstraintWeight
-AlphaTargetLowering::getSingleConstraintMatchWeight(
-    AsmOperandInfo &info, const char *constraint) const {
-  ConstraintWeight weight = CW_Invalid;
-  Value *CallOperandVal = info.CallOperandVal;
-    // If we don't have a value, we can't do a match,
-    // but allow it at the lowest weight.
-  if (CallOperandVal == NULL)
-    return CW_Default;
-  // Look at the constraint type.
-  switch (*constraint) {
-  default:
-    weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
-    break;
-  case 'f':
-    weight = CW_Register;
-    break;
-  }
-  return weight;
-}
-
-/// Given a register class constraint, like 'r', if this corresponds directly
-/// to an LLVM register class, return a register of 0 and the register class
-/// pointer.
-std::pair<unsigned, const TargetRegisterClass*> AlphaTargetLowering::
-getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
-{
-  if (Constraint.size() == 1) {
-    switch (Constraint[0]) {
-    case 'r':
-      return std::make_pair(0U, Alpha::GPRCRegisterClass);
-    case 'f':
-      return VT == MVT::f64 ? std::make_pair(0U, Alpha::F8RCRegisterClass) :
-	std::make_pair(0U, Alpha::F4RCRegisterClass);
-    }
-  }
-  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
-}
-
-//===----------------------------------------------------------------------===//
-//  Other Lowering Code
-//===----------------------------------------------------------------------===//
-
-MachineBasicBlock *
-AlphaTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
-                                                 MachineBasicBlock *BB) const {
-  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
-  assert((MI->getOpcode() == Alpha::CAS32 ||
-          MI->getOpcode() == Alpha::CAS64 ||
-          MI->getOpcode() == Alpha::LAS32 ||
-          MI->getOpcode() == Alpha::LAS64 ||
-          MI->getOpcode() == Alpha::SWAP32 ||
-          MI->getOpcode() == Alpha::SWAP64) &&
-         "Unexpected instr type to insert");
-
-  bool is32 = MI->getOpcode() == Alpha::CAS32 ||
-    MI->getOpcode() == Alpha::LAS32 ||
-    MI->getOpcode() == Alpha::SWAP32;
-
-  //Load locked store conditional for atomic ops take on the same form
-  //start:
-  //ll
-  //do stuff (maybe branch to exit)
-  //sc
-  //test sc and maybe branck to start
-  //exit:
-  const BasicBlock *LLVM_BB = BB->getBasicBlock();
-  DebugLoc dl = MI->getDebugLoc();
-  MachineFunction::iterator It = BB;
-  ++It;
-
-  MachineBasicBlock *thisMBB = BB;
-  MachineFunction *F = BB->getParent();
-  MachineBasicBlock *llscMBB = F->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
-
-  sinkMBB->splice(sinkMBB->begin(), thisMBB,
-                  llvm::next(MachineBasicBlock::iterator(MI)),
-                  thisMBB->end());
-  sinkMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
-
-  F->insert(It, llscMBB);
-  F->insert(It, sinkMBB);
-
-  BuildMI(thisMBB, dl, TII->get(Alpha::BR)).addMBB(llscMBB);
-
-  unsigned reg_res = MI->getOperand(0).getReg(),
-    reg_ptr = MI->getOperand(1).getReg(),
-    reg_v2 = MI->getOperand(2).getReg(),
-    reg_store = F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass);
-
-  BuildMI(llscMBB, dl, TII->get(is32 ? Alpha::LDL_L : Alpha::LDQ_L),
-          reg_res).addImm(0).addReg(reg_ptr);
-  switch (MI->getOpcode()) {
-  case Alpha::CAS32:
-  case Alpha::CAS64: {
-    unsigned reg_cmp
-      = F->getRegInfo().createVirtualRegister(&Alpha::GPRCRegClass);
-    BuildMI(llscMBB, dl, TII->get(Alpha::CMPEQ), reg_cmp)
-      .addReg(reg_v2).addReg(reg_res);
-    BuildMI(llscMBB, dl, TII->get(Alpha::BEQ))
-      .addImm(0).addReg(reg_cmp).addMBB(sinkMBB);
-    BuildMI(llscMBB, dl, TII->get(Alpha::BISr), reg_store)
-      .addReg(Alpha::R31).addReg(MI->getOperand(3).getReg());
-    break;
-  }
-  case Alpha::LAS32:
-  case Alpha::LAS64: {
-    BuildMI(llscMBB, dl,TII->get(is32 ? Alpha::ADDLr : Alpha::ADDQr), reg_store)
-      .addReg(reg_res).addReg(reg_v2);
-    break;
-  }
-  case Alpha::SWAP32:
-  case Alpha::SWAP64: {
-    BuildMI(llscMBB, dl, TII->get(Alpha::BISr), reg_store)
-      .addReg(reg_v2).addReg(reg_v2);
-    break;
-  }
-  }
-  BuildMI(llscMBB, dl, TII->get(is32 ? Alpha::STL_C : Alpha::STQ_C), reg_store)
-    .addReg(reg_store).addImm(0).addReg(reg_ptr);
-  BuildMI(llscMBB, dl, TII->get(Alpha::BEQ))
-    .addImm(0).addReg(reg_store).addMBB(llscMBB);
-  BuildMI(llscMBB, dl, TII->get(Alpha::BR)).addMBB(sinkMBB);
-
-  thisMBB->addSuccessor(llscMBB);
-  llscMBB->addSuccessor(llscMBB);
-  llscMBB->addSuccessor(sinkMBB);
-  MI->eraseFromParent();   // The pseudo instruction is gone now.
-
-  return sinkMBB;
-}
-
-bool
-AlphaTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
-  // The Alpha target isn't yet aware of offsets.
-  return false;
-}
-
-bool AlphaTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
-  if (VT != MVT::f32 && VT != MVT::f64)
-    return false;
-  // +0.0   F31
-  // +0.0f  F31
-  // -0.0  -F31
-  // -0.0f -F31
-  return Imm.isZero() || Imm.isNegZero();
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/AlphaISelLowering.h
--- a/head/contrib/llvm/lib/Target/Alpha/AlphaISelLowering.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,142 +0,0 @@
-//===-- AlphaISelLowering.h - Alpha DAG Lowering Interface ------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines the interfaces that Alpha uses to lower LLVM code into a
-// selection DAG.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_TARGET_ALPHA_ALPHAISELLOWERING_H
-#define LLVM_TARGET_ALPHA_ALPHAISELLOWERING_H
-
-#include "llvm/ADT/VectorExtras.h"
-#include "llvm/Target/TargetLowering.h"
-#include "llvm/CodeGen/SelectionDAG.h"
-#include "Alpha.h"
-
-namespace llvm {
-
-  namespace AlphaISD {
-    enum NodeType {
-      // Start the numbering where the builting ops and target ops leave off.
-      FIRST_NUMBER = ISD::BUILTIN_OP_END,
-      //These corrospond to the identical Instruction
-      CVTQT_, CVTQS_, CVTTQ_,
-
-      /// GPRelHi/GPRelLo - These represent the high and low 16-bit
-      /// parts of a global address respectively.
-      GPRelHi, GPRelLo,
-
-      /// RetLit - Literal Relocation of a Global
-      RelLit,
-
-      /// GlobalRetAddr - used to restore the return address
-      GlobalRetAddr,
-
-      /// CALL - Normal call.
-      CALL,
-
-      /// DIVCALL - used for special library calls for div and rem
-      DivCall,
-
-      /// return flag operand
-      RET_FLAG,
-
-      /// CHAIN = COND_BRANCH CHAIN, OPC, (G|F)PRC, DESTBB [, INFLAG] - This
-      /// corresponds to the COND_BRANCH pseudo instruction.
-      /// *PRC is the input register to compare to zero,
-      /// OPC is the branch opcode to use (e.g. Alpha::BEQ),
-      /// DESTBB is the destination block to branch to, and INFLAG is
-      /// an optional input flag argument.
-      COND_BRANCH_I, COND_BRANCH_F
-
-    };
-  }
-
-  class AlphaTargetLowering : public TargetLowering {
-  public:
-    explicit AlphaTargetLowering(TargetMachine &TM);
-
-    virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i64; }
-
-    /// getSetCCResultType - Get the SETCC result ValueType
-    virtual EVT getSetCCResultType(EVT VT) const;
-
-    /// LowerOperation - Provide custom lowering hooks for some operations.
-    ///
-    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
-
-    /// ReplaceNodeResults - Replace the results of node with an illegal result
-    /// type with new values built out of custom code.
-    ///
-    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
-                                    SelectionDAG &DAG) const;
-
-    // Friendly names for dumps
-    const char *getTargetNodeName(unsigned Opcode) const;
-
-    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
-                            CallingConv::ID CallConv, bool isVarArg,
-                            const SmallVectorImpl<ISD::InputArg> &Ins,
-                            DebugLoc dl, SelectionDAG &DAG,
-                            SmallVectorImpl<SDValue> &InVals) const;
-
-    ConstraintType getConstraintType(const std::string &Constraint) const;
-
-    /// Examine constraint string and operand type and determine a weight value.
-    /// The operand object must already have been set up with the operand type.
-    ConstraintWeight getSingleConstraintMatchWeight(
-      AsmOperandInfo &info, const char *constraint) const;
-
-    std::pair<unsigned, const TargetRegisterClass*>
-    getRegForInlineAsmConstraint(const std::string &Constraint,
-				 EVT VT) const;
-
-    MachineBasicBlock *
-      EmitInstrWithCustomInserter(MachineInstr *MI,
-                                  MachineBasicBlock *BB) const;
-
-    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
-
-    /// isFPImmLegal - Returns true if the target can instruction select the
-    /// specified FP immediate natively. If false, the legalizer will
-    /// materialize the FP immediate as a load from a constant pool.
-    virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
-
-  private:
-    // Helpers for custom lowering.
-    void LowerVAARG(SDNode *N, SDValue &Chain, SDValue &DataPtr,
-                    SelectionDAG &DAG) const;
-
-    virtual SDValue
-      LowerFormalArguments(SDValue Chain,
-                           CallingConv::ID CallConv, bool isVarArg,
-                           const SmallVectorImpl<ISD::InputArg> &Ins,
-                           DebugLoc dl, SelectionDAG &DAG,
-                           SmallVectorImpl<SDValue> &InVals) const;
-
-    virtual SDValue
-      LowerCall(SDValue Chain, SDValue Callee,
-                CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
-                const SmallVectorImpl<ISD::OutputArg> &Outs,
-                const SmallVectorImpl<SDValue> &OutVals,
-                const SmallVectorImpl<ISD::InputArg> &Ins,
-                DebugLoc dl, SelectionDAG &DAG,
-                SmallVectorImpl<SDValue> &InVals) const;
-
-    virtual SDValue
-      LowerReturn(SDValue Chain,
-                  CallingConv::ID CallConv, bool isVarArg,
-                  const SmallVectorImpl<ISD::OutputArg> &Outs,
-                  const SmallVectorImpl<SDValue> &OutVals,
-                  DebugLoc dl, SelectionDAG &DAG) const;
-  };
-}
-
-#endif   // LLVM_TARGET_ALPHA_ALPHAISELLOWERING_H
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/AlphaInstrFormats.td
--- a/head/contrib/llvm/lib/Target/Alpha/AlphaInstrFormats.td	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,268 +0,0 @@
-//===- AlphaInstrFormats.td - Alpha Instruction Formats ----*- tablegen -*-===//
-// 
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-// 
-//===----------------------------------------------------------------------===//
-//
-//
-//===----------------------------------------------------------------------===//
-
-//3.3:
-//Memory
-//Branch
-//Operate
-//Floating-point
-//PALcode
-
-def u8imm   : Operand<i64>;
-def s14imm  : Operand<i64>;
-def s16imm  : Operand<i64>;
-def s21imm  : Operand<i64>;
-def s64imm  : Operand<i64>;
-def u64imm  : Operand<i64>;
-
-//===----------------------------------------------------------------------===//
-// Instruction format superclass
-//===----------------------------------------------------------------------===//
-// Alpha instruction baseline
-class InstAlpha<bits<6> op, string asmstr, InstrItinClass itin> : Instruction {
-  field bits<32> Inst;
-  let Namespace = "Alpha";
-  let AsmString = asmstr;
-  let Inst{31-26} = op;
-  let Itinerary = itin;
-}
-
-
-//3.3.1
-class MForm<bits<6> opcode, bit load, string asmstr, list<dag> pattern, InstrItinClass itin> 
-        : InstAlpha<opcode, asmstr, itin> {
-  let Pattern = pattern;
-  let canFoldAsLoad = load;
-  let Defs = [R28]; //We may use this for frame index calculations, so reserve it here
-
-  bits<5> Ra;
-  bits<16> disp;
-  bits<5> Rb;
-
-  let Inst{25-21} = Ra;
-  let Inst{20-16} = Rb;
-  let Inst{15-0} = disp;
-}
-class MfcForm<bits<6> opcode, bits<16> fc, string asmstr, InstrItinClass itin> 
-        : InstAlpha<opcode, asmstr, itin> {    
-  bits<5> Ra;
-
-  let OutOperandList = (outs GPRC:$RA);
-  let InOperandList = (ins);
-  let Inst{25-21} = Ra;
-  let Inst{20-16} = 0;
-  let Inst{15-0} = fc;
-}
-class MfcPForm<bits<6> opcode, bits<16> fc, string asmstr, InstrItinClass itin> 
-        : InstAlpha<opcode, asmstr, itin> {    
-  let OutOperandList = (outs);
-  let InOperandList = (ins);
-  let Inst{25-21} = 0;
-  let Inst{20-16} = 0;
-  let Inst{15-0} = fc;
-}
-
-class MbrForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr, InstrItinClass itin>
-    : InstAlpha<opcode, asmstr, itin> {
-  bits<5> Ra;
-  bits<5> Rb;
-  bits<14> disp;
-
-  let OutOperandList = (outs);
-  let InOperandList = OL;
-
-  let Inst{25-21} = Ra;
-  let Inst{20-16} = Rb;
-  let Inst{15-14} = TB;
-  let Inst{13-0} = disp;
-}
-class MbrpForm<bits<6> opcode, bits<2> TB, dag OL, string asmstr, list<dag> pattern, InstrItinClass itin>
-    : InstAlpha<opcode, asmstr, itin> {
-  let Pattern=pattern;
-  bits<5> Ra;
-  bits<5> Rb;
-  bits<14> disp;
-
-  let OutOperandList = (outs);
-  let InOperandList = OL;
-
-  let Inst{25-21} = Ra;
-  let Inst{20-16} = Rb;
-  let Inst{15-14} = TB;
-  let Inst{13-0} = disp;
-}
-
-//3.3.2
-def target : Operand<OtherVT> {}
-
-let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
-class BFormN<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
-   : InstAlpha<opcode, asmstr, itin> {
-  let OutOperandList = (outs);
-  let InOperandList = OL;
-  bits<64> Opc; //dummy
-  bits<5> Ra;
-  bits<21> disp;
-
-  let Inst{25-21} = Ra;
-  let Inst{20-0} = disp;
-}
-}
-
-let isBranch = 1, isTerminator = 1 in
-class BFormD<bits<6> opcode, string asmstr, list<dag> pattern, InstrItinClass itin> 
-    : InstAlpha<opcode, asmstr, itin> {
-  let Pattern = pattern;
-  let OutOperandList = (outs);
-  let InOperandList = (ins target:$DISP);
-  bits<5> Ra;
-  bits<21> disp;
-
-  let Inst{25-21} = Ra;
-  let Inst{20-0} = disp;
-}
-
-//3.3.3
-class OForm<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> 
-    : InstAlpha<opcode, asmstr, itin> {
-  let Pattern = pattern;
-  let OutOperandList = (outs GPRC:$RC);
-  let InOperandList = (ins GPRC:$RA, GPRC:$RB);
-
-  bits<5> Rc;
-  bits<5> Ra;
-  bits<5> Rb;
-  bits<7> Function = fun;
-
-  let Inst{25-21} = Ra;
-  let Inst{20-16} = Rb;
-  let Inst{15-13} = 0;
-  let Inst{12} = 0;
-  let Inst{11-5} = Function;
-  let Inst{4-0} = Rc;
-}
-
-class OForm2<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> 
-    : InstAlpha<opcode, asmstr, itin> {
-  let Pattern = pattern;
-  let OutOperandList = (outs GPRC:$RC);
-  let InOperandList = (ins GPRC:$RB);
-
-  bits<5> Rc;
-  bits<5> Rb;
-  bits<7> Function = fun;
-
-  let Inst{25-21} = 31;
-  let Inst{20-16} = Rb;
-  let Inst{15-13} = 0;
-  let Inst{12} = 0;
-  let Inst{11-5} = Function;
-  let Inst{4-0} = Rc;
-}
-
-class OForm4<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> 
-    : InstAlpha<opcode, asmstr, itin> {
-  let Pattern = pattern;
-  let OutOperandList = (outs GPRC:$RDEST);
-  let InOperandList = (ins GPRC:$RCOND, GPRC:$RTRUE, GPRC:$RFALSE);
-  let Constraints = "$RFALSE = $RDEST";
-  let DisableEncoding = "$RFALSE";
-
-  bits<5> Rc;
-  bits<5> Ra;
-  bits<5> Rb;
-  bits<7> Function = fun;
-
-//  let Constraints = "$RFALSE = $RDEST";
-  let Inst{25-21} = Ra;
-  let Inst{20-16} = Rb;
-  let Inst{15-13} = 0;
-  let Inst{12} = 0;
-  let Inst{11-5} = Function;
-  let Inst{4-0} = Rc;
-}
-
-
-class OFormL<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> 
-    : InstAlpha<opcode, asmstr, itin> {
-  let Pattern = pattern;
-  let OutOperandList = (outs GPRC:$RC);
-  let InOperandList = (ins GPRC:$RA, u8imm:$L);
-
-  bits<5> Rc;
-  bits<5> Ra;
-  bits<8> LIT;
-  bits<7> Function = fun;
-
-  let Inst{25-21} = Ra;
-  let Inst{20-13} = LIT;
-  let Inst{12} = 1;
-  let Inst{11-5} = Function;
-  let Inst{4-0} = Rc;
-}
-
-class OForm4L<bits<6> opcode, bits<7> fun, string asmstr, list<dag> pattern, InstrItinClass itin> 
-    : InstAlpha<opcode, asmstr, itin> {
-  let Pattern = pattern;
-  let OutOperandList = (outs GPRC:$RDEST);
-  let InOperandList = (ins GPRC:$RCOND, s64imm:$RTRUE, GPRC:$RFALSE);
-  let Constraints = "$RFALSE = $RDEST";
-  let DisableEncoding = "$RFALSE";
-
-  bits<5> Rc;
-  bits<5> Ra;
-  bits<8> LIT;
-  bits<7> Function = fun;
-
-//  let Constraints = "$RFALSE = $RDEST";
-  let Inst{25-21} = Ra;
-  let Inst{20-13} = LIT;
-  let Inst{12} = 1;
-  let Inst{11-5} = Function;
-  let Inst{4-0} = Rc;
-}
-
-//3.3.4
-class FPForm<bits<6> opcode, bits<11> fun, string asmstr, list<dag> pattern, InstrItinClass itin> 
-    : InstAlpha<opcode, asmstr, itin> {
-  let Pattern = pattern;
-
-  bits<5> Fc;
-  bits<5> Fa;
-  bits<5> Fb;
-  bits<11> Function = fun;
-
-  let Inst{25-21} = Fa;
-  let Inst{20-16} = Fb;
-  let Inst{15-5} = Function;
-  let Inst{4-0} = Fc;
-}
-
-//3.3.5
-class PALForm<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
-    : InstAlpha<opcode, asmstr, itin> {
-  let OutOperandList = (outs);
-  let InOperandList = OL;
-  bits<26> Function;
-
-  let Inst{25-0} = Function;
-}
-
-
-// Pseudo instructions.
-class PseudoInstAlpha<dag OOL, dag IOL, string nm, list<dag> pattern, InstrItinClass itin> 
-    : InstAlpha<0, nm, itin>  {
-  let OutOperandList = OOL;
-  let InOperandList = IOL;
-  let Pattern = pattern;
-
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
--- a/head/contrib/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,382 +0,0 @@
-//===- AlphaInstrInfo.cpp - Alpha Instruction Information -------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains the Alpha implementation of the TargetInstrInfo class.
-//
-//===----------------------------------------------------------------------===//
-
-#include "Alpha.h"
-#include "AlphaInstrInfo.h"
-#include "AlphaMachineFunctionInfo.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/ADT/STLExtras.h"
-#include "llvm/ADT/SmallVector.h"
-#include "llvm/Support/ErrorHandling.h"
-
-#define GET_INSTRINFO_CTOR
-#include "AlphaGenInstrInfo.inc"
-using namespace llvm;
-
-AlphaInstrInfo::AlphaInstrInfo()
-  : AlphaGenInstrInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
-    RI(*this) {
-}
-
-
-unsigned 
-AlphaInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
-                                    int &FrameIndex) const {
-  switch (MI->getOpcode()) {
-  case Alpha::LDL:
-  case Alpha::LDQ:
-  case Alpha::LDBU:
-  case Alpha::LDWU:
-  case Alpha::LDS:
-  case Alpha::LDT:
-    if (MI->getOperand(1).isFI()) {
-      FrameIndex = MI->getOperand(1).getIndex();
-      return MI->getOperand(0).getReg();
-    }
-    break;
-  }
-  return 0;
-}
-
-unsigned 
-AlphaInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
-                                   int &FrameIndex) const {
-  switch (MI->getOpcode()) {
-  case Alpha::STL:
-  case Alpha::STQ:
-  case Alpha::STB:
-  case Alpha::STW:
-  case Alpha::STS:
-  case Alpha::STT:
-    if (MI->getOperand(1).isFI()) {
-      FrameIndex = MI->getOperand(1).getIndex();
-      return MI->getOperand(0).getReg();
-    }
-    break;
-  }
-  return 0;
-}
-
-static bool isAlphaIntCondCode(unsigned Opcode) {
-  switch (Opcode) {
-  case Alpha::BEQ: 
-  case Alpha::BNE: 
-  case Alpha::BGE: 
-  case Alpha::BGT: 
-  case Alpha::BLE: 
-  case Alpha::BLT: 
-  case Alpha::BLBC: 
-  case Alpha::BLBS:
-    return true;
-  default:
-    return false;
-  }
-}
-
-unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,
-                                      MachineBasicBlock *TBB,
-                                      MachineBasicBlock *FBB,
-                                      const SmallVectorImpl<MachineOperand> &Cond,
-                                      DebugLoc DL) const {
-  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
-  assert((Cond.size() == 2 || Cond.size() == 0) && 
-         "Alpha branch conditions have two components!");
-
-  // One-way branch.
-  if (FBB == 0) {
-    if (Cond.empty())   // Unconditional branch
-      BuildMI(&MBB, DL, get(Alpha::BR)).addMBB(TBB);
-    else                // Conditional branch
-      if (isAlphaIntCondCode(Cond[0].getImm()))
-        BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_I))
-          .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
-      else
-        BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_F))
-          .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
-    return 1;
-  }
-  
-  // Two-way Conditional Branch.
-  if (isAlphaIntCondCode(Cond[0].getImm()))
-    BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_I))
-      .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
-  else
-    BuildMI(&MBB, DL, get(Alpha::COND_BRANCH_F))
-      .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
-  BuildMI(&MBB, DL, get(Alpha::BR)).addMBB(FBB);
-  return 2;
-}
-
-void AlphaInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
-                                 MachineBasicBlock::iterator MI, DebugLoc DL,
-                                 unsigned DestReg, unsigned SrcReg,
-                                 bool KillSrc) const {
-  if (Alpha::GPRCRegClass.contains(DestReg, SrcReg)) {
-    BuildMI(MBB, MI, DL, get(Alpha::BISr), DestReg)
-      .addReg(SrcReg)
-      .addReg(SrcReg, getKillRegState(KillSrc));
-  } else if (Alpha::F4RCRegClass.contains(DestReg, SrcReg)) {
-    BuildMI(MBB, MI, DL, get(Alpha::CPYSS), DestReg)
-      .addReg(SrcReg)
-      .addReg(SrcReg, getKillRegState(KillSrc));
-  } else if (Alpha::F8RCRegClass.contains(DestReg, SrcReg)) {
-    BuildMI(MBB, MI, DL, get(Alpha::CPYST), DestReg)
-      .addReg(SrcReg)
-      .addReg(SrcReg, getKillRegState(KillSrc));
-  } else {
-    llvm_unreachable("Attempt to copy register that is not GPR or FPR");
-  }
-}
-
-void
-AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
-                                    MachineBasicBlock::iterator MI,
-                                    unsigned SrcReg, bool isKill, int FrameIdx,
-                                    const TargetRegisterClass *RC,
-                                    const TargetRegisterInfo *TRI) const {
-  //cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
-  //     << FrameIdx << "\n";
-  //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
-
-  DebugLoc DL;
-  if (MI != MBB.end()) DL = MI->getDebugLoc();
-
-  if (RC == Alpha::F4RCRegisterClass)
-    BuildMI(MBB, MI, DL, get(Alpha::STS))
-      .addReg(SrcReg, getKillRegState(isKill))
-      .addFrameIndex(FrameIdx).addReg(Alpha::F31);
-  else if (RC == Alpha::F8RCRegisterClass)
-    BuildMI(MBB, MI, DL, get(Alpha::STT))
-      .addReg(SrcReg, getKillRegState(isKill))
-      .addFrameIndex(FrameIdx).addReg(Alpha::F31);
-  else if (RC == Alpha::GPRCRegisterClass)
-    BuildMI(MBB, MI, DL, get(Alpha::STQ))
-      .addReg(SrcReg, getKillRegState(isKill))
-      .addFrameIndex(FrameIdx).addReg(Alpha::F31);
-  else
-    llvm_unreachable("Unhandled register class");
-}
-
-void
-AlphaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
-                                        MachineBasicBlock::iterator MI,
-                                        unsigned DestReg, int FrameIdx,
-                                     const TargetRegisterClass *RC,
-                                     const TargetRegisterInfo *TRI) const {
-  //cerr << "Trying to load " << getPrettyName(DestReg) << " to "
-  //     << FrameIdx << "\n";
-  DebugLoc DL;
-  if (MI != MBB.end()) DL = MI->getDebugLoc();
-
-  if (RC == Alpha::F4RCRegisterClass)
-    BuildMI(MBB, MI, DL, get(Alpha::LDS), DestReg)
-      .addFrameIndex(FrameIdx).addReg(Alpha::F31);
-  else if (RC == Alpha::F8RCRegisterClass)
-    BuildMI(MBB, MI, DL, get(Alpha::LDT), DestReg)
-      .addFrameIndex(FrameIdx).addReg(Alpha::F31);
-  else if (RC == Alpha::GPRCRegisterClass)
-    BuildMI(MBB, MI, DL, get(Alpha::LDQ), DestReg)
-      .addFrameIndex(FrameIdx).addReg(Alpha::F31);
-  else
-    llvm_unreachable("Unhandled register class");
-}
-
-static unsigned AlphaRevCondCode(unsigned Opcode) {
-  switch (Opcode) {
-  case Alpha::BEQ: return Alpha::BNE;
-  case Alpha::BNE: return Alpha::BEQ;
-  case Alpha::BGE: return Alpha::BLT;
-  case Alpha::BGT: return Alpha::BLE;
-  case Alpha::BLE: return Alpha::BGT;
-  case Alpha::BLT: return Alpha::BGE;
-  case Alpha::BLBC: return Alpha::BLBS;
-  case Alpha::BLBS: return Alpha::BLBC;
-  case Alpha::FBEQ: return Alpha::FBNE;
-  case Alpha::FBNE: return Alpha::FBEQ;
-  case Alpha::FBGE: return Alpha::FBLT;
-  case Alpha::FBGT: return Alpha::FBLE;
-  case Alpha::FBLE: return Alpha::FBGT;
-  case Alpha::FBLT: return Alpha::FBGE;
-  default:
-    llvm_unreachable("Unknown opcode");
-  }
-  return 0; // Not reached
-}
-
-// Branch analysis.
-bool AlphaInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
-                                   MachineBasicBlock *&FBB,
-                                   SmallVectorImpl<MachineOperand> &Cond,
-                                   bool AllowModify) const {
-  // If the block has no terminators, it just falls into the block after it.
-  MachineBasicBlock::iterator I = MBB.end();
-  if (I == MBB.begin())
-    return false;
-  --I;
-  while (I->isDebugValue()) {
-    if (I == MBB.begin())
-      return false;
-    --I;
-  }
-  if (!isUnpredicatedTerminator(I))
-    return false;
-
-  // Get the last instruction in the block.
-  MachineInstr *LastInst = I;
-  
-  // If there is only one terminator instruction, process it.
-  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
-    if (LastInst->getOpcode() == Alpha::BR) {
-      TBB = LastInst->getOperand(0).getMBB();
-      return false;
-    } else if (LastInst->getOpcode() == Alpha::COND_BRANCH_I ||
-               LastInst->getOpcode() == Alpha::COND_BRANCH_F) {
-      // Block ends with fall-through condbranch.
-      TBB = LastInst->getOperand(2).getMBB();
-      Cond.push_back(LastInst->getOperand(0));
-      Cond.push_back(LastInst->getOperand(1));
-      return false;
-    }
-    // Otherwise, don't know what this is.
-    return true;
-  }
-  
-  // Get the instruction before it if it's a terminator.
-  MachineInstr *SecondLastInst = I;
-
-  // If there are three terminators, we don't know what sort of block this is.
-  if (SecondLastInst && I != MBB.begin() &&
-      isUnpredicatedTerminator(--I))
-    return true;
-  
-  // If the block ends with Alpha::BR and Alpha::COND_BRANCH_*, handle it.
-  if ((SecondLastInst->getOpcode() == Alpha::COND_BRANCH_I ||
-      SecondLastInst->getOpcode() == Alpha::COND_BRANCH_F) && 
-      LastInst->getOpcode() == Alpha::BR) {
-    TBB =  SecondLastInst->getOperand(2).getMBB();
-    Cond.push_back(SecondLastInst->getOperand(0));
-    Cond.push_back(SecondLastInst->getOperand(1));
-    FBB = LastInst->getOperand(0).getMBB();
-    return false;
-  }
-  
-  // If the block ends with two Alpha::BRs, handle it.  The second one is not
-  // executed, so remove it.
-  if (SecondLastInst->getOpcode() == Alpha::BR && 
-      LastInst->getOpcode() == Alpha::BR) {
-    TBB = SecondLastInst->getOperand(0).getMBB();
-    I = LastInst;
-    if (AllowModify)
-      I->eraseFromParent();
-    return false;
-  }
-
-  // Otherwise, can't handle this.
-  return true;
-}
-
-unsigned AlphaInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
-  MachineBasicBlock::iterator I = MBB.end();
-  if (I == MBB.begin()) return 0;
-  --I;
-  while (I->isDebugValue()) {
-    if (I == MBB.begin())
-      return 0;
-    --I;
-  }
-  if (I->getOpcode() != Alpha::BR && 
-      I->getOpcode() != Alpha::COND_BRANCH_I &&
-      I->getOpcode() != Alpha::COND_BRANCH_F)
-    return 0;
-  
-  // Remove the branch.
-  I->eraseFromParent();
-  
-  I = MBB.end();
-
-  if (I == MBB.begin()) return 1;
-  --I;
-  if (I->getOpcode() != Alpha::COND_BRANCH_I && 
-      I->getOpcode() != Alpha::COND_BRANCH_F)
-    return 1;
-  
-  // Remove the branch.
-  I->eraseFromParent();
-  return 2;
-}
-
-void AlphaInstrInfo::insertNoop(MachineBasicBlock &MBB, 
-                                MachineBasicBlock::iterator MI) const {
-  DebugLoc DL;
-  BuildMI(MBB, MI, DL, get(Alpha::BISr), Alpha::R31)
-    .addReg(Alpha::R31)
-    .addReg(Alpha::R31);
-}
-
-bool AlphaInstrInfo::
-ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
-  assert(Cond.size() == 2 && "Invalid Alpha branch opcode!");
-  Cond[0].setImm(AlphaRevCondCode(Cond[0].getImm()));
-  return false;
-}
-
-/// getGlobalBaseReg - Return a virtual register initialized with the
-/// the global base register value. Output instructions required to
-/// initialize the register in the function entry block, if necessary.
-///
-unsigned AlphaInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
-  AlphaMachineFunctionInfo *AlphaFI = MF->getInfo<AlphaMachineFunctionInfo>();
-  unsigned GlobalBaseReg = AlphaFI->getGlobalBaseReg();
-  if (GlobalBaseReg != 0)
-    return GlobalBaseReg;
-
-  // Insert the set of GlobalBaseReg into the first MBB of the function
-  MachineBasicBlock &FirstMBB = MF->front();
-  MachineBasicBlock::iterator MBBI = FirstMBB.begin();
-  MachineRegisterInfo &RegInfo = MF->getRegInfo();
-  const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
-
-  GlobalBaseReg = RegInfo.createVirtualRegister(&Alpha::GPRCRegClass);
-  BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),
-          GlobalBaseReg).addReg(Alpha::R29);
-  RegInfo.addLiveIn(Alpha::R29);
-
-  AlphaFI->setGlobalBaseReg(GlobalBaseReg);
-  return GlobalBaseReg;
-}
-
-/// getGlobalRetAddr - Return a virtual register initialized with the
-/// the global base register value. Output instructions required to
-/// initialize the register in the function entry block, if necessary.
-///
-unsigned AlphaInstrInfo::getGlobalRetAddr(MachineFunction *MF) const {
-  AlphaMachineFunctionInfo *AlphaFI = MF->getInfo<AlphaMachineFunctionInfo>();
-  unsigned GlobalRetAddr = AlphaFI->getGlobalRetAddr();
-  if (GlobalRetAddr != 0)
-    return GlobalRetAddr;
-
-  // Insert the set of GlobalRetAddr into the first MBB of the function
-  MachineBasicBlock &FirstMBB = MF->front();
-  MachineBasicBlock::iterator MBBI = FirstMBB.begin();
-  MachineRegisterInfo &RegInfo = MF->getRegInfo();
-  const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
-
-  GlobalRetAddr = RegInfo.createVirtualRegister(&Alpha::GPRCRegClass);
-  BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),
-          GlobalRetAddr).addReg(Alpha::R26);
-  RegInfo.addLiveIn(Alpha::R26);
-
-  AlphaFI->setGlobalRetAddr(GlobalRetAddr);
-  return GlobalRetAddr;
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/AlphaInstrInfo.h
--- a/head/contrib/llvm/lib/Target/Alpha/AlphaInstrInfo.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,85 +0,0 @@
-//===- AlphaInstrInfo.h - Alpha Instruction Information ---------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains the Alpha implementation of the TargetInstrInfo class.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef ALPHAINSTRUCTIONINFO_H
-#define ALPHAINSTRUCTIONINFO_H
-
-#include "llvm/Target/TargetInstrInfo.h"
-#include "AlphaRegisterInfo.h"
-
-#define GET_INSTRINFO_HEADER
-#include "AlphaGenInstrInfo.inc"
-
-namespace llvm {
-
-class AlphaInstrInfo : public AlphaGenInstrInfo {
-  const AlphaRegisterInfo RI;
-public:
-  AlphaInstrInfo();
-
-  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
-  /// such, whenever a client has an instance of instruction info, it should
-  /// always be able to get register info as well (through this method).
-  ///
-  virtual const AlphaRegisterInfo &getRegisterInfo() const { return RI; }
-
-  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
-                                       int &FrameIndex) const;
-  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
-                                      int &FrameIndex) const;
-  
-  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
-                                MachineBasicBlock *FBB,
-                                const SmallVectorImpl<MachineOperand> &Cond,
-                                DebugLoc DL) const;
-  virtual void copyPhysReg(MachineBasicBlock &MBB,
-                           MachineBasicBlock::iterator MI, DebugLoc DL,
-                           unsigned DestReg, unsigned SrcReg,
-                           bool KillSrc) const;
-  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
-                                   MachineBasicBlock::iterator MBBI,
-                                   unsigned SrcReg, bool isKill, int FrameIndex,
-                                   const TargetRegisterClass *RC,
-                                   const TargetRegisterInfo *TRI) const;
-
-  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
-                                    MachineBasicBlock::iterator MBBI,
-                                    unsigned DestReg, int FrameIndex,
-                                    const TargetRegisterClass *RC,
-                                    const TargetRegisterInfo *TRI) const;
-  
-  bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
-                     MachineBasicBlock *&FBB,
-                     SmallVectorImpl<MachineOperand> &Cond,
-                     bool AllowModify) const;
-  unsigned RemoveBranch(MachineBasicBlock &MBB) const;
-  void insertNoop(MachineBasicBlock &MBB, 
-                  MachineBasicBlock::iterator MI) const;
-  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
-
-  /// getGlobalBaseReg - Return a virtual register initialized with the
-  /// the global base register value. Output instructions required to
-  /// initialize the register in the function entry block, if necessary.
-  ///
-  unsigned getGlobalBaseReg(MachineFunction *MF) const;
-
-  /// getGlobalRetAddr - Return a virtual register initialized with the
-  /// the global return address register value. Output instructions required to
-  /// initialize the register in the function entry block, if necessary.
-  ///
-  unsigned getGlobalRetAddr(MachineFunction *MF) const;
-};
-
-}
-
-#endif
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/AlphaInstrInfo.td
--- a/head/contrib/llvm/lib/Target/Alpha/AlphaInstrInfo.td	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1159 +0,0 @@
-//===- AlphaInstrInfo.td - The Alpha Instruction Set -------*- tablegen -*-===//
-// 
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-// 
-//===----------------------------------------------------------------------===//
-//
-//
-//===----------------------------------------------------------------------===//
-
-include "AlphaInstrFormats.td"
-
-//********************
-//Custom DAG Nodes
-//********************
-
-def SDTFPUnaryOpUnC  : SDTypeProfile<1, 1, [
-  SDTCisFP<1>, SDTCisFP<0>
-]>;
-def Alpha_cvtqt   : SDNode<"AlphaISD::CVTQT_",    SDTFPUnaryOpUnC, []>;
-def Alpha_cvtqs   : SDNode<"AlphaISD::CVTQS_",    SDTFPUnaryOpUnC, []>;
-def Alpha_cvttq   : SDNode<"AlphaISD::CVTTQ_"  ,  SDTFPUnaryOp, []>;
-def Alpha_gprello : SDNode<"AlphaISD::GPRelLo",   SDTIntBinOp, []>;
-def Alpha_gprelhi : SDNode<"AlphaISD::GPRelHi",   SDTIntBinOp, []>;
-def Alpha_rellit  : SDNode<"AlphaISD::RelLit",    SDTIntBinOp, [SDNPMayLoad]>;
-
-def retflag       : SDNode<"AlphaISD::RET_FLAG", SDTNone,
-                           [SDNPHasChain, SDNPOptInGlue]>;
-
-// These are target-independent nodes, but have target-specific formats.
-def SDT_AlphaCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i64> ]>;
-def SDT_AlphaCallSeqEnd   : SDCallSeqEnd<[ SDTCisVT<0, i64>,
-                                           SDTCisVT<1, i64> ]>;
-
-def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AlphaCallSeqStart,
-                           [SDNPHasChain, SDNPOutGlue]>;
-def callseq_end   : SDNode<"ISD::CALLSEQ_END",   SDT_AlphaCallSeqEnd,
-                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
-
-//********************
-//Paterns for matching
-//********************
-def invX : SDNodeXForm<imm, [{ //invert
-  return getI64Imm(~N->getZExtValue());
-}]>;
-def negX : SDNodeXForm<imm, [{ //negate
-  return getI64Imm(~N->getZExtValue() + 1);
-}]>;
-def SExt32 : SDNodeXForm<imm, [{ //signed extend int to long
-  return getI64Imm(((int64_t)N->getZExtValue() << 32) >> 32);
-}]>;
-def SExt16 : SDNodeXForm<imm, [{ //signed extend int to long
-  return getI64Imm(((int64_t)N->getZExtValue() << 48) >> 48);
-}]>;
-def LL16 : SDNodeXForm<imm, [{ //lda part of constant
-  return getI64Imm(get_lda16(N->getZExtValue()));
-}]>;
-def LH16 : SDNodeXForm<imm, [{ //ldah part of constant (or more if too big)
-  return getI64Imm(get_ldah16(N->getZExtValue()));
-}]>;
-def iZAPX : SDNodeXForm<and, [{ // get imm to ZAPi
-  ConstantSDNode *RHS = cast<ConstantSDNode>(N->getOperand(1));
-  return getI64Imm(get_zapImm(SDValue(), RHS->getZExtValue()));
-}]>;
-def nearP2X : SDNodeXForm<imm, [{
-  return getI64Imm(Log2_64(getNearPower2((uint64_t)N->getZExtValue())));
-}]>;
-def nearP2RemX : SDNodeXForm<imm, [{
-  uint64_t x =
-    abs64(N->getZExtValue() - getNearPower2((uint64_t)N->getZExtValue()));
-  return getI64Imm(Log2_64(x));
-}]>;
-
-def immUExt8  : PatLeaf<(imm), [{ //imm fits in 8 bit zero extended field
-  return (uint64_t)N->getZExtValue() == (uint8_t)N->getZExtValue();
-}]>;
-def immUExt8inv  : PatLeaf<(imm), [{ //inverted imm fits in 8 bit zero extended field
-  return (uint64_t)~N->getZExtValue() == (uint8_t)~N->getZExtValue();
-}], invX>;
-def immUExt8neg  : PatLeaf<(imm), [{ //negated imm fits in 8 bit zero extended field
-  return ((uint64_t)~N->getZExtValue() + 1) ==
-         (uint8_t)((uint64_t)~N->getZExtValue() + 1);
-}], negX>;
-def immSExt16  : PatLeaf<(imm), [{ //imm fits in 16 bit sign extended field
-  return ((int64_t)N->getZExtValue() << 48) >> 48 ==
-         (int64_t)N->getZExtValue();
-}]>;
-def immSExt16int  : PatLeaf<(imm), [{ //(int)imm fits in a 16 bit sign extended field
-  return ((int64_t)N->getZExtValue() << 48) >> 48 ==
-         ((int64_t)N->getZExtValue() << 32) >> 32;
-}], SExt16>;
-
-def zappat : PatFrag<(ops node:$LHS), (and node:$LHS, imm), [{
-  ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
-  if (!RHS) return 0;
-  uint64_t build = get_zapImm(N->getOperand(0), (uint64_t)RHS->getZExtValue());
-  return build != 0;
-}]>;
-
-def immFPZ  : PatLeaf<(fpimm), [{ //the only fpconstant nodes are +/- 0.0
-  (void)N; // silence warning.
-  return true;
-}]>;
-
-def immRem1 :PatLeaf<(imm),[{return chkRemNearPower2(N->getZExtValue(),1,0);}]>;
-def immRem2 :PatLeaf<(imm),[{return chkRemNearPower2(N->getZExtValue(),2,0);}]>;
-def immRem3 :PatLeaf<(imm),[{return chkRemNearPower2(N->getZExtValue(),3,0);}]>;
-def immRem4 :PatLeaf<(imm),[{return chkRemNearPower2(N->getZExtValue(),4,0);}]>;
-def immRem5 :PatLeaf<(imm),[{return chkRemNearPower2(N->getZExtValue(),5,0);}]>;
-def immRem1n:PatLeaf<(imm),[{return chkRemNearPower2(N->getZExtValue(),1,1);}]>;
-def immRem2n:PatLeaf<(imm),[{return chkRemNearPower2(N->getZExtValue(),2,1);}]>;
-def immRem3n:PatLeaf<(imm),[{return chkRemNearPower2(N->getZExtValue(),3,1);}]>;
-def immRem4n:PatLeaf<(imm),[{return chkRemNearPower2(N->getZExtValue(),4,1);}]>;
-def immRem5n:PatLeaf<(imm),[{return chkRemNearPower2(N->getZExtValue(),5,1);}]>;
-
-def immRemP2n : PatLeaf<(imm), [{
-  return isPowerOf2_64(getNearPower2((uint64_t)N->getZExtValue()) -
-                         N->getZExtValue());
-}]>;
-def immRemP2 : PatLeaf<(imm), [{
-  return isPowerOf2_64(N->getZExtValue() -
-                         getNearPower2((uint64_t)N->getZExtValue()));
-}]>;
-def immUExt8ME : PatLeaf<(imm), [{ //use this imm for mulqi
-  int64_t d =  abs64((int64_t)N->getZExtValue() -
-               (int64_t)getNearPower2((uint64_t)N->getZExtValue()));
-  if (isPowerOf2_64(d)) return false;
-  switch (d) {
-    case 1: case 3: case 5: return false; 
-    default: return (uint64_t)N->getZExtValue() == (uint8_t)N->getZExtValue();
-  };
-}]>;
-
-def intop : PatFrag<(ops node:$op), (sext_inreg node:$op, i32)>;
-def add4  : PatFrag<(ops node:$op1, node:$op2),
-                    (add (shl node:$op1, 2), node:$op2)>;
-def sub4  : PatFrag<(ops node:$op1, node:$op2),
-                    (sub (shl node:$op1, 2), node:$op2)>;
-def add8  : PatFrag<(ops node:$op1, node:$op2),
-                    (add (shl node:$op1, 3), node:$op2)>;
-def sub8  : PatFrag<(ops node:$op1, node:$op2),
-                    (sub (shl node:$op1, 3), node:$op2)>;
-class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
-class CmpOpFrag<dag res> : PatFrag<(ops node:$R), res>;
-
-//Pseudo ops for selection
-
-def WTF : PseudoInstAlpha<(outs), (ins variable_ops), "#wtf", [], s_pseudo>;
-
-let hasCtrlDep = 1, Defs = [R30], Uses = [R30] in {
-def ADJUSTSTACKUP : PseudoInstAlpha<(outs), (ins s64imm:$amt),
-                "; ADJUP $amt", 
-                [(callseq_start timm:$amt)], s_pseudo>;
-def ADJUSTSTACKDOWN : PseudoInstAlpha<(outs), (ins s64imm:$amt1, s64imm:$amt2),
-                "; ADJDOWN $amt1",
-                [(callseq_end timm:$amt1, timm:$amt2)], s_pseudo>;
-}
-
-def ALTENT : PseudoInstAlpha<(outs), (ins s64imm:$TARGET), "$$$TARGET..ng:\n", [], s_pseudo>;
-def PCLABEL : PseudoInstAlpha<(outs), (ins s64imm:$num), "PCMARKER_$num:\n",[], s_pseudo>;
-def MEMLABEL : PseudoInstAlpha<(outs), (ins s64imm:$i, s64imm:$j, s64imm:$k, s64imm:$m),
-         "LSMARKER$$$i$$$j$$$k$$$m:", [], s_pseudo>;
-
-
-let usesCustomInserter = 1 in {   // Expanded after instruction selection.
-def CAS32 : PseudoInstAlpha<(outs GPRC:$dst), (ins GPRC:$ptr, GPRC:$cmp, GPRC:$swp), "",
-      [(set GPRC:$dst, (atomic_cmp_swap_32 GPRC:$ptr, GPRC:$cmp, GPRC:$swp))], s_pseudo>;
-def CAS64 : PseudoInstAlpha<(outs GPRC:$dst), (ins GPRC:$ptr, GPRC:$cmp, GPRC:$swp), "",
-      [(set GPRC:$dst, (atomic_cmp_swap_64 GPRC:$ptr, GPRC:$cmp, GPRC:$swp))], s_pseudo>;
-
-def LAS32 : PseudoInstAlpha<(outs GPRC:$dst), (ins GPRC:$ptr, GPRC:$swp), "",
-      [(set GPRC:$dst, (atomic_load_add_32 GPRC:$ptr, GPRC:$swp))], s_pseudo>;
-def LAS64 :PseudoInstAlpha<(outs GPRC:$dst), (ins GPRC:$ptr, GPRC:$swp), "",
-      [(set GPRC:$dst, (atomic_load_add_64 GPRC:$ptr, GPRC:$swp))], s_pseudo>;
-
-def SWAP32 : PseudoInstAlpha<(outs GPRC:$dst), (ins GPRC:$ptr, GPRC:$swp), "",
-        [(set GPRC:$dst, (atomic_swap_32 GPRC:$ptr, GPRC:$swp))], s_pseudo>;
-def SWAP64 :PseudoInstAlpha<(outs GPRC:$dst), (ins GPRC:$ptr, GPRC:$swp), "",
-        [(set GPRC:$dst, (atomic_swap_64 GPRC:$ptr, GPRC:$swp))], s_pseudo>;
-}
-
-//***********************
-//Real instructions
-//***********************
-
-//Operation Form:
-
-//conditional moves, int
-
-multiclass cmov_inst<bits<7> fun, string asmstr, PatFrag OpNode> {
-def r : OForm4<0x11, fun, !strconcat(asmstr, " $RCOND,$RTRUE,$RDEST"),
-             [(set GPRC:$RDEST, (select (OpNode GPRC:$RCOND), GPRC:$RTRUE, GPRC:$RFALSE))], s_cmov>;
-def i : OForm4L<0x11, fun, !strconcat(asmstr, " $RCOND,$RTRUE,$RDEST"),
-             [(set GPRC:$RDEST, (select (OpNode GPRC:$RCOND), immUExt8:$RTRUE, GPRC:$RFALSE))], s_cmov>;
-}
-
-defm CMOVEQ  : cmov_inst<0x24, "cmoveq",  CmpOpFrag<(seteq node:$R, 0)>>;
-defm CMOVNE  : cmov_inst<0x26, "cmovne",  CmpOpFrag<(setne node:$R, 0)>>;
-defm CMOVLT  : cmov_inst<0x44, "cmovlt",  CmpOpFrag<(setlt node:$R, 0)>>;
-defm CMOVLE  : cmov_inst<0x64, "cmovle",  CmpOpFrag<(setle node:$R, 0)>>;
-defm CMOVGT  : cmov_inst<0x66, "cmovgt",  CmpOpFrag<(setgt node:$R, 0)>>;
-defm CMOVGE  : cmov_inst<0x46, "cmovge",  CmpOpFrag<(setge node:$R, 0)>>;
-defm CMOVLBC : cmov_inst<0x16, "cmovlbc", CmpOpFrag<(xor   node:$R, 1)>>;
-defm CMOVLBS : cmov_inst<0x14, "cmovlbs", CmpOpFrag<(and   node:$R, 1)>>;
-
-//General pattern for cmov
-def : Pat<(select GPRC:$which, GPRC:$src1, GPRC:$src2),
-      (CMOVNEr GPRC:$src2, GPRC:$src1, GPRC:$which)>;
-def : Pat<(select GPRC:$which, GPRC:$src1, immUExt8:$src2),
-      (CMOVEQi GPRC:$src1, immUExt8:$src2, GPRC:$which)>;
-
-//Invert sense when we can for constants:
-def : Pat<(select (setne GPRC:$RCOND, 0), GPRC:$RTRUE, immUExt8:$RFALSE),
-          (CMOVEQi GPRC:$RCOND, immUExt8:$RFALSE, GPRC:$RTRUE)>;
-def : Pat<(select (setgt GPRC:$RCOND, 0), GPRC:$RTRUE, immUExt8:$RFALSE),
-          (CMOVLEi GPRC:$RCOND, immUExt8:$RFALSE, GPRC:$RTRUE)>;
-def : Pat<(select (setge GPRC:$RCOND, 0), GPRC:$RTRUE, immUExt8:$RFALSE),
-          (CMOVLTi GPRC:$RCOND, immUExt8:$RFALSE, GPRC:$RTRUE)>;
-def : Pat<(select (setlt GPRC:$RCOND, 0), GPRC:$RTRUE, immUExt8:$RFALSE),
-          (CMOVGEi GPRC:$RCOND, immUExt8:$RFALSE, GPRC:$RTRUE)>;
-def : Pat<(select (setle GPRC:$RCOND, 0), GPRC:$RTRUE, immUExt8:$RFALSE),
-          (CMOVGTi GPRC:$RCOND, immUExt8:$RFALSE, GPRC:$RTRUE)>;
-
-multiclass all_inst<bits<6> opc, bits<7> funl, bits<7> funq, 
-                    string asmstr, PatFrag OpNode, InstrItinClass itin> {
-  def Lr : OForm< opc, funl, !strconcat(asmstr, "l $RA,$RB,$RC"),
-               [(set GPRC:$RC, (intop (OpNode GPRC:$RA, GPRC:$RB)))], itin>;
-  def Li : OFormL<opc, funl, !strconcat(asmstr, "l $RA,$L,$RC"),
-               [(set GPRC:$RC, (intop (OpNode GPRC:$RA, immUExt8:$L)))], itin>;
-  def Qr : OForm< opc, funq, !strconcat(asmstr, "q $RA,$RB,$RC"),
-               [(set GPRC:$RC, (OpNode GPRC:$RA, GPRC:$RB))], itin>;
-  def Qi : OFormL<opc, funq, !strconcat(asmstr, "q $RA,$L,$RC"),
-               [(set GPRC:$RC, (OpNode GPRC:$RA, immUExt8:$L))], itin>;
-}
-
-defm MUL   : all_inst<0x13, 0x00, 0x20, "mul",   BinOpFrag<(mul node:$LHS, node:$RHS)>, s_imul>;
-defm ADD   : all_inst<0x10, 0x00, 0x20, "add",   BinOpFrag<(add node:$LHS, node:$RHS)>, s_iadd>;
-defm S4ADD : all_inst<0x10, 0x02, 0x22, "s4add", add4, s_iadd>;
-defm S8ADD : all_inst<0x10, 0x12, 0x32, "s8add", add8, s_iadd>;
-defm S4SUB : all_inst<0x10, 0x0B, 0x2B, "s4sub", sub4, s_iadd>;
-defm S8SUB : all_inst<0x10, 0x1B, 0x3B, "s8sub", sub8, s_iadd>;
-defm SUB   : all_inst<0x10, 0x09, 0x29, "sub",   BinOpFrag<(sub node:$LHS, node:$RHS)>, s_iadd>;
-//Const cases since legalize does sub x, int -> add x, inv(int) + 1
-def : Pat<(intop (add GPRC:$RA, immUExt8neg:$L)), (SUBLi GPRC:$RA, immUExt8neg:$L)>;
-def : Pat<(add GPRC:$RA, immUExt8neg:$L), (SUBQi GPRC:$RA, immUExt8neg:$L)>;
-def : Pat<(intop (add4 GPRC:$RA, immUExt8neg:$L)), (S4SUBLi GPRC:$RA, immUExt8neg:$L)>;
-def : Pat<(add4 GPRC:$RA, immUExt8neg:$L), (S4SUBQi GPRC:$RA, immUExt8neg:$L)>;
-def : Pat<(intop (add8 GPRC:$RA, immUExt8neg:$L)), (S8SUBLi GPRC:$RA, immUExt8neg:$L)>;
-def : Pat<(add8 GPRC:$RA, immUExt8neg:$L), (S8SUBQi GPRC:$RA, immUExt8neg:$L)>;
-
-multiclass log_inst<bits<6> opc, bits<7> fun, string asmstr, SDNode OpNode, InstrItinClass itin> {
-def r : OForm<opc, fun, !strconcat(asmstr, " $RA,$RB,$RC"),
-              [(set GPRC:$RC, (OpNode GPRC:$RA, GPRC:$RB))], itin>;
-def i : OFormL<opc, fun, !strconcat(asmstr, " $RA,$L,$RC"),
-              [(set GPRC:$RC, (OpNode GPRC:$RA, immUExt8:$L))], itin>;
-}
-multiclass inv_inst<bits<6> opc, bits<7> fun, string asmstr, SDNode OpNode, InstrItinClass itin> {
-def r : OForm<opc, fun, !strconcat(asmstr, " $RA,$RB,$RC"),
-              [(set GPRC:$RC, (OpNode GPRC:$RA, (not GPRC:$RB)))], itin>;
-def i : OFormL<opc, fun, !strconcat(asmstr, " $RA,$L,$RC"),
-              [(set GPRC:$RC, (OpNode GPRC:$RA, immUExt8inv:$L))], itin>;
-}
-
-defm AND   : log_inst<0x11, 0x00, "and",   and,   s_ilog>;
-defm BIC   : inv_inst<0x11, 0x08, "bic",   and,   s_ilog>;
-defm BIS   : log_inst<0x11, 0x20, "bis",   or,    s_ilog>;
-defm ORNOT : inv_inst<0x11, 0x28, "ornot", or,    s_ilog>;
-defm XOR   : log_inst<0x11, 0x40, "xor",   xor,   s_ilog>;
-defm EQV   : inv_inst<0x11, 0x48, "eqv",   xor,   s_ilog>;
-
-defm SL    : log_inst<0x12, 0x39, "sll",   shl,   s_ishf>;
-defm SRA   : log_inst<0x12, 0x3c, "sra",   sra,   s_ishf>;
-defm SRL   : log_inst<0x12, 0x34, "srl",   srl,   s_ishf>;
-defm UMULH : log_inst<0x13, 0x30, "umulh", mulhu, s_imul>;
-
-def CTLZ     : OForm2<0x1C, 0x32, "CTLZ $RB,$RC", 
-                      [(set GPRC:$RC, (ctlz GPRC:$RB))], s_imisc>;
-def CTPOP    : OForm2<0x1C, 0x30, "CTPOP $RB,$RC", 
-                      [(set GPRC:$RC, (ctpop GPRC:$RB))], s_imisc>;
-def CTTZ     : OForm2<0x1C, 0x33, "CTTZ $RB,$RC", 
-                      [(set GPRC:$RC, (cttz GPRC:$RB))], s_imisc>;
-def EXTBL    : OForm< 0x12, 0x06, "EXTBL $RA,$RB,$RC", 
-                      [(set GPRC:$RC, (and (srl GPRC:$RA, (shl GPRC:$RB, 3)), 255))], s_ishf>;
-def EXTWL    : OForm< 0x12, 0x16, "EXTWL $RA,$RB,$RC", 
-                      [(set GPRC:$RC, (and (srl GPRC:$RA, (shl GPRC:$RB, 3)), 65535))], s_ishf>;
-def EXTLL    : OForm< 0x12, 0x26, "EXTLL $RA,$RB,$RC", 
-                      [(set GPRC:$RC, (and (srl GPRC:$RA, (shl GPRC:$RB, 3)), 4294967295))], s_ishf>;
-def SEXTB    : OForm2<0x1C, 0x00, "sextb $RB,$RC", 
-                      [(set GPRC:$RC, (sext_inreg GPRC:$RB, i8))], s_ishf>;
-def SEXTW    : OForm2<0x1C, 0x01, "sextw $RB,$RC", 
-                      [(set GPRC:$RC, (sext_inreg GPRC:$RB, i16))], s_ishf>;
-
-//def EXTBLi   : OFormL<0x12, 0x06, "EXTBL $RA,$L,$RC", []>; //Extract byte low
-//def EXTLH    : OForm< 0x12, 0x6A, "EXTLH $RA,$RB,$RC", []>; //Extract longword high
-//def EXTLHi   : OFormL<0x12, 0x6A, "EXTLH $RA,$L,$RC", []>; //Extract longword high
-//def EXTLLi   : OFormL<0x12, 0x26, "EXTLL $RA,$L,$RC", []>; //Extract longword low
-//def EXTQH    : OForm< 0x12, 0x7A, "EXTQH $RA,$RB,$RC", []>; //Extract quadword high
-//def EXTQHi   : OFormL<0x12, 0x7A, "EXTQH $RA,$L,$RC", []>; //Extract quadword high
-//def EXTQ     : OForm< 0x12, 0x36, "EXTQ $RA,$RB,$RC", []>; //Extract quadword low
-//def EXTQi    : OFormL<0x12, 0x36, "EXTQ $RA,$L,$RC", []>; //Extract quadword low
-//def EXTWH    : OForm< 0x12, 0x5A, "EXTWH $RA,$RB,$RC", []>; //Extract word high
-//def EXTWHi   : OFormL<0x12, 0x5A, "EXTWH $RA,$L,$RC", []>; //Extract word high
-//def EXTWLi   : OFormL<0x12, 0x16, "EXTWL $RA,$L,$RC", []>; //Extract word low
-
-//def INSBL    : OForm< 0x12, 0x0B, "INSBL $RA,$RB,$RC", []>; //Insert byte low
-//def INSBLi   : OFormL<0x12, 0x0B, "INSBL $RA,$L,$RC", []>; //Insert byte low
-//def INSLH    : OForm< 0x12, 0x67, "INSLH $RA,$RB,$RC", []>; //Insert longword high
-//def INSLHi   : OFormL<0x12, 0x67, "INSLH $RA,$L,$RC", []>; //Insert longword high
-//def INSLL    : OForm< 0x12, 0x2B, "INSLL $RA,$RB,$RC", []>; //Insert longword low
-//def INSLLi   : OFormL<0x12, 0x2B, "INSLL $RA,$L,$RC", []>; //Insert longword low
-//def INSQH    : OForm< 0x12, 0x77, "INSQH $RA,$RB,$RC", []>; //Insert quadword high
-//def INSQHi   : OFormL<0x12, 0x77, "INSQH $RA,$L,$RC", []>; //Insert quadword high
-//def INSQL    : OForm< 0x12, 0x3B, "INSQL $RA,$RB,$RC", []>; //Insert quadword low
-//def INSQLi   : OFormL<0x12, 0x3B, "INSQL $RA,$L,$RC", []>; //Insert quadword low
-//def INSWH    : OForm< 0x12, 0x57, "INSWH $RA,$RB,$RC", []>; //Insert word high
-//def INSWHi   : OFormL<0x12, 0x57, "INSWH $RA,$L,$RC", []>; //Insert word high
-//def INSWL    : OForm< 0x12, 0x1B, "INSWL $RA,$RB,$RC", []>; //Insert word low
-//def INSWLi   : OFormL<0x12, 0x1B, "INSWL $RA,$L,$RC", []>; //Insert word low
-
-//def MSKBL    : OForm< 0x12, 0x02, "MSKBL $RA,$RB,$RC", []>; //Mask byte low
-//def MSKBLi   : OFormL<0x12, 0x02, "MSKBL $RA,$L,$RC", []>; //Mask byte low
-//def MSKLH    : OForm< 0x12, 0x62, "MSKLH $RA,$RB,$RC", []>; //Mask longword high
-//def MSKLHi   : OFormL<0x12, 0x62, "MSKLH $RA,$L,$RC", []>; //Mask longword high
-//def MSKLL    : OForm< 0x12, 0x22, "MSKLL $RA,$RB,$RC", []>; //Mask longword low
-//def MSKLLi   : OFormL<0x12, 0x22, "MSKLL $RA,$L,$RC", []>; //Mask longword low
-//def MSKQH    : OForm< 0x12, 0x72, "MSKQH $RA,$RB,$RC", []>; //Mask quadword high
-//def MSKQHi   : OFormL<0x12, 0x72, "MSKQH $RA,$L,$RC", []>; //Mask quadword high
-//def MSKQL    : OForm< 0x12, 0x32, "MSKQL $RA,$RB,$RC", []>; //Mask quadword low
-//def MSKQLi   : OFormL<0x12, 0x32, "MSKQL $RA,$L,$RC", []>; //Mask quadword low
-//def MSKWH    : OForm< 0x12, 0x52, "MSKWH $RA,$RB,$RC", []>; //Mask word high
-//def MSKWHi   : OFormL<0x12, 0x52, "MSKWH $RA,$L,$RC", []>; //Mask word high
-//def MSKWL    : OForm< 0x12, 0x12, "MSKWL $RA,$RB,$RC", []>; //Mask word low
-//def MSKWLi   : OFormL<0x12, 0x12, "MSKWL $RA,$L,$RC", []>; //Mask word low
-                      
-def ZAPNOTi  : OFormL<0x12, 0x31, "zapnot $RA,$L,$RC", [], s_ishf>;
-
-// Define the pattern that produces ZAPNOTi.
-def : Pat<(zappat:$imm GPRC:$RA),
-          (ZAPNOTi GPRC:$RA, (iZAPX GPRC:$imm))>;
-
-
-//Comparison, int
-//So this is a waste of what this instruction can do, but it still saves something
-def CMPBGE  : OForm< 0x10, 0x0F, "cmpbge $RA,$RB,$RC", 
-                     [(set GPRC:$RC, (setuge (and GPRC:$RA, 255), (and GPRC:$RB, 255)))], s_ilog>;
-def CMPBGEi : OFormL<0x10, 0x0F, "cmpbge $RA,$L,$RC",
-                     [(set GPRC:$RC, (setuge (and GPRC:$RA, 255), immUExt8:$L))], s_ilog>;
-def CMPEQ   : OForm< 0x10, 0x2D, "cmpeq $RA,$RB,$RC", 
-                     [(set GPRC:$RC, (seteq GPRC:$RA, GPRC:$RB))], s_iadd>;
-def CMPEQi  : OFormL<0x10, 0x2D, "cmpeq $RA,$L,$RC", 
-                     [(set GPRC:$RC, (seteq GPRC:$RA, immUExt8:$L))], s_iadd>;
-def CMPLE   : OForm< 0x10, 0x6D, "cmple $RA,$RB,$RC", 
-                     [(set GPRC:$RC, (setle GPRC:$RA, GPRC:$RB))], s_iadd>;
-def CMPLEi  : OFormL<0x10, 0x6D, "cmple $RA,$L,$RC",
-                     [(set GPRC:$RC, (setle GPRC:$RA, immUExt8:$L))], s_iadd>;
-def CMPLT   : OForm< 0x10, 0x4D, "cmplt $RA,$RB,$RC",
-                     [(set GPRC:$RC, (setlt GPRC:$RA, GPRC:$RB))], s_iadd>;
-def CMPLTi  : OFormL<0x10, 0x4D, "cmplt $RA,$L,$RC",
-                     [(set GPRC:$RC, (setlt GPRC:$RA, immUExt8:$L))], s_iadd>;
-def CMPULE  : OForm< 0x10, 0x3D, "cmpule $RA,$RB,$RC",
-                     [(set GPRC:$RC, (setule GPRC:$RA, GPRC:$RB))], s_iadd>;
-def CMPULEi : OFormL<0x10, 0x3D, "cmpule $RA,$L,$RC",
-                     [(set GPRC:$RC, (setule GPRC:$RA, immUExt8:$L))], s_iadd>;
-def CMPULT  : OForm< 0x10, 0x1D, "cmpult $RA,$RB,$RC",
-                     [(set GPRC:$RC, (setult GPRC:$RA, GPRC:$RB))], s_iadd>;
-def CMPULTi : OFormL<0x10, 0x1D, "cmpult $RA,$L,$RC", 
-                      [(set GPRC:$RC, (setult GPRC:$RA, immUExt8:$L))], s_iadd>;
-
-//Patterns for unsupported int comparisons
-def : Pat<(setueq GPRC:$X, GPRC:$Y), (CMPEQ GPRC:$X, GPRC:$Y)>;
-def : Pat<(setueq GPRC:$X, immUExt8:$Y), (CMPEQi GPRC:$X, immUExt8:$Y)>;
-
-def : Pat<(setugt GPRC:$X, GPRC:$Y), (CMPULT GPRC:$Y, GPRC:$X)>;
-def : Pat<(setugt immUExt8:$X, GPRC:$Y), (CMPULTi GPRC:$Y, immUExt8:$X)>;
-
-def : Pat<(setuge GPRC:$X, GPRC:$Y), (CMPULE GPRC:$Y, GPRC:$X)>;
-def : Pat<(setuge immUExt8:$X, GPRC:$Y), (CMPULEi GPRC:$Y, immUExt8:$X)>;
-
-def : Pat<(setgt GPRC:$X, GPRC:$Y), (CMPLT GPRC:$Y, GPRC:$X)>;
-def : Pat<(setgt immUExt8:$X, GPRC:$Y), (CMPLTi GPRC:$Y, immUExt8:$X)>;
-
-def : Pat<(setge GPRC:$X, GPRC:$Y), (CMPLE GPRC:$Y, GPRC:$X)>;
-def : Pat<(setge immUExt8:$X, GPRC:$Y), (CMPLEi GPRC:$Y, immUExt8:$X)>;
-
-def : Pat<(setne GPRC:$X, GPRC:$Y), (CMPEQi (CMPEQ GPRC:$X, GPRC:$Y), 0)>;
-def : Pat<(setne GPRC:$X, immUExt8:$Y), (CMPEQi (CMPEQi GPRC:$X, immUExt8:$Y), 0)>;
-
-def : Pat<(setune GPRC:$X, GPRC:$Y), (CMPEQi (CMPEQ GPRC:$X, GPRC:$Y), 0)>;
-def : Pat<(setune GPRC:$X, immUExt8:$Y), (CMPEQi (CMPEQ GPRC:$X, immUExt8:$Y), 0)>;
-
-
-let isReturn = 1, isTerminator = 1, isBarrier = 1, Ra = 31, Rb = 26, disp = 1, Uses = [R26] in {
-  def RETDAG : MbrForm< 0x1A, 0x02, (ins), "ret $$31,($$26),1", s_jsr>; //Return from subroutine
-  def RETDAGp : MbrpForm< 0x1A, 0x02, (ins), "ret $$31,($$26),1", [(retflag)], s_jsr>; //Return from subroutine
-}
-
-let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1, Ra = 31, disp = 0 in
-def JMP : MbrpForm< 0x1A, 0x00, (ins GPRC:$RS), "jmp $$31,($RS),0", 
-          [(brind GPRC:$RS)], s_jsr>; //Jump
-
-let isCall = 1, Ra = 26,
-    Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19,
-            R20, R21, R22, R23, R24, R25, R26, R27, R28, R29,
-            F0, F1,
-            F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
-            F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30], Uses = [R29] in {
-    def BSR : BFormD<0x34, "bsr $$26,$$$DISP..ng", [], s_jsr>; //Branch to subroutine
-}
-let isCall = 1, Ra = 26, Rb = 27, disp = 0,
-    Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19,
-            R20, R21, R22, R23, R24, R25, R26, R27, R28, R29,
-            F0, F1,
-            F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
-            F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30], Uses = [R27, R29] in {
-    def JSR : MbrForm< 0x1A, 0x01, (ins), "jsr $$26,($$27),0", s_jsr>; //Jump to subroutine
-}
-
-let isCall = 1, Ra = 23, Rb = 27, disp = 0,
-    Defs = [R23, R24, R25, R27, R28], Uses = [R24, R25, R27] in
-  def JSRs : MbrForm< 0x1A, 0x01, (ins), "jsr $$23,($$27),0", s_jsr>; //Jump to div or rem
-
-
-def JSR_COROUTINE : MbrForm< 0x1A, 0x03, (ins GPRC:$RD, GPRC:$RS, s14imm:$DISP), "jsr_coroutine $RD,($RS),$DISP", s_jsr>; //Jump to subroutine return
-
-
-let OutOperandList = (outs GPRC:$RA), InOperandList = (ins s64imm:$DISP, GPRC:$RB) in {
-def LDQ   : MForm<0x29, 1, "ldq $RA,$DISP($RB)",
-                 [(set GPRC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))], s_ild>;
-def LDQr  : MForm<0x29, 1, "ldq $RA,$DISP($RB)\t\t!gprellow",
-                 [(set GPRC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_ild>;
-def LDL   : MForm<0x28, 1, "ldl $RA,$DISP($RB)",
-                 [(set GPRC:$RA, (sextloadi32 (add GPRC:$RB, immSExt16:$DISP)))], s_ild>;
-def LDLr  : MForm<0x28, 1, "ldl $RA,$DISP($RB)\t\t!gprellow",
-                 [(set GPRC:$RA, (sextloadi32 (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_ild>;
-def LDBU  : MForm<0x0A, 1, "ldbu $RA,$DISP($RB)",
-                 [(set GPRC:$RA, (zextloadi8 (add GPRC:$RB, immSExt16:$DISP)))], s_ild>;
-def LDBUr : MForm<0x0A, 1, "ldbu $RA,$DISP($RB)\t\t!gprellow",
-                 [(set GPRC:$RA, (zextloadi8 (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_ild>;
-def LDWU  : MForm<0x0C, 1, "ldwu $RA,$DISP($RB)",
-                 [(set GPRC:$RA, (zextloadi16 (add GPRC:$RB, immSExt16:$DISP)))], s_ild>;
-def LDWUr : MForm<0x0C, 1, "ldwu $RA,$DISP($RB)\t\t!gprellow",
-                 [(set GPRC:$RA, (zextloadi16 (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_ild>;
-}
-
-
-let OutOperandList = (outs), InOperandList = (ins GPRC:$RA, s64imm:$DISP, GPRC:$RB) in {
-def STB   : MForm<0x0E, 0, "stb $RA,$DISP($RB)",
-                 [(truncstorei8 GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>;
-def STBr  : MForm<0x0E, 0, "stb $RA,$DISP($RB)\t\t!gprellow",
-                 [(truncstorei8 GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>;
-def STW   : MForm<0x0D, 0, "stw $RA,$DISP($RB)",
-                 [(truncstorei16 GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>;
-def STWr  : MForm<0x0D, 0, "stw $RA,$DISP($RB)\t\t!gprellow",
-                 [(truncstorei16 GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>;
-def STL   : MForm<0x2C, 0, "stl $RA,$DISP($RB)",
-                 [(truncstorei32 GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>;
-def STLr  : MForm<0x2C, 0, "stl $RA,$DISP($RB)\t\t!gprellow",
-                 [(truncstorei32 GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>;
-def STQ   : MForm<0x2D, 0, "stq $RA,$DISP($RB)",
-                 [(store GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>;
-def STQr  : MForm<0x2D, 0, "stq $RA,$DISP($RB)\t\t!gprellow",
-                 [(store GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>;
-}
-
-//Load address
-let OutOperandList = (outs GPRC:$RA), InOperandList = (ins s64imm:$DISP, GPRC:$RB) in {
-def LDA   : MForm<0x08, 0, "lda $RA,$DISP($RB)",
-                 [(set GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_lda>;
-def LDAr  : MForm<0x08, 0, "lda $RA,$DISP($RB)\t\t!gprellow",
-                 [(set GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_lda>;  //Load address
-def LDAH  : MForm<0x09, 0, "ldah $RA,$DISP($RB)",
-                 [], s_lda>;  //Load address high
-def LDAHr : MForm<0x09, 0, "ldah $RA,$DISP($RB)\t\t!gprelhigh",
-                 [(set GPRC:$RA, (Alpha_gprelhi tglobaladdr:$DISP, GPRC:$RB))], s_lda>;  //Load address high
-}
-
-let OutOperandList = (outs), InOperandList = (ins F4RC:$RA, s64imm:$DISP, GPRC:$RB) in {
-def STS  : MForm<0x26, 0, "sts $RA,$DISP($RB)",
-                [(store F4RC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_fst>;
-def STSr : MForm<0x26, 0, "sts $RA,$DISP($RB)\t\t!gprellow",
-                [(store F4RC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_fst>;
-}
-let OutOperandList = (outs F4RC:$RA), InOperandList = (ins s64imm:$DISP, GPRC:$RB) in {
-def LDS  : MForm<0x22, 1, "lds $RA,$DISP($RB)",
-                [(set F4RC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))], s_fld>;
-def LDSr : MForm<0x22, 1, "lds $RA,$DISP($RB)\t\t!gprellow",
-                [(set F4RC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_fld>;
-}
-let OutOperandList = (outs), InOperandList = (ins F8RC:$RA, s64imm:$DISP, GPRC:$RB) in {
-def STT  : MForm<0x27, 0, "stt $RA,$DISP($RB)",
-                 [(store F8RC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_fst>;
-def STTr : MForm<0x27, 0, "stt $RA,$DISP($RB)\t\t!gprellow",
-                 [(store F8RC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_fst>;
-}
-let OutOperandList = (outs F8RC:$RA), InOperandList = (ins s64imm:$DISP, GPRC:$RB) in {
-def LDT  : MForm<0x23, 1, "ldt $RA,$DISP($RB)",
-                [(set F8RC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))], s_fld>;
-def LDTr : MForm<0x23, 1, "ldt $RA,$DISP($RB)\t\t!gprellow",
-                [(set F8RC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_fld>;
-}
-
-
-//constpool rels
-def : Pat<(i64 (load (Alpha_gprello tconstpool:$DISP, GPRC:$RB))),
-          (LDQr tconstpool:$DISP, GPRC:$RB)>;
-def : Pat<(i64 (sextloadi32 (Alpha_gprello tconstpool:$DISP, GPRC:$RB))),
-          (LDLr tconstpool:$DISP, GPRC:$RB)>;
-def : Pat<(i64 (zextloadi8 (Alpha_gprello tconstpool:$DISP, GPRC:$RB))),
-          (LDBUr tconstpool:$DISP, GPRC:$RB)>;
-def : Pat<(i64 (zextloadi16 (Alpha_gprello tconstpool:$DISP, GPRC:$RB))),
-          (LDWUr tconstpool:$DISP, GPRC:$RB)>;
-def : Pat<(i64 (Alpha_gprello tconstpool:$DISP, GPRC:$RB)),
-          (LDAr tconstpool:$DISP, GPRC:$RB)>;
-def : Pat<(i64 (Alpha_gprelhi tconstpool:$DISP, GPRC:$RB)),
-          (LDAHr tconstpool:$DISP, GPRC:$RB)>;
-def : Pat<(f32 (load (Alpha_gprello tconstpool:$DISP, GPRC:$RB))),
-          (LDSr tconstpool:$DISP, GPRC:$RB)>;
-def : Pat<(f64 (load (Alpha_gprello tconstpool:$DISP, GPRC:$RB))),
-          (LDTr tconstpool:$DISP, GPRC:$RB)>;
-
-//jumptable rels
-def : Pat<(i64 (Alpha_gprelhi tjumptable:$DISP, GPRC:$RB)),
-          (LDAHr tjumptable:$DISP, GPRC:$RB)>;
-def : Pat<(i64 (Alpha_gprello tjumptable:$DISP, GPRC:$RB)),
-          (LDAr tjumptable:$DISP, GPRC:$RB)>;
-
-
-//misc ext patterns
-def : Pat<(i64 (extloadi8 (add GPRC:$RB, immSExt16:$DISP))),
-          (LDBU   immSExt16:$DISP, GPRC:$RB)>;
-def : Pat<(i64 (extloadi16 (add GPRC:$RB, immSExt16:$DISP))),
-          (LDWU  immSExt16:$DISP, GPRC:$RB)>;
-def : Pat<(i64 (extloadi32 (add GPRC:$RB, immSExt16:$DISP))),
-          (LDL   immSExt16:$DISP, GPRC:$RB)>;
-
-//0 disp patterns
-def : Pat<(i64 (load GPRC:$addr)),
-          (LDQ  0, GPRC:$addr)>;
-def : Pat<(f64 (load GPRC:$addr)),
-          (LDT  0, GPRC:$addr)>;
-def : Pat<(f32 (load GPRC:$addr)),
-          (LDS  0, GPRC:$addr)>;
-def : Pat<(i64 (sextloadi32 GPRC:$addr)),
-          (LDL  0, GPRC:$addr)>;
-def : Pat<(i64 (zextloadi16 GPRC:$addr)),
-          (LDWU 0, GPRC:$addr)>;
-def : Pat<(i64 (zextloadi8 GPRC:$addr)),
-          (LDBU 0, GPRC:$addr)>;
-def : Pat<(i64 (extloadi8 GPRC:$addr)),
-          (LDBU 0, GPRC:$addr)>;
-def : Pat<(i64 (extloadi16 GPRC:$addr)),
-          (LDWU 0, GPRC:$addr)>;
-def : Pat<(i64 (extloadi32 GPRC:$addr)),
-          (LDL  0, GPRC:$addr)>;
-
-def : Pat<(store GPRC:$DATA, GPRC:$addr),
-          (STQ  GPRC:$DATA, 0, GPRC:$addr)>;
-def : Pat<(store F8RC:$DATA, GPRC:$addr),
-          (STT  F8RC:$DATA, 0, GPRC:$addr)>;
-def : Pat<(store F4RC:$DATA, GPRC:$addr),
-          (STS  F4RC:$DATA, 0, GPRC:$addr)>;
-def : Pat<(truncstorei32 GPRC:$DATA, GPRC:$addr),
-          (STL  GPRC:$DATA, 0, GPRC:$addr)>;
-def : Pat<(truncstorei16 GPRC:$DATA, GPRC:$addr),
-          (STW GPRC:$DATA, 0, GPRC:$addr)>;
-def : Pat<(truncstorei8 GPRC:$DATA, GPRC:$addr),
-          (STB GPRC:$DATA, 0, GPRC:$addr)>;
-
-
-//load address, rellocated gpdist form
-let OutOperandList = (outs GPRC:$RA),
-    InOperandList = (ins s16imm:$DISP, GPRC:$RB, s16imm:$NUM),
-    mayLoad = 1 in {
-def LDAg  : MForm<0x08, 1, "lda $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>;  //Load address
-def LDAHg : MForm<0x09, 1, "ldah $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>;  //Load address
-}
-
-//Load quad, rellocated literal form
-let OutOperandList = (outs GPRC:$RA), InOperandList = (ins s64imm:$DISP, GPRC:$RB) in 
-def LDQl : MForm<0x29, 1, "ldq $RA,$DISP($RB)\t\t!literal",
-                 [(set GPRC:$RA, (Alpha_rellit tglobaladdr:$DISP, GPRC:$RB))], s_ild>;
-def : Pat<(Alpha_rellit texternalsym:$ext, GPRC:$RB),
-          (LDQl texternalsym:$ext, GPRC:$RB)>;
-
-let OutOperandList = (outs GPRC:$RR),
-    InOperandList = (ins GPRC:$RA, s64imm:$DISP, GPRC:$RB),
-    Constraints = "$RA = $RR",
-    DisableEncoding = "$RR" in {
-def STQ_C : MForm<0x2F, 0, "stq_l $RA,$DISP($RB)", [], s_ist>;
-def STL_C : MForm<0x2E, 0, "stl_l $RA,$DISP($RB)", [], s_ist>;
-}
-let OutOperandList = (outs GPRC:$RA),
-    InOperandList = (ins s64imm:$DISP, GPRC:$RB),
-    mayLoad = 1 in {
-def LDQ_L : MForm<0x2B, 1, "ldq_l $RA,$DISP($RB)", [], s_ild>;
-def LDL_L : MForm<0x2A, 1, "ldl_l $RA,$DISP($RB)", [], s_ild>;
-}
-
-def RPCC : MfcForm<0x18, 0xC000, "rpcc $RA", s_rpcc>; //Read process cycle counter
-def MB  : MfcPForm<0x18, 0x4000, "mb",  s_imisc>; //memory barrier
-def WMB : MfcPForm<0x18, 0x4400, "wmb", s_imisc>; //write memory barrier
-
-def : Pat<(membarrier (i64 imm), (i64 imm), (i64 imm), (i64 1), (i64 imm)),
-          (WMB)>;
-def : Pat<(membarrier (i64 imm), (i64 imm), (i64 imm), (i64 imm), (i64 imm)),
-          (MB)>;
-
-def : Pat<(atomic_fence (imm), (imm)), (MB)>;
-
-//Basic Floating point ops
-
-//Floats
-
-let OutOperandList = (outs F4RC:$RC), InOperandList = (ins F4RC:$RB), Fa = 31 in 
-def SQRTS : FPForm<0x14, 0x58B, "sqrts/su $RB,$RC",
-                   [(set F4RC:$RC, (fsqrt F4RC:$RB))], s_fsqrts>;
-
-let OutOperandList = (outs F4RC:$RC), InOperandList = (ins F4RC:$RA, F4RC:$RB) in {
-def ADDS  : FPForm<0x16, 0x580, "adds/su $RA,$RB,$RC",
-                   [(set F4RC:$RC, (fadd F4RC:$RA, F4RC:$RB))], s_fadd>;
-def SUBS  : FPForm<0x16, 0x581, "subs/su $RA,$RB,$RC",
-                   [(set F4RC:$RC, (fsub F4RC:$RA, F4RC:$RB))], s_fadd>;
-def DIVS  : FPForm<0x16, 0x583, "divs/su $RA,$RB,$RC",
-                   [(set F4RC:$RC, (fdiv F4RC:$RA, F4RC:$RB))], s_fdivs>;
-def MULS  : FPForm<0x16, 0x582, "muls/su $RA,$RB,$RC",
-                   [(set F4RC:$RC, (fmul F4RC:$RA, F4RC:$RB))], s_fmul>;
-
-def CPYSS  : FPForm<0x17, 0x020, "cpys $RA,$RB,$RC",
-                   [(set F4RC:$RC, (fcopysign F4RC:$RB, F4RC:$RA))], s_fadd>;
-def CPYSES : FPForm<0x17, 0x022, "cpyse $RA,$RB,$RC",[], s_fadd>; //Copy sign and exponent
-def CPYSNS : FPForm<0x17, 0x021, "cpysn $RA,$RB,$RC",
-                   [(set F4RC:$RC, (fneg (fcopysign F4RC:$RB, F4RC:$RA)))], s_fadd>;
-}
-
-//Doubles
-
-let OutOperandList = (outs F8RC:$RC), InOperandList = (ins F8RC:$RB), Fa = 31 in 
-def SQRTT : FPForm<0x14, 0x5AB, "sqrtt/su $RB,$RC",
-                   [(set F8RC:$RC, (fsqrt F8RC:$RB))], s_fsqrtt>;
-
-let OutOperandList = (outs F8RC:$RC), InOperandList = (ins F8RC:$RA, F8RC:$RB) in {
-def ADDT  : FPForm<0x16, 0x5A0, "addt/su $RA,$RB,$RC",
-                   [(set F8RC:$RC, (fadd F8RC:$RA, F8RC:$RB))], s_fadd>;
-def SUBT  : FPForm<0x16, 0x5A1, "subt/su $RA,$RB,$RC",
-                   [(set F8RC:$RC, (fsub F8RC:$RA, F8RC:$RB))], s_fadd>;
-def DIVT  : FPForm<0x16, 0x5A3, "divt/su $RA,$RB,$RC",
-                   [(set F8RC:$RC, (fdiv F8RC:$RA, F8RC:$RB))], s_fdivt>;
-def MULT  : FPForm<0x16, 0x5A2, "mult/su $RA,$RB,$RC",
-                   [(set F8RC:$RC, (fmul F8RC:$RA, F8RC:$RB))], s_fmul>;
-
-def CPYST  : FPForm<0x17, 0x020, "cpys $RA,$RB,$RC",
-                   [(set F8RC:$RC, (fcopysign F8RC:$RB, F8RC:$RA))], s_fadd>;
-def CPYSET : FPForm<0x17, 0x022, "cpyse $RA,$RB,$RC",[], s_fadd>; //Copy sign and exponent
-def CPYSNT : FPForm<0x17, 0x021, "cpysn $RA,$RB,$RC",
-                   [(set F8RC:$RC, (fneg (fcopysign F8RC:$RB, F8RC:$RA)))], s_fadd>;
-
-def CMPTEQ : FPForm<0x16, 0x5A5, "cmpteq/su $RA,$RB,$RC", [], s_fadd>;
-//                    [(set F8RC:$RC, (seteq F8RC:$RA, F8RC:$RB))]>;
-def CMPTLE : FPForm<0x16, 0x5A7, "cmptle/su $RA,$RB,$RC", [], s_fadd>;
-//                    [(set F8RC:$RC, (setle F8RC:$RA, F8RC:$RB))]>;
-def CMPTLT : FPForm<0x16, 0x5A6, "cmptlt/su $RA,$RB,$RC", [], s_fadd>;
-//                    [(set F8RC:$RC, (setlt F8RC:$RA, F8RC:$RB))]>;
-def CMPTUN : FPForm<0x16, 0x5A4, "cmptun/su $RA,$RB,$RC", [], s_fadd>;
-//                    [(set F8RC:$RC, (setuo F8RC:$RA, F8RC:$RB))]>;
-}
-
-//More CPYS forms:
-let OutOperandList = (outs F8RC:$RC), InOperandList = (ins F4RC:$RA, F8RC:$RB) in {
-def CPYSTs  : FPForm<0x17, 0x020, "cpys $RA,$RB,$RC",
-                   [(set F8RC:$RC, (fcopysign F8RC:$RB, F4RC:$RA))], s_fadd>;
-def CPYSNTs : FPForm<0x17, 0x021, "cpysn $RA,$RB,$RC",
-                   [(set F8RC:$RC, (fneg (fcopysign F8RC:$RB, F4RC:$RA)))], s_fadd>;
-}
-let OutOperandList = (outs F4RC:$RC), InOperandList = (ins F8RC:$RA, F4RC:$RB) in {
-def CPYSSt  : FPForm<0x17, 0x020, "cpys $RA,$RB,$RC",
-                   [(set F4RC:$RC, (fcopysign F4RC:$RB, F8RC:$RA))], s_fadd>;
-def CPYSESt : FPForm<0x17, 0x022, "cpyse $RA,$RB,$RC",[], s_fadd>; //Copy sign and exponent
-def CPYSNSt : FPForm<0x17, 0x021, "cpysn $RA,$RB,$RC",
-                   [(set F4RC:$RC, (fneg (fcopysign F4RC:$RB, F8RC:$RA)))], s_fadd>;
-}
-
-//conditional moves, floats
-let OutOperandList = (outs F4RC:$RDEST),
-    InOperandList = (ins F4RC:$RFALSE, F4RC:$RTRUE, F8RC:$RCOND),
-    Constraints = "$RTRUE = $RDEST" in {
-def FCMOVEQS : FPForm<0x17, 0x02A, 
-                      "fcmoveq $RCOND,$RTRUE,$RDEST",
-                      [], s_fcmov>; //FCMOVE if = zero
-def FCMOVGES : FPForm<0x17, 0x02D, 
-                      "fcmovge $RCOND,$RTRUE,$RDEST",
-                      [], s_fcmov>; //FCMOVE if >= zero
-def FCMOVGTS : FPForm<0x17, 0x02F, 
-                      "fcmovgt $RCOND,$RTRUE,$RDEST",
-                      [], s_fcmov>; //FCMOVE if > zero
-def FCMOVLES : FPForm<0x17, 0x02E, 
-                      "fcmovle $RCOND,$RTRUE,$RDEST",
-                      [], s_fcmov>; //FCMOVE if <= zero
-def FCMOVLTS : FPForm<0x17, 0x02C,
-                      "fcmovlt $RCOND,$RTRUE,$RDEST",
-                      [], s_fcmov>; // FCMOVE if < zero
-def FCMOVNES : FPForm<0x17, 0x02B, 
-                      "fcmovne $RCOND,$RTRUE,$RDEST",
-                      [], s_fcmov>; //FCMOVE if != zero
-}
-//conditional moves, doubles
-let OutOperandList = (outs F8RC:$RDEST), 
-    InOperandList = (ins F8RC:$RFALSE, F8RC:$RTRUE, F8RC:$RCOND),
-    Constraints = "$RTRUE = $RDEST" in {
-def FCMOVEQT : FPForm<0x17, 0x02A, "fcmoveq $RCOND,$RTRUE,$RDEST", [], s_fcmov>;
-def FCMOVGET : FPForm<0x17, 0x02D, "fcmovge $RCOND,$RTRUE,$RDEST", [], s_fcmov>;
-def FCMOVGTT : FPForm<0x17, 0x02F, "fcmovgt $RCOND,$RTRUE,$RDEST", [], s_fcmov>;
-def FCMOVLET : FPForm<0x17, 0x02E, "fcmovle $RCOND,$RTRUE,$RDEST", [], s_fcmov>;
-def FCMOVLTT : FPForm<0x17, 0x02C, "fcmovlt $RCOND,$RTRUE,$RDEST", [], s_fcmov>;
-def FCMOVNET : FPForm<0x17, 0x02B, "fcmovne $RCOND,$RTRUE,$RDEST", [], s_fcmov>;
-}
-
-//misc FP selects
-//Select double
-
-def : Pat<(select (seteq F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
-      (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTEQ F8RC:$RA, F8RC:$RB))>;
-def : Pat<(select (setoeq F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
-      (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTEQ F8RC:$RA, F8RC:$RB))>;
-def : Pat<(select (setueq F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
-      (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTEQ F8RC:$RA, F8RC:$RB))>;
-
-def : Pat<(select (setne F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
-      (FCMOVEQT F8RC:$sf, F8RC:$st, (CMPTEQ F8RC:$RA, F8RC:$RB))>;
-def : Pat<(select (setone F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
-      (FCMOVEQT F8RC:$sf, F8RC:$st, (CMPTEQ F8RC:$RA, F8RC:$RB))>;
-def : Pat<(select (setune F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
-      (FCMOVEQT F8RC:$sf, F8RC:$st, (CMPTEQ F8RC:$RA, F8RC:$RB))>;
-
-def : Pat<(select (setgt F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
-      (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTLT F8RC:$RB, F8RC:$RA))>;
-def : Pat<(select (setogt F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
-      (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTLT F8RC:$RB, F8RC:$RA))>;
-def : Pat<(select (setugt F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
-      (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTLT F8RC:$RB, F8RC:$RA))>;
-
-def : Pat<(select (setge F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
-      (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTLE F8RC:$RB, F8RC:$RA))>;
-def : Pat<(select (setoge F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
-      (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTLE F8RC:$RB, F8RC:$RA))>;
-def : Pat<(select (setuge F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
-      (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTLE F8RC:$RB, F8RC:$RA))>;
-
-def : Pat<(select (setlt F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
-      (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTLT F8RC:$RA, F8RC:$RB))>;
-def : Pat<(select (setolt F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
-      (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTLT F8RC:$RA, F8RC:$RB))>;
-def : Pat<(select (setult F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
-      (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTLT F8RC:$RA, F8RC:$RB))>;
-
-def : Pat<(select (setle F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
-      (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTLE F8RC:$RA, F8RC:$RB))>;
-def : Pat<(select (setole F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
-      (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTLE F8RC:$RA, F8RC:$RB))>;
-def : Pat<(select (setule F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
-      (FCMOVNET F8RC:$sf, F8RC:$st, (CMPTLE F8RC:$RA, F8RC:$RB))>;
-
-//Select single
-def : Pat<(select (seteq F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
-      (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTEQ F8RC:$RA, F8RC:$RB))>;
-def : Pat<(select (setoeq F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
-      (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTEQ F8RC:$RA, F8RC:$RB))>;
-def : Pat<(select (setueq F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
-      (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTEQ F8RC:$RA, F8RC:$RB))>;
-
-def : Pat<(select (setne F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
-      (FCMOVEQS F4RC:$sf, F4RC:$st, (CMPTEQ F8RC:$RA, F8RC:$RB))>;
-def : Pat<(select (setone F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
-      (FCMOVEQS F4RC:$sf, F4RC:$st, (CMPTEQ F8RC:$RA, F8RC:$RB))>;
-def : Pat<(select (setune F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
-      (FCMOVEQS F4RC:$sf, F4RC:$st, (CMPTEQ F8RC:$RA, F8RC:$RB))>;
-
-def : Pat<(select (setgt F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
-      (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTLT F8RC:$RB, F8RC:$RA))>;
-def : Pat<(select (setogt F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
-      (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTLT F8RC:$RB, F8RC:$RA))>;
-def : Pat<(select (setugt F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
-      (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTLT F8RC:$RB, F8RC:$RA))>;
-
-def : Pat<(select (setge F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
-      (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTLE F8RC:$RB, F8RC:$RA))>;
-def : Pat<(select (setoge F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
-      (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTLE F8RC:$RB, F8RC:$RA))>;
-def : Pat<(select (setuge F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
-      (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTLE F8RC:$RB, F8RC:$RA))>;
-
-def : Pat<(select (setlt F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
-      (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTLT F8RC:$RA, F8RC:$RB))>;
-def : Pat<(select (setolt F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
-      (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTLT F8RC:$RA, F8RC:$RB))>;
-def : Pat<(select (setult F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
-      (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTLT F8RC:$RA, F8RC:$RB))>;
-
-def : Pat<(select (setle F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
-      (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTLE F8RC:$RA, F8RC:$RB))>;
-def : Pat<(select (setole F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
-      (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTLE F8RC:$RA, F8RC:$RB))>;
-def : Pat<(select (setule F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf),
-      (FCMOVNES F4RC:$sf, F4RC:$st, (CMPTLE F8RC:$RA, F8RC:$RB))>;
-
-
-
-let OutOperandList = (outs GPRC:$RC), InOperandList = (ins F4RC:$RA), Fb = 31 in 
-def FTOIS : FPForm<0x1C, 0x078, "ftois $RA,$RC",
-        [(set GPRC:$RC, (bitconvert F4RC:$RA))], s_ftoi>; //Floating to integer move, S_floating
-let OutOperandList = (outs GPRC:$RC), InOperandList = (ins F8RC:$RA), Fb = 31 in 
-def FTOIT : FPForm<0x1C, 0x070, "ftoit $RA,$RC",
-        [(set GPRC:$RC, (bitconvert F8RC:$RA))], s_ftoi>; //Floating to integer move
-let OutOperandList = (outs F4RC:$RC), InOperandList = (ins GPRC:$RA), Fb = 31 in 
-def ITOFS : FPForm<0x14, 0x004, "itofs $RA,$RC",
-    	[(set F4RC:$RC, (bitconvert GPRC:$RA))], s_itof>; //Integer to floating move, S_floating
-let OutOperandList = (outs F8RC:$RC), InOperandList = (ins GPRC:$RA), Fb = 31 in 
-def ITOFT : FPForm<0x14, 0x024, "itoft $RA,$RC",
-        [(set F8RC:$RC, (bitconvert GPRC:$RA))], s_itof>; //Integer to floating move
-
-
-let OutOperandList = (outs F4RC:$RC), InOperandList = (ins F8RC:$RB), Fa = 31 in 
-def CVTQS : FPForm<0x16, 0x7BC, "cvtqs/sui $RB,$RC",
-        [(set F4RC:$RC, (Alpha_cvtqs F8RC:$RB))], s_fadd>;
-let OutOperandList = (outs F8RC:$RC), InOperandList = (ins F8RC:$RB), Fa = 31 in 
-def CVTQT : FPForm<0x16, 0x7BE, "cvtqt/sui $RB,$RC",
-        [(set F8RC:$RC, (Alpha_cvtqt F8RC:$RB))], s_fadd>;
-let OutOperandList = (outs F8RC:$RC), InOperandList = (ins F8RC:$RB), Fa = 31 in 
-def CVTTQ : FPForm<0x16, 0x52F, "cvttq/svc $RB,$RC",
-        [(set F8RC:$RC, (Alpha_cvttq F8RC:$RB))], s_fadd>;
-let OutOperandList = (outs F8RC:$RC), InOperandList = (ins F4RC:$RB), Fa = 31 in 
-def CVTST : FPForm<0x16, 0x6AC, "cvtst/s $RB,$RC",
-                   [(set F8RC:$RC, (fextend F4RC:$RB))], s_fadd>;
-let OutOperandList = (outs F4RC:$RC), InOperandList = (ins F8RC:$RB), Fa = 31 in 
-def CVTTS : FPForm<0x16, 0x7AC, "cvtts/sui $RB,$RC",
-                   [(set F4RC:$RC, (fround F8RC:$RB))], s_fadd>;
-
-def :  Pat<(select GPRC:$RC, F8RC:$st, F8RC:$sf),
-       (f64 (FCMOVEQT  F8RC:$st, F8RC:$sf, (ITOFT GPRC:$RC)))>; 
-def :  Pat<(select GPRC:$RC, F4RC:$st, F4RC:$sf),
-       (f32 (FCMOVEQS  F4RC:$st, F4RC:$sf, (ITOFT GPRC:$RC)))>; 
-
-/////////////////////////////////////////////////////////
-//Branching
-/////////////////////////////////////////////////////////
-class br_icc<bits<6> opc, string asmstr>
-  : BFormN<opc, (ins u64imm:$opc, GPRC:$R, target:$dst), 
-    !strconcat(asmstr, " $R,$dst"),  s_icbr>;
-class br_fcc<bits<6> opc, string asmstr>
-  : BFormN<opc, (ins u64imm:$opc, F8RC:$R, target:$dst), 
-    !strconcat(asmstr, " $R,$dst"),  s_fbr>;
-
-let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
-let Ra = 31, isBarrier = 1 in
-def BR : BFormD<0x30, "br $$31,$DISP", [(br bb:$DISP)], s_ubr>;
-
-def COND_BRANCH_I : BFormN<0, (ins u64imm:$opc, GPRC:$R, target:$dst), 
-                    "{:comment} COND_BRANCH imm:$opc, GPRC:$R, bb:$dst", 
-                    s_icbr>;
-def COND_BRANCH_F : BFormN<0, (ins u64imm:$opc, F8RC:$R, target:$dst), 
-                    "{:comment} COND_BRANCH imm:$opc, F8RC:$R, bb:$dst",
-                    s_fbr>;
-//Branches, int
-def BEQ  : br_icc<0x39, "beq">;
-def BGE  : br_icc<0x3E, "bge">;
-def BGT  : br_icc<0x3F, "bgt">;
-def BLBC : br_icc<0x38, "blbc">;
-def BLBS : br_icc<0x3C, "blbs">;
-def BLE  : br_icc<0x3B, "ble">;
-def BLT  : br_icc<0x3A, "blt">;
-def BNE  : br_icc<0x3D, "bne">;
-
-//Branches, float
-def FBEQ : br_fcc<0x31, "fbeq">;
-def FBGE : br_fcc<0x36, "fbge">;
-def FBGT : br_fcc<0x37, "fbgt">;
-def FBLE : br_fcc<0x33, "fble">;
-def FBLT : br_fcc<0x32, "fblt">;
-def FBNE : br_fcc<0x36, "fbne">;
-}
-
-//An ugly trick to get the opcode as an imm I can use
-def immBRCond : SDNodeXForm<imm, [{
-  switch((uint64_t)N->getZExtValue()) {
-    default: assert(0 && "Unknown branch type");
-    case 0:  return getI64Imm(Alpha::BEQ);
-    case 1:  return getI64Imm(Alpha::BNE);
-    case 2:  return getI64Imm(Alpha::BGE);
-    case 3:  return getI64Imm(Alpha::BGT);
-    case 4:  return getI64Imm(Alpha::BLE);
-    case 5:  return getI64Imm(Alpha::BLT);
-    case 6:  return getI64Imm(Alpha::BLBS);
-    case 7:  return getI64Imm(Alpha::BLBC);
-    case 20: return getI64Imm(Alpha::FBEQ);
-    case 21: return getI64Imm(Alpha::FBNE);
-    case 22: return getI64Imm(Alpha::FBGE);
-    case 23: return getI64Imm(Alpha::FBGT);
-    case 24: return getI64Imm(Alpha::FBLE);
-    case 25: return getI64Imm(Alpha::FBLT);
-  }
-}]>;
-
-//Int cond patterns
-def : Pat<(brcond (seteq GPRC:$RA, 0), bb:$DISP), 
-      (COND_BRANCH_I (immBRCond 0),  GPRC:$RA, bb:$DISP)>;
-def : Pat<(brcond (setge GPRC:$RA, 0), bb:$DISP), 
-      (COND_BRANCH_I (immBRCond 2),  GPRC:$RA, bb:$DISP)>;
-def : Pat<(brcond (setgt GPRC:$RA, 0), bb:$DISP), 
-      (COND_BRANCH_I (immBRCond 3),  GPRC:$RA, bb:$DISP)>;
-def : Pat<(brcond (and GPRC:$RA, 1), bb:$DISP), 
-      (COND_BRANCH_I (immBRCond 6),  GPRC:$RA, bb:$DISP)>;
-def : Pat<(brcond (setle GPRC:$RA, 0), bb:$DISP), 
-      (COND_BRANCH_I (immBRCond 4),  GPRC:$RA, bb:$DISP)>;
-def : Pat<(brcond (setlt GPRC:$RA, 0), bb:$DISP), 
-      (COND_BRANCH_I (immBRCond 5),  GPRC:$RA, bb:$DISP)>;
-def : Pat<(brcond (setne GPRC:$RA, 0), bb:$DISP), 
-      (COND_BRANCH_I (immBRCond 1),  GPRC:$RA, bb:$DISP)>;
-
-def : Pat<(brcond GPRC:$RA, bb:$DISP), 
-      (COND_BRANCH_I (immBRCond 1), GPRC:$RA, bb:$DISP)>;
-def : Pat<(brcond (setne GPRC:$RA, GPRC:$RB), bb:$DISP), 
-      (COND_BRANCH_I (immBRCond 0), (CMPEQ GPRC:$RA, GPRC:$RB), bb:$DISP)>;
-def : Pat<(brcond (setne GPRC:$RA, immUExt8:$L), bb:$DISP), 
-      (COND_BRANCH_I (immBRCond 0), (CMPEQi GPRC:$RA, immUExt8:$L), bb:$DISP)>;
-
-//FP cond patterns
-def : Pat<(brcond (seteq F8RC:$RA, immFPZ), bb:$DISP), 
-      (COND_BRANCH_F (immBRCond 20),  F8RC:$RA, bb:$DISP)>;
-def : Pat<(brcond (setne F8RC:$RA, immFPZ), bb:$DISP), 
-      (COND_BRANCH_F (immBRCond 21),  F8RC:$RA, bb:$DISP)>;
-def : Pat<(brcond (setge F8RC:$RA, immFPZ), bb:$DISP), 
-      (COND_BRANCH_F (immBRCond 22),  F8RC:$RA, bb:$DISP)>;
-def : Pat<(brcond (setgt F8RC:$RA, immFPZ), bb:$DISP), 
-      (COND_BRANCH_F (immBRCond 23),  F8RC:$RA, bb:$DISP)>;
-def : Pat<(brcond (setle F8RC:$RA, immFPZ), bb:$DISP), 
-      (COND_BRANCH_F (immBRCond 24),  F8RC:$RA, bb:$DISP)>;
-def : Pat<(brcond (setlt F8RC:$RA, immFPZ), bb:$DISP), 
-      (COND_BRANCH_F (immBRCond 25),  F8RC:$RA, bb:$DISP)>;
-
-
-def : Pat<(brcond (seteq F8RC:$RA, F8RC:$RB), bb:$DISP),  
-      (COND_BRANCH_F (immBRCond 21), (CMPTEQ F8RC:$RA, F8RC:$RB), bb:$DISP)>;
-def : Pat<(brcond (setoeq F8RC:$RA, F8RC:$RB), bb:$DISP), 
-      (COND_BRANCH_F (immBRCond 21), (CMPTEQ F8RC:$RA, F8RC:$RB), bb:$DISP)>;
-def : Pat<(brcond (setueq F8RC:$RA, F8RC:$RB), bb:$DISP), 
-      (COND_BRANCH_F (immBRCond 21), (CMPTEQ F8RC:$RA, F8RC:$RB), bb:$DISP)>;
-
-def : Pat<(brcond (setlt F8RC:$RA, F8RC:$RB), bb:$DISP),  
-      (COND_BRANCH_F (immBRCond 21), (CMPTLT F8RC:$RA, F8RC:$RB), bb:$DISP)>;
-def : Pat<(brcond (setolt F8RC:$RA, F8RC:$RB), bb:$DISP), 
-      (COND_BRANCH_F (immBRCond 21), (CMPTLT F8RC:$RA, F8RC:$RB), bb:$DISP)>;
-def : Pat<(brcond (setult F8RC:$RA, F8RC:$RB), bb:$DISP), 
-      (COND_BRANCH_F (immBRCond 21), (CMPTLT F8RC:$RA, F8RC:$RB), bb:$DISP)>;
-
-def : Pat<(brcond (setle F8RC:$RA, F8RC:$RB), bb:$DISP),  
-      (COND_BRANCH_F (immBRCond 21), (CMPTLE F8RC:$RA, F8RC:$RB), bb:$DISP)>;
-def : Pat<(brcond (setole F8RC:$RA, F8RC:$RB), bb:$DISP), 
-      (COND_BRANCH_F (immBRCond 21), (CMPTLE F8RC:$RA, F8RC:$RB), bb:$DISP)>;
-def : Pat<(brcond (setule F8RC:$RA, F8RC:$RB), bb:$DISP), 
-      (COND_BRANCH_F (immBRCond 21), (CMPTLE F8RC:$RA, F8RC:$RB), bb:$DISP)>;
-
-def : Pat<(brcond (setgt F8RC:$RA, F8RC:$RB), bb:$DISP),  
-      (COND_BRANCH_F (immBRCond 21), (CMPTLT F8RC:$RB, F8RC:$RA), bb:$DISP)>;
-def : Pat<(brcond (setogt F8RC:$RA, F8RC:$RB), bb:$DISP), 
-      (COND_BRANCH_F (immBRCond 21), (CMPTLT F8RC:$RB, F8RC:$RA), bb:$DISP)>;
-def : Pat<(brcond (setugt F8RC:$RA, F8RC:$RB), bb:$DISP), 
-      (COND_BRANCH_F (immBRCond 21), (CMPTLT F8RC:$RB, F8RC:$RA), bb:$DISP)>;
-
-def : Pat<(brcond (setge F8RC:$RA, F8RC:$RB), bb:$DISP),  
-      (COND_BRANCH_F (immBRCond 21), (CMPTLE F8RC:$RB, F8RC:$RA), bb:$DISP)>;
-def : Pat<(brcond (setoge F8RC:$RA, F8RC:$RB), bb:$DISP), 
-      (COND_BRANCH_F (immBRCond 21), (CMPTLE F8RC:$RB, F8RC:$RA), bb:$DISP)>;
-def : Pat<(brcond (setuge F8RC:$RA, F8RC:$RB), bb:$DISP), 
-      (COND_BRANCH_F (immBRCond 21), (CMPTLE F8RC:$RB, F8RC:$RA), bb:$DISP)>;
-
-def : Pat<(brcond (setne F8RC:$RA, F8RC:$RB), bb:$DISP),  
-      (COND_BRANCH_F (immBRCond 20), (CMPTEQ F8RC:$RA, F8RC:$RB), bb:$DISP)>;
-def : Pat<(brcond (setone F8RC:$RA, F8RC:$RB), bb:$DISP), 
-      (COND_BRANCH_F (immBRCond 20), (CMPTEQ F8RC:$RA, F8RC:$RB), bb:$DISP)>;
-def : Pat<(brcond (setune F8RC:$RA, F8RC:$RB), bb:$DISP), 
-      (COND_BRANCH_F (immBRCond 20), (CMPTEQ F8RC:$RA, F8RC:$RB), bb:$DISP)>;
-
-
-def : Pat<(brcond (setoeq F8RC:$RA, immFPZ), bb:$DISP),   
-      (COND_BRANCH_F (immBRCond 20), F8RC:$RA,bb:$DISP)>;
-def : Pat<(brcond (setueq F8RC:$RA, immFPZ), bb:$DISP),   
-      (COND_BRANCH_F (immBRCond 20), F8RC:$RA,bb:$DISP)>;
-
-def : Pat<(brcond (setoge F8RC:$RA, immFPZ), bb:$DISP),   
-      (COND_BRANCH_F (immBRCond 22), F8RC:$RA,bb:$DISP)>;
-def : Pat<(brcond (setuge F8RC:$RA, immFPZ), bb:$DISP),   
-      (COND_BRANCH_F (immBRCond 22), F8RC:$RA,bb:$DISP)>;
-
-def : Pat<(brcond (setogt F8RC:$RA, immFPZ), bb:$DISP),   
-      (COND_BRANCH_F (immBRCond 23), F8RC:$RA,bb:$DISP)>;
-def : Pat<(brcond (setugt F8RC:$RA, immFPZ), bb:$DISP),   
-      (COND_BRANCH_F (immBRCond 23), F8RC:$RA,bb:$DISP)>;
-
-def : Pat<(brcond (setole F8RC:$RA, immFPZ), bb:$DISP),   
-      (COND_BRANCH_F (immBRCond 24), F8RC:$RA,bb:$DISP)>;
-def : Pat<(brcond (setule F8RC:$RA, immFPZ), bb:$DISP),   
-      (COND_BRANCH_F (immBRCond 24), F8RC:$RA,bb:$DISP)>;
-
-def : Pat<(brcond (setolt F8RC:$RA, immFPZ), bb:$DISP),   
-      (COND_BRANCH_F (immBRCond 25), F8RC:$RA,bb:$DISP)>;
-def : Pat<(brcond (setult F8RC:$RA, immFPZ), bb:$DISP),   
-      (COND_BRANCH_F (immBRCond 25), F8RC:$RA,bb:$DISP)>;
-
-def : Pat<(brcond (setone F8RC:$RA, immFPZ), bb:$DISP),   
-      (COND_BRANCH_F (immBRCond 21), F8RC:$RA,bb:$DISP)>;
-def : Pat<(brcond (setune F8RC:$RA, immFPZ), bb:$DISP),   
-      (COND_BRANCH_F (immBRCond 21), F8RC:$RA,bb:$DISP)>;
-
-//End Branches
-
-//S_floating : IEEE Single
-//T_floating : IEEE Double
-
-//Unused instructions
-//Mnemonic Format Opcode Description
-//CALL_PAL Pcd 00 Trap to PALcode
-//ECB Mfc 18.E800 Evict cache block
-//EXCB Mfc 18.0400 Exception barrier
-//FETCH Mfc 18.8000 Prefetch data
-//FETCH_M Mfc 18.A000 Prefetch data, modify intent
-//LDQ_U Mem 0B Load unaligned quadword
-//MB Mfc 18.4000 Memory barrier
-//STQ_U Mem 0F Store unaligned quadword
-//TRAPB Mfc 18.0000 Trap barrier
-//WH64 Mfc 18.F800 Write hint  64 bytes
-//WMB Mfc 18.4400 Write memory barrier
-//MF_FPCR F-P 17.025 Move from FPCR
-//MT_FPCR F-P 17.024 Move to FPCR
-//There are in the Multimedia extensions, so let's not use them yet
-//def MAXSB8  : OForm<0x1C, 0x3E, "MAXSB8 $RA,$RB,$RC">; //Vector signed byte maximum
-//def MAXSW4 : OForm< 0x1C, 0x3F, "MAXSW4 $RA,$RB,$RC">; //Vector signed word maximum
-//def MAXUB8  : OForm<0x1C, 0x3C, "MAXUB8 $RA,$RB,$RC">; //Vector unsigned byte maximum
-//def MAXUW4 : OForm< 0x1C, 0x3D, "MAXUW4 $RA,$RB,$RC">; //Vector unsigned word maximum
-//def MINSB8 : OForm< 0x1C, 0x38, "MINSB8 $RA,$RB,$RC">; //Vector signed byte minimum
-//def MINSW4 : OForm< 0x1C, 0x39, "MINSW4 $RA,$RB,$RC">; //Vector signed word minimum
-//def MINUB8 : OForm< 0x1C, 0x3A, "MINUB8 $RA,$RB,$RC">; //Vector unsigned byte minimum
-//def MINUW4 : OForm< 0x1C, 0x3B, "MINUW4 $RA,$RB,$RC">; //Vector unsigned word minimum
-//def PERR : OForm< 0x1C, 0x31, "PERR $RA,$RB,$RC">; //Pixel error
-//def PKLB : OForm< 0x1C, 0x37, "PKLB $RA,$RB,$RC">; //Pack longwords to bytes
-//def PKWB  : OForm<0x1C, 0x36, "PKWB $RA,$RB,$RC">; //Pack words to bytes
-//def UNPKBL : OForm< 0x1C, 0x35, "UNPKBL $RA,$RB,$RC">; //Unpack bytes to longwords
-//def UNPKBW : OForm< 0x1C, 0x34, "UNPKBW $RA,$RB,$RC">; //Unpack bytes to words
-//CVTLQ F-P 17.010 Convert longword to quadword
-//CVTQL F-P 17.030 Convert quadword to longword
-
-
-//Constant handling
-
-def immConst2Part  : PatLeaf<(imm), [{
-  //true if imm fits in a LDAH LDA pair
-  int64_t val = (int64_t)N->getZExtValue();
-  return (val <= IMM_FULLHIGH  && val >= IMM_FULLLOW);
-}]>;
-def immConst2PartInt  : PatLeaf<(imm), [{
-  //true if imm fits in a LDAH LDA pair with zeroext
-  uint64_t uval = N->getZExtValue();
-  int32_t val32 = (int32_t)uval;
-  return ((uval >> 32) == 0 && //empty upper bits
-          val32 <= IMM_FULLHIGH);
-//          val32 >= IMM_FULLLOW  + IMM_LOW  * IMM_MULT); //Always True
-}], SExt32>;
-
-def : Pat<(i64 immConst2Part:$imm),
-          (LDA (LL16 immConst2Part:$imm), (LDAH (LH16 immConst2Part:$imm), R31))>;
-
-def : Pat<(i64 immSExt16:$imm),
-          (LDA immSExt16:$imm, R31)>;
-
-def : Pat<(i64 immSExt16int:$imm),
-          (ZAPNOTi (LDA (SExt16 immSExt16int:$imm), R31), 15)>;
-def : Pat<(i64 immConst2PartInt:$imm),
-          (ZAPNOTi (LDA (LL16 (i64 (SExt32 immConst2PartInt:$imm))),
-                        (LDAH (LH16 (i64 (SExt32 immConst2PartInt:$imm))), R31)), 15)>;
-
-
-//TODO: I want to just define these like this!
-//def : Pat<(i64 0),
-//          (R31)>;
-//def : Pat<(f64 0.0),
-//          (F31)>;
-//def : Pat<(f64 -0.0),
-//          (CPYSNT F31, F31)>;
-//def : Pat<(f32 0.0),
-//          (F31)>;
-//def : Pat<(f32 -0.0),
-//          (CPYSNS F31, F31)>;
-
-//Misc Patterns:
-
-def : Pat<(sext_inreg GPRC:$RB, i32),
-          (ADDLi GPRC:$RB, 0)>;
-
-def : Pat<(fabs F8RC:$RB),
-          (CPYST F31, F8RC:$RB)>;
-def : Pat<(fabs F4RC:$RB),
-          (CPYSS F31, F4RC:$RB)>;
-def : Pat<(fneg F8RC:$RB),
-          (CPYSNT F8RC:$RB, F8RC:$RB)>;
-def : Pat<(fneg F4RC:$RB),
-          (CPYSNS F4RC:$RB, F4RC:$RB)>;
-
-def : Pat<(fcopysign F4RC:$A, (fneg F4RC:$B)),
-          (CPYSNS F4RC:$B, F4RC:$A)>;
-def : Pat<(fcopysign F8RC:$A, (fneg F8RC:$B)),
-          (CPYSNT F8RC:$B, F8RC:$A)>;
-def : Pat<(fcopysign F4RC:$A, (fneg F8RC:$B)),
-          (CPYSNSt F8RC:$B, F4RC:$A)>;
-def : Pat<(fcopysign F8RC:$A, (fneg F4RC:$B)),
-          (CPYSNTs F4RC:$B, F8RC:$A)>;
-
-//Yes, signed multiply high is ugly
-def : Pat<(mulhs GPRC:$RA, GPRC:$RB),
-          (SUBQr (UMULHr GPRC:$RA, GPRC:$RB), (ADDQr (CMOVGEr GPRC:$RB, R31, GPRC:$RA), 
-                                                     (CMOVGEr GPRC:$RA, R31, GPRC:$RB)))>;
-
-//Stupid crazy arithmetic stuff:
-let AddedComplexity = 1 in {
-def : Pat<(mul GPRC:$RA, 5), (S4ADDQr GPRC:$RA, GPRC:$RA)>;
-def : Pat<(mul GPRC:$RA, 9), (S8ADDQr GPRC:$RA, GPRC:$RA)>;
-def : Pat<(mul GPRC:$RA, 3), (S4SUBQr GPRC:$RA, GPRC:$RA)>;
-def : Pat<(mul GPRC:$RA, 7), (S8SUBQr GPRC:$RA, GPRC:$RA)>;
-
-//slight tree expansion if we are multiplying near to a power of 2
-//n is above a power of 2
-def : Pat<(mul GPRC:$RA, immRem1:$imm), 
-          (ADDQr (SLr GPRC:$RA, (nearP2X immRem1:$imm)), GPRC:$RA)>;
-def : Pat<(mul GPRC:$RA, immRem2:$imm), 
-          (ADDQr (SLr GPRC:$RA, (nearP2X immRem2:$imm)), (ADDQr GPRC:$RA, GPRC:$RA))>;
-def : Pat<(mul GPRC:$RA, immRem3:$imm),
-          (ADDQr (SLr GPRC:$RA, (nearP2X immRem3:$imm)), (S4SUBQr GPRC:$RA, GPRC:$RA))>;
-def : Pat<(mul GPRC:$RA, immRem4:$imm),
-          (S4ADDQr GPRC:$RA, (SLr GPRC:$RA, (nearP2X immRem4:$imm)))>;
-def : Pat<(mul GPRC:$RA, immRem5:$imm),
-          (ADDQr (SLr GPRC:$RA, (nearP2X immRem5:$imm)), (S4ADDQr GPRC:$RA, GPRC:$RA))>;
-def : Pat<(mul GPRC:$RA, immRemP2:$imm),
-          (ADDQr (SLr GPRC:$RA, (nearP2X immRemP2:$imm)), (SLi GPRC:$RA, (nearP2RemX immRemP2:$imm)))>;
-
-//n is below a power of 2
-//FIXME: figure out why something is truncating the imm to 32bits
-// this will fix 2007-11-27-mulneg3
-//def : Pat<(mul GPRC:$RA, immRem1n:$imm), 
-//          (SUBQr (SLr GPRC:$RA, (nearP2X immRem1n:$imm)), GPRC:$RA)>;
-//def : Pat<(mul GPRC:$RA, immRem2n:$imm), 
-//          (SUBQr (SLr GPRC:$RA, (nearP2X immRem2n:$imm)), (ADDQr GPRC:$RA, GPRC:$RA))>;
-//def : Pat<(mul GPRC:$RA, immRem3n:$imm),
-//          (SUBQr (SLr GPRC:$RA, (nearP2X immRem3n:$imm)), (S4SUBQr GPRC:$RA, GPRC:$RA))>;
-//def : Pat<(mul GPRC:$RA, immRem4n:$imm),
-//          (SUBQr (SLr GPRC:$RA, (nearP2X immRem4n:$imm)), (SLi GPRC:$RA, 2))>;
-//def : Pat<(mul GPRC:$RA, immRem5n:$imm),
-//          (SUBQr (SLr GPRC:$RA, (nearP2X immRem5n:$imm)), (S4ADDQr GPRC:$RA, GPRC:$RA))>;
-//def : Pat<(mul GPRC:$RA, immRemP2n:$imm),
-//          (SUBQr (SLr GPRC:$RA, (nearP2X immRemP2n:$imm)), (SLi GPRC:$RA, (nearP2RemX immRemP2n:$imm)))>;
-} //Added complexity
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/AlphaLLRP.cpp
--- a/head/contrib/llvm/lib/Target/Alpha/AlphaLLRP.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,158 +0,0 @@
-//===-- AlphaLLRP.cpp - Alpha Load Load Replay Trap elimination pass. -- --===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// Here we check for potential replay traps introduced by the spiller
-// We also align some branch targets if we can do so for free.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "alpha-nops"
-#include "Alpha.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/ADT/SetOperations.h"
-#include "llvm/ADT/Statistic.h"
-#include "llvm/Support/CommandLine.h"
-using namespace llvm;
-
-STATISTIC(nopintro, "Number of nops inserted");
-STATISTIC(nopalign, "Number of nops inserted for alignment");
-
-namespace {
-  cl::opt<bool>
-  AlignAll("alpha-align-all", cl::Hidden,
-                   cl::desc("Align all blocks"));
-
-  struct AlphaLLRPPass : public MachineFunctionPass {
-    /// Target machine description which we query for reg. names, data
-    /// layout, etc.
-    ///
-    AlphaTargetMachine &TM;
-
-    static char ID;
-    AlphaLLRPPass(AlphaTargetMachine &tm) 
-      : MachineFunctionPass(ID), TM(tm) { }
-
-    virtual const char *getPassName() const {
-      return "Alpha NOP inserter";
-    }
-
-    bool runOnMachineFunction(MachineFunction &F) {
-      const TargetInstrInfo *TII = F.getTarget().getInstrInfo();
-      bool Changed = false;
-      MachineInstr* prev[3] = {0,0,0};
-      DebugLoc dl;
-      unsigned count = 0;
-      for (MachineFunction::iterator FI = F.begin(), FE = F.end();
-           FI != FE; ++FI) {
-        MachineBasicBlock& MBB = *FI;
-        bool ub = false;
-        for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
-          if (count%4 == 0)
-            prev[0] = prev[1] = prev[2] = 0; //Slots cleared at fetch boundary
-          ++count;
-          MachineInstr *MI = I++;
-          switch (MI->getOpcode()) {
-          case Alpha::LDQ:  case Alpha::LDL:
-          case Alpha::LDWU: case Alpha::LDBU:
-          case Alpha::LDT: case Alpha::LDS:
-          case Alpha::STQ:  case Alpha::STL:
-          case Alpha::STW:  case Alpha::STB:
-          case Alpha::STT: case Alpha::STS:
-           if (MI->getOperand(2).getReg() == Alpha::R30) {
-             if (prev[0] && 
-                 prev[0]->getOperand(2).getReg() == MI->getOperand(2).getReg()&&
-                 prev[0]->getOperand(1).getImm() == MI->getOperand(1).getImm()){
-               prev[0] = prev[1];
-               prev[1] = prev[2];
-               prev[2] = 0;
-               BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
-                 .addReg(Alpha::R31)
-                 .addReg(Alpha::R31); 
-               Changed = true; nopintro += 1;
-               count += 1;
-             } else if (prev[1] 
-                        && prev[1]->getOperand(2).getReg() == 
-                        MI->getOperand(2).getReg()
-                        && prev[1]->getOperand(1).getImm() == 
-                        MI->getOperand(1).getImm()) {
-               prev[0] = prev[2];
-               prev[1] = prev[2] = 0;
-               BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
-                 .addReg(Alpha::R31)
-                 .addReg(Alpha::R31); 
-               BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
-                 .addReg(Alpha::R31)
-                 .addReg(Alpha::R31);
-               Changed = true; nopintro += 2;
-               count += 2;
-             } else if (prev[2] 
-                        && prev[2]->getOperand(2).getReg() == 
-                        MI->getOperand(2).getReg()
-                        && prev[2]->getOperand(1).getImm() == 
-                        MI->getOperand(1).getImm()) {
-               prev[0] = prev[1] = prev[2] = 0;
-               BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
-                 .addReg(Alpha::R31).addReg(Alpha::R31);
-               BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
-                 .addReg(Alpha::R31).addReg(Alpha::R31);
-               BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
-                 .addReg(Alpha::R31).addReg(Alpha::R31);
-               Changed = true; nopintro += 3;
-               count += 3;
-             }
-             prev[0] = prev[1];
-             prev[1] = prev[2];
-             prev[2] = MI;
-             break;
-           }
-           prev[0] = prev[1];
-           prev[1] = prev[2];
-           prev[2] = 0;
-           break;
-          case Alpha::ALTENT:
-          case Alpha::MEMLABEL:
-          case Alpha::PCLABEL:
-            --count;
-            break;
-          case Alpha::BR:
-          case Alpha::JMP:
-            ub = true;
-            //fall through
-          default:
-            prev[0] = prev[1];
-            prev[1] = prev[2];
-            prev[2] = 0;
-            break;
-          }
-        }
-        if (ub || AlignAll) {
-          //we can align stuff for free at this point
-          while (count % 4) {
-            BuildMI(MBB, MBB.end(), dl, TII->get(Alpha::BISr), Alpha::R31)
-              .addReg(Alpha::R31).addReg(Alpha::R31);
-            ++count;
-            ++nopalign;
-            prev[0] = prev[1];
-            prev[1] = prev[2];
-            prev[2] = 0;
-          }
-        }
-      }
-      return Changed;
-    }
-  };
-  char AlphaLLRPPass::ID = 0;
-} // end of anonymous namespace
-
-FunctionPass *llvm::createAlphaLLRPPass(AlphaTargetMachine &tm) {
-  return new AlphaLLRPPass(tm);
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/AlphaMachineFunctionInfo.h
--- a/head/contrib/llvm/lib/Target/Alpha/AlphaMachineFunctionInfo.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,62 +0,0 @@
-//====- AlphaMachineFuctionInfo.h - Alpha machine function info -*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file declares Alpha-specific per-machine-function information.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef ALPHAMACHINEFUNCTIONINFO_H
-#define ALPHAMACHINEFUNCTIONINFO_H
-
-#include "llvm/CodeGen/MachineFunction.h"
-
-namespace llvm {
-
-/// AlphaMachineFunctionInfo - This class is derived from MachineFunction
-/// private Alpha target-specific information for each MachineFunction.
-class AlphaMachineFunctionInfo : public MachineFunctionInfo {
-  /// GlobalBaseReg - keeps track of the virtual register initialized for
-  /// use as the global base register. This is used for PIC in some PIC
-  /// relocation models.
-  unsigned GlobalBaseReg;
-
-  /// GlobalRetAddr = keeps track of the virtual register initialized for
-  /// the return address value.
-  unsigned GlobalRetAddr;
-
-  /// VarArgsOffset - What is the offset to the first vaarg
-  int VarArgsOffset;
-  /// VarArgsBase - What is the base FrameIndex
-  int VarArgsBase;
-
-public:
-  AlphaMachineFunctionInfo() : GlobalBaseReg(0), GlobalRetAddr(0),
-                               VarArgsOffset(0), VarArgsBase(0) {}
-
-  explicit AlphaMachineFunctionInfo(MachineFunction &MF) : GlobalBaseReg(0),
-                                                           GlobalRetAddr(0),
-                                                           VarArgsOffset(0),
-                                                           VarArgsBase(0) {}
-
-  unsigned getGlobalBaseReg() const { return GlobalBaseReg; }
-  void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; }
-
-  unsigned getGlobalRetAddr() const { return GlobalRetAddr; }
-  void setGlobalRetAddr(unsigned Reg) { GlobalRetAddr = Reg; }
-
-  int getVarArgsOffset() const { return VarArgsOffset; }
-  void setVarArgsOffset(int Offset) { VarArgsOffset = Offset; }
-
-  int getVarArgsBase() const { return VarArgsBase; }
-  void setVarArgsBase(int Base) { VarArgsBase = Base; }
-};
-
-} // End llvm namespace
-
-#endif
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
--- a/head/contrib/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,199 +0,0 @@
-//===- AlphaRegisterInfo.cpp - Alpha Register Information -------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains the Alpha implementation of the TargetRegisterInfo class.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "reginfo"
-#include "Alpha.h"
-#include "AlphaRegisterInfo.h"
-#include "llvm/Constants.h"
-#include "llvm/Type.h"
-#include "llvm/Function.h"
-#include "llvm/CodeGen/ValueTypes.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/Target/TargetFrameLowering.h"
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/Support/CommandLine.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/raw_ostream.h"
-#include "llvm/ADT/BitVector.h"
-#include "llvm/ADT/STLExtras.h"
-#include <cstdlib>
-
-#define GET_REGINFO_TARGET_DESC
-#include "AlphaGenRegisterInfo.inc"
-
-using namespace llvm;
-
-AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
-  : AlphaGenRegisterInfo(Alpha::R26), TII(tii) {
-}
-
-static long getUpper16(long l) {
-  long y = l / Alpha::IMM_MULT;
-  if (l % Alpha::IMM_MULT > Alpha::IMM_HIGH)
-    ++y;
-  return y;
-}
-
-static long getLower16(long l) {
-  long h = getUpper16(l);
-  return l - h * Alpha::IMM_MULT;
-}
-
-const unsigned* AlphaRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
-                                                                         const {
-  static const unsigned CalleeSavedRegs[] = {
-    Alpha::R9, Alpha::R10,
-    Alpha::R11, Alpha::R12,
-    Alpha::R13, Alpha::R14,
-    Alpha::F2, Alpha::F3,
-    Alpha::F4, Alpha::F5,
-    Alpha::F6, Alpha::F7,
-    Alpha::F8, Alpha::F9,  0
-  };
-  return CalleeSavedRegs;
-}
-
-BitVector AlphaRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
-  BitVector Reserved(getNumRegs());
-  Reserved.set(Alpha::R15);
-  Reserved.set(Alpha::R29);
-  Reserved.set(Alpha::R30);
-  Reserved.set(Alpha::R31);
-  return Reserved;
-}
-
-//===----------------------------------------------------------------------===//
-// Stack Frame Processing methods
-//===----------------------------------------------------------------------===//
-
-void AlphaRegisterInfo::
-eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
-                              MachineBasicBlock::iterator I) const {
-  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
-
-  if (TFI->hasFP(MF)) {
-    // If we have a frame pointer, turn the adjcallstackup instruction into a
-    // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
-    // <amt>'
-    MachineInstr *Old = I;
-    uint64_t Amount = Old->getOperand(0).getImm();
-    if (Amount != 0) {
-      // We need to keep the stack aligned properly.  To do this, we round the
-      // amount of space needed for the outgoing arguments up to the next
-      // alignment boundary.
-      unsigned Align = TFI->getStackAlignment();
-      Amount = (Amount+Align-1)/Align*Align;
-
-      MachineInstr *New;
-      if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) {
-        New=BuildMI(MF, Old->getDebugLoc(), TII.get(Alpha::LDA), Alpha::R30)
-          .addImm(-Amount).addReg(Alpha::R30);
-      } else {
-         assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP);
-         New=BuildMI(MF, Old->getDebugLoc(), TII.get(Alpha::LDA), Alpha::R30)
-          .addImm(Amount).addReg(Alpha::R30);
-      }
-
-      // Replace the pseudo instruction with a new instruction...
-      MBB.insert(I, New);
-    }
-  }
-
-  MBB.erase(I);
-}
-
-//Alpha has a slightly funny stack:
-//Args
-//<- incoming SP
-//fixed locals (and spills, callee saved, etc)
-//<- FP
-//variable locals
-//<- SP
-
-void
-AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
-                                       int SPAdj, RegScavenger *RS) const {
-  assert(SPAdj == 0 && "Unexpected");
-
-  unsigned i = 0;
-  MachineInstr &MI = *II;
-  MachineBasicBlock &MBB = *MI.getParent();
-  MachineFunction &MF = *MBB.getParent();
-  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
-
-  bool FP = TFI->hasFP(MF);
-
-  while (!MI.getOperand(i).isFI()) {
-    ++i;
-    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
-  }
-
-  int FrameIndex = MI.getOperand(i).getIndex();
-
-  // Add the base register of R30 (SP) or R15 (FP).
-  MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30, false);
-
-  // Now add the frame object offset to the offset from the virtual frame index.
-  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
-
-  DEBUG(errs() << "FI: " << FrameIndex << " Offset: " << Offset << "\n");
-
-  Offset += MF.getFrameInfo()->getStackSize();
-
-  DEBUG(errs() << "Corrected Offset " << Offset
-       << " for stack size: " << MF.getFrameInfo()->getStackSize() << "\n");
-
-  if (Offset > Alpha::IMM_HIGH || Offset < Alpha::IMM_LOW) {
-    DEBUG(errs() << "Unconditionally using R28 for evil purposes Offset: "
-          << Offset << "\n");
-    //so in this case, we need to use a temporary register, and move the
-    //original inst off the SP/FP
-    //fix up the old:
-    MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false);
-    MI.getOperand(i).ChangeToImmediate(getLower16(Offset));
-    //insert the new
-    MachineInstr* nMI=BuildMI(MF, MI.getDebugLoc(),
-                              TII.get(Alpha::LDAH), Alpha::R28)
-      .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
-    MBB.insert(II, nMI);
-  } else {
-    MI.getOperand(i).ChangeToImmediate(Offset);
-  }
-}
-
-unsigned AlphaRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
-  const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
-
-  return TFI->hasFP(MF) ? Alpha::R15 : Alpha::R30;
-}
-
-unsigned AlphaRegisterInfo::getEHExceptionRegister() const {
-  llvm_unreachable("What is the exception register");
-  return 0;
-}
-
-unsigned AlphaRegisterInfo::getEHHandlerRegister() const {
-  llvm_unreachable("What is the exception handler register");
-  return 0;
-}
-
-std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
-{
-  std::string s(AlphaRegDesc[reg].Name);
-  return s;
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/AlphaRegisterInfo.h
--- a/head/contrib/llvm/lib/Target/Alpha/AlphaRegisterInfo.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-//===- AlphaRegisterInfo.h - Alpha Register Information Impl ----*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains the Alpha implementation of the TargetRegisterInfo class.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef ALPHAREGISTERINFO_H
-#define ALPHAREGISTERINFO_H
-
-#include "llvm/Target/TargetRegisterInfo.h"
-
-#define GET_REGINFO_HEADER
-#include "AlphaGenRegisterInfo.inc"
-
-namespace llvm {
-
-class TargetInstrInfo;
-class Type;
-
-struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
-  const TargetInstrInfo &TII;
-
-  AlphaRegisterInfo(const TargetInstrInfo &tii);
-
-  /// Code Generation virtual methods...
-  const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
-
-  BitVector getReservedRegs(const MachineFunction &MF) const;
-
-  void eliminateCallFramePseudoInstr(MachineFunction &MF,
-                                     MachineBasicBlock &MBB,
-                                     MachineBasicBlock::iterator I) const;
-
-  void eliminateFrameIndex(MachineBasicBlock::iterator II,
-                           int SPAdj, RegScavenger *RS = NULL) const;
-
-  // Debug information queries.
-  unsigned getFrameRegister(const MachineFunction &MF) const;
-
-  // Exception handling queries.
-  unsigned getEHExceptionRegister() const;
-  unsigned getEHHandlerRegister() const;
-
-  static std::string getPrettyName(unsigned reg);
-};
-
-} // end namespace llvm
-
-#endif
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/AlphaRegisterInfo.td
--- a/head/contrib/llvm/lib/Target/Alpha/AlphaRegisterInfo.td	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,133 +0,0 @@
-//===- AlphaRegisterInfo.td - The Alpha Register File ------*- tablegen -*-===//
-// 
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-// 
-//===----------------------------------------------------------------------===//
-//
-// This file describes the Alpha register set.
-//
-//===----------------------------------------------------------------------===//
-
-class AlphaReg<string n> : Register<n> {
-  field bits<5> Num;
-  let Namespace = "Alpha";
-}
-
-// We identify all our registers with a 5-bit ID, for consistency's sake.
-
-// GPR - One of the 32 32-bit general-purpose registers
-class GPR<bits<5> num, string n> : AlphaReg<n> {
-  let Num = num;
-}
-
-// FPR - One of the 32 64-bit floating-point registers
-class FPR<bits<5> num, string n> : AlphaReg<n> {
-  let Num = num;
-}
-
-//#define FP    $15
-//#define RA    $26
-//#define PV    $27
-//#define GP    $29
-//#define SP    $30
-
-// General-purpose registers
-def R0  : GPR< 0,  "$0">, DwarfRegNum<[0]>;
-def R1  : GPR< 1,  "$1">, DwarfRegNum<[1]>;
-def R2  : GPR< 2,  "$2">, DwarfRegNum<[2]>;
-def R3  : GPR< 3,  "$3">, DwarfRegNum<[3]>;
-def R4  : GPR< 4,  "$4">, DwarfRegNum<[4]>;
-def R5  : GPR< 5,  "$5">, DwarfRegNum<[5]>;
-def R6  : GPR< 6,  "$6">, DwarfRegNum<[6]>;
-def R7  : GPR< 7,  "$7">, DwarfRegNum<[7]>;
-def R8  : GPR< 8,  "$8">, DwarfRegNum<[8]>;
-def R9  : GPR< 9,  "$9">, DwarfRegNum<[9]>;
-def R10 : GPR<10, "$10">, DwarfRegNum<[10]>;
-def R11 : GPR<11, "$11">, DwarfRegNum<[11]>;
-def R12 : GPR<12, "$12">, DwarfRegNum<[12]>;
-def R13 : GPR<13, "$13">, DwarfRegNum<[13]>;
-def R14 : GPR<14, "$14">, DwarfRegNum<[14]>;
-def R15 : GPR<15, "$15">, DwarfRegNum<[15]>;
-def R16 : GPR<16, "$16">, DwarfRegNum<[16]>;
-def R17 : GPR<17, "$17">, DwarfRegNum<[17]>;
-def R18 : GPR<18, "$18">, DwarfRegNum<[18]>;
-def R19 : GPR<19, "$19">, DwarfRegNum<[19]>;
-def R20 : GPR<20, "$20">, DwarfRegNum<[20]>;
-def R21 : GPR<21, "$21">, DwarfRegNum<[21]>;
-def R22 : GPR<22, "$22">, DwarfRegNum<[22]>;
-def R23 : GPR<23, "$23">, DwarfRegNum<[23]>;
-def R24 : GPR<24, "$24">, DwarfRegNum<[24]>;
-def R25 : GPR<25, "$25">, DwarfRegNum<[25]>;
-def R26 : GPR<26, "$26">, DwarfRegNum<[26]>;
-def R27 : GPR<27, "$27">, DwarfRegNum<[27]>;
-def R28 : GPR<28, "$28">, DwarfRegNum<[28]>;
-def R29 : GPR<29, "$29">, DwarfRegNum<[29]>;
-def R30 : GPR<30, "$30">, DwarfRegNum<[30]>;
-def R31 : GPR<31, "$31">, DwarfRegNum<[31]>;
-
-// Floating-point registers
-def F0  : FPR< 0,  "$f0">, DwarfRegNum<[33]>;
-def F1  : FPR< 1,  "$f1">, DwarfRegNum<[34]>;
-def F2  : FPR< 2,  "$f2">, DwarfRegNum<[35]>;
-def F3  : FPR< 3,  "$f3">, DwarfRegNum<[36]>;
-def F4  : FPR< 4,  "$f4">, DwarfRegNum<[37]>;
-def F5  : FPR< 5,  "$f5">, DwarfRegNum<[38]>;
-def F6  : FPR< 6,  "$f6">, DwarfRegNum<[39]>;
-def F7  : FPR< 7,  "$f7">, DwarfRegNum<[40]>;
-def F8  : FPR< 8,  "$f8">, DwarfRegNum<[41]>;
-def F9  : FPR< 9,  "$f9">, DwarfRegNum<[42]>;
-def F10 : FPR<10, "$f10">, DwarfRegNum<[43]>;
-def F11 : FPR<11, "$f11">, DwarfRegNum<[44]>;
-def F12 : FPR<12, "$f12">, DwarfRegNum<[45]>;
-def F13 : FPR<13, "$f13">, DwarfRegNum<[46]>;
-def F14 : FPR<14, "$f14">, DwarfRegNum<[47]>;
-def F15 : FPR<15, "$f15">, DwarfRegNum<[48]>;
-def F16 : FPR<16, "$f16">, DwarfRegNum<[49]>;
-def F17 : FPR<17, "$f17">, DwarfRegNum<[50]>;
-def F18 : FPR<18, "$f18">, DwarfRegNum<[51]>;
-def F19 : FPR<19, "$f19">, DwarfRegNum<[52]>;
-def F20 : FPR<20, "$f20">, DwarfRegNum<[53]>;
-def F21 : FPR<21, "$f21">, DwarfRegNum<[54]>;
-def F22 : FPR<22, "$f22">, DwarfRegNum<[55]>;
-def F23 : FPR<23, "$f23">, DwarfRegNum<[56]>;
-def F24 : FPR<24, "$f24">, DwarfRegNum<[57]>;
-def F25 : FPR<25, "$f25">, DwarfRegNum<[58]>;
-def F26 : FPR<26, "$f26">, DwarfRegNum<[59]>;
-def F27 : FPR<27, "$f27">, DwarfRegNum<[60]>;
-def F28 : FPR<28, "$f28">, DwarfRegNum<[61]>;
-def F29 : FPR<29, "$f29">, DwarfRegNum<[62]>;
-def F30 : FPR<30, "$f30">, DwarfRegNum<[63]>;
-def F31 : FPR<31, "$f31">, DwarfRegNum<[64]>;
-
-  // //#define FP    $15
-  // //#define RA    $26
-  // //#define PV    $27
-  // //#define GP    $29
-  // //#define SP    $30
-  // $28 is undefined after any and all calls
-
-/// Register classes
-def GPRC : RegisterClass<"Alpha", [i64], 64, (add
-     // Volatile
-     R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22,
-     R23, R24, R25, R28,
-     //Special meaning, but volatile
-     R27, //procedure address
-     R26, //return address
-     R29, //global offset table address
-     // Non-volatile
-     R9, R10, R11, R12, R13, R14,
-// Don't allocate 15, 30, 31
-     R15, R30, R31)>; //zero
-
-def F4RC : RegisterClass<"Alpha", [f32], 64, (add F0, F1,
-        F10, F11, F12, F13, F14, F15, F16, F17, F18, F19,
-        F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30,
-        // Saved:
-        F2, F3, F4, F5, F6, F7, F8, F9,
-        F31)>; //zero
-
-def F8RC : RegisterClass<"Alpha", [f64], 64, (add F4RC)>;
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/AlphaRelocations.h
--- a/head/contrib/llvm/lib/Target/Alpha/AlphaRelocations.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-//===- AlphaRelocations.h - Alpha Code Relocations --------------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines the Alpha target-specific relocation types.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef ALPHARELOCATIONS_H
-#define ALPHARELOCATIONS_H
-
-#include "llvm/CodeGen/MachineRelocation.h"
-
-namespace llvm {
-  namespace Alpha {
-    enum RelocationType {
-      reloc_literal,
-      reloc_gprellow,
-      reloc_gprelhigh,
-      reloc_gpdist,
-      reloc_bsr
-    };
-  }
-}
-
-#endif
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/AlphaSchedule.td
--- a/head/contrib/llvm/lib/Target/Alpha/AlphaSchedule.td	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,85 +0,0 @@
-//===- AlphaSchedule.td - Alpha Scheduling Definitions -----*- tablegen -*-===//
-// 
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-// 
-//===----------------------------------------------------------------------===//
-
-//This is table 2-2 from the 21264 compiler writers guide
-//modified some
-
-//Pipelines
-
-def L0   : FuncUnit;
-def L1   : FuncUnit;
-def FST0 : FuncUnit;
-def FST1 : FuncUnit;
-def U0   : FuncUnit;
-def U1   : FuncUnit;
-def FA   : FuncUnit;
-def FM   : FuncUnit;
-
-def s_ild   : InstrItinClass;
-def s_fld   : InstrItinClass;
-def s_ist   : InstrItinClass;
-def s_fst   : InstrItinClass;
-def s_lda   : InstrItinClass;
-def s_rpcc  : InstrItinClass;
-def s_rx    : InstrItinClass;
-def s_mxpr  : InstrItinClass;
-def s_icbr  : InstrItinClass;
-def s_ubr   : InstrItinClass;
-def s_jsr   : InstrItinClass;
-def s_iadd  : InstrItinClass;
-def s_ilog  : InstrItinClass;
-def s_ishf  : InstrItinClass;
-def s_cmov  : InstrItinClass;
-def s_imul  : InstrItinClass;
-def s_imisc : InstrItinClass;
-def s_fbr   : InstrItinClass;
-def s_fadd  : InstrItinClass;
-def s_fmul  : InstrItinClass;
-def s_fcmov : InstrItinClass;
-def s_fdivt : InstrItinClass;
-def s_fdivs : InstrItinClass;
-def s_fsqrts: InstrItinClass;
-def s_fsqrtt: InstrItinClass;
-def s_ftoi  : InstrItinClass;
-def s_itof  : InstrItinClass;
-def s_pseudo : InstrItinClass;
-
-//Table 2-4 Instruction Class Latency in Cycles
-//modified some
-
-def Alpha21264Itineraries : ProcessorItineraries<
-  [L0, L1, FST0, FST1, U0, U1, FA, FM], [], [
-  InstrItinData<s_ild    , [InstrStage<3, [L0, L1]>]>,
-  InstrItinData<s_fld    , [InstrStage<4, [L0, L1]>]>,
-  InstrItinData<s_ist    , [InstrStage<0, [L0, L1]>]>,
-  InstrItinData<s_fst    , [InstrStage<0, [FST0, FST1, L0, L1]>]>,
-  InstrItinData<s_lda    , [InstrStage<1, [L0, L1, U0, U1]>]>,
-  InstrItinData<s_rpcc   , [InstrStage<1, [L1]>]>,
-  InstrItinData<s_rx     , [InstrStage<1, [L1]>]>,
-  InstrItinData<s_mxpr   , [InstrStage<1, [L0, L1]>]>,
-  InstrItinData<s_icbr   , [InstrStage<0, [U0, U1]>]>,
-  InstrItinData<s_ubr    , [InstrStage<3, [U0, U1]>]>,
-  InstrItinData<s_jsr    , [InstrStage<3, [L0]>]>,
-  InstrItinData<s_iadd   , [InstrStage<1, [L0, U0, L1, U1]>]>,
-  InstrItinData<s_ilog   , [InstrStage<1, [L0, U0, L1, U1]>]>,
-  InstrItinData<s_ishf   , [InstrStage<1, [U0, U1]>]>,
-  InstrItinData<s_cmov   , [InstrStage<1, [L0, U0, L1, U1]>]>,
-  InstrItinData<s_imul   , [InstrStage<7, [U1]>]>,
-  InstrItinData<s_imisc  , [InstrStage<3, [U0]>]>,
-  InstrItinData<s_fbr    , [InstrStage<0, [FA]>]>,
-  InstrItinData<s_fadd   , [InstrStage<6, [FA]>]>,
-  InstrItinData<s_fmul   , [InstrStage<6, [FM]>]>,
-  InstrItinData<s_fcmov  , [InstrStage<6, [FA]>]>,
-  InstrItinData<s_fdivs  , [InstrStage<12, [FA]>]>,
-  InstrItinData<s_fdivt  , [InstrStage<15, [FA]>]>,
-  InstrItinData<s_fsqrts , [InstrStage<18, [FA]>]>,
-  InstrItinData<s_fsqrtt , [InstrStage<33, [FA]>]>,
-  InstrItinData<s_ftoi   , [InstrStage<3, [FST0, FST1, L0, L1]>]>,
-  InstrItinData<s_itof   , [InstrStage<4, [L0, L1]>]>
-]>;
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/AlphaSelectionDAGInfo.cpp
--- a/head/contrib/llvm/lib/Target/Alpha/AlphaSelectionDAGInfo.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,23 +0,0 @@
-//===-- AlphaSelectionDAGInfo.cpp - Alpha SelectionDAG Info ---------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements the AlphaSelectionDAGInfo class.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "alpha-selectiondag-info"
-#include "AlphaTargetMachine.h"
-using namespace llvm;
-
-AlphaSelectionDAGInfo::AlphaSelectionDAGInfo(const AlphaTargetMachine &TM)
-  : TargetSelectionDAGInfo(TM) {
-}
-
-AlphaSelectionDAGInfo::~AlphaSelectionDAGInfo() {
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/AlphaSelectionDAGInfo.h
--- a/head/contrib/llvm/lib/Target/Alpha/AlphaSelectionDAGInfo.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-//===-- AlphaSelectionDAGInfo.h - Alpha SelectionDAG Info -------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines the Alpha subclass for TargetSelectionDAGInfo.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef ALPHASELECTIONDAGINFO_H
-#define ALPHASELECTIONDAGINFO_H
-
-#include "llvm/Target/TargetSelectionDAGInfo.h"
-
-namespace llvm {
-
-class AlphaTargetMachine;
-
-class AlphaSelectionDAGInfo : public TargetSelectionDAGInfo {
-public:
-  explicit AlphaSelectionDAGInfo(const AlphaTargetMachine &TM);
-  ~AlphaSelectionDAGInfo();
-};
-
-}
-
-#endif
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/AlphaSubtarget.cpp
--- a/head/contrib/llvm/lib/Target/Alpha/AlphaSubtarget.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,35 +0,0 @@
-//===- AlphaSubtarget.cpp - Alpha Subtarget Information ---------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements the Alpha specific subclass of TargetSubtargetInfo.
-//
-//===----------------------------------------------------------------------===//
-
-#include "AlphaSubtarget.h"
-#include "Alpha.h"
-
-#define GET_SUBTARGETINFO_TARGET_DESC
-#define GET_SUBTARGETINFO_CTOR
-#include "AlphaGenSubtargetInfo.inc"
-
-using namespace llvm;
-
-AlphaSubtarget::AlphaSubtarget(const std::string &TT, const std::string &CPU,
-                               const std::string &FS)
-  : AlphaGenSubtargetInfo(TT, CPU, FS), HasCT(false) {
-  std::string CPUName = CPU;
-  if (CPUName.empty())
-    CPUName = "generic";
-
-  // Parse features string.
-  ParseSubtargetFeatures(CPUName, FS);
-
-  // Initialize scheduling itinerary for the specified CPU.
-  InstrItins = getInstrItineraryForCPU(CPUName);
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/AlphaSubtarget.h
--- a/head/contrib/llvm/lib/Target/Alpha/AlphaSubtarget.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,49 +0,0 @@
-//=====-- AlphaSubtarget.h - Define Subtarget for the Alpha --*- C++ -*--====//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file declares the Alpha specific subclass of TargetSubtargetInfo.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef ALPHASUBTARGET_H
-#define ALPHASUBTARGET_H
-
-#include "llvm/Target/TargetSubtargetInfo.h"
-#include "llvm/MC/MCInstrItineraries.h"
-#include <string>
-
-#define GET_SUBTARGETINFO_HEADER
-#include "AlphaGenSubtargetInfo.inc"
-
-namespace llvm {
-class StringRe;
-
-class AlphaSubtarget : public AlphaGenSubtargetInfo {
-protected:
-
-  bool HasCT;
-
-  InstrItineraryData InstrItins;
-
-public:
-  /// This constructor initializes the data members to match that
-  /// of the specified triple.
-  ///
-  AlphaSubtarget(const std::string &TT, const std::string &CPU,
-                 const std::string &FS);
-  
-  /// ParseSubtargetFeatures - Parses features string setting specified 
-  /// subtarget options.  Definition of function is auto generated by tblgen.
-  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
-
-  bool hasCT() const { return HasCT; }
-};
-} // End llvm namespace
-
-#endif
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/AlphaTargetMachine.cpp
--- a/head/contrib/llvm/lib/Target/Alpha/AlphaTargetMachine.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,51 +0,0 @@
-//===-- AlphaTargetMachine.cpp - Define TargetMachine for Alpha -----------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-//
-//===----------------------------------------------------------------------===//
-
-#include "Alpha.h"
-#include "AlphaTargetMachine.h"
-#include "llvm/PassManager.h"
-#include "llvm/Support/FormattedStream.h"
-#include "llvm/Support/TargetRegistry.h"
-using namespace llvm;
-
-extern "C" void LLVMInitializeAlphaTarget() { 
-  // Register the target.
-  RegisterTargetMachine<AlphaTargetMachine> X(TheAlphaTarget);
-}
-
-AlphaTargetMachine::AlphaTargetMachine(const Target &T, StringRef TT,
-                                       StringRef CPU, StringRef FS,
-                                       Reloc::Model RM, CodeModel::Model CM)
-  : LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
-    DataLayout("e-f128:128:128-n64"),
-    FrameLowering(Subtarget),
-    Subtarget(TT, CPU, FS),
-    TLInfo(*this),
-    TSInfo(*this) {
-}
-
-//===----------------------------------------------------------------------===//
-// Pass Pipeline Configuration
-//===----------------------------------------------------------------------===//
-
-bool AlphaTargetMachine::addInstSelector(PassManagerBase &PM,
-                                         CodeGenOpt::Level OptLevel) {
-  PM.add(createAlphaISelDag(*this));
-  return false;
-}
-bool AlphaTargetMachine::addPreEmitPass(PassManagerBase &PM,
-                                        CodeGenOpt::Level OptLevel) {
-  // Must run branch selection immediately preceding the asm printer
-  PM.add(createAlphaBranchSelectionPass());
-  PM.add(createAlphaLLRPPass(*this));
-  return false;
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/AlphaTargetMachine.h
--- a/head/contrib/llvm/lib/Target/Alpha/AlphaTargetMachine.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,66 +0,0 @@
-//===-- AlphaTargetMachine.h - Define TargetMachine for Alpha ---*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file declares the Alpha-specific subclass of TargetMachine.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef ALPHA_TARGETMACHINE_H
-#define ALPHA_TARGETMACHINE_H
-
-#include "AlphaInstrInfo.h"
-#include "AlphaISelLowering.h"
-#include "AlphaFrameLowering.h"
-#include "AlphaSelectionDAGInfo.h"
-#include "AlphaSubtarget.h"
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetData.h"
-#include "llvm/Target/TargetFrameLowering.h"
-
-namespace llvm {
-
-class GlobalValue;
-
-class AlphaTargetMachine : public LLVMTargetMachine {
-  const TargetData DataLayout;       // Calculates type size & alignment
-  AlphaInstrInfo InstrInfo;
-  AlphaFrameLowering FrameLowering;
-  AlphaSubtarget Subtarget;
-  AlphaTargetLowering TLInfo;
-  AlphaSelectionDAGInfo TSInfo;
-
-public:
-  AlphaTargetMachine(const Target &T, StringRef TT,
-                     StringRef CPU, StringRef FS,
-                     Reloc::Model RM, CodeModel::Model CM);
-
-  virtual const AlphaInstrInfo *getInstrInfo() const { return &InstrInfo; }
-  virtual const TargetFrameLowering  *getFrameLowering() const {
-    return &FrameLowering;
-  }
-  virtual const AlphaSubtarget   *getSubtargetImpl() const{ return &Subtarget; }
-  virtual const AlphaRegisterInfo *getRegisterInfo() const {
-    return &InstrInfo.getRegisterInfo();
-  }
-  virtual const AlphaTargetLowering* getTargetLowering() const {
-    return &TLInfo;
-  }
-  virtual const AlphaSelectionDAGInfo* getSelectionDAGInfo() const {
-    return &TSInfo;
-  }
-  virtual const TargetData       *getTargetData() const { return &DataLayout; }
-
-  // Pass Pipeline Configuration
-  virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
-  virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
-};
-
-} // end namespace llvm
-
-#endif
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/MCTargetDesc/AlphaMCAsmInfo.cpp
--- a/head/contrib/llvm/lib/Target/Alpha/MCTargetDesc/AlphaMCAsmInfo.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,23 +0,0 @@
-//===-- AlphaMCAsmInfo.cpp - Alpha asm properties ---------------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains the declarations of the AlphaMCAsmInfo properties.
-//
-//===----------------------------------------------------------------------===//
-
-#include "AlphaMCAsmInfo.h"
-using namespace llvm;
-
-AlphaMCAsmInfo::AlphaMCAsmInfo(const Target &T, StringRef TT) {
-  AlignmentIsInBytes = false;
-  PrivateGlobalPrefix = "$";
-  GPRel32Directive = ".gprel32";
-  WeakRefDirective = "\t.weak\t";
-  HasSetDirective = false;
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/MCTargetDesc/AlphaMCAsmInfo.h
--- a/head/contrib/llvm/lib/Target/Alpha/MCTargetDesc/AlphaMCAsmInfo.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,29 +0,0 @@
-//=====-- AlphaMCAsmInfo.h - Alpha asm properties -------------*- C++ -*--====//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains the declaration of the AlphaMCAsmInfo class.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef ALPHATARGETASMINFO_H
-#define ALPHATARGETASMINFO_H
-
-#include "llvm/ADT/StringRef.h"
-#include "llvm/MC/MCAsmInfo.h"
-
-namespace llvm {
-  class Target;
-
-  struct AlphaMCAsmInfo : public MCAsmInfo {
-    explicit AlphaMCAsmInfo(const Target &T, StringRef TT);
-  };
-
-} // namespace llvm
-
-#endif
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp
--- a/head/contrib/llvm/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,78 +0,0 @@
-//===-- AlphaMCTargetDesc.cpp - Alpha Target Descriptions -------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file provides Alpha specific target descriptions.
-//
-//===----------------------------------------------------------------------===//
-
-#include "AlphaMCTargetDesc.h"
-#include "AlphaMCAsmInfo.h"
-#include "llvm/MC/MCCodeGenInfo.h"
-#include "llvm/MC/MCInstrInfo.h"
-#include "llvm/MC/MCRegisterInfo.h"
-#include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/Support/TargetRegistry.h"
-
-#define GET_INSTRINFO_MC_DESC
-#include "AlphaGenInstrInfo.inc"
-
-#define GET_SUBTARGETINFO_MC_DESC
-#include "AlphaGenSubtargetInfo.inc"
-
-#define GET_REGINFO_MC_DESC
-#include "AlphaGenRegisterInfo.inc"
-
-using namespace llvm;
-
-
-static MCInstrInfo *createAlphaMCInstrInfo() {
-  MCInstrInfo *X = new MCInstrInfo();
-  InitAlphaMCInstrInfo(X);
-  return X;
-}
-
-static MCRegisterInfo *createAlphaMCRegisterInfo(StringRef TT) {
-  MCRegisterInfo *X = new MCRegisterInfo();
-  InitAlphaMCRegisterInfo(X, Alpha::R26);
-  return X;
-}
-
-static MCSubtargetInfo *createAlphaMCSubtargetInfo(StringRef TT, StringRef CPU,
-                                                   StringRef FS) {
-  MCSubtargetInfo *X = new MCSubtargetInfo();
-  InitAlphaMCSubtargetInfo(X, TT, CPU, FS);
-  return X;
-}
-
-static MCCodeGenInfo *createAlphaMCCodeGenInfo(StringRef TT, Reloc::Model RM,
-                                               CodeModel::Model CM) {
-  MCCodeGenInfo *X = new MCCodeGenInfo();
-  X->InitMCCodeGenInfo(Reloc::PIC_, CM);
-  return X;
-}
-
-// Force static initialization.
-extern "C" void LLVMInitializeAlphaTargetMC() {
-  // Register the MC asm info.
-  RegisterMCAsmInfo<AlphaMCAsmInfo> X(TheAlphaTarget);
-
-  // Register the MC codegen info.
-  TargetRegistry::RegisterMCCodeGenInfo(TheAlphaTarget,
-                                        createAlphaMCCodeGenInfo);
-
-  // Register the MC instruction info.
-  TargetRegistry::RegisterMCInstrInfo(TheAlphaTarget, createAlphaMCInstrInfo);
-
-  // Register the MC register info.
-  TargetRegistry::RegisterMCRegInfo(TheAlphaTarget, createAlphaMCRegisterInfo);
-
-  // Register the MC subtarget info.
-  TargetRegistry::RegisterMCSubtargetInfo(TheAlphaTarget,
-                                          createAlphaMCSubtargetInfo);
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.h
--- a/head/contrib/llvm/lib/Target/Alpha/MCTargetDesc/AlphaMCTargetDesc.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,40 +0,0 @@
-//===-- AlphaMCTargetDesc.h - Alpha Target Descriptions ---------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file provides Alpha specific target descriptions.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef ALPHAMCTARGETDESC_H
-#define ALPHAMCTARGETDESC_H
-
-namespace llvm {
-class MCSubtargetInfo;
-class Target;
-class StringRef;
-
-extern Target TheAlphaTarget;
-
-} // End llvm namespace
-
-// Defines symbolic names for Alpha registers.  This defines a mapping from
-// register name to register number.
-//
-#define GET_REGINFO_ENUM
-#include "AlphaGenRegisterInfo.inc"
-
-// Defines symbolic names for the Alpha instructions.
-//
-#define GET_INSTRINFO_ENUM
-#include "AlphaGenInstrInfo.inc"
-
-#define GET_SUBTARGETINFO_ENUM
-#include "AlphaGenSubtargetInfo.inc"
-
-#endif
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Alpha/TargetInfo/AlphaTargetInfo.cpp
--- a/head/contrib/llvm/lib/Target/Alpha/TargetInfo/AlphaTargetInfo.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,20 +0,0 @@
-//===-- AlphaTargetInfo.cpp - Alpha Target Implementation -----------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#include "Alpha.h"
-#include "llvm/Module.h"
-#include "llvm/Support/TargetRegistry.h"
-using namespace llvm;
-
-llvm::Target llvm::TheAlphaTarget;
-
-extern "C" void LLVMInitializeAlphaTargetInfo() { 
-  RegisterTarget<Triple::alpha, /*HasJIT=*/true>
-    X(TheAlphaTarget, "alpha", "Alpha [experimental]");
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Blackfin/Blackfin.h
--- a/head/contrib/llvm/lib/Target/Blackfin/Blackfin.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-//=== Blackfin.h - Top-level interface for Blackfin backend -----*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains the entry points for global functions defined in the LLVM
-// Blackfin back-end.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef TARGET_BLACKFIN_H
-#define TARGET_BLACKFIN_H
-
-#include "MCTargetDesc/BlackfinMCTargetDesc.h"
-#include "llvm/Target/TargetMachine.h"
-
-namespace llvm {
-
-  class FunctionPass;
-  class BlackfinTargetMachine;
-
-  FunctionPass *createBlackfinISelDag(BlackfinTargetMachine &TM,
-                                      CodeGenOpt::Level OptLevel);
-
-} // end namespace llvm
-
-#endif
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Blackfin/Blackfin.td
--- a/head/contrib/llvm/lib/Target/Blackfin/Blackfin.td	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,202 +0,0 @@
-//===- Blackfin.td - Describe the Blackfin Target Machine --*- tablegen -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-//
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// Target-independent interfaces which we are implementing
-//===----------------------------------------------------------------------===//
-
-include "llvm/Target/Target.td"
-
-//===----------------------------------------------------------------------===//
-// Blackfin Subtarget features.
-//===----------------------------------------------------------------------===//
-
-def FeatureSDRAM : SubtargetFeature<"sdram", "sdram", "true",
-    "Build for SDRAM">;
-
-def FeatureICPLB : SubtargetFeature<"icplb", "icplb", "true",
-    "Assume instruction cache lookaside buffers are enabled at runtime">;
-
-//===----------------------------------------------------------------------===//
-// Bugs in the silicon becomes workarounds in the compiler.
-// See http://www.analog.com/ for the full list of IC anomalies.
-//===----------------------------------------------------------------------===//
-
-def WA_MI_SHIFT : SubtargetFeature<"mi-shift-anomaly","wa_mi_shift", "true",
-    "Work around 05000074 - "
-    "Multi-Issue Instruction with dsp32shiftimm and P-reg Store">;
-
-def WA_CSYNC : SubtargetFeature<"csync-anomaly","wa_csync", "true",
-    "Work around 05000244 - "
-    "If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control">;
-
-def WA_SPECLD : SubtargetFeature<"specld-anomaly","wa_specld", "true",
-    "Work around 05000245 - "
-    "Access in the Shadow of a Conditional Branch">;
-
-def WA_HWLOOP : SubtargetFeature<"hwloop-anomaly","wa_hwloop", "true",
-    "Work around 05000257 - "
-    "Interrupt/Exception During Short Hardware Loop">;
-
-def WA_MMR_STALL : SubtargetFeature<"mmr-stall-anomaly","wa_mmr_stall", "true",
-    "Work around 05000283 - "
-    "System MMR Write Is Stalled Indefinitely when Killed">;
-
-def WA_LCREGS : SubtargetFeature<"lcregs-anomaly","wa_lcregs", "true",
-    "Work around 05000312 - "
-    "SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted">;
-
-def WA_KILLED_MMR : SubtargetFeature<"killed-mmr-anomaly",
-                                     "wa_killed_mmr", "true",
-    "Work around 05000315 - "
-    "Killed System MMR Write Completes Erroneously on Next System MMR Access">;
-
-def WA_RETS : SubtargetFeature<"rets-anomaly", "wa_rets", "true",
-    "Work around 05000371 - "
-    "Possible RETS Register Corruption when Subroutine Is under 5 Cycles">;
-
-def WA_IND_CALL : SubtargetFeature<"ind-call-anomaly", "wa_ind_call", "true",
-    "Work around 05000426 - "
-    "Speculative Fetches of Indirect-Pointer Instructions">;
-
-//===----------------------------------------------------------------------===//
-// Register File, Calling Conv, Instruction Descriptions
-//===----------------------------------------------------------------------===//
-
-include "BlackfinRegisterInfo.td"
-include "BlackfinCallingConv.td"
-include "BlackfinIntrinsics.td"
-include "BlackfinInstrInfo.td"
-
-def BlackfinInstrInfo : InstrInfo {}
-
-//===----------------------------------------------------------------------===//
-// Blackfin processors supported.
-//===----------------------------------------------------------------------===//
-
-class Proc<string Name, string Suffix, list<SubtargetFeature> Features>
- : Processor<!strconcat(Name, Suffix), NoItineraries, Features>;
-
-def : Proc<"generic", "", []>;
-
-multiclass Core<string Name,string Suffix,
-                list<SubtargetFeature> Features> {
-  def : Proc<Name, Suffix, Features>;
-  def : Proc<Name, "", Features>;
-  def : Proc<Name, "-none", []>;
-}
-
-multiclass CoreEdinburgh<string Name>
-      : Core<Name, "-0.6", [WA_MI_SHIFT, WA_SPECLD, WA_LCREGS]> {
-  def : Proc<Name, "-0.5",
-        [WA_MI_SHIFT, WA_SPECLD, WA_MMR_STALL, WA_LCREGS, WA_KILLED_MMR,
-         WA_RETS]>;
-  def : Proc<Name, "-0.4",
-        [WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
-         WA_KILLED_MMR, WA_RETS]>;
-  def : Proc<Name, "-0.3",
-        [WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
-         WA_KILLED_MMR, WA_RETS]>;
-  def : Proc<Name, "-any",
-        [WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
-         WA_KILLED_MMR, WA_RETS]>;
-}
-multiclass CoreBraemar<string Name>
-       : Core<Name, "-0.3",
-         [WA_MI_SHIFT, WA_SPECLD, WA_LCREGS, WA_RETS, WA_IND_CALL]> {
-  def  : Proc<Name, "-0.2",
-         [WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
-          WA_KILLED_MMR, WA_RETS, WA_IND_CALL]>;
-  def  : Proc<Name, "-any",
-         [WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
-          WA_KILLED_MMR, WA_RETS, WA_IND_CALL]>;
-}
-multiclass CoreStirling<string Name>
-      : Core<Name, "-0.5", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]> {
-  def : Proc<Name, "-0.4",
-        [WA_MI_SHIFT, WA_SPECLD, WA_LCREGS, WA_RETS, WA_IND_CALL]>;
-  def : Proc<Name, "-0.3",
-        [WA_MI_SHIFT, WA_SPECLD, WA_MMR_STALL, WA_LCREGS, WA_KILLED_MMR,
-         WA_RETS, WA_IND_CALL]>;
-  def : Proc<Name, "-any",
-        [WA_MI_SHIFT, WA_SPECLD, WA_MMR_STALL, WA_LCREGS, WA_KILLED_MMR,
-         WA_RETS, WA_IND_CALL]>;
-}
-multiclass CoreMoab<string Name>
-      : Core<Name, "-0.3", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]> {
-  def : Proc<Name, "-0.2", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]>;
-  def : Proc<Name, "-0.1", [WA_MI_SHIFT, WA_SPECLD, WA_RETS, WA_IND_CALL]>;
-  def : Proc<Name, "-0.0",
-        [WA_MI_SHIFT, WA_SPECLD, WA_LCREGS, WA_RETS, WA_IND_CALL]>;
-  def : Proc<Name, "-any",
-        [WA_MI_SHIFT, WA_SPECLD, WA_LCREGS, WA_RETS, WA_IND_CALL]>;
-}
-multiclass CoreTeton<string Name>
-      : Core<Name, "-0.5",
-        [WA_MI_SHIFT, WA_SPECLD, WA_MMR_STALL, WA_LCREGS, WA_KILLED_MMR,
-         WA_RETS, WA_IND_CALL]> {
-  def : Proc<Name, "-0.3",
-        [WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
-         WA_KILLED_MMR, WA_RETS, WA_IND_CALL]>;
-  def : Proc<Name, "-any",
-        [WA_MI_SHIFT, WA_CSYNC, WA_SPECLD, WA_HWLOOP, WA_MMR_STALL, WA_LCREGS,
-         WA_KILLED_MMR, WA_RETS, WA_IND_CALL]>;
-}
-multiclass CoreKookaburra<string Name>
-      : Core<Name, "-0.2", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]> {
-  def : Proc<Name, "-0.1", [WA_MI_SHIFT, WA_SPECLD, WA_RETS, WA_IND_CALL]>;
-  def : Proc<Name, "-0.0", [WA_MI_SHIFT, WA_SPECLD, WA_RETS, WA_IND_CALL]>;
-  def : Proc<Name, "-any", [WA_MI_SHIFT, WA_SPECLD, WA_RETS, WA_IND_CALL]>;
-}
-multiclass CoreMockingbird<string Name>
-      : Core<Name, "-0.1", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]> {
-  def : Proc<Name, "-0.0", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]>;
-  def : Proc<Name, "-any", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]>;
-}
-multiclass CoreBrodie<string Name>
-      : Core<Name, "-0.1", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]> {
-  def : Proc<Name, "-0.0", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]>;
-  def : Proc<Name, "-any", [WA_MI_SHIFT, WA_SPECLD, WA_IND_CALL]>;
-}
-
-defm BF512 : CoreBrodie<"bf512">;
-defm BF514 : CoreBrodie<"bf514">;
-defm BF516 : CoreBrodie<"bf516">;
-defm BF518 : CoreBrodie<"bf518">;
-defm BF522 : CoreMockingbird<"bf522">;
-defm BF523 : CoreKookaburra<"bf523">;
-defm BF524 : CoreMockingbird<"bf524">;
-defm BF525 : CoreKookaburra<"bf525">;
-defm BF526 : CoreMockingbird<"bf526">;
-defm BF527 : CoreKookaburra<"bf527">;
-defm BF531 : CoreEdinburgh<"bf531">;
-defm BF532 : CoreEdinburgh<"bf532">;
-defm BF533 : CoreEdinburgh<"bf533">;
-defm BF534 : CoreBraemar<"bf534">;
-defm BF536 : CoreBraemar<"bf536">;
-defm BF537 : CoreBraemar<"bf537">;
-defm BF538 : CoreStirling<"bf538">;
-defm BF539 : CoreStirling<"bf539">;
-defm BF542 : CoreMoab<"bf542">;
-defm BF544 : CoreMoab<"bf544">;
-defm BF548 : CoreMoab<"bf548">;
-defm BF549 : CoreMoab<"bf549">;
-defm BF561 : CoreTeton<"bf561">;
-
-//===----------------------------------------------------------------------===//
-// Declare the target which we are implementing
-//===----------------------------------------------------------------------===//
-
-def Blackfin : Target {
-  // Pull in Instruction Info:
-  let InstructionSet = BlackfinInstrInfo;
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Blackfin/BlackfinAsmPrinter.cpp
--- a/head/contrib/llvm/lib/Target/Blackfin/BlackfinAsmPrinter.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,156 +0,0 @@
-//===-- BlackfinAsmPrinter.cpp - Blackfin LLVM assembly writer ------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains a printer that converts from our internal representation
-// of machine-dependent LLVM code to GAS-format BLACKFIN assembly language.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "asm-printer"
-#include "Blackfin.h"
-#include "BlackfinInstrInfo.h"
-#include "llvm/Constants.h"
-#include "llvm/DerivedTypes.h"
-#include "llvm/Module.h"
-#include "llvm/CodeGen/AsmPrinter.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineConstantPool.h"
-#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/MC/MCStreamer.h"
-#include "llvm/MC/MCAsmInfo.h"
-#include "llvm/MC/MCContext.h"
-#include "llvm/MC/MCSymbol.h"
-#include "llvm/Target/Mangler.h"
-#include "llvm/Target/TargetData.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
-#include "llvm/ADT/SmallString.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/TargetRegistry.h"
-#include "llvm/Support/raw_ostream.h"
-using namespace llvm;
-
-namespace {
-  class BlackfinAsmPrinter : public AsmPrinter {
-  public:
-    BlackfinAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
-      : AsmPrinter(TM, Streamer) {}
-
-    virtual const char *getPassName() const {
-      return "Blackfin Assembly Printer";
-    }
-
-    void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
-    void printMemoryOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
-    void printInstruction(const MachineInstr *MI, raw_ostream &O);// autogen'd.
-    static const char *getRegisterName(unsigned RegNo);
-
-    void EmitInstruction(const MachineInstr *MI) {
-      SmallString<128> Str;
-      raw_svector_ostream OS(Str);
-      printInstruction(MI, OS);
-      OutStreamer.EmitRawText(OS.str());
-    }
-    bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
-                         unsigned AsmVariant, const char *ExtraCode,
-                         raw_ostream &O);
-    bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
-                               unsigned AsmVariant, const char *ExtraCode,
-                               raw_ostream &O);
-  };
-} // end of anonymous namespace
-
-#include "BlackfinGenAsmWriter.inc"
-
-extern "C" void LLVMInitializeBlackfinAsmPrinter() {
-  RegisterAsmPrinter<BlackfinAsmPrinter> X(TheBlackfinTarget);
-}
-
-void BlackfinAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
-                                      raw_ostream &O) {
-  const MachineOperand &MO = MI->getOperand(opNum);
-  switch (MO.getType()) {
-  case MachineOperand::MO_Register:
-    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
-           "Virtual registers should be already mapped!");
-    O << getRegisterName(MO.getReg());
-    break;
-
-  case MachineOperand::MO_Immediate:
-    O << MO.getImm();
-    break;
-  case MachineOperand::MO_MachineBasicBlock:
-    O << *MO.getMBB()->getSymbol();
-    return;
-  case MachineOperand::MO_GlobalAddress:
-    O << *Mang->getSymbol(MO.getGlobal());
-    printOffset(MO.getOffset(), O);
-    break;
-  case MachineOperand::MO_ExternalSymbol:
-    O << *GetExternalSymbolSymbol(MO.getSymbolName());
-    break;
-  case MachineOperand::MO_ConstantPoolIndex:
-    O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << "_"
-      << MO.getIndex();
-    break;
-  case MachineOperand::MO_JumpTableIndex:
-    O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
-      << '_' << MO.getIndex();
-    break;
-  default:
-    llvm_unreachable("<unknown operand type>");
-    break;
-  }
-}
-
-void BlackfinAsmPrinter::printMemoryOperand(const MachineInstr *MI, int opNum,
-                                            raw_ostream &O) {
-  printOperand(MI, opNum, O);
-
-  if (MI->getOperand(opNum+1).isImm() && MI->getOperand(opNum+1).getImm() == 0)
-    return;
-
-  O << " + ";
-  printOperand(MI, opNum+1, O);
-}
-
-/// PrintAsmOperand - Print out an operand for an inline asm expression.
-///
-bool BlackfinAsmPrinter::PrintAsmOperand(const MachineInstr *MI,
-                                         unsigned OpNo, unsigned AsmVariant,
-                                         const char *ExtraCode,
-                                         raw_ostream &O) {
-  if (ExtraCode && ExtraCode[0]) {
-    if (ExtraCode[1] != 0) return true; // Unknown modifier.
-
-    switch (ExtraCode[0]) {
-    default: return true;  // Unknown modifier.
-    case 'r':
-      break;
-    }
-  }
-
-  printOperand(MI, OpNo, O);
-
-  return false;
-}
-
-bool BlackfinAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
-                                               unsigned OpNo,
-                                               unsigned AsmVariant,
-                                               const char *ExtraCode,
-                                               raw_ostream &O) {
-  if (ExtraCode && ExtraCode[0])
-    return true;  // Unknown modifier
-
-  O << '[';
-  printOperand(MI, OpNo, O);
-  O << ']';
-
-  return false;
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Blackfin/BlackfinCallingConv.td
--- a/head/contrib/llvm/lib/Target/Blackfin/BlackfinCallingConv.td	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,30 +0,0 @@
-//===--- BlackfinCallingConv.td - Calling Conventions ------*- tablegen -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This describes the calling conventions for the Blackfin architectures.
-//
-//===----------------------------------------------------------------------===//
-
-// Blackfin C Calling convention.
-def CC_Blackfin : CallingConv<[
-  CCIfType<[i16], CCPromoteToType<i32>>,
-  CCIfSRet<CCAssignToReg<[P0]>>,
-  CCAssignToReg<[R0, R1, R2]>,
-  CCAssignToStack<4, 4>
-]>;
-
-//===----------------------------------------------------------------------===//
-// Return Value Calling Conventions
-//===----------------------------------------------------------------------===//
-
-// Blackfin C return-value convention.
-def RetCC_Blackfin : CallingConv<[
-  CCIfType<[i16], CCPromoteToType<i32>>,
-  CCAssignToReg<[R0, R1]>
-]>;
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Blackfin/BlackfinFrameLowering.cpp
--- a/head/contrib/llvm/lib/Target/Blackfin/BlackfinFrameLowering.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,130 +0,0 @@
-//====- BlackfinFrameLowering.cpp - Blackfin Frame Information --*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains the Blackfin implementation of TargetFrameLowering class.
-//
-//===----------------------------------------------------------------------===//
-
-#include "BlackfinFrameLowering.h"
-#include "BlackfinInstrInfo.h"
-#include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/RegisterScavenging.h"
-#include "llvm/Target/TargetOptions.h"
-
-using namespace llvm;
-
-
-// hasFP - Return true if the specified function should have a dedicated frame
-// pointer register.  This is true if the function has variable sized allocas or
-// if frame pointer elimination is disabled.
-bool BlackfinFrameLowering::hasFP(const MachineFunction &MF) const {
-  const MachineFrameInfo *MFI = MF.getFrameInfo();
-  return DisableFramePointerElim(MF) ||
-    MFI->adjustsStack() || MFI->hasVarSizedObjects();
-}
-
-// Always reserve a call frame. We dont have enough registers to adjust SP.
-bool BlackfinFrameLowering::
-hasReservedCallFrame(const MachineFunction &MF) const {
-  return true;
-}
-
-// Emit a prologue that sets up a stack frame.
-// On function entry, R0-R2 and P0 may hold arguments.
-// R3, P1, and P2 may be used as scratch registers
-void BlackfinFrameLowering::emitPrologue(MachineFunction &MF) const {
-  MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
-  MachineBasicBlock::iterator MBBI = MBB.begin();
-  MachineFrameInfo *MFI = MF.getFrameInfo();
-  const BlackfinRegisterInfo *RegInfo =
-    static_cast<const BlackfinRegisterInfo*>(MF.getTarget().getRegisterInfo());
-  const BlackfinInstrInfo &TII =
-    *static_cast<const BlackfinInstrInfo*>(MF.getTarget().getInstrInfo());
-
-  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
-
-  int FrameSize = MFI->getStackSize();
-  if (FrameSize%4) {
-    FrameSize = (FrameSize+3) & ~3;
-    MFI->setStackSize(FrameSize);
-  }
-
-  if (!hasFP(MF)) {
-    assert(!MFI->adjustsStack() &&
-           "FP elimination on a non-leaf function is not supported");
-    RegInfo->adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, -FrameSize);
-    return;
-  }
-
-  // emit a LINK instruction
-  if (FrameSize <= 0x3ffff) {
-    BuildMI(MBB, MBBI, dl, TII.get(BF::LINK)).addImm(FrameSize);
-    return;
-  }
-
-  // Frame is too big, do a manual LINK:
-  // [--SP] = RETS;
-  // [--SP] = FP;
-  // FP = SP;
-  // P1 = -FrameSize;
-  // SP = SP + P1;
-  BuildMI(MBB, MBBI, dl, TII.get(BF::PUSH))
-    .addReg(BF::RETS, RegState::Kill);
-  BuildMI(MBB, MBBI, dl, TII.get(BF::PUSH))
-    .addReg(BF::FP, RegState::Kill);
-  BuildMI(MBB, MBBI, dl, TII.get(BF::MOVE), BF::FP)
-    .addReg(BF::SP);
-  RegInfo->loadConstant(MBB, MBBI, dl, BF::P1, -FrameSize);
-  BuildMI(MBB, MBBI, dl, TII.get(BF::ADDpp), BF::SP)
-    .addReg(BF::SP, RegState::Kill)
-    .addReg(BF::P1, RegState::Kill);
-
-}
-
-void BlackfinFrameLowering::emitEpilogue(MachineFunction &MF,
-                                     MachineBasicBlock &MBB) const {
-  MachineFrameInfo *MFI = MF.getFrameInfo();
-  const BlackfinRegisterInfo *RegInfo =
-    static_cast<const BlackfinRegisterInfo*>(MF.getTarget().getRegisterInfo());
-  const BlackfinInstrInfo &TII =
-    *static_cast<const BlackfinInstrInfo*>(MF.getTarget().getInstrInfo());
-  MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
-  DebugLoc dl = MBBI->getDebugLoc();
-
-  int FrameSize = MFI->getStackSize();
-  assert(FrameSize%4 == 0 && "Misaligned frame size");
-
-  if (!hasFP(MF)) {
-    assert(!MFI->adjustsStack() &&
-           "FP elimination on a non-leaf function is not supported");
-    RegInfo->adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, FrameSize);
-    return;
-  }
-
-  // emit an UNLINK instruction
-  BuildMI(MBB, MBBI, dl, TII.get(BF::UNLINK));
-}
-
-void BlackfinFrameLowering::
-processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
-                                     RegScavenger *RS) const {
-  MachineFrameInfo *MFI = MF.getFrameInfo();
-  const BlackfinRegisterInfo *RegInfo =
-    static_cast<const BlackfinRegisterInfo*>(MF.getTarget().getRegisterInfo());
-  const TargetRegisterClass *RC = BF::DPRegisterClass;
-
-  if (RegInfo->requiresRegisterScavenging(MF)) {
-    // Reserve a slot close to SP or frame pointer.
-    RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
-                                                       RC->getAlignment(),
-                                                       false));
-  }
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Blackfin/BlackfinFrameLowering.h
--- a/head/contrib/llvm/lib/Target/Blackfin/BlackfinFrameLowering.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,47 +0,0 @@
-//=- BlackfinFrameLowering.h - Define frame lowering for Blackfin -*- C++ -*-=//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-//
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef BLACKFIN_FRAMEINFO_H
-#define BLACKFIN_FRAMEINFO_H
-
-#include "Blackfin.h"
-#include "BlackfinSubtarget.h"
-#include "llvm/Target/TargetFrameLowering.h"
-
-namespace llvm {
-  class BlackfinSubtarget;
-
-class BlackfinFrameLowering : public TargetFrameLowering {
-protected:
-  const BlackfinSubtarget &STI;
-
-public:
-  explicit BlackfinFrameLowering(const BlackfinSubtarget &sti)
-    : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 4, 0), STI(sti) {
-  }
-
-  /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
-  /// the function.
-  void emitPrologue(MachineFunction &MF) const;
-  void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
-
-  bool hasFP(const MachineFunction &MF) const;
-  bool hasReservedCallFrame(const MachineFunction &MF) const;
-
-  void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
-                                            RegScavenger *RS) const;
-};
-
-} // End llvm namespace
-
-#endif
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp
--- a/head/contrib/llvm/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,180 +0,0 @@
-//===- BlackfinISelDAGToDAG.cpp - A dag to dag inst selector for Blackfin -===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines an instruction selector for the Blackfin target.
-//
-//===----------------------------------------------------------------------===//
-
-#include "Blackfin.h"
-#include "BlackfinTargetMachine.h"
-#include "BlackfinRegisterInfo.h"
-#include "llvm/Intrinsics.h"
-#include "llvm/CodeGen/SelectionDAGISel.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/Support/Compiler.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/raw_ostream.h"
-
-using namespace llvm;
-
-//===----------------------------------------------------------------------===//
-// Instruction Selector Implementation
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-/// BlackfinDAGToDAGISel - Blackfin specific code to select blackfin machine
-/// instructions for SelectionDAG operations.
-namespace {
-  class BlackfinDAGToDAGISel : public SelectionDAGISel {
-    /// Subtarget - Keep a pointer to the Blackfin Subtarget around so that we
-    /// can make the right decision when generating code for different targets.
-    //const BlackfinSubtarget &Subtarget;
-  public:
-    BlackfinDAGToDAGISel(BlackfinTargetMachine &TM, CodeGenOpt::Level OptLevel)
-      : SelectionDAGISel(TM, OptLevel) {}
-
-    virtual void PostprocessISelDAG();
-
-    virtual const char *getPassName() const {
-      return "Blackfin DAG->DAG Pattern Instruction Selection";
-    }
-
-    // Include the pieces autogenerated from the target description.
-#include "BlackfinGenDAGISel.inc"
-
-  private:
-    SDNode *Select(SDNode *N);
-    bool SelectADDRspii(SDValue Addr, SDValue &Base, SDValue &Offset);
-
-    // Walk the DAG after instruction selection, fixing register class issues.
-    void FixRegisterClasses(SelectionDAG &DAG);
-
-    const BlackfinInstrInfo &getInstrInfo() {
-      return *static_cast<const BlackfinTargetMachine&>(TM).getInstrInfo();
-    }
-    const BlackfinRegisterInfo *getRegisterInfo() {
-      return static_cast<const BlackfinTargetMachine&>(TM).getRegisterInfo();
-    }
-  };
-}  // end anonymous namespace
-
-FunctionPass *llvm::createBlackfinISelDag(BlackfinTargetMachine &TM,
-                                          CodeGenOpt::Level OptLevel) {
-  return new BlackfinDAGToDAGISel(TM, OptLevel);
-}
-
-void BlackfinDAGToDAGISel::PostprocessISelDAG() {
-  FixRegisterClasses(*CurDAG);
-}
-
-SDNode *BlackfinDAGToDAGISel::Select(SDNode *N) {
-  if (N->isMachineOpcode())
-    return NULL;   // Already selected.
-
-  switch (N->getOpcode()) {
-  default: break;
-  case ISD::FrameIndex: {
-    // Selects to ADDpp FI, 0 which in turn will become ADDimm7 SP, imm or ADDpp
-    // SP, Px
-    int FI = cast<FrameIndexSDNode>(N)->getIndex();
-    SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);
-    return CurDAG->SelectNodeTo(N, BF::ADDpp, MVT::i32, TFI,
-                                CurDAG->getTargetConstant(0, MVT::i32));
-  }
-  }
-
-  return SelectCode(N);
-}
-
-bool BlackfinDAGToDAGISel::SelectADDRspii(SDValue Addr,
-                                          SDValue &Base,
-                                          SDValue &Offset) {
-  FrameIndexSDNode *FIN = 0;
-  if ((FIN = dyn_cast<FrameIndexSDNode>(Addr))) {
-    Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
-    Offset = CurDAG->getTargetConstant(0, MVT::i32);
-    return true;
-  }
-  if (Addr.getOpcode() == ISD::ADD) {
-    ConstantSDNode *CN = 0;
-    if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) &&
-        (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) &&
-        (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) {
-      // Constant positive word offset from frame index
-      Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
-      Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);
-      return true;
-    }
-  }
-  return false;
-}
-
-static inline bool isCC(const TargetRegisterClass *RC) {
-  return BF::AnyCCRegClass.hasSubClassEq(RC);
-}
-
-static inline bool isDCC(const TargetRegisterClass *RC) {
-  return BF::DRegClass.hasSubClassEq(RC) || isCC(RC);
-}
-
-static void UpdateNodeOperand(SelectionDAG &DAG,
-                              SDNode *N,
-                              unsigned Num,
-                              SDValue Val) {
-  SmallVector<SDValue, 8> ops(N->op_begin(), N->op_end());
-  ops[Num] = Val;
-  SDNode *New = DAG.UpdateNodeOperands(N, ops.data(), ops.size());
-  DAG.ReplaceAllUsesWith(N, New);
-}
-
-// After instruction selection, insert COPY_TO_REGCLASS nodes to help in
-// choosing the proper register classes.
-void BlackfinDAGToDAGISel::FixRegisterClasses(SelectionDAG &DAG) {
-  const BlackfinInstrInfo &TII = getInstrInfo();
-  const BlackfinRegisterInfo *TRI = getRegisterInfo();
-  DAG.AssignTopologicalOrder();
-  HandleSDNode Dummy(DAG.getRoot());
-
-  for (SelectionDAG::allnodes_iterator NI = DAG.allnodes_begin();
-       NI != DAG.allnodes_end(); ++NI) {
-    if (NI->use_empty() || !NI->isMachineOpcode())
-      continue;
-    const MCInstrDesc &DefMCID = TII.get(NI->getMachineOpcode());
-    for (SDNode::use_iterator UI = NI->use_begin(); !UI.atEnd(); ++UI) {
-      if (!UI->isMachineOpcode())
-        continue;
-
-      if (UI.getUse().getResNo() >= DefMCID.getNumDefs())
-        continue;
-      const TargetRegisterClass *DefRC =
-        TII.getRegClass(DefMCID, UI.getUse().getResNo(), TRI);
-
-      const MCInstrDesc &UseMCID = TII.get(UI->getMachineOpcode());
-      if (UseMCID.getNumDefs()+UI.getOperandNo() >= UseMCID.getNumOperands())
-        continue;
-      const TargetRegisterClass *UseRC =
-        TII.getRegClass(UseMCID, UseMCID.getNumDefs()+UI.getOperandNo(), TRI);
-      if (!DefRC || !UseRC)
-        continue;
-      // We cannot copy CC <-> !(CC/D)
-      if ((isCC(DefRC) && !isDCC(UseRC)) || (isCC(UseRC) && !isDCC(DefRC))) {
-        SDNode *Copy =
-          DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
-                             NI->getDebugLoc(),
-                             MVT::i32,
-                             UI.getUse().get(),
-                             DAG.getTargetConstant(BF::DRegClassID, MVT::i32));
-        UpdateNodeOperand(DAG, *UI, UI.getOperandNo(), SDValue(Copy, 0));
-      }
-    }
-  }
-  DAG.setRoot(Dummy.getValue());
-}
-
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Blackfin/BlackfinISelLowering.cpp
--- a/head/contrib/llvm/lib/Target/Blackfin/BlackfinISelLowering.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,645 +0,0 @@
-//===- BlackfinISelLowering.cpp - Blackfin DAG Lowering Implementation ----===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file implements the interfaces that Blackfin uses to lower LLVM code
-// into a selection DAG.
-//
-//===----------------------------------------------------------------------===//
-
-#include "BlackfinISelLowering.h"
-#include "BlackfinTargetMachine.h"
-#include "llvm/Function.h"
-#include "llvm/Type.h"
-#include "llvm/CodeGen/CallingConvLower.h"
-#include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/PseudoSourceValue.h"
-#include "llvm/CodeGen/SelectionDAG.h"
-#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
-#include "llvm/ADT/VectorExtras.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/ErrorHandling.h"
-using namespace llvm;
-
-//===----------------------------------------------------------------------===//
-// Calling Convention Implementation
-//===----------------------------------------------------------------------===//
-
-#include "BlackfinGenCallingConv.inc"
-
-//===----------------------------------------------------------------------===//
-// TargetLowering Implementation
-//===----------------------------------------------------------------------===//
-
-BlackfinTargetLowering::BlackfinTargetLowering(TargetMachine &TM)
-  : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
-  setBooleanContents(ZeroOrOneBooleanContent);
-  setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
-  setStackPointerRegisterToSaveRestore(BF::SP);
-  setIntDivIsCheap(false);
-
-  // Set up the legal register classes.
-  addRegisterClass(MVT::i32, BF::DRegisterClass);
-  addRegisterClass(MVT::i16, BF::D16RegisterClass);
-
-  computeRegisterProperties();
-
-  // Blackfin doesn't have i1 loads or stores
-  setLoadExtAction(ISD::EXTLOAD,  MVT::i1, Promote);
-  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
-  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
-
-  setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
-  setOperationAction(ISD::JumpTable,     MVT::i32, Custom);
-
-  setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
-  setOperationAction(ISD::BR_JT,     MVT::Other, Expand);
-  setOperationAction(ISD::BR_CC,     MVT::Other, Expand);
-
-  // i16 registers don't do much
-  setOperationAction(ISD::AND,   MVT::i16, Promote);
-  setOperationAction(ISD::OR,    MVT::i16, Promote);
-  setOperationAction(ISD::XOR,   MVT::i16, Promote);
-  setOperationAction(ISD::CTPOP, MVT::i16, Promote);
-  // The expansion of CTLZ/CTTZ uses AND/OR, so we might as well promote
-  // immediately.
-  setOperationAction(ISD::CTLZ,  MVT::i16, Promote);
-  setOperationAction(ISD::CTTZ,  MVT::i16, Promote);
-  setOperationAction(ISD::SETCC, MVT::i16, Promote);
-
-  // Blackfin has no division
-  setOperationAction(ISD::SDIV,    MVT::i16, Expand);
-  setOperationAction(ISD::SDIV,    MVT::i32, Expand);
-  setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
-  setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
-  setOperationAction(ISD::SREM,    MVT::i16, Expand);
-  setOperationAction(ISD::SREM,    MVT::i32, Expand);
-  setOperationAction(ISD::UDIV,    MVT::i16, Expand);
-  setOperationAction(ISD::UDIV,    MVT::i32, Expand);
-  setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
-  setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
-  setOperationAction(ISD::UREM,    MVT::i16, Expand);
-  setOperationAction(ISD::UREM,    MVT::i32, Expand);
-
-  setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
-  setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
-  setOperationAction(ISD::MULHU,     MVT::i32, Expand);
-  setOperationAction(ISD::MULHS,     MVT::i32, Expand);
-
-  // No carry-in operations.
-  setOperationAction(ISD::ADDE, MVT::i32, Custom);
-  setOperationAction(ISD::SUBE, MVT::i32, Custom);
-
-  // Blackfin has no intrinsics for these particular operations.
-  setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
-  setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
-  setOperationAction(ISD::BSWAP, MVT::i32, Expand);
-
-  setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
-  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
-  setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
-
-  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
-
-  // i32 has native CTPOP, but not CTLZ/CTTZ
-  setOperationAction(ISD::CTLZ, MVT::i32, Expand);
-  setOperationAction(ISD::CTTZ, MVT::i32, Expand);
-
-  // READCYCLECOUNTER needs special type legalization.
-  setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
-
-  setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
-
-  // Use the default implementation.
-  setOperationAction(ISD::VACOPY, MVT::Other, Expand);
-  setOperationAction(ISD::VAEND, MVT::Other, Expand);
-  setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
-  setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
-
-  setMinFunctionAlignment(2);
-}
-
-const char *BlackfinTargetLowering::getTargetNodeName(unsigned Opcode) const {
-  switch (Opcode) {
-  default: return 0;
-  case BFISD::CALL:     return "BFISD::CALL";
-  case BFISD::RET_FLAG: return "BFISD::RET_FLAG";
-  case BFISD::Wrapper:  return "BFISD::Wrapper";
-  }
-}
-
-EVT BlackfinTargetLowering::getSetCCResultType(EVT VT) const {
-  // SETCC always sets the CC register. Technically that is an i1 register, but
-  // that type is not legal, so we treat it as an i32 register.
-  return MVT::i32;
-}
-
-SDValue BlackfinTargetLowering::LowerGlobalAddress(SDValue Op,
-                                                   SelectionDAG &DAG) const {
-  DebugLoc DL = Op.getDebugLoc();
-  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
-
-  Op = DAG.getTargetGlobalAddress(GV, DL, MVT::i32);
-  return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op);
-}
-
-SDValue BlackfinTargetLowering::LowerJumpTable(SDValue Op,
-                                               SelectionDAG &DAG) const {
-  DebugLoc DL = Op.getDebugLoc();
-  int JTI = cast<JumpTableSDNode>(Op)->getIndex();
-
-  Op = DAG.getTargetJumpTable(JTI, MVT::i32);
-  return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op);
-}
-
-SDValue
-BlackfinTargetLowering::LowerFormalArguments(SDValue Chain,
-                                             CallingConv::ID CallConv, bool isVarArg,
-                                            const SmallVectorImpl<ISD::InputArg>
-                                               &Ins,
-                                             DebugLoc dl, SelectionDAG &DAG,
-                                             SmallVectorImpl<SDValue> &InVals)
-                                               const {
-
-  MachineFunction &MF = DAG.getMachineFunction();
-  MachineFrameInfo *MFI = MF.getFrameInfo();
-
-  SmallVector<CCValAssign, 16> ArgLocs;
-  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
-		 getTargetMachine(), ArgLocs, *DAG.getContext());
-  CCInfo.AllocateStack(12, 4);  // ABI requires 12 bytes stack space
-  CCInfo.AnalyzeFormalArguments(Ins, CC_Blackfin);
-
-  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
-    CCValAssign &VA = ArgLocs[i];
-
-    if (VA.isRegLoc()) {
-      EVT RegVT = VA.getLocVT();
-      TargetRegisterClass *RC = VA.getLocReg() == BF::P0 ?
-        BF::PRegisterClass : BF::DRegisterClass;
-      assert(RC->contains(VA.getLocReg()) && "Unexpected regclass in CCState");
-      assert(RC->hasType(RegVT) && "Unexpected regclass in CCState");
-
-      unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
-      MF.getRegInfo().addLiveIn(VA.getLocReg(), Reg);
-      SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
-
-      // If this is an 8 or 16-bit value, it is really passed promoted to 32
-      // bits.  Insert an assert[sz]ext to capture this, then truncate to the
-      // right size.
-      if (VA.getLocInfo() == CCValAssign::SExt)
-        ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
-                               DAG.getValueType(VA.getValVT()));
-      else if (VA.getLocInfo() == CCValAssign::ZExt)
-        ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
-                               DAG.getValueType(VA.getValVT()));
-
-      if (VA.getLocInfo() != CCValAssign::Full)
-        ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
-
-      InVals.push_back(ArgValue);
-    } else {
-      assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc");
-      unsigned ObjSize = VA.getLocVT().getStoreSize();
-      int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
-      SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
-      InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
-                                   MachinePointerInfo(),
-                                   false, false, 0));
-    }
-  }
-
-  return Chain;
-}
-
-SDValue
-BlackfinTargetLowering::LowerReturn(SDValue Chain,
-                                    CallingConv::ID CallConv, bool isVarArg,
-                                    const SmallVectorImpl<ISD::OutputArg> &Outs,
-                                    const SmallVectorImpl<SDValue> &OutVals,
-                                    DebugLoc dl, SelectionDAG &DAG) const {
-
-  // CCValAssign - represent the assignment of the return value to locations.
-  SmallVector<CCValAssign, 16> RVLocs;
-
-  // CCState - Info about the registers and stack slot.
-  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
-		 DAG.getTarget(), RVLocs, *DAG.getContext());
-
-  // Analize return values.
-  CCInfo.AnalyzeReturn(Outs, RetCC_Blackfin);
-
-  // If this is the first return lowered for this function, add the regs to the
-  // liveout set for the function.
-  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
-    for (unsigned i = 0; i != RVLocs.size(); ++i)
-      DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
-  }
-
-  SDValue Flag;
-
-  // Copy the result values into the output registers.
-  for (unsigned i = 0; i != RVLocs.size(); ++i) {
-    CCValAssign &VA = RVLocs[i];
-    assert(VA.isRegLoc() && "Can only return in registers!");
-    SDValue Opi = OutVals[i];
-
-    // Expand to i32 if necessary
-    switch (VA.getLocInfo()) {
-    default: llvm_unreachable("Unknown loc info!");
-    case CCValAssign::Full: break;
-    case CCValAssign::SExt:
-      Opi = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Opi);
-      break;
-    case CCValAssign::ZExt:
-      Opi = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Opi);
-      break;
-    case CCValAssign::AExt:
-      Opi = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Opi);
-      break;
-    }
-    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Opi, SDValue());
-    // Guarantee that all emitted copies are stuck together with flags.
-    Flag = Chain.getValue(1);
-  }
-
-  if (Flag.getNode()) {
-    return DAG.getNode(BFISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
-  } else {
-    return DAG.getNode(BFISD::RET_FLAG, dl, MVT::Other, Chain);
-  }
-}
-
-SDValue
-BlackfinTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
-                                  CallingConv::ID CallConv, bool isVarArg,
-                                  bool &isTailCall,
-                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
-                                  const SmallVectorImpl<SDValue> &OutVals,
-                                  const SmallVectorImpl<ISD::InputArg> &Ins,
-                                  DebugLoc dl, SelectionDAG &DAG,
-                                  SmallVectorImpl<SDValue> &InVals) const {
-  // Blackfin target does not yet support tail call optimization.
-  isTailCall = false;
-
-  // Analyze operands of the call, assigning locations to each operand.
-  SmallVector<CCValAssign, 16> ArgLocs;
-  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
-		 DAG.getTarget(), ArgLocs, *DAG.getContext());
-  CCInfo.AllocateStack(12, 4);  // ABI requires 12 bytes stack space
-  CCInfo.AnalyzeCallOperands(Outs, CC_Blackfin);
-
-  // Get the size of the outgoing arguments stack space requirement.
-  unsigned ArgsSize = CCInfo.getNextStackOffset();
-
-  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true));
-  SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
-  SmallVector<SDValue, 8> MemOpChains;
-
-  // Walk the register/memloc assignments, inserting copies/loads.
-  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
-    CCValAssign &VA = ArgLocs[i];
-    SDValue Arg = OutVals[i];
-
-    // Promote the value if needed.
-    switch (VA.getLocInfo()) {
-    default: llvm_unreachable("Unknown loc info!");
-    case CCValAssign::Full: break;
-    case CCValAssign::SExt:
-      Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
-      break;
-    case CCValAssign::ZExt:
-      Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
-      break;
-    case CCValAssign::AExt:
-      Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
-      break;
-    }
-
-    // Arguments that can be passed on register must be kept at
-    // RegsToPass vector
-    if (VA.isRegLoc()) {
-      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
-    } else {
-      assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc");
-      int Offset = VA.getLocMemOffset();
-      assert(Offset%4 == 0 && "Unaligned LocMemOffset");
-      assert(VA.getLocVT()==MVT::i32 && "Illegal CCValAssign type");
-      SDValue SPN = DAG.getCopyFromReg(Chain, dl, BF::SP, MVT::i32);
-      SDValue OffsetN = DAG.getIntPtrConstant(Offset);
-      OffsetN = DAG.getNode(ISD::ADD, dl, MVT::i32, SPN, OffsetN);
-      MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, OffsetN,
-                                         MachinePointerInfo(),false, false, 0));
-    }
-  }
-
-  // Transform all store nodes into one single node because
-  // all store nodes are independent of each other.
-  if (!MemOpChains.empty())
-    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
-                        &MemOpChains[0], MemOpChains.size());
-
-  // Build a sequence of copy-to-reg nodes chained together with token
-  // chain and flag operands which copy the outgoing args into registers.
-  // The InFlag in necessary since all emitted instructions must be
-  // stuck together.
-  SDValue InFlag;
-  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
-    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
-                             RegsToPass[i].second, InFlag);
-    InFlag = Chain.getValue(1);
-  }
-
-  // If the callee is a GlobalAddress node (quite common, every direct call is)
-  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
-  // Likewise ExternalSymbol -> TargetExternalSymbol.
-  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
-    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);
-  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
-    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
-
-  std::vector<EVT> NodeTys;
-  NodeTys.push_back(MVT::Other);   // Returns a chain
-  NodeTys.push_back(MVT::Glue);    // Returns a flag for retval copy to use.
-  SDValue Ops[] = { Chain, Callee, InFlag };
-  Chain = DAG.getNode(BFISD::CALL, dl, NodeTys, Ops,
-                      InFlag.getNode() ? 3 : 2);
-  InFlag = Chain.getValue(1);
-
-  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
-                             DAG.getIntPtrConstant(0, true), InFlag);
-  InFlag = Chain.getValue(1);
-
-  // Assign locations to each value returned by this call.
-  SmallVector<CCValAssign, 16> RVLocs;
-  CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(),
-		 DAG.getTarget(), RVLocs, *DAG.getContext());
-
-  RVInfo.AnalyzeCallResult(Ins, RetCC_Blackfin);
-
-  // Copy all of the result registers out of their specified physreg.
-  for (unsigned i = 0; i != RVLocs.size(); ++i) {
-    CCValAssign &RV = RVLocs[i];
-    unsigned Reg = RV.getLocReg();
-
-    Chain = DAG.getCopyFromReg(Chain, dl, Reg,
-                               RVLocs[i].getLocVT(), InFlag);
-    SDValue Val = Chain.getValue(0);
-    InFlag = Chain.getValue(2);
-    Chain = Chain.getValue(1);
-
-    // Callee is responsible for extending any i16 return values.
-    switch (RV.getLocInfo()) {
-    case CCValAssign::SExt:
-      Val = DAG.getNode(ISD::AssertSext, dl, RV.getLocVT(), Val,
-                        DAG.getValueType(RV.getValVT()));
-      break;
-    case CCValAssign::ZExt:
-      Val = DAG.getNode(ISD::AssertZext, dl, RV.getLocVT(), Val,
-                        DAG.getValueType(RV.getValVT()));
-      break;
-    default:
-      break;
-    }
-
-    // Truncate to valtype
-    if (RV.getLocInfo() != CCValAssign::Full)
-      Val = DAG.getNode(ISD::TRUNCATE, dl, RV.getValVT(), Val);
-    InVals.push_back(Val);
-  }
-
-  return Chain;
-}
-
-// Expansion of ADDE / SUBE. This is a bit involved since blackfin doesn't have
-// add-with-carry instructions.
-SDValue BlackfinTargetLowering::LowerADDE(SDValue Op, SelectionDAG &DAG) const {
-  // Operands: lhs, rhs, carry-in (AC0 flag)
-  // Results: sum, carry-out (AC0 flag)
-  DebugLoc dl = Op.getDebugLoc();
-
-  unsigned Opcode = Op.getOpcode()==ISD::ADDE ? BF::ADD : BF::SUB;
-
-  // zext incoming carry flag in AC0 to 32 bits
-  SDNode* CarryIn = DAG.getMachineNode(BF::MOVE_cc_ac0, dl, MVT::i32,
-                                       /* flag= */ Op.getOperand(2));
-  CarryIn = DAG.getMachineNode(BF::MOVECC_zext, dl, MVT::i32,
-                               SDValue(CarryIn, 0));
-
-  // Add operands, produce sum and carry flag
-  SDNode *Sum = DAG.getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
-                                   Op.getOperand(0), Op.getOperand(1));
-
-  // Store intermediate carry from Sum
-  SDNode* Carry1 = DAG.getMachineNode(BF::MOVE_cc_ac0, dl, MVT::i32,
-                                      /* flag= */ SDValue(Sum, 1));
-
-  // Add incoming carry, again producing an output flag
-  Sum = DAG.getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
-                           SDValue(Sum, 0), SDValue(CarryIn, 0));
-
-  // Update AC0 with the intermediate carry, producing a flag.
-  SDNode *CarryOut = DAG.getMachineNode(BF::OR_ac0_cc, dl, MVT::Glue,
-                                        SDValue(Carry1, 0));
-
-  // Compose (i32, flag) pair
-  SDValue ops[2] = { SDValue(Sum, 0), SDValue(CarryOut, 0) };
-  return DAG.getMergeValues(ops, 2, dl);
-}
-
-SDValue BlackfinTargetLowering::LowerOperation(SDValue Op,
-                                               SelectionDAG &DAG) const {
-  switch (Op.getOpcode()) {
-  default:
-    Op.getNode()->dump();
-    llvm_unreachable("Should not custom lower this!");
-  case ISD::GlobalAddress:      return LowerGlobalAddress(Op, DAG);
-  case ISD::GlobalTLSAddress:
-    llvm_unreachable("TLS not implemented for Blackfin.");
-  case ISD::JumpTable:          return LowerJumpTable(Op, DAG);
-    // Frame & Return address.  Currently unimplemented
-  case ISD::FRAMEADDR:          return SDValue();
-  case ISD::RETURNADDR:         return SDValue();
-  case ISD::ADDE:
-  case ISD::SUBE:               return LowerADDE(Op, DAG);
-  }
-}
-
-void
-BlackfinTargetLowering::ReplaceNodeResults(SDNode *N,
-                                           SmallVectorImpl<SDValue> &Results,
-                                           SelectionDAG &DAG) const {
-  DebugLoc dl = N->getDebugLoc();
-  switch (N->getOpcode()) {
-  default:
-    llvm_unreachable("Do not know how to custom type legalize this operation!");
-    return;
-  case ISD::READCYCLECOUNTER: {
-    // The low part of the cycle counter is in CYCLES, the high part in
-    // CYCLES2. Reading CYCLES will latch the value of CYCLES2, so we must read
-    // CYCLES2 last.
-    SDValue TheChain = N->getOperand(0);
-    SDValue lo = DAG.getCopyFromReg(TheChain, dl, BF::CYCLES, MVT::i32);
-    SDValue hi = DAG.getCopyFromReg(lo.getValue(1), dl, BF::CYCLES2, MVT::i32);
-    // Use a buildpair to merge the two 32-bit values into a 64-bit one.
-    Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, lo, hi));
-    // Outgoing chain. If we were to use the chain from lo instead, it would be
-    // possible to entirely eliminate the CYCLES2 read in (i32 (trunc
-    // readcyclecounter)). Unfortunately this could possibly delay the CYCLES2
-    // read beyond the next CYCLES read, leading to invalid results.
-    Results.push_back(hi.getValue(1));
-    return;
-  }
-  }
-}
-
-//===----------------------------------------------------------------------===//
-//                         Blackfin Inline Assembly Support
-//===----------------------------------------------------------------------===//
-
-/// getConstraintType - Given a constraint letter, return the type of
-/// constraint it is for this target.
-BlackfinTargetLowering::ConstraintType
-BlackfinTargetLowering::getConstraintType(const std::string &Constraint) const {
-  if (Constraint.size() != 1)
-    return TargetLowering::getConstraintType(Constraint);
-
-  switch (Constraint[0]) {
-    // Standard constraints
-  case 'r':
-    return C_RegisterClass;
-
-    // Blackfin-specific constraints
-  case 'a':
-  case 'd':
-  case 'z':
-  case 'D':
-  case 'W':
-  case 'e':
-  case 'b':
-  case 'v':
-  case 'f':
-  case 'c':
-  case 't':
-  case 'u':
-  case 'k':
-  case 'x':
-  case 'y':
-  case 'w':
-    return C_RegisterClass;
-  case 'A':
-  case 'B':
-  case 'C':
-  case 'Z':
-  case 'Y':
-    return C_Register;
-  }
-
-  // Not implemented: q0-q7, qA. Use {R2} etc instead
-
-  return TargetLowering::getConstraintType(Constraint);
-}
-
-/// Examine constraint type and operand type and determine a weight value.
-/// This object must already have been set up with the operand type
-/// and the current alternative constraint selected.
-TargetLowering::ConstraintWeight
-BlackfinTargetLowering::getSingleConstraintMatchWeight(
-    AsmOperandInfo &info, const char *constraint) const {
-  ConstraintWeight weight = CW_Invalid;
-  Value *CallOperandVal = info.CallOperandVal;
-    // If we don't have a value, we can't do a match,
-    // but allow it at the lowest weight.
-  if (CallOperandVal == NULL)
-    return CW_Default;
-  // Look at the constraint type.
-  switch (*constraint) {
-  default:
-    weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
-    break;
-
-    // Blackfin-specific constraints
-  case 'a':
-  case 'd':
-  case 'z':
-  case 'D':
-  case 'W':
-  case 'e':
-  case 'b':
-  case 'v':
-  case 'f':
-  case 'c':
-  case 't':
-  case 'u':
-  case 'k':
-  case 'x':
-  case 'y':
-  case 'w':
-    return CW_Register;
-  case 'A':
-  case 'B':
-  case 'C':
-  case 'Z':
-  case 'Y':
-    return CW_SpecificReg;
-  }
-  return weight;
-}
-
-/// getRegForInlineAsmConstraint - Return register no and class for a C_Register
-/// constraint.
-std::pair<unsigned, const TargetRegisterClass*> BlackfinTargetLowering::
-getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const {
-  typedef std::pair<unsigned, const TargetRegisterClass*> Pair;
-  using namespace BF;
-
-  if (Constraint.size() != 1)
-    return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
-
-  switch (Constraint[0]) {
-    // Standard constraints
-  case 'r':
-    return Pair(0U, VT == MVT::i16 ? D16RegisterClass : DPRegisterClass);
-
-    // Blackfin-specific constraints
-  case 'a': return Pair(0U, PRegisterClass);
-  case 'd': return Pair(0U, DRegisterClass);
-  case 'e': return Pair(0U, AccuRegisterClass);
-  case 'A': return Pair(A0, AccuRegisterClass);
-  case 'B': return Pair(A1, AccuRegisterClass);
-  case 'b': return Pair(0U, IRegisterClass);
-  case 'v': return Pair(0U, BRegisterClass);
-  case 'f': return Pair(0U, MRegisterClass);
-  case 'C': return Pair(CC, JustCCRegisterClass);
-  case 'x': return Pair(0U, GRRegisterClass);
-  case 'w': return Pair(0U, ALLRegisterClass);
-  case 'Z': return Pair(P3, PRegisterClass);
-  case 'Y': return Pair(P1, PRegisterClass);
-  case 'z': return Pair(0U, zConsRegisterClass);
-  case 'D': return Pair(0U, DConsRegisterClass);
-  case 'W': return Pair(0U, WConsRegisterClass);
-  case 'c': return Pair(0U, cConsRegisterClass);
-  case 't': return Pair(0U, tConsRegisterClass);
-  case 'u': return Pair(0U, uConsRegisterClass);
-  case 'k': return Pair(0U, kConsRegisterClass);
-  case 'y': return Pair(0U, yConsRegisterClass);
-  }
-
-  // Not implemented: q0-q7, qA. Use {R2} etc instead.
-
-  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
-}
-
-bool BlackfinTargetLowering::
-isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
-  // The Blackfin target isn't yet aware of offsets.
-  return false;
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Blackfin/BlackfinISelLowering.h
--- a/head/contrib/llvm/lib/Target/Blackfin/BlackfinISelLowering.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,83 +0,0 @@
-//===- BlackfinISelLowering.h - Blackfin DAG Lowering Interface -*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines the interfaces that Blackfin uses to lower LLVM code into a
-// selection DAG.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef BLACKFIN_ISELLOWERING_H
-#define BLACKFIN_ISELLOWERING_H
-
-#include "llvm/Target/TargetLowering.h"
-#include "Blackfin.h"
-
-namespace llvm {
-
-  namespace BFISD {
-    enum {
-      FIRST_NUMBER = ISD::BUILTIN_OP_END,
-      CALL,                     // A call instruction.
-      RET_FLAG,                 // Return with a flag operand.
-      Wrapper                   // Address wrapper
-    };
-  }
-
-  class BlackfinTargetLowering : public TargetLowering {
-  public:
-    BlackfinTargetLowering(TargetMachine &TM);
-    virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i16; }
-    virtual EVT getSetCCResultType(EVT VT) const;
-    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
-    virtual void ReplaceNodeResults(SDNode *N,
-                                    SmallVectorImpl<SDValue> &Results,
-                                    SelectionDAG &DAG) const;
-
-    ConstraintType getConstraintType(const std::string &Constraint) const;
-
-    /// Examine constraint string and operand type and determine a weight value.
-    /// The operand object must already have been set up with the operand type.
-    ConstraintWeight getSingleConstraintMatchWeight(
-      AsmOperandInfo &info, const char *constraint) const;
-
-    std::pair<unsigned, const TargetRegisterClass*>
-    getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
-    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
-    const char *getTargetNodeName(unsigned Opcode) const;
-
-  private:
-    SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
-    SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
-    SDValue LowerADDE(SDValue Op, SelectionDAG &DAG) const;
-
-    virtual SDValue
-      LowerFormalArguments(SDValue Chain,
-                           CallingConv::ID CallConv, bool isVarArg,
-                           const SmallVectorImpl<ISD::InputArg> &Ins,
-                           DebugLoc dl, SelectionDAG &DAG,
-                           SmallVectorImpl<SDValue> &InVals) const;
-    virtual SDValue
-      LowerCall(SDValue Chain, SDValue Callee,
-                CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
-                const SmallVectorImpl<ISD::OutputArg> &Outs,
-                const SmallVectorImpl<SDValue> &OutVals,
-                const SmallVectorImpl<ISD::InputArg> &Ins,
-                DebugLoc dl, SelectionDAG &DAG,
-                SmallVectorImpl<SDValue> &InVals) const;
-
-    virtual SDValue
-      LowerReturn(SDValue Chain,
-                  CallingConv::ID CallConv, bool isVarArg,
-                  const SmallVectorImpl<ISD::OutputArg> &Outs,
-                  const SmallVectorImpl<SDValue> &OutVals,
-                  DebugLoc dl, SelectionDAG &DAG) const;
-  };
-} // end namespace llvm
-
-#endif    // BLACKFIN_ISELLOWERING_H
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Blackfin/BlackfinInstrFormats.td
--- a/head/contrib/llvm/lib/Target/Blackfin/BlackfinInstrFormats.td	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,34 +0,0 @@
-//===--- BlackfinInstrFormats.td ---------------------------*- tablegen -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// Instruction format superclass
-//===----------------------------------------------------------------------===//
-
-class InstBfin<dag outs, dag ins, string asmstr, list<dag> pattern>
-  : Instruction {
-  field bits<32> Inst;
-
-  let Namespace = "BF";
-
-  dag OutOperandList = outs;
-  dag InOperandList = ins;
-  let AsmString   = asmstr;
-  let Pattern = pattern;
-}
-
-// Single-word (16-bit) instructions
-class F1<dag outs, dag ins, string asmstr, list<dag> pattern>
-    : InstBfin<outs, ins, asmstr, pattern> {
-}
-
-// Double-word (32-bit) instructions
-class F2<dag outs, dag ins, string asmstr, list<dag> pattern>
-    : InstBfin<outs, ins, asmstr, pattern> {
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Blackfin/BlackfinInstrInfo.cpp
--- a/head/contrib/llvm/lib/Target/Blackfin/BlackfinInstrInfo.cpp	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,256 +0,0 @@
-//===- BlackfinInstrInfo.cpp - Blackfin Instruction Information -*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains the Blackfin implementation of the TargetInstrInfo class.
-//
-//===----------------------------------------------------------------------===//
-
-#include "BlackfinInstrInfo.h"
-#include "BlackfinSubtarget.h"
-#include "Blackfin.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/ADT/STLExtras.h"
-#include "llvm/ADT/SmallVector.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/TargetRegistry.h"
-
-#define GET_INSTRINFO_CTOR
-#include "BlackfinGenInstrInfo.inc"
-
-using namespace llvm;
-
-BlackfinInstrInfo::BlackfinInstrInfo(BlackfinSubtarget &ST)
-  : BlackfinGenInstrInfo(BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP),
-    RI(ST, *this),
-    Subtarget(ST) {}
-
-/// isLoadFromStackSlot - If the specified machine instruction is a direct
-/// load from a stack slot, return the virtual or physical register number of
-/// the destination along with the FrameIndex of the loaded stack slot.  If
-/// not, return 0.  This predicate must return 0 if the instruction has
-/// any side effects other than loading from the stack slot.
-unsigned BlackfinInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
-                                                int &FrameIndex) const {
-  switch (MI->getOpcode()) {
-  default: break;
-  case BF::LOAD32fi:
-  case BF::LOAD16fi:
-    if (MI->getOperand(1).isFI() &&
-        MI->getOperand(2).isImm() &&
-        MI->getOperand(2).getImm() == 0) {
-      FrameIndex = MI->getOperand(1).getIndex();
-      return MI->getOperand(0).getReg();
-    }
-    break;
-  }
-  return 0;
-}
-
-/// isStoreToStackSlot - If the specified machine instruction is a direct
-/// store to a stack slot, return the virtual or physical register number of
-/// the source reg along with the FrameIndex of the loaded stack slot.  If
-/// not, return 0.  This predicate must return 0 if the instruction has
-/// any side effects other than storing to the stack slot.
-unsigned BlackfinInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
-                                               int &FrameIndex) const {
-  switch (MI->getOpcode()) {
-  default: break;
-  case BF::STORE32fi:
-  case BF::STORE16fi:
-    if (MI->getOperand(1).isFI() &&
-        MI->getOperand(2).isImm() &&
-        MI->getOperand(2).getImm() == 0) {
-      FrameIndex = MI->getOperand(1).getIndex();
-      return MI->getOperand(0).getReg();
-    }
-    break;
-  }
-  return 0;
-}
-
-unsigned BlackfinInstrInfo::
-InsertBranch(MachineBasicBlock &MBB,
-             MachineBasicBlock *TBB,
-             MachineBasicBlock *FBB,
-             const SmallVectorImpl<MachineOperand> &Cond,
-             DebugLoc DL) const {
-  // Shouldn't be a fall through.
-  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
-  assert((Cond.size() == 1 || Cond.size() == 0) &&
-         "Branch conditions have one component!");
-
-  if (Cond.empty()) {
-    // Unconditional branch?
-    assert(!FBB && "Unconditional branch with multiple successors!");
-    BuildMI(&MBB, DL, get(BF::JUMPa)).addMBB(TBB);
-    return 1;
-  }
-
-  // Conditional branch.
-  llvm_unreachable("Implement conditional branches!");
-}
-
-void BlackfinInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
-                                    MachineBasicBlock::iterator I, DebugLoc DL,
-                                    unsigned DestReg, unsigned SrcReg,
-                                    bool KillSrc) const {
-  if (BF::ALLRegClass.contains(DestReg, SrcReg)) {
-    BuildMI(MBB, I, DL, get(BF::MOVE), DestReg)
-      .addReg(SrcReg, getKillRegState(KillSrc));
-    return;
-  }
-
-  if (BF::D16RegClass.contains(DestReg, SrcReg)) {
-    BuildMI(MBB, I, DL, get(BF::SLL16i), DestReg)
-      .addReg(SrcReg, getKillRegState(KillSrc))
-      .addImm(0);
-    return;
-  }
-
-  if (BF::DRegClass.contains(DestReg)) {
-    if (SrcReg == BF::NCC) {
-      BuildMI(MBB, I, DL, get(BF::MOVENCC_z), DestReg)
-        .addReg(SrcReg, getKillRegState(KillSrc));
-      BuildMI(MBB, I, DL, get(BF::BITTGL), DestReg).addReg(DestReg).addImm(0);
-      return;
-    }
-    if (SrcReg == BF::CC) {
-      BuildMI(MBB, I, DL, get(BF::MOVECC_zext), DestReg)
-        .addReg(SrcReg, getKillRegState(KillSrc));
-      return;
-    }
-  }
-
-  if (BF::DRegClass.contains(SrcReg)) {
-    if (DestReg == BF::NCC) {
-      BuildMI(MBB, I, DL, get(BF::SETEQri_not), DestReg)
-        .addReg(SrcReg, getKillRegState(KillSrc)).addImm(0);
-      return;
-    }
-    if (DestReg == BF::CC) {
-      BuildMI(MBB, I, DL, get(BF::MOVECC_nz), DestReg)
-        .addReg(SrcReg, getKillRegState(KillSrc));
-      return;
-    }
-  }
-
-
-  if (DestReg == BF::NCC && SrcReg == BF::CC) {
-    BuildMI(MBB, I, DL, get(BF::MOVE_ncccc), DestReg)
-      .addReg(SrcReg, getKillRegState(KillSrc));
-    return;
-  }
-
-  if (DestReg == BF::CC && SrcReg == BF::NCC) {
-    BuildMI(MBB, I, DL, get(BF::MOVE_ccncc), DestReg)
-      .addReg(SrcReg, getKillRegState(KillSrc));
-    return;
-  }
-
-  llvm_unreachable("Bad reg-to-reg copy");
-}
-
-static bool inClass(const TargetRegisterClass &Test,
-                    unsigned Reg,
-                    const TargetRegisterClass *RC) {
-  if (TargetRegisterInfo::isPhysicalRegister(Reg))
-    return Test.contains(Reg);
-  else
-    return Test.hasSubClassEq(RC);
-}
-
-void
-BlackfinInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
-                                       MachineBasicBlock::iterator I,
-                                       unsigned SrcReg,
-                                       bool isKill,
-                                       int FI,
-                                       const TargetRegisterClass *RC,
-                                       const TargetRegisterInfo *TRI) const {
-  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
-
-  if (inClass(BF::DPRegClass, SrcReg, RC)) {
-    BuildMI(MBB, I, DL, get(BF::STORE32fi))
-      .addReg(SrcReg, getKillRegState(isKill))
-      .addFrameIndex(FI)
-      .addImm(0);
-    return;
-  }
-
-  if (inClass(BF::D16RegClass, SrcReg, RC)) {
-    BuildMI(MBB, I, DL, get(BF::STORE16fi))
-      .addReg(SrcReg, getKillRegState(isKill))
-      .addFrameIndex(FI)
-      .addImm(0);
-    return;
-  }
-
-  if (inClass(BF::AnyCCRegClass, SrcReg, RC)) {
-    BuildMI(MBB, I, DL, get(BF::STORE8fi))
-      .addReg(SrcReg, getKillRegState(isKill))
-      .addFrameIndex(FI)
-      .addImm(0);
-    return;
-  }
-
-  llvm_unreachable((std::string("Cannot store regclass to stack slot: ")+
-                    RC->getName()).c_str());
-}
-
-void BlackfinInstrInfo::
-storeRegToAddr(MachineFunction &MF,
-               unsigned SrcReg,
-               bool isKill,
-               SmallVectorImpl<MachineOperand> &Addr,
-               const TargetRegisterClass *RC,
-               SmallVectorImpl<MachineInstr*> &NewMIs) const {
-  llvm_unreachable("storeRegToAddr not implemented");
-}
-
-void
-BlackfinInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
-                                        MachineBasicBlock::iterator I,
-                                        unsigned DestReg,
-                                        int FI,
-                                        const TargetRegisterClass *RC,
-                                        const TargetRegisterInfo *TRI) const {
-  DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
-  if (inClass(BF::DPRegClass, DestReg, RC)) {
-    BuildMI(MBB, I, DL, get(BF::LOAD32fi), DestReg)
-      .addFrameIndex(FI)
-      .addImm(0);
-    return;
-  }
-
-  if (inClass(BF::D16RegClass, DestReg, RC)) {
-    BuildMI(MBB, I, DL, get(BF::LOAD16fi), DestReg)
-      .addFrameIndex(FI)
-      .addImm(0);
-    return;
-  }
-
-  if (inClass(BF::AnyCCRegClass, DestReg, RC)) {
-    BuildMI(MBB, I, DL, get(BF::LOAD8fi), DestReg)
-      .addFrameIndex(FI)
-      .addImm(0);
-    return;
-  }
-
-  llvm_unreachable("Cannot load regclass from stack slot");
-}
-
-void BlackfinInstrInfo::
-loadRegFromAddr(MachineFunction &MF,
-                unsigned DestReg,
-                SmallVectorImpl<MachineOperand> &Addr,
-                const TargetRegisterClass *RC,
-                SmallVectorImpl<MachineInstr*> &NewMIs) const {
-  llvm_unreachable("loadRegFromAddr not implemented");
-}
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Blackfin/BlackfinInstrInfo.h
--- a/head/contrib/llvm/lib/Target/Blackfin/BlackfinInstrInfo.h	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,81 +0,0 @@
-//===- BlackfinInstrInfo.h - Blackfin Instruction Information ---*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains the Blackfin implementation of the TargetInstrInfo class.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef BLACKFININSTRUCTIONINFO_H
-#define BLACKFININSTRUCTIONINFO_H
-
-#include "llvm/Target/TargetInstrInfo.h"
-#include "BlackfinRegisterInfo.h"
-
-#define GET_INSTRINFO_HEADER
-#include "BlackfinGenInstrInfo.inc"
-
-namespace llvm {
-
-  class BlackfinInstrInfo : public BlackfinGenInstrInfo {
-    const BlackfinRegisterInfo RI;
-    const BlackfinSubtarget& Subtarget;
-  public:
-    explicit BlackfinInstrInfo(BlackfinSubtarget &ST);
-
-    /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
-    /// such, whenever a client has an instance of instruction info, it should
-    /// always be able to get register info as well (through this method).
-    virtual const BlackfinRegisterInfo &getRegisterInfo() const { return RI; }
-
-    virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
-                                         int &FrameIndex) const;
-
-    virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
-                                        int &FrameIndex) const;
-
-    virtual unsigned
-    InsertBranch(MachineBasicBlock &MBB,
-                 MachineBasicBlock *TBB,
-                 MachineBasicBlock *FBB,
-                 const SmallVectorImpl<MachineOperand> &Cond,
-                 DebugLoc DL) const;
-
-    virtual void copyPhysReg(MachineBasicBlock &MBB,
-                             MachineBasicBlock::iterator MI, DebugLoc DL,
-                             unsigned DestReg, unsigned SrcReg,
-                             bool KillSrc) const;
-
-    virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
-                                     MachineBasicBlock::iterator MBBI,
-                                     unsigned SrcReg, bool isKill,
-                                     int FrameIndex,
-                                     const TargetRegisterClass *RC,
-                                     const TargetRegisterInfo *TRI) const;
-
-    virtual void storeRegToAddr(MachineFunction &MF,
-                                unsigned SrcReg, bool isKill,
-                                SmallVectorImpl<MachineOperand> &Addr,
-                                const TargetRegisterClass *RC,
-                                SmallVectorImpl<MachineInstr*> &NewMIs) const;
-
-    virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
-                                      MachineBasicBlock::iterator MBBI,
-                                      unsigned DestReg, int FrameIndex,
-                                      const TargetRegisterClass *RC,
-                                      const TargetRegisterInfo *TRI) const;
-
-    virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
-                                 SmallVectorImpl<MachineOperand> &Addr,
-                                 const TargetRegisterClass *RC,
-                                 SmallVectorImpl<MachineInstr*> &NewMIs) const;
-  };
-
-} // end namespace llvm
-
-#endif
diff -r 7bbd6bca528b -r 428842767fa6 head/contrib/llvm/lib/Target/Blackfin/BlackfinInstrInfo.td
--- a/head/contrib/llvm/lib/Target/Blackfin/BlackfinInstrInfo.td	Tue Apr 17 11:33:49 2012 +0300
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,862 +0,0 @@
-//===- BlackfinInstrInfo.td - Target Description for Blackfin Target ------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file describes the Blackfin instructions in TableGen format.
-//
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// Instruction format superclass
-//===----------------------------------------------------------------------===//
-
-include "BlackfinInstrFormats.td"
-
-// These are target-independent nodes, but have target-specific formats.
-def SDT_BfinCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
-def SDT_BfinCallSeqEnd   : SDCallSeqEnd<[ SDTCisVT<0, i32>,
-                                        SDTCisVT<1, i32> ]>;
-
-def BfinCallseqStart : SDNode<"ISD::CALLSEQ_START", SDT_BfinCallSeqStart,
-                              [SDNPHasChain, SDNPOutGlue]>;
-def BfinCallseqEnd   : SDNode<"ISD::CALLSEQ_END",   SDT_BfinCallSeqEnd,
-                              [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
-
-def SDT_BfinCall  : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
-def BfinCall      : SDNode<"BFISD::CALL", SDT_BfinCall,
-                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
-                            SDNPVariadic]>;
-
-def BfinRet: SDNode<"BFISD::RET_FLAG", SDTNone,
-                    [SDNPHasChain, SDNPOptInGlue]>;
-
-def BfinWrapper: SDNode<"BFISD::Wrapper", SDTIntUnaryOp>;
-
-//===----------------------------------------------------------------------===//
-// Transformations
-//===----------------------------------------------------------------------===//
-
-def trailingZeros_xform : SDNodeXForm<imm, [{
-  return CurDAG->getTargetConstant(N->getAPIntValue().countTrailingZeros(),
-                                   MVT::i32);
-}]>;
-
-def trailingOnes_xform : SDNodeXForm<imm, [{
-  return CurDAG->getTargetConstant(N->getAPIntValue().countTrailingOnes(),
-                                   MVT::i32);
-}]>;
-
-def LO16 : SDNodeXForm<imm, [{
-  return CurDAG->getTargetConstant((unsigned short)N->getZExtValue(), MVT::i16);
-}]>;
-
-def HI16 : SDNodeXForm<imm, [{
-  // Transformation function: shift the immediate value down into the low bits.
-  return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 16, MVT::i16);
-}]>;
-
-//===----------------------------------------------------------------------===//
-// Immediates
-//===----------------------------------------------------------------------===//
-
-def imm3  : PatLeaf<(imm), [{return isInt<3>(N->getSExtValue());}]>;
-def uimm3 : PatLeaf<(imm), [{return isUInt<3>(N->getZExtValue());}]>;
-def uimm4 : PatLeaf<(imm), [{return isUInt<4>(N->getZExtValue());}]>;
-def uimm5 : PatLeaf<(imm), [{return isUInt<5>(N->getZExtValue());}]>;
-
-def uimm5m2 : PatLeaf<(imm), [{
-    uint64_t value = N->getZExtValue();
-    return value % 2 == 0 && isUInt<5>(value);
-}]>;
-
-def uimm6m4 : PatLeaf<(imm), [{
-    uint64_t value = N->getZExtValue();
-    return value % 4 == 0 && isUInt<6>(value);
-}]>;
-
-def imm7   : PatLeaf<(imm), [{return isInt<7>(N->getSExtValue());}]>;
-def imm16  : PatLeaf<(imm), [{return isInt<16>(N->getSExtValue());}]>;
-def uimm16 : PatLeaf<(imm), [{return isUInt<16>(N->getZExtValue());}]>;
-
-def ximm16 : PatLeaf<(imm), [{
-    int64_t value = N->getSExtValue();
-    return value < (1<<16) && value >= -(1<<15);
-}]>;
-
-def imm17m2 : PatLeaf<(imm), [{
-    int64_t value = N->getSExtValue();
-    return value % 2 == 0 && isInt<17>(value);
-}]>;
-
-def imm18m4 : PatLeaf<(imm), [{
-    int64_t value = N->getSExtValue();
-    return value % 4 == 0 && isInt<18>(value);
-}]>;
-
-// 32-bit bitmask transformed to a bit number
-def uimm5mask : Operand<i32>, PatLeaf<(imm), [{
-    return isPowerOf2_32(N->getZExtValue());
-}], trailingZeros_xform>;
-
-// 32-bit inverse bitmask transformed to a bit number
-def uimm5imask : Operand<i32>, PatLeaf<(imm), [{
-    return isPowerOf2_32(~N->getZExtValue());
-}], trailingOnes_xform>;
-
-//===----------------------------------------------------------------------===//
-// Operands
-//===----------------------------------------------------------------------===//
-
-def calltarget : Operand<iPTR>;
-
-def brtarget : Operand<OtherVT>;
-
-// Addressing modes
-def ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>;
-
-// Address operands
-def MEMii : Operand<i32> {
-  let PrintMethod = "printMemoryOperand";
-  let MIOperandInfo = (ops i32imm, i32imm);
-}
-
-//===----------------------------------------------------------------------===//
-// Instructions
-//===----------------------------------------------------------------------===//
-
-// Pseudo instructions.
-class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
-   : InstBfin<outs, ins, asmstr, pattern>;
-
-let Defs = [SP], Uses = [SP] in {
-def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
-                              "${:comment}ADJCALLSTACKDOWN $amt",
-                              [(BfinCallseqStart timm:$amt)]>;
-def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
-                            "${:comment}ADJCALLSTACKUP $amt1 $amt2",
-                            [(BfinCallseqEnd timm:$amt1, timm:$amt2)]>;
-}
-
-//===----------------------------------------------------------------------===//
-// Table C-9. Program Flow Control Instructions
-//===----------------------------------------------------------------------===//
-
-let isBranch = 1, isTerminator = 1 in {
-
-let isIndirectBranch = 1 in
-def JUMPp : F1<(outs), (ins P:$target),
-               "JUMP ($target);",
-               [(brind P:$target)]>;
-
-// TODO JUMP (PC-P)
-
-// NOTE: assembler chooses between JUMP.S and JUMP.L
-def JUMPa : F1<(outs), (ins brtarget:$target),
-               "jump $target;",
-               [(br bb:$target)]>;
-
-def JUMPcc : F1<(outs), (ins AnyCC:$cc, brtarget:$target),
-               "if $cc jump $target;",
-               [(brcond AnyCC:$cc, bb:$target)]>;
-}
-
-let isCall = 1,
-    Defs   = [R0, R1, R2, R3, P0, P1, P2, LB0, LB1, LC0, LC1, RETS, ASTAT] in {
-def CALLa: F1<(outs), (ins calltarget:$func, variable_ops),
-              "call $func;", []>;
-def CALLp: F1<(outs), (ins P:$func, variable_ops),
-              "call ($func);", [(BfinCall P:$func)]>;
-}
-
-let isReturn     = 1,
-    isTerminator = 1,
-    isBarrier    = 1,
-    Uses         = [RETS] in
-def RTS: F1<(outs), (ins), "rts;", [(BfinRet)]>;
-
-//===----------------------------------------------------------------------===//
-// Table C-10. Load / Store Instructions
-//===----------------------------------------------------------------------===//
-
-// Immediate constant loads
-
-// sext immediate, i32 D/P regs
-def LOADimm7: F1<(outs DP:$dst), (ins i32imm:$src),
-                 "$dst = $src (x);",
-                 [(set DP:$dst, imm7:$src)]>;
-
-// zext immediate, i32 reg groups 0-3
-def LOADuimm16: F2<(outs GR:$dst), (ins i32imm:$src),
-                   "$dst = $src (z);",
-                   [(set GR:$dst, uimm16:$src)]>;
-
-// sext immediate, i32 reg groups 0-3
-def LOADimm16: F2<(outs GR:$dst), (ins i32imm:$src),
-                  "$dst = $src (x);",
-                  [(set GR:$dst, imm16:$src)]>;
-
-// Pseudo-instruction for loading a general 32-bit constant.
-def LOAD32imm: Pseudo<(outs GR:$dst), (ins i32imm:$src),
-                      "$dst.h = ($src >> 16); $dst.l = ($src & 0xffff);",
-                      [(set GR:$dst, imm:$src)]>;
-
-def LOAD32sym: Pseudo<(outs GR:$dst), (ins i32imm:$src),
-                      "$dst.h = $src; $dst.l = $src;", []>;
-
-
-// 16-bit immediate, i16 reg groups 0-3
-def LOAD16i: F2<(outs GR16:$dst), (ins i16imm:$src),
-                 "$dst = $src;", []>;
-
-def : Pat<(BfinWrapper (i32 tglobaladdr:$addr)),
-          (LOAD32sym tglobaladdr:$addr)>;
-
-def : Pat<(BfinWrapper (i32 tjumptable:$addr)),
-          (LOAD32sym tjumptable:$addr)>;
-
-// We cannot copy from GR16 to D16, and codegen wants to insert copies if we
-// emit GR16 instructions. As a hack, we use this fake instruction instead.
-def LOAD16i_d16: F2<(outs D16:$dst), (ins i16imm:$src),
-                    "$dst = $src;",
-                    [(set D16:$dst, ximm16:$src)]>;
-
-// Memory loads with patterns
-
-def LOAD32p: F1<(outs DP:$dst), (ins P:$ptr),
-                "$dst = [$ptr];",
-                [(set DP:$dst, (load P:$ptr))]>;
-
-// Pseudo-instruction for loading a stack slot
-def LOAD32fi: Pseudo<(outs DP:$dst), (ins MEMii:$mem),
-                     "${:comment}FI $dst = [$mem];",
-                     [(set DP:$dst, (load ADDRspii:$mem))]>;
-
-// Note: Expands to multiple insns
-def LOAD16fi: Pseudo<(outs D16:$dst), (ins MEMii:$mem),
-                     "${:comment}FI $dst = [$mem];",
-                     [(set D16:$dst, (load ADDRspii:$mem))]>;
-
-// Pseudo-instruction for loading a stack slot, used for AnyCC regs.
-// Replaced with Load D + CC=D
-def LOAD8fi: Pseudo<(outs AnyCC:$dst), (ins MEMii:$mem),
-                    "${:comment}FI $dst = B[$mem];",
-                    [(set AnyCC:$dst, (load ADDRspii:$mem))]>;
-
-def LOAD32p_uimm6m4: F1<(outs DP:$dst), (ins P:$ptr, i32imm:$off),
-                        "$dst = [$ptr + $off];",
-                        [(set DP:$dst, (load (add P:$ptr, uimm6m4:$off)))]>;
-
-def LOAD32p_imm18m4: F2<(outs DP:$dst), (ins P:$ptr, i32imm:$off),
-                         "$dst = [$ptr + $off];",
-                         [(set DP:$dst, (load (add P:$ptr, imm18m4:$off)))]>;
-
-def LOAD32p_16z: F1<(outs D:$dst), (ins P:$ptr),
-                    "$dst = W[$ptr] (z);",
-                    [(set D:$dst, (zextloadi16 P:$ptr))]>;
-
-def : Pat<(i32 (extloadi16 P:$ptr)),(LOAD32p_16z P:$ptr)>;
-
-def LOAD32p_uimm5m2_16z: F1<(outs D:$dst), (ins P:$ptr, i32imm:$off),
-                            "$dst = w[$ptr + $off] (z);",
-                            [(set D:$dst, (zextloadi16 (add P:$ptr,
-                                                        uimm5m2:$off)))]>;
-
-def : Pat<(i32 (extloadi16 (add P:$ptr, uimm5m2:$off))),
-          (LOAD32p_uimm5m2_16z P:$ptr, imm:$off)>;
-
-def LOAD32p_imm17m2_16z: F1<(outs D:$dst), (ins P:$ptr, i32imm:$off),
-                            "$dst = w[$ptr + $off] (z);",
-                            [(set D:$dst,
-                                  (zextloadi16 (add P:$ptr, imm17m2:$off)))]>;
-
-def : Pat<(i32 (extloadi16 (add P:$ptr, imm17m2:$off))),
-          (LOAD32p_imm17m2_16z P:$ptr, imm:$off)>;
-
-def LOAD32p_16s: F1<(outs D:$dst), (ins P:$ptr),
-                    "$dst = w[$ptr] (x);",
-                    [(set D:$dst, (sextloadi16 P:$ptr))]>;
-
-def LOAD32p_uimm5m2_16s: F1<(outs D:$dst), (ins P:$ptr, i32imm:$off),
-                            "$dst = w[$ptr + $off] (x);",
-                            [(set D:$dst,
-                                  (sextloadi16 (add P:$ptr, uimm5m2:$off)))]>;
-
-def LOAD32p_imm17m2_16s: F1<(outs D:$dst), (ins P:$ptr, i32imm:$off),
-                            "$dst = w[$ptr + $off] (x);",
-                            [(set D:$dst,
-                                  (sextloadi16 (add P:$ptr, imm17m2:$off)))]>;
-
-def LOAD16pi: F1<(outs D16:$dst), (ins PI:$ptr),
-                "$dst = w[$ptr];",
-                [(set D16:$dst, (load PI:$ptr))]>;
-
-def LOAD32p_8z: F1<(outs D:$dst), (ins P:$ptr),
-                   "$dst = B[$ptr] (z);",
-                   [(set D:$dst, (zextloadi8 P:$ptr))]>;
-
-def : Pat<(i32 (extloadi8 P:$ptr)), (LOAD32p_8z P:$ptr)>;
-def : Pat<(i16 (extloadi8 P:$ptr)),
-          (EXTRACT_SUBREG (LOAD32p_8z P:$ptr), lo16)>;
-def : Pat<(i16 (zextloadi8 P:$ptr)),
-          (EXTRACT_SUBREG (LOAD32p_8z P:$ptr), lo16)>;
-
-def LOAD32p_imm16_8z: F1<(outs D:$dst), (ins P:$ptr, i32imm:$off),
-                         "$dst = b[$ptr + $off] (z);",
-                         [(set D:$dst, (zextloadi8 (add P:$ptr, imm16:$off)))]>;
-
-def : Pat<(i32 (extloadi8 (add P:$ptr, imm16:$off))),
-          (LOAD32p_imm16_8z P:$ptr, imm:$off)>;
-def : Pat<(i16 (extloadi8 (add P:$ptr, imm16:$off))),
-          (EXTRACT_SUBREG (LOAD32p_imm16_8z P:$ptr, imm:$off),
-                           lo16)>;
-def : Pat<(i16 (zextloadi8 (add P:$ptr, imm16:$off))),
-          (EXTRACT_SUBREG (LOAD32p_imm16_8z P:$ptr, imm:$off),
-                           lo16)>;
-
-def LOAD32p_8s: F1<(outs D:$dst), (ins P:$ptr),
-                   "$dst = b[$ptr] (x);",
-                   [(set D:$dst, (sextloadi8 P:$ptr))]>;
-
-def : Pat<(i16 (sextloadi8 P:$ptr)),
-          (EXTRACT_SUBREG (LOAD32p_8s P:$ptr), lo16)>;
-
-def LOAD32p_imm16_8s: F1<(outs D:$dst), (ins P:$ptr, i32imm:$off),
-                         "$dst = b[$ptr + $off] (x);",
-                         [(set D:$dst, (sextloadi8 (add P:$ptr, imm16:$off)))]>;
-
-def : Pat<(i16 (sextloadi8 (add P:$ptr, imm16:$off))),
-          (EXTRACT_SUBREG (LOAD32p_imm16_8s P:$ptr, imm:$off),
-                           lo16)>;
-// Memory loads without patterns
-
-let mayLoad = 1 in {
-
-multiclass LOAD_incdec<RegisterClass drc, RegisterClass prc,
-                       string mem="", string suf=";"> {
-  def _inc : F1<(outs drc:$dst, prc:$ptr_wb), (ins prc:$ptr),
-                !strconcat(!subst("M", mem, "$dst = M[$ptr++]"), suf), []>;
-  def _dec : F1<(outs drc:$dst, prc:$ptr_wb), (ins prc:$ptr),
-                !strconcat(!subst("M", mem, "$dst = M[$ptr--]"), suf), []>;
-}
-multiclass LOAD_incdecpost<RegisterClass drc, RegisterClass prc,
-                           string mem="", string suf=";">
-         : LOAD_incdec<drc, prc, mem, suf> {
-  def _post : F1<(outs drc:$dst, prc:$ptr_wb), (ins prc:$ptr, prc:$off),
-                 !strconcat(!subst("M", mem, "$dst = M[$ptr++$off]"), suf), []>;
-}
-
-defm LOAD32p:    LOAD_incdec<DP, P>;
-defm LOAD32i:    LOAD_incdec<D, I>;
-defm LOAD8z32p:  LOAD_incdec<D, P, "b", " (z);">;
-defm LOAD8s32p:  LOAD_incdec<D, P, "b", " (x);">;
-defm LOADhi:     LOAD_incdec<D16, I, "w">;
-defm LOAD16z32p: LOAD_incdecpost<D, P, "w", " (z);">;
-defm LOAD16s32p: LOAD_incdecpost<D, P, "w", " (x);">;
-
-def LOAD32p_post: F1<(outs D:$dst, P:$ptr_wb), (ins P:$ptr, P:$off),
-                     "$dst = [$ptr ++ $off];", []>;
-
-// Note: $fp MUST be FP
-def LOAD32fp_nimm7m4: F1<(outs DP:$dst), (ins P:$fp, i32imm:$off),
-                         "$dst = [$fp - $off];", []>;
-
-def LOAD32i:      F1<(outs D:$dst), (ins I:$ptr),
-                     "$dst = [$ptr];", []>;
-def LOAD32i_post: F1<(outs D:$dst, I:$ptr_wb), (ins I:$ptr, M:$off),
-                     "$dst = [$ptr ++ $off];", []>;
-
-
-
-def LOADhp_post: F1<(outs D16:$dst, P:$ptr_wb), (ins P:$ptr, P:$off),
-                    "$dst = w[$ptr ++ $off];", []>;
-
-
-}
-
-// Memory stores with patterns
-def STORE32p: F1<(outs), (ins DP:$val, P:$ptr),
-                 "[$ptr] = $val;",
-                 [(store DP:$val, P:$ptr)]>;
-
-// Pseudo-instructions for storing to a stack slot
-def STORE32fi: Pseudo<(outs), (ins DP:$val, MEMii:$mem),
-                      "${:comment}FI [$mem] = $val;",
-                      [(store DP:$val, ADDRspii:$mem)]>;
-
-// Note: This stack-storing pseudo-instruction is expanded to multiple insns
-def STORE16fi: Pseudo<(outs), (ins D16:$val, MEMii:$mem),
-                  "${:comment}FI [$mem] = $val;",
-                  [(store D16:$val, ADDRspii:$mem)]>;
-
-// Pseudo-instructions for storing AnyCC register to a stack slot.
-// Replaced with D=CC + STORE byte
-def STORE8fi: Pseudo<(outs), (ins AnyCC:$val, MEMii:$mem),
-                      "${:comment}FI b[$mem] = $val;",
-                      [(store AnyCC:$val, ADDRspii:$mem)]>;
-
-def STORE32p_uimm6m4: F1<(outs), (ins DP:$val, P:$ptr, i32imm:$off),
-                 "[$ptr + $off] = $val;",
-                 [(store DP:$val, (add P:$ptr, uimm6m4:$off))]>;
-
-def STORE32p_imm18m4: F1<(outs), (ins DP:$val, P:$ptr, i32imm:$off),
-                 "[$ptr + $off] = $val;",
-                 [(store DP:$val, (add P:$ptr, imm18m4:$off))]>;
-
-def STORE16pi: F1<(outs), (ins D16:$val, PI:$ptr),
-                  "w[$ptr] = $val;",
-                  [(store D16:$val, PI:$ptr)]>;
-
-def STORE8p: F1<(outs), (ins D:$val, P:$ptr),
-                "b[$ptr] = $val;",
-                [(truncstorei8 D:$val, P:$ptr)]>;
-
-def STORE8p_imm16: F1<(outs), (ins D:$val, P:$ptr, i32imm:$off),
-                 "b[$ptr + $off] = $val;",
-                 [(truncstorei8 D:$val, (add P:$ptr, imm16:$off))]>;
-
-let Constraints = "$ptr = $ptr_wb" in {
-
-multiclass STORE_incdec<RegisterClass drc, RegisterClass prc,
-                        int off=4, string pre=""> {
-  def _inc : F1<(outs prc:$ptr_wb), (ins drc:$val, prc:$ptr),
-                !strconcat(pre, "[$ptr++] = $val;"),
-                [(set prc:$ptr_wb, (post_store drc:$val, prc:$ptr, off))]>;
-  def _dec : F1<(outs prc:$ptr_wb), (ins drc:$val, prc:$ptr),
-                !strconcat(pre, "[$ptr--] = $val;"),
-                [(set prc:$ptr_wb, (post_store drc:$val, prc:$ptr,
-                                               (ineg off)))]>;
-}
-
-defm STORE32p: STORE_incdec<DP, P>;
-defm STORE16i: STORE_incdec<D16, I, 2, "w">;
-defm STORE8p:  STORE_incdec<D, P, 1, "b">;
-
-def STORE32p_post: F1<(outs P:$ptr_wb), (ins D:$val, P:$ptr, P:$off),
-                      "[$ptr ++ $off] = $val;",
-                      [(set P:$ptr_wb, (post_store D:$val, P:$ptr, P:$off))]>;
-
-def STORE16p_post: F1<(outs P:$ptr_wb), (ins D16:$val, P:$ptr, P:$off),
-                      "w[$ptr ++ $off] = $val;",
-                      [(set P:$ptr_wb, (post_store D16:$val, P:$ptr, P:$off))]>;
-}
-
-// Memory stores without patterns
-
-let mayStore = 1 in {
-
-// Note: only works for $fp == FP
-def STORE32fp_nimm7m4: F1<(outs), (ins DP:$val, P:$fp, i32imm:$off),
-                         "[$fp - $off] = $val;", []>;
-
-def STORE32i: F1<(outs), (ins D:$val, I:$ptr),
-                 "[$ptr] = $val;", []>;
-
-def STORE32i_inc: F1<(outs I:$ptr_wb), (ins D:$val, I:$ptr),
-                 "[$ptr++] = $val;", []>;
-
-def STORE32i_dec: F1<(outs I:$ptr_wb), (ins D:$val, I:$ptr),
-                 "[$ptr--] = $val;", []>;
-
-def STORE32i_post: F1<(outs I:$ptr_wb), (ins D:$val, I:$ptr, M:$off),
-                      "[$ptr ++ $off] = $val;", []>;
-}
-
-def : Pat<(truncstorei16 D:$val, PI:$ptr),
-          (STORE16pi (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS D:$val, D)),
-                                     lo16), PI:$ptr)>;
-
-def : Pat<(truncstorei16 (srl D:$val, (i16 16)), PI:$ptr),
-          (STORE16pi (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS D:$val, D)),
-                                     hi16), PI:$ptr)>;
-
-def : Pat<(truncstorei8 D16L:$val, P:$ptr),
-          (STORE8p (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
-                                  (i16 (COPY_TO_REGCLASS D16L:$val, D16L)),
-                                  lo16),
-                   P:$ptr)>;
-
-//===----------------------------------------------------------------------===//
-// Table C-11. Move Instructions.
-//===----------------------------------------------------------------------===//
-
-def MOVE: F1<(outs ALL:$dst), (ins ALL:$src),
-             "$dst = $src;",
-             []>;
-
-let Constraints = "$src1 = $dst" in
-def MOVEcc: F1<(outs DP:$dst), (ins DP:$src1, DP:$src2, AnyCC:$cc),
-               "if $cc $dst = $src2;",
-               [(set DP:$dst, (select AnyCC:$cc, DP:$src2, DP:$src1))]>;
-
-let Defs = [AZ, AN, AC0, V] in {
-def MOVEzext: F1<(outs D:$dst), (ins D16L:$src),
-                 "$dst = $src (z);",
-                 [(set D:$dst, (zext D16L:$src))]>;
-
-def MOVEsext: F1<(outs D:$dst), (ins D16L:$src),
-                 "$dst = $src (x);",
-                 [(set D:$dst, (sext D16L:$src))]>;
-
-def MOVEzext8: F1<(outs D:$dst), (ins D:$src),
-                  "$dst = $src.b (z);",
-                  [(set D:$dst, (and D:$src, 0xff))]>;
-
-def MOVEsext8: F1<(outs D:$dst), (ins D:$src),
-                  "$dst = $src.b (x);",
-                  [(set D:$dst, (sext_inreg D:$src, i8))]>;
-
-}
-
-def : Pat<(sext_inreg D16L:$src, i8),
-          (EXTRACT_SUBREG (MOVEsext8
-                           (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
-                                          D16L:$src,
-                                          lo16)),
-                          lo16)>;
-
-def : Pat<(sext_inreg D:$src, i16),
-          (MOVEsext (EXTRACT_SUBREG D:$src, lo16))>;
-
-def : Pat<(and D:$src, 0xffff),
-          (MOVEzext (EXTRACT_SUBREG D:$src, lo16))>;
-
-def : Pat<(i32 (anyext D16L:$src)),
-          (INSERT_SUBREG (i32 (IMPLICIT_DEF)),
-                         (i16 (COPY_TO_REGCLASS D16L:$src, D16L)),
-                         lo16)>;
-
-// TODO Dreg = Dreg_byte (X/Z)
-
-// TODO Accumulator moves
-
-//===----------------------------------------------------------------------===//
-// Table C-12. Stack Control Instructions
-//===----------------------------------------------------------------------===//
-
-let Uses = [SP], Defs = [SP] in {
-def PUSH: F1<(outs), (ins ALL:$src),
-             "[--sp] = $src;", []> { let mayStore = 1; }
-
-// NOTE: POP does not work for DP regs, use LOAD instead
-def POP:  F1<(outs ALL:$dst), (ins),
-             "$dst = [sp++];", []> { let mayLoad = 1; }
-}
-
-// TODO: push/pop multiple
-
-def LINK: F2<(outs), (ins i32imm:$amount),
-             "link $amount;", []>;
-
-def UNLINK: F2<(outs), (ins),
-               "unlink;", []>;
-
-//===----------------------------------------------------------------------===//
-// Table C-13. Control Code Bit Management Instructions
-//===----------------------------------------------------------------------===//
-
-multiclass SETCC<PatFrag opnode, PatFrag invnode, string cond, string suf=";"> {
-  def dd : F1<(outs JustCC:$cc), (ins D:$a, D:$b),
-              !strconcat(!subst("XX", cond, "cc = $a XX $b"), suf),
-              [(set JustCC:$cc, (opnode  D:$a, D:$b))]>;
-
-  def ri : F1<(outs JustCC:$cc), (ins DP:$a, i32imm:$b),
-              !strconcat(!subst("XX", cond, "cc = $a XX $b"), suf),
-              [(set JustCC:$cc, (opnode  DP:$a, imm3:$b))]>;
-
-  def pp : F1<(outs JustCC:$cc), (ins P:$a, P:$b),
-              !strconcat(!subst("XX", cond, "cc = $a XX $b"), suf),
-              []>;
-
-  def ri_not : F1<(outs NotCC:$cc), (ins DP:$a, i32imm:$b),
-                  !strconcat(!subst("XX", cond, "cc = $a XX $b"), suf),
-                  [(set NotCC:$cc, (invnode  DP:$a, imm3:$b))]>;
-}
-
-defm SETEQ  : SETCC<seteq,  setne,  "==">;
-defm SETLT  : SETCC<setlt,  setge,  "<">;
-defm SETLE  : SETCC<setle,  setgt,  "<=">;
-defm SETULT : SETCC<setult, setuge, "<",  " (iu);">;
-defm SETULE : SETCC<setule, setugt, "<=", " (iu);">;
-
-def SETNEdd : F1<(outs NotCC:$cc), (ins D:$a, D:$b),
-                 "cc = $a == $b;",
-                 [(set NotCC:$cc, (setne  D:$a, D:$b))]>;
-
-def : Pat<(setgt  D:$a, D:$b), (SETLTdd  D:$b, D:$a)>;
-def : Pat<(setge  D:$a, D:$b), (SETLEdd  D:$b, D:$a)>;
-def : Pat<(setugt D:$a, D:$b), (SETULTdd D:$b, D:$a)>;
-def : Pat<(setuge D:$a, D:$b), (SETULEdd D:$b, D:$a)>;
-
-// TODO: compare pointer for P-P comparisons
-// TODO: compare accumulator
-
-let Defs = [AC0] in
-def OR_ac0_cc : F1<(outs), (ins JustCC:$cc),
-                   "ac0 \\|= cc;", []>;
-
-let Uses = [AC0] in
-def MOVE_cc_ac0 : F1<(outs JustCC:$cc), (ins),
-                   "cc = ac0;", []>;
-
-def MOVE_ccncc : F1<(outs JustCC:$cc), (ins NotCC:$sb),
-                    "cc = !cc;", []>;
-
-def MOVE_ncccc : F1<(outs NotCC:$cc), (ins JustCC:$sb),
-                    "cc = !cc;", []>;
-
-def MOVECC_zext : F1<(outs D:$dst), (ins JustCC:$cc),
-                      "$dst = $cc;", []>;
-
-def MOVENCC_z : F1<(outs D:$dst), (ins NotCC:$cc),
-                   "$dst = cc;", []>;
-
-def MOVECC_nz : F1<(outs AnyCC:$cc), (ins D:$src),
-                   "cc = $src;",
-                   [(set AnyCC:$cc, (setne D:$src, 0))]>;
-
-//===----------------------------------------------------------------------===//
-// Table C-14. Logical Operations Instructions
-//===----------------------------------------------------------------------===//
-
-def AND: F1<(outs D:$dst), (ins D:$src1, D:$src2),
-            "$dst = $src1 & $src2;",
-            [(set D:$dst, (and D:$src1, D:$src2))]>;
-
-def NOT: F1<(outs D:$dst), (ins D:$src),
-            "$dst = ~$src;",
-            [(set D:$dst, (not D:$src))]>;
-
-def OR: F1<(outs D:$dst), (ins D:$src1, D:$src2),
-           "$dst = $src1 \\| $src2;",
-           [(set D:$dst, (or D:$src1, D:$src2))]>;
-
-def XOR: F1<(outs D:$dst), (ins D:$src1, D:$src2),
-            "$dst = $src1 ^ $src2;",
-            [(set D:$dst, (xor D:$src1, D:$src2))]>;
-
-// missing: BXOR, BXORSHIFT
-
-//===----------------------------------------------------------------------===//
-// Table C-15. Bit Operations Instructions
-//===----------------------------------------------------------------------===//
-
-let Constraints = "$src1 = $dst" in {
-def BITCLR: F1<(outs D:$dst), (ins D:$src1, uimm5imask:$src2),
-              "bitclr($dst, $src2);",
-              [(set D:$dst, (and D:$src1, uimm5imask:$src2))]>;
-
-def BITSET: F1<(outs D:$dst), (ins D:$src1, uimm5mask:$src2),
-              "bitset($dst, $src2);",
-              [(set D:$dst, (or D:$src1, uimm5mask:$src2))]>;
-
-def BITTGL: F1<(outs D:$dst), (ins D:$src1, uimm5mask:$src2),
-              "bittgl($dst, $src2);",
-              [(set D:$dst, (xor D:$src1, uimm5mask:$src2))]>;
-}
-
-def BITTST: F1<(outs JustCC:$cc), (ins D:$src1, uimm5mask:$src2),
-              "cc = bittst($src1, $src2);",
-              [(set JustCC:$cc, (setne (and D:$src1, uimm5mask:$src2),
-                                       (i32 0)))]>;
-
-def NBITTST: F1<(outs JustCC:$cc), (ins D:$src1, uimm5mask:$src2),
-               "cc = !bittst($src1, $src2);",
-               [(set JustCC:$cc, (seteq (and D:$src1, uimm5mask:$src2),
-                                        (i32 0)))]>;
-
-// TODO: DEPOSIT, EXTRACT, BITMUX
-
-def ONES: F2<(outs D16L:$dst), (ins D:$src),
-              "$dst = ones $src;",
-              [(set D16L:$dst, (trunc (ctpop D:$src)))]>;
-
-def : Pat<(ctpop D:$src), (MOVEzext (ONES D:$src))>;
-
-//===----------------------------------------------------------------------===//
-// Table C-16. Shift / Rotate Instructions
-//===----------------------------------------------------------------------===//
-
-multiclass SHIFT32<SDNode opnode, string ops> {
-  def i : F1<(outs D:$dst), (ins D:$src, i16imm:$amount),
-             !subst("XX", ops, "$dst XX= $amount;"),
-             [(set D:$dst, (opnode D:$src, (i16 uimm5:$amount)))]>;
-  def r : F1<(outs D:$dst), (ins D:$src, D:$amount),
-             !subst("XX", ops, "$dst XX= $amount;"),
-             [(set D:$dst, (opnode D:$src, D:$amount))]>;
-}
-
-let Defs = [AZ, AN, V, VS],
-    Constraints = "$src = $dst" in {
-defm SRA : SHIFT32<sra, ">>>">;
-defm SRL : SHIFT32<srl, ">>">;
-defm SLL : SHIFT32<shl, "<<">;
-}
-
-// TODO: automatic switching between 2-addr and 3-addr (?)
-
-let Defs = [AZ, AN, V, VS] in {
-def SLLr16: F2<(outs D:$dst), (ins D:$src, D16L:$amount),
-             "$dst = lshift $src by $amount;",
-             [(set D:$dst, (shl D:$src, D16L:$amount))]>;
-
-// Arithmetic left-shift = saturing overflow.
-def SLAr16: F2<(outs D:$dst), (ins D:$src, D16L:$amount),
-             "$dst = ashift $src by $amount;",
-             [(set D:$dst, (sra D:$src, (ineg D16L:$amount)))]>;
-
-def SRA16i: F1<(outs D16:$dst), (ins D16:$src, i16imm:$amount),
-              "$dst = $src >>> $amount;",
-              [(set D16:$dst, (sra D16:$src, (i16 uimm4:$amount)))]>;
-
-def SRL16i: F1<(outs D16:$dst), (ins D16:$src, i16imm:$amount),
-              "$dst = $src >> $amount;",
-              [(set D16:$dst, (srl D16:$src, (i16 uimm4:$amount)))]>;
-
-// Arithmetic left-shift = saturing overflow.
-def SLA16r: F1<(outs D16:$dst), (ins D16:$src, D16L:$amount),
-              "$dst = ashift $src BY $amount;",
-              [(set D16:$dst, (srl D16:$src, (ineg D16L:$amount)))]>;
-
-def SLL16i: F1<(outs D16:$dst), (ins D16:$src, i16imm:$amount),
-              "$dst = $src << $amount;",
-              [(set D16:$dst, (shl D16:$src, (i16 uimm4:$amount)))]>;
-
-def SLL16r: F1<(outs D16:$dst), (ins D16:$src, D16L:$amount),
-              "$dst = lshift $src by