[Zrouter-src-freebsd] ZRouter.org: push to FreeBSD HEAD tree
zrouter-src-freebsd at zrouter.org
zrouter-src-freebsd at zrouter.org
Sat Jan 21 15:30:22 UTC 2012
details: http://zrouter.org/hg/FreeBSD/head//rev/1f7980008e67
changeset: 286:1f7980008e67
user: ray at terran.dlink.ua
date: Sat Jan 21 17:32:13 2012 +0200
description:
Switch Framework tidyup
diffstat:
head/sys/dev/switch/ar8x16_switch.c | 38 ++-
head/sys/dev/switch/ar8x16_switchreg.h | 6 +-
head/sys/dev/switch/bcm5325_switch.c | 33 +-
head/sys/dev/switch/bcm5325_switchreg.h | 63 +----
head/sys/dev/switch/bcm5325_switchvar.h | 2 +-
head/sys/dev/switch/floatphy.c | 2 +-
head/sys/dev/switch/rt305x_switch.c | 254 +++---------------------
head/sys/dev/switch/rt305x_switchreg.h | 2 +-
head/sys/dev/switch/rt305x_switchvar.h | 2 +-
head/sys/dev/switch/rtl830x_switch.c | 183 +----------------
head/sys/dev/switch/rtl830x_switchreg.h | 332 +++++++++++++++----------------
head/sys/dev/switch/rtl830x_switchvar.h | 2 +-
head/sys/dev/switch/switch.c | 62 +++--
head/sys/dev/switch/switch_if.m | 46 +----
head/sys/dev/switch/switch_ioctl.h | 114 +++++-----
head/sys/dev/switch/switch_mii.c | 8 +-
head/sys/dev/switch/switch_obio.c | 4 +-
head/sys/dev/switch/switchb_if.m | 4 +-
head/sys/dev/switch/switchpub_if.m | 2 +-
head/sys/dev/switch/switchvar.h | 25 +-
20 files changed, 392 insertions(+), 792 deletions(-)
diffs (2046 lines):
diff -r 7cd2c83e9de7 -r 1f7980008e67 head/sys/dev/switch/ar8x16_switch.c
--- a/head/sys/dev/switch/ar8x16_switch.c Sat Jan 21 01:20:20 2012 +0100
+++ b/head/sys/dev/switch/ar8x16_switch.c Sat Jan 21 17:32:13 2012 +0200
@@ -112,6 +112,7 @@
(reg << AR8X16_MDIO_CTRL_REG_ADDR_SHIFT) |
(value & AR8X16_MDIO_CTRL_DATA_MASK));
+ /* TODO: use pause */
if (WAIT4(sc, AR8X16_REG_MDIO_CTRL, AR8X16_MDIO_CTRL_BUSY, 0, 1000))
return (-1);
@@ -131,6 +132,7 @@
(phy << AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT) |
(reg << AR8X16_MDIO_CTRL_REG_ADDR_SHIFT));
+ /* TODO: use pause */
if (WAIT4(sc, AR8X16_REG_MDIO_CTRL, AR8X16_MDIO_CTRL_BUSY, 0, 1000))
return (0xffff);
@@ -143,10 +145,11 @@
struct ar8x16_switch_softc *sc;
sc = device_get_softc(dev);
- if (reg & 0x80000000)
+ if (reg & SWITCH_REG_TYPE_RAW)
*value = READ4(sc, reg);
- else if (reg & 0x40000000)
- *value = miibus_readreg(dev, ((reg >> 8) & 0xff), (reg & 0xff));
+ else if (reg & SWITCH_REG_TYPE_PHY)
+ *value = miibus_readreg(dev, ((reg >> 8) & 0xff),
+ (reg & 0xff));
else
*value = MII_SW_READ4(sc, reg);
return (0);
@@ -159,12 +162,13 @@
uint32_t old;
sc = device_get_softc(dev);
- if (reg & 0x80000000) {
+ if (reg & SWITCH_REG_TYPE_RAW) {
old = READ4(sc, reg);
WRITE4(sc, reg, *value);
- } else if (reg & 0x40000000) {
+ } else if (reg & SWITCH_REG_TYPE_PHY) {
old = miibus_readreg(dev, ((reg >> 8) & 0xff), (reg & 0xff));
- *value = miibus_writereg(dev, ((reg >> 8) & 0xff), (reg & 0xff), *value);
+ *value = miibus_writereg(dev, ((reg >> 8) & 0xff),
+ (reg & 0xff), *value);
} else {
old = MII_SW_READ4(sc, reg);
MII_SW_WRITE4(sc, reg, *value);
@@ -182,6 +186,7 @@
/* Reset the switch. */
WRITE4(sc, AR8X16_REG_MASK_CTRL, AR8X16_MASK_CTRL_SOFT_RESET);
+ /* TODO: use pause */
ret = WAIT4(sc, AR8X16_REG_MASK_CTRL, AR8X16_MASK_CTRL_SOFT_RESET, 0,
1000);
return ret;
@@ -270,8 +275,6 @@
{
uint32_t mode;
- WRITE4(sc, AR8X16_REG_MODE, AR8X16_MODE_DIR_615_MY);
-
mode = READ4(sc, AR8X16_REG_MODE);
if (sc->sc_mii_mode != mode) {
device_printf(sc->sc_dev, "Initializing the switch mode.\n");
@@ -361,7 +364,9 @@
READ4(sc, AR8X16_REG_PORT_CTRL(port)) &
~AR8X16_PORT_CTRL_HEADER);
}
+#if 0
pause("PhyNeg", hz*3);
+#endif
return (0);
}
@@ -398,7 +403,8 @@
sc->caps->main = S_C(MAIN_PORT_POWER);
sc->caps->vlan = S_C(VLAN_GLBL_UNTG) | S_C(VLAN_DOT1Q) |
S_C(VLAN_DOUBLE_TAG) |
- ((sc->vlans << S_C(VLAN_MAX_SHIFT_SHIFT)) & S_C(VLAN_MAX_SHIFT_MASK));
+ ((sc->vlans << S_C(VLAN_MAX_SHIFT_SHIFT)) &
+ S_C(VLAN_MAX_SHIFT_MASK));
sc->caps->qos = (2 << S_C(QOS_QUEUES_SHIFT)) & S_C(QOS_QUEUES_MASK);
sc->caps->lacp = 0; /* No LACP caps */
sc->caps->stp = 0; /* No STP caps */
@@ -457,6 +463,8 @@
sc = device_get_softc(dev);
+ /* TODO */
+
return (idx);
}
@@ -464,6 +472,9 @@
mac_table_write(device_t dev, uint64_t mac, int idx, uint32_t port_map,
uint8_t age, int *hash_idx )
{
+
+ /* TODO */
+
return (0);
}
@@ -517,12 +528,14 @@
if (((reg & 0x300) >> 8) == AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_ADD)
*flags |= DOT1Q_VLAN_PORT_FLAG_TAGGED;
- else if (((reg & 0x300) >> 8) == AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_STRIP)
+ else if (((reg & 0x300) >> 8) ==
+ AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_STRIP)
*flags |= DOT1Q_VLAN_PORT_FLAG_UNTAGGED;
/* Ingress filter */
reg = READ4(sc, AR8X16_REG_PORT_VLAN(port));
- if ((reg >> AR8X16_PORT_VLAN_MODE_SHIFT) & AR8X16_PORT_VLAN_MODE_SECURE)
+ if ((reg >> AR8X16_PORT_VLAN_MODE_SHIFT) &
+ AR8X16_PORT_VLAN_MODE_SECURE)
*flags |= DOT1Q_VLAN_PORT_FLAG_INGRESS;
return (0);
@@ -709,7 +722,8 @@
case SWITCH_RESETSUB_VLANS:
if (WAIT4(sc, AR8X16_REG_VLAN_CTRL, AR8X16_VLAN_ACTIVE, 0, 5))
return (EBUSY);
- WRITE4(sc, AR8X16_REG_VLAN_CTRL, AR8X16_VLAN_ACTIVE | AR8X16_VLAN_OP_FLUSH);
+ WRITE4(sc, AR8X16_REG_VLAN_CTRL,
+ AR8X16_VLAN_ACTIVE | AR8X16_VLAN_OP_FLUSH);
break;
case SWITCH_RESETSUB_QOS:
break;
diff -r 7cd2c83e9de7 -r 1f7980008e67 head/sys/dev/switch/ar8x16_switchreg.h
--- a/head/sys/dev/switch/ar8x16_switchreg.h Sat Jan 21 01:20:20 2012 +0100
+++ b/head/sys/dev/switch/ar8x16_switchreg.h Sat Jan 21 17:32:13 2012 +0200
@@ -38,8 +38,6 @@
#define AR8X16_REG_MODE 0x0008
/* DIR-615 E4 U-Boot */
#define AR8X16_MODE_DIR_615_UBOOT 0x8d1003e0
-/* Mode enable all PHYs and maybe pass MII1 data to PHY4(WAN) (XXX check it) */
-#define AR8X16_MODE_DIR_615_MY 0x814603ea /* (MMI0 - RGMII, MMI1 - RGMII, !PORTx_ISO) */
/* From Ubiquiti RSPRO */
#define AR8X16_MODE_RGMII_PORT4_ISO 0x81461bea
#define AR8X16_MODE_RGMII_PORT4_SWITCH 0x01261be2
@@ -169,6 +167,7 @@
#define AR8X16_PORT_CTRL_STATE_LEARN 3
#define AR8X16_PORT_CTRL_STATE_FORWARD 4
#define AR8X16_PORT_CTRL_LEARN_LOCK (1 << 7)
+#define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_MASK 0x00000300
#define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_SHIFT 8
#define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_KEEP 0
#define AR8X16_PORT_CTRL_EGRESS_VLAN_MODE_STRIP 1
@@ -266,7 +265,8 @@
#define AR8X16_PORT_MASK(_port) (1 << (_port))
#define AR8X16_PORT_MASK_ALL ((1<<AR8X16_NUM_PORTS)-1)
-#define AR8X16_PORT_MASK_BUT(_port) (AR8X16_PORT_MASK_ALL & ~(1 << (_port)))
+#define AR8X16_PORT_MASK_BUT(_port) \
+ (AR8X16_PORT_MASK_ALL & ~(1 << (_port)))
#define AR8X16_MAX_VLANS 16
diff -r 7cd2c83e9de7 -r 1f7980008e67 head/sys/dev/switch/bcm5325_switch.c
--- a/head/sys/dev/switch/bcm5325_switch.c Sat Jan 21 01:20:20 2012 +0100
+++ b/head/sys/dev/switch/bcm5325_switch.c Sat Jan 21 17:32:13 2012 +0200
@@ -189,14 +189,8 @@
res = device_get_ivars(dev);
-//model SWITCHFW BCM5325 0x0201 Broadcom BCM5325 switch family (5354, 53115, etc)
-
/* XXX: bcm5325 show at leaset 5 PHYs */
-#ifdef notyet
- if ((res->phys & 0x1f) != 0x1f)
-#else
if (!res->phys)
-#endif
return (ENXIO);
device_set_desc(dev, "BCM5325 family ethernet switch");
@@ -372,7 +366,9 @@
sc = device_get_softc(dev);
- if (reg & 0x80000000ul) {
+ switch (reg & SWITCH_REG_TYPE_MASK) {
+ case SWITCH_REG_TYPE_PHY: /* Same in BCM53xx case */
+ case SWITCH_REG_TYPE_RAW:
*value = MII_SW_READ4(sc, reg);
return (0);
}
@@ -404,7 +400,9 @@
sc = device_get_softc(dev);
- if (reg & 0x80000000ul) {
+ switch (reg & SWITCH_REG_TYPE_MASK) {
+ case SWITCH_REG_TYPE_PHY: /* Same in BCM53xx case */
+ case SWITCH_REG_TYPE_RAW:
old = MII_SW_READ4(sc, reg);
MII_SW_WRITE4(sc, reg, *value);
*value = old;
@@ -542,7 +540,8 @@
}
static int
-bcm5325_vlan_write(struct bcm5325_switch_softc *sc, uint16_t vid, uint8_t tports, uint8_t uports)
+bcm5325_vlan_write(struct bcm5325_switch_softc *sc, uint16_t vid,
+ uint8_t tports, uint8_t uports)
{
uint64_t reg;
int error = 0;
@@ -561,7 +560,8 @@
}
static int
-bcm5325_vlan_read(struct bcm5325_switch_softc *sc, uint16_t vid, uint8_t *tports, uint8_t *uports)
+bcm5325_vlan_read(struct bcm5325_switch_softc *sc, uint16_t vid,
+ uint8_t *tports, uint8_t *uports)
{
uint64_t reg;
int error = 0;
@@ -580,7 +580,8 @@
if (tports != NULL)
*tports = (reg & VLAN_RW_MEMBER_MASK) >> VLAN_RW_MEMBER_SHIFT;
if (uports != NULL)
- *uports = (reg & VLAN_RW_UNTAGGED_MASK) >> VLAN_RW_UNTAGGED_SHIFT;
+ *uports =
+ (reg & VLAN_RW_UNTAGGED_MASK) >> VLAN_RW_UNTAGGED_SHIFT;
return (error);
}
@@ -592,7 +593,6 @@
* VID = base_vlan << 4(or 8, dep on chip) + idx.
* When base_vlan not equal with previouse value, WARNING displayed.
*/
-
static int
set_vid(device_t dev, int idx, uint16_t vid)
{
@@ -607,7 +607,8 @@
base_vlan_mask = ~(sc->vlans - 1);
if ((vid & base_vlan_mask) != sc->base_vlan) {
sc->base_vlan = (vid & base_vlan_mask);
- device_printf(sc->sc_dev, "WARNING: Base VLAN changed %04x\n", sc->base_vlan);
+ device_printf(sc->sc_dev, "WARNING: Base VLAN changed %04x\n",
+ sc->base_vlan);
}
error = bcm5325_vlan_read(sc, vid, NULL, NULL);
@@ -691,7 +692,8 @@
return (EINVAL);
bcm5325_vlan_read(sc, idx /* must be vid */, &memb, NULL);
- error = bcm5325_vlan_write(sc, idx /* must be vid */, memb | umemb, umemb);
+ error = bcm5325_vlan_write(sc, idx /* must be vid */, memb | umemb,
+ umemb);
return (error);
}
@@ -755,6 +757,7 @@
};
static devclass_t bcm5325_switch_devclass;
-DRIVER_MODULE(bcm5325_switch, switch, bcm5325_switch_driver, bcm5325_switch_devclass, 0, 0);
+DRIVER_MODULE(bcm5325_switch, switch, bcm5325_switch_driver,
+ bcm5325_switch_devclass, 0, 0);
MODULE_VERSION(bcm5325_switch, 1);
MODULE_DEPEND(bcm5325_switch, switch, 1, 1, 1);
diff -r 7cd2c83e9de7 -r 1f7980008e67 head/sys/dev/switch/bcm5325_switchreg.h
--- a/head/sys/dev/switch/bcm5325_switchreg.h Sat Jan 21 01:20:20 2012 +0100
+++ b/head/sys/dev/switch/bcm5325_switchreg.h Sat Jan 21 17:32:13 2012 +0200
@@ -104,14 +104,14 @@
#define PORTMII_STATUS_FORCE_LINK 0x01
#define POWER_DOWN_MODE (S1 | PAGE(0x00) | 0x0f)
-#define PORT7_POWER_DOWN 0x80
-#define PORT6_POWER_DOWN 0x40
-#define PORT5_POWER_DOWN 0x20
-#define PORT4_POWER_DOWN 0x10
-#define PORT3_POWER_DOWN 0x08
-#define PORT2_POWER_DOWN 0x04
-#define PORT1_POWER_DOWN 0x02
-#define PORT0_POWER_DOWN 0x01 /* Do not set bit 0 to 1.
+#define PORT7_POWER_DOWN 0x80
+#define PORT6_POWER_DOWN 0x40
+#define PORT5_POWER_DOWN 0x20
+#define PORT4_POWER_DOWN 0x10
+#define PORT3_POWER_DOWN 0x08
+#define PORT2_POWER_DOWN 0x04
+#define PORT1_POWER_DOWN 0x02
+#define PORT0_POWER_DOWN 0x01 /* Do not set bit 0 to 1.
* Doing so will disable
* the PLL power and the
* switch function. */
@@ -207,39 +207,6 @@
#define SECURE_DST_PORT_MASK (S2 | PAGE(0x04) | 0x32)
#define SECURE_DST_PORT(_p) (1 << (_p))
-#if 0 /* Switch internal usage */
-struct arl_ucast_entry {
- uint8_t mac[6];
- uint16_t mixed;
-#define MIXED_RXPORT_MASK 0x000f
-#define MIXED_DID_MASK 0x0030
-#define MIXED_DID_SHIFT 4
-#define MIXED_BID_MASK 0x0040
-#define MIXED_BID_SHIFT 6
-#define MIXED_VID_LOW_MASK 0x0780
-#define MIXED_VID_LOW_SHIFT 7
-#define MIXED_PRIO_MASK 0x1800
-#define MIXED_PRIO_SHIFT 11
-#define MIXED_AGE_MASK 0x2000
-#define MIXED_AGE_SHIFT 13
-#define MIXED_STATIC_MASK 0x4000
-#define MIXED_STATIC_SHIFT 14
-#define MIXED_VALID_MASK 0x8000
-#define MIXED_VALID_SHIFT 15
- uint8_t vid_high;
-};
-
-struct arl_mcast_entry {
- uint8_t mac[6];
- uint16_t mixed;
-/* XXX: how this can be applied to sw w/ 8 PHY ports */
-#define MIXED_MCAST_PORT_MASK 0x007f
-#define MIXED_RSVD_MASK 0x2000
-#define MIXED_RSVD_SHIFT 13
- uint8_t vid_high;
-};
-#endif
-
#define ARL_RW_CTL (S1 | PAGE(0x05) | 0x00)
#define ARL_RW_CTL_START 0x80
#define ARL_RW_CTL_DONE 0x80
@@ -317,7 +284,7 @@
Page PRT, Address 30h-31h Auxiliary Control/Status Register
Page PRT, Address 32h-33h Auxiliary Status Summary Register
Page PRT, Address 36h-37h Auxiliary Mode 2
-Page PRT, Address 38h-39h 10BASE-T Auxiliary Error & General Status Register
+Page PRT, Address 38h-39h 10BASE-T Auxiliary Error & General Status
Page PRT, Address 3Ch-3Dh Auxiliary Multiple PHY Register
Page PRT, Address 3Eh-3Fh Broadcom Test
Page PRT, Address 1Eh-1Fh DPM Register
@@ -394,12 +361,12 @@
#define DSCP_TO_QUEUE(_d, _q) ((_q) << (((_d) & 0x3f) * 2))
/* BCM5395/5397/5398/53115 */
-#define ROBO_VTBL_ACCESS 0x60 /* VLAN table access: 8bit */
-#define ROBO_VTBL_INDX 0x61 /* VLAN table address index: 16bit */
-#define ROBO_VTBL_ENTRY 0x63 /* VLAN table entry: 32bit */
-#define ROBO_VTBL_ACCESS_5395 0x80 /* VLAN table access: 8bit */
-#define ROBO_VTBL_INDX_5395 0x81 /* VLAN table address index: 16bit */
-#define ROBO_VTBL_ENTRY_5395 0x83 /* VLAN table entry: 32bit */
+#define ROBO_VTBL_ACCESS 0x60 /* VLAN table access: 8bit */
+#define ROBO_VTBL_INDX 0x61 /* VLAN table address index: 16bit */
+#define ROBO_VTBL_ENTRY 0x63 /* VLAN table entry: 32bit */
+#define ROBO_VTBL_ACCESS_5395 0x80 /* VLAN table access: 8bit */
+#define ROBO_VTBL_INDX_5395 0x81 /* VLAN table address index: 16bit */
+#define ROBO_VTBL_ENTRY_5395 0x83 /* VLAN table entry: 32bit */
#define VLAN_GLOBAL_CTL0 (S1 | PAGE(0x34) | 0x00)
diff -r 7cd2c83e9de7 -r 1f7980008e67 head/sys/dev/switch/bcm5325_switchvar.h
--- a/head/sys/dev/switch/bcm5325_switchvar.h Sat Jan 21 01:20:20 2012 +0100
+++ b/head/sys/dev/switch/bcm5325_switchvar.h Sat Jan 21 17:32:13 2012 +0200
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2011 Aleksandr Rybalko.
+ * Copyright (c) 2011,2012 Aleksandr Rybalko.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff -r 7cd2c83e9de7 -r 1f7980008e67 head/sys/dev/switch/floatphy.c
--- a/head/sys/dev/switch/floatphy.c Sat Jan 21 01:20:20 2012 +0100
+++ b/head/sys/dev/switch/floatphy.c Sat Jan 21 17:32:13 2012 +0200
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2012, Aleksandr Rybalko
+ * Copyright (c) 2011-2012 Aleksandr Rybalko
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff -r 7cd2c83e9de7 -r 1f7980008e67 head/sys/dev/switch/rt305x_switch.c
--- a/head/sys/dev/switch/rt305x_switch.c Sat Jan 21 01:20:20 2012 +0100
+++ b/head/sys/dev/switch/rt305x_switch.c Sat Jan 21 17:32:13 2012 +0200
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2010-2011 Aleksandr Rybalko.
+ * Copyright (c) 2010-2012 Aleksandr Rybalko.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -66,14 +66,7 @@
static int get_port_speed(device_t dev, int port);
static int force_port_mode(device_t dev, int port, uint32_t mode);
-#ifdef mustbe_rewriten
-static uint32_t stat_good_in_packet_count(device_t dev, int port);
-static uint32_t stat_good_out_packet_count(device_t dev, int port);
-static uint32_t stat_bad_in_packet_count(device_t dev, int port);
-static uint32_t stat_bad_out_packet_count(device_t dev, int port);
-#endif
-
-static int rt305x_switch_isr(void *arg);
+static int rt305x_switch_isr(void *arg);
static int
rt305x_switch_probe(device_t dev)
@@ -82,7 +75,6 @@
res = device_get_ivars(dev);
-//model SWITCHFW RT305X 0x0601 Ralink RT3050F/RT3052F internal switch
/* rt305x internal switch require mem region */
if (res->memres_size < (RT_SW_P5PC - RT_SW_ISR))
return (ENXIO);
@@ -106,36 +98,33 @@
reg = READ4(sc, RT_SW_MTI);
if (reg & AT_RAM_TEST_FAIL) {
- printf("rt305x_switch: Address Table RAM test failed\n");
+ device_printf(dev, "Address Table RAM test failed\n");
return (ENXIO);
}
if (reg & LK_RAM_TEST_FAIL) {
- printf("rt305x_switch: Link RAM test failed\n");
+ device_printf(dev, "Link RAM test failed\n");
return (ENXIO);
}
if (reg & DT_RAM_TEST_FAIL) {
- printf("rt305x_switch: Data buffer RAM test failed\n");
+ device_printf(dev, "Data buffer RAM test failed\n");
return (ENXIO);
}
if (!(reg & SW_RAM_TEST_DONE))
- printf(
- "rt305x_switch: WARNING: Switch memory test not done\n");
+ device_printf(dev, "WARNING: Switch memory test not done\n");
if (!(reg & AT_RAM_TEST_DONE))
- printf(
- "rt305x_switch: WARNING: Address Table RAM test not done\n");
+ device_printf(dev,
+ "WARNING: Address Table RAM test not done\n");
if (!(reg & LK_RAM_TEST_DONE))
- printf(
- "rt305x_switch: WARNING: Link RAM test not done\n");
+ device_printf(dev, "WARNING: Link RAM test not done\n");
if (!(reg & DT_RAM_TEST_DONE))
- printf(
- "rt305x_switch: WARNING: Data buffer RAM test not done\n");
+ device_printf(dev, "WARNING: Data buffer RAM test not done\n");
if (!(reg & (SW_RAM_TEST_DONE | AT_RAM_TEST_DONE |
LK_RAM_TEST_DONE | DT_RAM_TEST_DONE))) {
- printf(
- "rt305x_switch: ERROR: All RAM tests not done or not RT305xF"
- " internal switch\n");
+ device_printf(dev,
+ "ERROR: All RAM tests not done or not RT305xF"
+ " internal switch\n");
return (ENXIO);
}
@@ -182,13 +171,20 @@
set_port_vid(dev, 4, 1);
set_port_vid(dev, 5, 1);
set_port_vid(dev, 6, 1);
- set_port_flags(dev, 0, DOT1Q_VLAN_PORT_FLAG_UNTAGGED|DOT1Q_VLAN_PORT_FLAG_LAN);
- set_port_flags(dev, 1, DOT1Q_VLAN_PORT_FLAG_UNTAGGED|DOT1Q_VLAN_PORT_FLAG_LAN);
- set_port_flags(dev, 2, DOT1Q_VLAN_PORT_FLAG_UNTAGGED|DOT1Q_VLAN_PORT_FLAG_LAN);
- set_port_flags(dev, 3, DOT1Q_VLAN_PORT_FLAG_UNTAGGED|DOT1Q_VLAN_PORT_FLAG_LAN);
- set_port_flags(dev, 4, DOT1Q_VLAN_PORT_FLAG_UNTAGGED|DOT1Q_VLAN_PORT_FLAG_LAN);
- set_port_flags(dev, 5, DOT1Q_VLAN_PORT_FLAG_UNTAGGED|DOT1Q_VLAN_PORT_FLAG_LAN);
- set_port_flags(dev, 6, DOT1Q_VLAN_PORT_FLAG_UNTAGGED|DOT1Q_VLAN_PORT_FLAG_LAN);
+ set_port_flags(dev, 0, DOT1Q_VLAN_PORT_FLAG_UNTAGGED|
+ DOT1Q_VLAN_PORT_FLAG_LAN);
+ set_port_flags(dev, 1, DOT1Q_VLAN_PORT_FLAG_UNTAGGED|
+ DOT1Q_VLAN_PORT_FLAG_LAN);
+ set_port_flags(dev, 2, DOT1Q_VLAN_PORT_FLAG_UNTAGGED|
+ DOT1Q_VLAN_PORT_FLAG_LAN);
+ set_port_flags(dev, 3, DOT1Q_VLAN_PORT_FLAG_UNTAGGED|
+ DOT1Q_VLAN_PORT_FLAG_LAN);
+ set_port_flags(dev, 4, DOT1Q_VLAN_PORT_FLAG_UNTAGGED|
+ DOT1Q_VLAN_PORT_FLAG_LAN);
+ set_port_flags(dev, 5, DOT1Q_VLAN_PORT_FLAG_UNTAGGED|
+ DOT1Q_VLAN_PORT_FLAG_LAN);
+ set_port_flags(dev, 6, DOT1Q_VLAN_PORT_FLAG_UNTAGGED|
+ DOT1Q_VLAN_PORT_FLAG_LAN);
set_vid(dev, 0, 1);
set_vlan_ports(dev, 0, 0x7f);
@@ -261,7 +257,6 @@
printf("%s: port=%d\n", __func__, port);
}
-
static int
rt305x_switch_isr(void *arg)
{
@@ -352,7 +347,6 @@
return (FILTER_HANDLED);
}
-
/*
* Switch interface methods
*/
@@ -366,7 +360,6 @@
return (sc->caps);
}
-
static int
find_mac_addr(device_t dev, uint64_t mac)
{
@@ -389,23 +382,7 @@
mac_table_write(device_t dev, uint64_t mac, int idx, uint32_t port_map,
uint8_t age, int *hash_idx )
{
- struct rt305x_switch_softc *sc = device_get_softc(dev);
- uint32_t reg;
-
- WRITE4(sc, RT_SW_WMAD1, (uint32_t)mac & 0xffff);
- WRITE4(sc, RT_SW_WMAD2, (uint32_t)(mac >> 16) & 0xffffffff);
-
- reg = READ4(sc, RT_SW_WMAD0);
-
-/*XXX test !(reg & W_MAC_CMD)*/
-
- WRITE4(sc, RT_SW_WMAD0,
- ((port_map << WMAD0_W_PORT_MAP_SHIFT) & WMAD0_W_PORT_MAP_MASK) |
- ((idx << WMAD0_W_INDEX_SHIFT) & WMAD0_W_INDEX_MASK) |
- ((age << WMAD0_W_AGE_FLD_SHIFT) & WMAD0_W_AGE_FLD_MASK) |
- WMAD0_W_MC_INGRESS | WMAD0_W_MAC_CMD);
-
-/*XXX test !(reg & W_MAC_CMD) && reg & W_MAC_DONE*/
+ /* TODO */
return (0);
}
@@ -574,49 +551,6 @@
return (0);
}
-#if 0
-/* Use global tagging option */
-static int
-set_vlan_untagged_ports(device_t dev, int idx, uint32_t memb)
-{
- struct rt305x_switch_softc *sc = device_get_softc(dev);
- uint32_t reg;
-
- printf("%s: idx=%d, memb=%08x\n", __func__, idx, memb);
-
- if (idx > (sc->vlans - 1))
- return (EINVAL);
- if (memb & ~((1 << sc->ports) - 1))
- return (EINVAL);
-
- /* RT305XF support only global port untaged flags */
- reg = READ4(sc, RT_SW_POC2);
- reg &= ~((1 << sc->ports) - 1);
- reg |= (((1 << sc->ports) - 1) & memb);
- WRITE4(sc, RT_SW_POC2, reg);
-
- return (0);
-}
-
-static uint32_t
-get_vlan_untagged_ports(device_t dev, int idx, uint32_t *memb)
-{
- struct rt305x_switch_softc *sc = device_get_softc(dev);
- uint32_t reg;
-
- if (idx > (sc->vlans - 1))
- return (EINVAL);
-
- /* RT305XF support only global port untaged flags */
- reg = READ4(sc, RT_SW_POC2);
- reg &= ((1 << sc->ports) - 1);
-
- printf("%s: idx=%d, memb=%08x\n", __func__, idx, reg);
- *memb = reg;
- return (0);
-}
-#endif
-
static int
get_port_link(device_t dev, int port)
{
@@ -712,115 +646,6 @@
return (0);
}
-#ifdef mustbe_rewriten
-static uint32_t
-stat_good_in_packet_count(device_t dev, int port)
-{
- struct rt305x_switch_softc *sc;
- uint32_t reg;
-
- sc = device_get_softc(dev);
- if (port < 6) {
- reg = READ4(sc, RT_SW_P0PC);
- reg &= GOOD_PCOUNT_MASK;
- reg >>= GOOD_PCOUNT_SHIFT;
- return (reg);
- }
-
- if (port < 7) {
- reg = READ4(sc, RT_SW_PPC);
- reg >>= SW2FE_CNT_SHIFT;
- return (reg & 0xffff);
- }
-
- return (~0);
-}
-
-static uint32_t
-stat_good_out_packet_count(device_t dev, int port)
-{
- struct rt305x_switch_softc *sc;
- uint32_t reg;
-
- sc = device_get_softc(dev);
- if (port < 6) {
- /* PHY ports have only sum couters */
- reg = READ4(sc, RT_SW_P0PC);
- reg &= GOOD_PCOUNT_MASK;
- reg >>= GOOD_PCOUNT_SHIFT;
- return (reg);
- }
-
- if (port < 7) {
- reg = READ4(sc, RT_SW_PPC);
- reg >>= FE2SW_CNT_SHIFT;
- return (reg & 0xffff);
- }
-
- return (~0);
-}
-
-static uint32_t
-stat_bad_in_packet_count(device_t dev, int port)
-{
- struct rt305x_switch_softc *sc;
- uint32_t reg;
-
- sc = device_get_softc(dev);
- if (port < 6) {
- reg = READ4(sc, RT_SW_P0PC);
- reg &= BAD_PCOUNT_MASK;
- reg >>= BAD_PCOUNT_SHIFT;
- return (reg);
- }
-
- if (port < 7) {
- /* Port 6 always good :) */
- return (0);
- }
-
- return (~0);
-}
-
-static uint32_t
-stat_bad_out_packet_count(device_t dev, int port)
-{
- struct rt305x_switch_softc *sc;
- uint32_t reg;
-
- sc = device_get_softc(dev);
- if (port < 6) {
- /* PHY ports have only sum couters */
- reg = READ4(sc, RT_SW_P0PC);
- reg &= BAD_PCOUNT_MASK;
- reg >>= BAD_PCOUNT_SHIFT;
- return (reg);
- }
-
- if (port < 7) {
- /* Port 6 always good :) */
- return (0);
- }
-
- return (~0);
-}
-#endif
-
-#define RT_SW_PCR0 0xc0
-#define PCR0_NWAY_MASK 0xffff0000
-#define PCR0_NWAY_SHIFT 16
-#define PCR0_PHY_READ (1 << 14)
-#define PCR0_PHY_WRITE (1 << 13)
-#define PCR0_REGADDR_MASK 0x00001f00
-#define PCR0_REGADDR_SHIFT 8
-#define PCR0_PHYADDR_MASK 0x0000001f
-#define PCR0_PHYADDR_SHIFT 0
-#define RT_SW_PCR1 0xc4
-#define PCR1_PHYDATA_MASK 0xffff0000
-#define PCR1_PHYDATA_SHIFT 16
-#define PCR1_PHY_READ_DONE (1 << 1)
-#define PCR1_PHY_WRITE_DONE (1 << 0)
-
static int
miibus_writereg(device_t dev, int phy, int reg, int value)
{
@@ -865,9 +690,9 @@
struct rt305x_switch_softc *sc;
sc = device_get_softc(dev);
- if (reg & 0x80000000)
+ if (reg & SWITCH_REG_TYPE_RAW)
*value = READ4(sc, reg & 0xffff);
- else if (reg & 0x40000000)
+ else if (reg & SWITCH_REG_TYPE_PHY)
*value = miibus_readreg(dev, ((reg >> 8) & 0xff),
(reg & 0xff));
else
@@ -882,10 +707,10 @@
uint32_t old;
sc = device_get_softc(dev);
- if (reg & 0x80000000) {
+ if (reg & SWITCH_REG_TYPE_RAW) {
old = READ4(sc, reg & 0xffff);
WRITE4(sc, reg & 0xffff, *value);
- } else if (reg & 0x40000000) {
+ } else if (reg & SWITCH_REG_TYPE_PHY) {
old = miibus_readreg(dev, ((reg >> 8) & 0xff), (reg & 0xff));
*value = miibus_writereg(dev, ((reg >> 8) & 0xff),
(reg & 0xff), *value);
@@ -925,9 +750,7 @@
}
break;
case SWITCH_RESETSUB_VLANS:
-// if (WAIT4(sc, AR8X16_REG_VLAN_CTRL, AR8X16_VLAN_ACTIVE, 0, 5))
-// return (EBUSY);
-// WRITE4(sc, AR8X16_REG_VLAN_CTRL, AR8X16_VLAN_ACTIVE | AR8X16_VLAN_OP_FLUSH);
+ /* TODO */
break;
case SWITCH_RESETSUB_QOS:
break;
@@ -966,14 +789,6 @@
DEVMETHOD(switch_get_portspeed, get_port_speed),
DEVMETHOD(switch_force_mode, force_port_mode),
-#ifdef mustbe_rewriten
- /* Statistics */
- DEVMETHOD(switch_good_in_cnt, stat_good_in_packet_count),
- DEVMETHOD(switch_good_out_cnt, stat_good_out_packet_count),
- DEVMETHOD(switch_bad_in_cnt, stat_bad_in_packet_count),
- DEVMETHOD(switch_bad_out_cnt, stat_bad_out_packet_count),
-#endif
-
{0, 0},
};
@@ -984,7 +799,8 @@
};
static devclass_t rt305x_switch_devclass;
-DRIVER_MODULE(rt305x_switch, switch, rt305x_switch_driver, rt305x_switch_devclass, 0, 0);
+DRIVER_MODULE(rt305x_switch, switch, rt305x_switch_driver,
+ rt305x_switch_devclass, 0, 0);
MODULE_VERSION(rt305x_switch, 1);
MODULE_DEPEND(rt305x_switch, switch, 1, 1, 1);
diff -r 7cd2c83e9de7 -r 1f7980008e67 head/sys/dev/switch/rt305x_switchreg.h
--- a/head/sys/dev/switch/rt305x_switchreg.h Sat Jan 21 01:20:20 2012 +0100
+++ b/head/sys/dev/switch/rt305x_switchreg.h Sat Jan 21 17:32:13 2012 +0200
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2010-2011 Aleksandr Rybalko.
+ * Copyright (c) 2010-2012 Aleksandr Rybalko.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff -r 7cd2c83e9de7 -r 1f7980008e67 head/sys/dev/switch/rt305x_switchvar.h
--- a/head/sys/dev/switch/rt305x_switchvar.h Sat Jan 21 01:20:20 2012 +0100
+++ b/head/sys/dev/switch/rt305x_switchvar.h Sat Jan 21 17:32:13 2012 +0200
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2010-2011 Aleksandr Rybalko.
+ * Copyright (c) 2010-2012 Aleksandr Rybalko.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff -r 7cd2c83e9de7 -r 1f7980008e67 head/sys/dev/switch/rtl830x_switch.c
--- a/head/sys/dev/switch/rtl830x_switch.c Sat Jan 21 01:20:20 2012 +0100
+++ b/head/sys/dev/switch/rtl830x_switch.c Sat Jan 21 17:32:13 2012 +0200
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2011 Aleksandr Rybalko.
+ * Copyright (c) 2011,2012 Aleksandr Rybalko.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -56,9 +56,9 @@
static int set_port_vid_idx(struct rtl830x_switch_softc *sc, int port,
int idx);
static int get_reg(device_t dev, uint32_t reg, uint32_t *value);
-static int set_reg(device_t dev, uint32_t reg, uint32_t *value);
+static int set_reg(device_t dev, uint32_t reg, uint32_t *value);
static int set_port_vid(device_t dev, int port, uint16_t pvid);
-static int get_port_vid(device_t dev, int port, uint16_t *pvid);
+static int get_port_vid(device_t dev, int port, uint16_t *pvid);
static int set_vid(device_t dev, int idx, uint16_t vid);
static int get_vid(device_t dev, int idx, uint16_t *vid);
static int set_vlan_ports(device_t dev, int idx, uint32_t memb);
@@ -68,30 +68,14 @@
static int get_port_speed(device_t dev, int port);
static int force_port_mode(device_t dev, int port, uint32_t mode);
-#ifdef mustbe_rewriten
-static uint32_t stat_good_in_packet_count(device_t dev, int port);
-static uint32_t stat_good_out_packet_count(device_t dev, int port);
-static uint32_t stat_bad_in_packet_count(device_t dev, int port);
-static uint32_t stat_bad_out_packet_count(device_t dev, int port);
-#endif
-
-
static int
rtl830x_switch_probe(device_t dev)
{
struct child_res_avl *res;
res = device_get_ivars(dev);
-//model SWITCHFW RTL830x 0x0701 Realtek RTL8306/RTL8309
-#define RTL830X_PHYMASK 0x000001ff
-
- /* rtl830x internal switch require PHYs set */
- if ((res->phys & RTL830X_PHYMASK) != RTL830X_PHYMASK)
- return (ENXIO);
-
-
- device_set_desc(dev, "RT305XF internal ethernet switch");
+ device_set_desc(dev, "RTL830x ethernet switch");
return (BUS_PROBE_DEFAULT);
}
@@ -118,7 +102,8 @@
#define S_C(x) SWITCH_CAPS_ ## x
sc->caps->main = S_C(MAIN_PORT_POWER);
sc->caps->vlan = S_C(VLAN_DOT1Q) | S_C(VLAN_DOUBLE_TAG) |
- ((sc->vlans << S_C(VLAN_MAX_SHIFT_SHIFT)) & S_C(VLAN_MAX_SHIFT_MASK));
+ ((sc->vlans << S_C(VLAN_MAX_SHIFT_SHIFT)) &
+ S_C(VLAN_MAX_SHIFT_MASK));
sc->caps->qos = (2 << S_C(QOS_QUEUES_SHIFT)) & S_C(QOS_QUEUES_MASK);
sc->caps->lacp = 0; /* No LACP caps */
sc->caps->stp = 0; /* No STP caps */
@@ -157,10 +142,11 @@
/* Insert tag on ingress packet */
for (i = 1; i < 8; i++)
- WRITE4(sc, PHY_CTRL0(i), (READ4(sc, PHY_CTRL0(i)) & 0xfffc) | CTRL0_TAG_I_UTG);
+ WRITE4(sc, PHY_CTRL0(i), (READ4(sc, PHY_CTRL0(i)) & 0xfffc) |
+ CTRL0_TAG_I_UTG);
WRITE4(sc, GCNTRL0,
- (6 << GCNTRL0_LED_MODE_SHIFT) | /* LED Mode 6: Activity, Speed, Link */
+ (6 << GCNTRL0_LED_MODE_SHIFT) | /* LED Mode6: Activity,Speed,Link */
GCNTRL0_INGRESS_CHECK_DIS |
GCNTRL0_TAG_ONLY_DIS |
GCNTRL0_TX_FC |
@@ -189,7 +175,8 @@
/* Remove isolate flag */
for (i = 1; i < 8; i++)
- WRITE4(sc, PHY_CTL(i), READ4(sc, PHY_CTL(i)) & ~PHY_CTL_ISOLATE);
+ WRITE4(sc, PHY_CTL(i),
+ READ4(sc, PHY_CTL(i)) & ~PHY_CTL_ISOLATE);
return (0);
}
@@ -543,49 +530,6 @@
return (0);
}
-#if 0
-/* Use global tagging option */
-static int
-set_vlan_untagged_ports(device_t dev, int idx, uint32_t memb)
-{
- struct rtl830x_switch_softc *sc = device_get_softc(dev);
- uint32_t reg;
-
- printf("%s: idx=%d, memb=%08x\n", __func__, idx, memb);
-
- if (idx > (sc->vlans - 1))
- return (EINVAL);
- if (memb & ~((1 << sc->ports) - 1))
- return (EINVAL);
-
- /* RT305XF support only global port untaged flags */
- reg = READ4(sc, PHY0_CTL);
- reg &= ~((1 << sc->ports) - 1);
- reg |= (((1 << sc->ports) - 1) & memb);
- WRITE4(sc, PHY0_CTL, reg);
-
- return (0);
-}
-
-static uint32_t
-get_vlan_untagged_ports(device_t dev, int idx, uint32_t *memb)
-{
- struct rtl830x_switch_softc *sc = device_get_softc(dev);
- uint32_t reg;
-
- if (idx > (sc->vlans - 1))
- return (EINVAL);
-
- /* RT305XF support only global port untaged flags */
- reg = READ4(sc, PHY0_CTL);
- reg &= ((1 << sc->ports) - 1);
-
- printf("%s: idx=%d, memb=%08x\n", __func__, idx, reg);
- *memb = reg;
- return (0);
-}
-#endif
-
static int
get_port_link(device_t dev, int port)
{
@@ -694,100 +638,6 @@
return;
}
-#ifdef mustbe_rewriten
-static uint32_t
-stat_good_in_packet_count(device_t dev, int port)
-{
- struct rtl830x_switch_softc *sc;
- uint32_t reg;
-
- sc = device_get_softc(dev);
- if (port < 6) {
- reg = READ4(sc, PHY0_CTL);
- reg &= 0xffff0000;
- reg >>= 16;
- return (reg);
- }
-
- if (port < 7) {
- reg = READ4(sc, PHY0_CTL);
- reg >>= 16;
- return (reg & 0xffff);
- }
-
- return (~0);
-}
-
-static uint32_t
-stat_good_out_packet_count(device_t dev, int port)
-{
- struct rtl830x_switch_softc *sc;
- uint32_t reg;
-
- sc = device_get_softc(dev);
- if (port < 6) {
- /* PHY ports have only sum couters */
- reg = READ4(sc, PHY0_CTL);
- reg &= 0xffff0000;
- reg >>= 16;
- return (reg);
- }
-
- if (port < 7) {
- reg = READ4(sc, PHY0_CTL);
- reg >>= 16;
- return (reg & 0xffff);
- }
-
- return (~0);
-}
-
-static uint32_t
-stat_bad_in_packet_count(device_t dev, int port)
-{
- struct rtl830x_switch_softc *sc;
- uint32_t reg;
-
- sc = device_get_softc(dev);
- if (port < 6) {
- reg = READ4(sc, PHY0_CTL);
- reg &= 0xffff0000;
- reg >>= 16;
- return (reg);
- }
-
- if (port < 7) {
- /* Port 6 always good :) */
- return (0);
- }
-
- return (~0);
-}
-
-static uint32_t
-stat_bad_out_packet_count(device_t dev, int port)
-{
- struct rtl830x_switch_softc *sc;
- uint32_t reg;
-
- sc = device_get_softc(dev);
- if (port < 6) {
- /* PHY ports have only sum couters */
- reg = READ4(sc, PHY0_CTL);
- reg &= 0xffff0000;
- reg >>= 16;
- return (reg);
- }
-
- if (port < 7) {
- /* Port 6 always good :) */
- return (0);
- }
-
- return (~0);
-}
-#endif
-
static device_method_t rtl830x_switch_methods[] = {
DEVMETHOD(device_probe, rtl830x_switch_probe),
DEVMETHOD(device_attach, rtl830x_switch_attach),
@@ -818,14 +668,6 @@
DEVMETHOD(switch_force_mode, force_port_mode),
DEVMETHOD(switch_tick, rtl830x_tick),
-#ifdef mustbe_rewriten
- /* Statistics */
- DEVMETHOD(switch_good_in_cnt, stat_good_in_packet_count),
- DEVMETHOD(switch_good_out_cnt, stat_good_out_packet_count),
- DEVMETHOD(switch_bad_in_cnt, stat_bad_in_packet_count),
- DEVMETHOD(switch_bad_out_cnt, stat_bad_out_packet_count),
-#endif
-
{0, 0},
};
@@ -836,7 +678,8 @@
};
static devclass_t rtl830x_switch_devclass;
-DRIVER_MODULE(rtl830x_switch, switch, rtl830x_switch_driver, rtl830x_switch_devclass, 0, 0);
+DRIVER_MODULE(rtl830x_switch, switch, rtl830x_switch_driver,
+ rtl830x_switch_devclass, 0, 0);
MODULE_VERSION(rtl830x_switch, 1);
MODULE_DEPEND(rtl830x_switch, switch, 1, 1, 1);
diff -r 7cd2c83e9de7 -r 1f7980008e67 head/sys/dev/switch/rtl830x_switchreg.h
--- a/head/sys/dev/switch/rtl830x_switchreg.h Sat Jan 21 01:20:20 2012 +0100
+++ b/head/sys/dev/switch/rtl830x_switchreg.h Sat Jan 21 17:32:13 2012 +0200
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2011 Aleksandr Rybalko.
+ * Copyright (c) 2011,2012 Aleksandr Rybalko.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -27,7 +27,7 @@
*/
#ifndef _RTL830X_SWITCHREG_H_
-#define _RTL830X_SWITCHREG_H_
+#define _RTL830X_SWITCHREG_H_
enum phy_names {
PHY0 = 0,
@@ -44,183 +44,181 @@
#define ID(_phy, _reg) ((_phy)<<16 | (_reg))
-#define PHY_CTL(p) ID(p, 0)
-#define PHY0_CTL ID(PHY0, 0)
-#define PHY1_CTL ID(PHY1, 0)
-#define PHY2_CTL ID(PHY2, 0)
-#define PHY3_CTL ID(PHY3, 0)
-#define PHY4_CTL ID(PHY4, 0)
-#define PHY5_CTL ID(PHY5, 0)
-#define PHY6_CTL ID(PHY6, 0)
-#define PHY7_CTL ID(PHY7, 0)
-#define PHY_CTL_RESET (1<<15)
-#define PHY_CTL_LOOPBACK (1<<14)
-#define PHY_CTL_100M (1<<13)
-#define PHY_CTL_ANEG (1<<12)
-#define PHY_CTL_POWERDOWN (1<<11)
-#define PHY_CTL_ISOLATE (1<<10)
-#define PHY_CTL_ANEG_RESTART (1<< 9)
-#define PHY_CTL_FDX (1<< 8)
+#define PHY_CTL(p) ID(p, 0)
+#define PHY0_CTL ID(PHY0, 0)
+#define PHY1_CTL ID(PHY1, 0)
+#define PHY2_CTL ID(PHY2, 0)
+#define PHY3_CTL ID(PHY3, 0)
+#define PHY4_CTL ID(PHY4, 0)
+#define PHY5_CTL ID(PHY5, 0)
+#define PHY6_CTL ID(PHY6, 0)
+#define PHY7_CTL ID(PHY7, 0)
+#define PHY_CTL_RESET (1<<15)
+#define PHY_CTL_LOOPBACK (1<<14)
+#define PHY_CTL_100M (1<<13)
+#define PHY_CTL_ANEG (1<<12)
+#define PHY_CTL_POWERDOWN (1<<11)
+#define PHY_CTL_ISOLATE (1<<10)
+#define PHY_CTL_ANEG_RESTART (1<< 9)
+#define PHY_CTL_FDX (1<< 8)
-#define PHY_STS(p) ID(p, 1)
-#define PHY0_STS ID(PHY0, 1)
-#define PHY1_STS ID(PHY1, 1)
-#define PHY2_STS ID(PHY2, 1)
-#define PHY3_STS ID(PHY3, 1)
-#define PHY4_STS ID(PHY4, 1)
-#define PHY5_STS ID(PHY5, 1)
-#define PHY6_STS ID(PHY6, 1)
-#define PHY7_STS ID(PHY7, 1)
-#define PHY_STS_100_T4 (1<<15)
-#define PHY_STS_100_F (1<<14)
-#define PHY_STS_100_H (1<<13)
-#define PHY_STS_10_F (1<<12)
-#define PHY_STS_10_H (1<<11)
-#define PHY_STS_MF_PRMBL (1<< 6)
-#define PHY_STS_ANEG_CMPL (1<< 5)
-#define PHY_STS_RMT_FLT (1<< 4)
-#define PHY_STS_NW_ANEG (1<< 3)
-#define PHY_STS_LINK_UP (1<< 2)
-#define PHY_STS_JABBER (1<< 1)
-#define PHY_STS_EXT_CAP (1<< 0)
+#define PHY_STS(p) ID(p, 1)
+#define PHY0_STS ID(PHY0, 1)
+#define PHY1_STS ID(PHY1, 1)
+#define PHY2_STS ID(PHY2, 1)
+#define PHY3_STS ID(PHY3, 1)
+#define PHY4_STS ID(PHY4, 1)
+#define PHY5_STS ID(PHY5, 1)
+#define PHY6_STS ID(PHY6, 1)
+#define PHY7_STS ID(PHY7, 1)
+#define PHY_STS_100_T4 (1<<15)
+#define PHY_STS_100_F (1<<14)
+#define PHY_STS_100_H (1<<13)
+#define PHY_STS_10_F (1<<12)
+#define PHY_STS_10_H (1<<11)
+#define PHY_STS_MF_PRMBL (1<< 6)
+#define PHY_STS_ANEG_CMPL (1<< 5)
+#define PHY_STS_RMT_FLT (1<< 4)
+#define PHY_STS_NW_ANEG (1<< 3)
+#define PHY_STS_LINK_UP (1<< 2)
+#define PHY_STS_JABBER (1<< 1)
+#define PHY_STS_EXT_CAP (1<< 0)
-#define PHY_ANEG_ADV(p) ID(p, 4)
-#define PHY0_ANEG_ADV ID(PHY0, 4)
-#define PHY1_ANEG_ADV ID(PHY1, 4)
-#define PHY2_ANEG_ADV ID(PHY2, 4)
-#define PHY3_ANEG_ADV ID(PHY3, 4)
-#define PHY4_ANEG_ADV ID(PHY4, 4)
-#define PHY5_ANEG_ADV ID(PHY5, 4)
-#define PHY6_ANEG_ADV ID(PHY6, 4)
-#define PHY7_ANEG_ADV ID(PHY7, 4)
-#define PHY_ANEG_ADV_NP_DIS (1<<15)
-#define PHY_ANEG_ADV_ACK (1<<14)
-#define PHY_ANEG_ADV_FLT_ADV (1<<13)
-#define PHY_ANEG_ADV_ADV (1<<10)
-#define PHY_ANEG_ADV_100_T4 (1<< 9)
-#define PHY_ANEG_ADV_100_F (1<< 8)
-#define PHY_ANEG_ADV_100_H (1<< 7)
-#define PHY_ANEG_ADV_10_F (1<< 6)
-#define PHY_ANEG_ADV_10_H (1<< 5)
-#define PHY_ANEG_ADV_SEL_FLD_SHIFT 0
-#define PHY_ANEG_ADV_SEL_FLD_MASK 0x1f
+#define PHY_ANEG_ADV(p) ID(p, 4)
+#define PHY0_ANEG_ADV ID(PHY0, 4)
+#define PHY1_ANEG_ADV ID(PHY1, 4)
+#define PHY2_ANEG_ADV ID(PHY2, 4)
+#define PHY3_ANEG_ADV ID(PHY3, 4)
+#define PHY4_ANEG_ADV ID(PHY4, 4)
+#define PHY5_ANEG_ADV ID(PHY5, 4)
+#define PHY6_ANEG_ADV ID(PHY6, 4)
+#define PHY7_ANEG_ADV ID(PHY7, 4)
+#define PHY_ANEG_ADV_NP_DIS (1<<15)
+#define PHY_ANEG_ADV_ACK (1<<14)
+#define PHY_ANEG_ADV_FLT_ADV (1<<13)
+#define PHY_ANEG_ADV_ADV (1<<10)
+#define PHY_ANEG_ADV_100_T4 (1<< 9)
+#define PHY_ANEG_ADV_100_F (1<< 8)
+#define PHY_ANEG_ADV_100_H (1<< 7)
+#define PHY_ANEG_ADV_10_F (1<< 6)
+#define PHY_ANEG_ADV_10_H (1<< 5)
+#define PHY_ANEG_ADV_SEL_FLD_SHIFT 0
+#define PHY_ANEG_ADV_SEL_FLD_MASK 0x1f
-#define PHY_ANEG_PRTN(p) ID(p, 5)
-#define PHY0_ANEG_PRTN ID(PHY0, 5)
-#define PHY1_ANEG_PRTN ID(PHY1, 5)
-#define PHY2_ANEG_PRTN ID(PHY2, 5)
-#define PHY3_ANEG_PRTN ID(PHY3, 5)
-#define PHY4_ANEG_PRTN ID(PHY4, 5)
-#define PHY5_ANEG_PRTN ID(PHY5, 5)
-#define PHY6_ANEG_PRTN ID(PHY6, 5)
-#define PHY7_ANEG_PRTN ID(PHY7, 5)
-#define PHY_ANEG_PRTN_NP_DIS (1<<15)
-#define PHY_ANEG_PRTN_ACK (1<<14)
-#define PHY_ANEG_PRTN_RMT_FLT (1<<13)
-#define PHY_ANEG_PRTN_FC_ABLE (1<<10)
-#define PHY_ANEG_PRTN_100_T4 (1<< 9)
-#define PHY_ANEG_PRTN_100_F (1<< 8)
-#define PHY_ANEG_PRTN_100_H (1<< 7)
-#define PHY_ANEG_PRTN_10_F (1<< 6)
-#define PHY_ANEG_PRTN_10_H (1<< 5)
-#define PHY_ANEG_PRTN_SEL_FLD_SHIFT 0
-#define PHY_ANEG_PRTN_SEL_FLD_MASK 0x1f
+#define PHY_ANEG_PRTN(p) ID(p, 5)
+#define PHY0_ANEG_PRTN ID(PHY0, 5)
+#define PHY1_ANEG_PRTN ID(PHY1, 5)
+#define PHY2_ANEG_PRTN ID(PHY2, 5)
+#define PHY3_ANEG_PRTN ID(PHY3, 5)
+#define PHY4_ANEG_PRTN ID(PHY4, 5)
+#define PHY5_ANEG_PRTN ID(PHY5, 5)
+#define PHY6_ANEG_PRTN ID(PHY6, 5)
+#define PHY7_ANEG_PRTN ID(PHY7, 5)
+#define PHY_ANEG_PRTN_NP_DIS (1<<15)
+#define PHY_ANEG_PRTN_ACK (1<<14)
+#define PHY_ANEG_PRTN_RMT_FLT (1<<13)
+#define PHY_ANEG_PRTN_FC_ABLE (1<<10)
+#define PHY_ANEG_PRTN_100_T4 (1<< 9)
+#define PHY_ANEG_PRTN_100_F (1<< 8)
+#define PHY_ANEG_PRTN_100_H (1<< 7)
+#define PHY_ANEG_PRTN_10_F (1<< 6)
+#define PHY_ANEG_PRTN_10_H (1<< 5)
+#define PHY_ANEG_PRTN_SEL_FLD_SHIFT 0
+#define PHY_ANEG_PRTN_SEL_FLD_MASK 0x1f
-#define PHY_ANEG_EXP(p) ID(p, 6)
-#define PHY0_ANEG_EXP ID(PHY0, 6)
-#define PHY1_ANEG_EXP ID(PHY1, 6)
-#define PHY2_ANEG_EXP ID(PHY2, 6)
-#define PHY3_ANEG_EXP ID(PHY3, 6)
-#define PHY4_ANEG_EXP ID(PHY4, 6)
-#define PHY5_ANEG_EXP ID(PHY5, 6)
-#define PHY6_ANEG_EXP ID(PHY6, 6)
-#define PHY7_ANEG_EXP ID(PHY7, 6)
-#define PHY_ANEG_EXP_PD_FLT (1<< 4)
-#define PHY_ANEG_EXP_PRTN_NXTPG (1<< 3)
-#define PHY_ANEG_EXP_NXTPG (1<< 2)
-#define PHY_ANEG_EXP_PG_RCV (1<< 1)
-#define PHY_ANEG_EXP_PRTN_ANEG (1<< 0)
+#define PHY_ANEG_EXP(p) ID(p, 6)
+#define PHY0_ANEG_EXP ID(PHY0, 6)
+#define PHY1_ANEG_EXP ID(PHY1, 6)
+#define PHY2_ANEG_EXP ID(PHY2, 6)
+#define PHY3_ANEG_EXP ID(PHY3, 6)
+#define PHY4_ANEG_EXP ID(PHY4, 6)
+#define PHY5_ANEG_EXP ID(PHY5, 6)
+#define PHY6_ANEG_EXP ID(PHY6, 6)
+#define PHY7_ANEG_EXP ID(PHY7, 6)
+#define PHY_ANEG_EXP_PD_FLT (1<< 4)
+#define PHY_ANEG_EXP_PRTN_NXTPG (1<< 3)
+#define PHY_ANEG_EXP_NXTPG (1<< 2)
+#define PHY_ANEG_EXP_PG_RCV (1<< 1)
+#define PHY_ANEG_EXP_PRTN_ANEG (1<< 0)
-#define GCNTRL0 ID(PHY0, 16)
-#define GCNTRL0_LED_MODE_SHIFT 13
-#define GCNTRL0_LED_MODE_MASK 0xe000
-#define GCNTRL0_SOFT_RSET (1<<12)
-#define GCNTRL0_VLAN_DIS (1<<11)
-#define GCNTRL0_DOT1Q_DIS (1<<10)
-#define GCNTRL0_INGRESS_CHECK_DIS (1<<9)
-#define GCNTRL0_TAG_ONLY_DIS (1<<8)
-#define GCNTRL0_EEPROM (1<<7)
-#define GCNTRL0_FILTER_BAD (1<<6)
-#define GCNTRL0_TX_FC (1<<5)
-#define GCNTRL0_RX_FC (1<<4)
-#define GCNTRL0_BCAST_IN_DROP (1<<3)
-#define GCNTRL0_AGN_EN (1<<2)
-#define GCNTRL0_FAST_AGN (1<<1)
-#define GCNTRL0_MACAT (1<<0)
+#define GCNTRL0 ID(PHY0, 16)
+#define GCNTRL0_LED_MODE_SHIFT 13
+#define GCNTRL0_LED_MODE_MASK 0xe000
+#define GCNTRL0_SOFT_RSET (1<<12)
+#define GCNTRL0_VLAN_DIS (1<<11)
+#define GCNTRL0_DOT1Q_DIS (1<<10)
+#define GCNTRL0_INGRESS_CHECK_DIS (1<<9)
+#define GCNTRL0_TAG_ONLY_DIS (1<<8)
+#define GCNTRL0_EEPROM (1<<7)
+#define GCNTRL0_FILTER_BAD (1<<6)
+#define GCNTRL0_TX_FC (1<<5)
+#define GCNTRL0_RX_FC (1<<4)
+#define GCNTRL0_BCAST_IN_DROP (1<<3)
+#define GCNTRL0_AGN_EN (1<<2)
+#define GCNTRL0_FAST_AGN (1<<1)
+#define GCNTRL0_MACAT (1<<0)
-#define GCNTRL1 ID(PHY0, 17)
-#define GCNTRL2 ID(PHY0, 18)
-#define GCNTRL3 ID(PHY0, 19)
+#define GCNTRL1 ID(PHY0, 17)
+#define GCNTRL2 ID(PHY0, 18)
+#define GCNTRL3 ID(PHY0, 19)
-#define PHY_CTRL0(p) ID(p, 22)
-#define PHY0_CTRL0 ID(PHY0, 22)
-#define PHY1_CTRL0 ID(PHY1, 22)
-#define PHY2_CTRL0 ID(PHY2, 22)
-#define PHY3_CTRL0 ID(PHY3, 22)
-#define PHY4_CTRL0 ID(PHY4, 22)
-#define PHY5_CTRL0 ID(PHY5, 22)
-#define PHY6_CTRL0 ID(PHY6, 22)
-#define PHY7_CTRL0 ID(PHY7, 22)
+#define PHY_CTRL0(p) ID(p, 22)
+#define PHY0_CTRL0 ID(PHY0, 22)
+#define PHY1_CTRL0 ID(PHY1, 22)
+#define PHY2_CTRL0 ID(PHY2, 22)
+#define PHY3_CTRL0 ID(PHY3, 22)
+#define PHY4_CTRL0 ID(PHY4, 22)
+#define PHY5_CTRL0 ID(PHY5, 22)
+#define PHY6_CTRL0 ID(PHY6, 22)
+#define PHY7_CTRL0 ID(PHY7, 22)
+#define CTRL0_LOOP (1<<13)
+#define CTRL0_R_NL_VID (1<<12)
+#define CTRL0_I_CH_EN (1<<11)
+#define CTRL0_1P_DIS (1<<10)
+#define CTRL0_DFSRV_DIS (1<<9)
+#define CTRL0_PQOS_DIS (1<<8)
+#define CTRL0_TAG_MODE_MASK 3
+#define CTRL0_TAG_NI_NR 3 /* Not insert, not remove */
+#define CTRL0_TAG_I_UTG 2 /* Ingress Insert for untagged */
+#define CTRL0_TAG_R_TG 1 /* Remove Tag on Egress */
+#define CTRL0_TAG_IR 0 /* Insert or Replace Tag */
-#define CTRL0_LOOP (1<<13)
-#define CTRL0_R_NL_VID (1<<12)
-#define CTRL0_I_CH_EN (1<<11)
-#define CTRL0_1P_DIS (1<<10)
-#define CTRL0_DFSRV_DIS (1<<9)
-#define CTRL0_PQOS_DIS (1<<8)
-#define CTRL0_TAG_MODE_MASK 3
-#define CTRL0_TAG_NI_NR 3 /* Not insert, not remove */
-#define CTRL0_TAG_I_UTG 2 /* Ingress Insert for untagged */
-#define CTRL0_TAG_R_TG 1 /* Remove Tag on Egress */
-#define CTRL0_TAG_IR 0 /* Insert or Replace Tag */
+#define PHY_CTRL1(p) ID(p, 23)
+#define PHY0_CTRL1 ID(PHY0, 23)
+#define PHY1_CTRL1 ID(PHY1, 23)
+#define PHY2_CTRL1 ID(PHY2, 23)
+#define PHY3_CTRL1 ID(PHY3, 23)
+#define PHY4_CTRL1 ID(PHY4, 23)
+#define PHY5_CTRL1 ID(PHY5, 23)
+#define PHY6_CTRL1 ID(PHY6, 23)
+#define PHY7_CTRL1 ID(PHY7, 23)
+#define CTRL1_TX_EN (1<<11)
+#define CTRL1_RX_EN (1<<10)
+#define CTRL1_LRN_EN (1<<9)
+#define CTRL1_LOOP_DET (1<<8)
+#define CTRL1_LQ_MASK 0x00f0
+#define CTRL1_LQ_SHIFT 4
-#define PHY_CTRL1(p) ID(p, 23)
-#define PHY0_CTRL1 ID(PHY0, 23)
-#define PHY1_CTRL1 ID(PHY1, 23)
-#define PHY2_CTRL1 ID(PHY2, 23)
-#define PHY3_CTRL1 ID(PHY3, 23)
-#define PHY4_CTRL1 ID(PHY4, 23)
-#define PHY5_CTRL1 ID(PHY5, 23)
-#define PHY6_CTRL1 ID(PHY6, 23)
-#define PHY7_CTRL1 ID(PHY7, 23)
+#define PORT_PVID(p) ID((PHY0+p), 24)
+#define VLAN_MEMB(v) ID((PHY0+v), 24)
+#define VLAN_ID(v) ID((PHY0+v), 25)
+#define VLAN_ID_MASK 0x0fff
+#define VLAN_ID_SHIFT 0
-#define CTRL1_TX_EN (1<<11)
-#define CTRL1_RX_EN (1<<10)
-#define CTRL1_LRN_EN (1<<9)
-#define CTRL1_LOOP_DET (1<<8)
-#define CTRL1_LQ_MASK 0x00f0
-#define CTRL1_LQ_SHIFT 4
+#define PORT0_PVID ID(PHY0, 24)
+#define VLAN_A_MEMB ID(PHY0, 24)
+#define VLAN_A_ID ID(PHY0, 25)
-#define PORT_PVID(p) ID((PHY0+p), 24)
-#define VLAN_MEMB(v) ID((PHY0+v), 24)
-#define VLAN_ID(v) ID((PHY0+v), 25)
-#define VLAN_ID_MASK 0x0fff
-#define VLAN_ID_SHIFT 0
+#define PORT8_PVID ID(PHY5, 17)
+#define VLAN_I_MEMB ID(PHY5, 17)
+#define VLAN_I_ID ID(PHY5, 18)
-#define PORT0_PVID ID(PHY0, 24)
-#define VLAN_A_MEMB ID(PHY0, 24)
-#define VLAN_A_ID ID(PHY0, 25)
-
-#define PORT8_PVID ID(PHY5, 17)
-#define VLAN_I_MEMB ID(PHY5, 17)
-#define VLAN_I_ID ID(PHY5, 18)
-
-#define PORT0_PVID_IDX_SHIFT 12
-#define PORT0_PVID_IDX_MASK 0xf000
-#define PORT8_PVID_IDX_SHIFT 9
-#define PORT8_PVID_IDX_MASK 0x1e00
-#define VLAN_A_MEMB_SHIFT 0
-#define VLAN_A_MEMB_MASK 0x01ff
+#define PORT0_PVID_IDX_SHIFT 12
+#define PORT0_PVID_IDX_MASK 0xf000
+#define PORT8_PVID_IDX_SHIFT 9
+#define PORT8_PVID_IDX_MASK 0x1e00
+#define VLAN_A_MEMB_SHIFT 0
+#define VLAN_A_MEMB_MASK 0x01ff
#endif /* _RTL830X_SWITCHREG_H_ */
diff -r 7cd2c83e9de7 -r 1f7980008e67 head/sys/dev/switch/rtl830x_switchvar.h
--- a/head/sys/dev/switch/rtl830x_switchvar.h Sat Jan 21 01:20:20 2012 +0100
+++ b/head/sys/dev/switch/rtl830x_switchvar.h Sat Jan 21 17:32:13 2012 +0200
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2011 Aleksandr Rybalko.
+ * Copyright (c) 2011,2012 Aleksandr Rybalko.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff -r 7cd2c83e9de7 -r 1f7980008e67 head/sys/dev/switch/switch.c
--- a/head/sys/dev/switch/switch.c Sat Jan 21 01:20:20 2012 +0100
+++ b/head/sys/dev/switch/switch.c Sat Jan 21 17:32:13 2012 +0200
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2010-2011, Aleksandr Rybalko
+ * Copyright (c) 2010-2012 Aleksandr Rybalko
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -47,7 +47,8 @@
#include "switch_if.h"
#include "switchb_if.h"
-//#define CREATE_CHILD_MDIO_BUS
+#undef CREATE_CHILD_MDIO_BUS
+
#ifdef CREATE_CHILD_MDIO_BUS
#include <sys/socket.h>
#include <net/if.h>
@@ -150,7 +151,8 @@
return (0);
}
-static int switch_getreg_sub(struct switch_softc *sc, struct switch_reg *reg)
+static int
+switch_getreg_sub(struct switch_softc *sc, struct switch_reg *reg)
{
int error = 0;
@@ -160,7 +162,9 @@
return (error);
}
-static int switch_setreg_sub(struct switch_softc *sc, struct switch_reg *reg)
+
+static int
+switch_setreg_sub(struct switch_softc *sc, struct switch_reg *reg)
{
int error = 0;
@@ -182,7 +186,7 @@
}
if (vlan_config->cmd == 1) {
- /* Set */
+ /* TODO: Set VLAN mode (portbased/802.1q)*/
} else {
/* Get */
}
@@ -213,13 +217,6 @@
case DOT1Q_PORT_VLAN_CONFIG_VLAN_NONE:
/* FALLTHROUGH */
case DOT1Q_PORT_VLAN_CONFIG_VLAN_FORBIDDEN:
- if (sc->caps->vlan & SWITCH_CAPS_VLAN_GLBL_UNTG) {
- /*
- * Save untagged flag for switches
- * with global tagging flag
- */
- /* XXX: uports |= (1 << port); */
- }
break;
case DOT1Q_PORT_VLAN_CONFIG_VLAN_UNTAGGED:
uports |= (1 << port);
@@ -273,7 +270,8 @@
}
static int
-vlan_port_config_sub(struct switch_softc *sc, struct vlan_port_config *vlan_port)
+vlan_port_config_sub(struct switch_softc *sc,
+ struct vlan_port_config *vlan_port)
{
int error;
@@ -313,7 +311,7 @@
}
-static int
+static int
switch_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
struct thread *td)
{
@@ -326,7 +324,8 @@
case IOCTL_SWITCH_CONFIG:
ret = switch_config_sub(sc, (struct switch_config *)kdata);
if (ret) {
- device_printf(sc->sc_dev, "switch_config_sub return error\n");
+ device_printf(sc->sc_dev,
+ "switch_config_sub return error\n");
/* XXX: handle error */
break;
}
@@ -334,7 +333,8 @@
case IOCTL_SWITCH_CAP:
ret = switch_caps_sub(sc, (struct switch_caps *)kdata);
if (ret) {
- device_printf(sc->sc_dev, "switch_caps_sub return error\n");
+ device_printf(sc->sc_dev,
+ "switch_caps_sub return error\n");
/* XXX: handle error */
break;
}
@@ -342,7 +342,8 @@
case IOCTL_SWITCH_GETREG:
ret = switch_getreg_sub(sc, (struct switch_reg *)kdata);
if (ret) {
- device_printf(sc->sc_dev, "switch_getreg_sub return error\n");
+ device_printf(sc->sc_dev,
+ "switch_getreg_sub return error\n");
/* XXX: handle error */
break;
}
@@ -350,7 +351,8 @@
case IOCTL_SWITCH_SETREG:
ret = switch_setreg_sub(sc, (struct switch_reg *)kdata);
if (ret) {
- device_printf(sc->sc_dev, "switch_setreg_sub return error\n");
+ device_printf(sc->sc_dev,
+ "switch_setreg_sub return error\n");
/* XXX: handle error */
break;
}
@@ -358,7 +360,8 @@
case IOCTL_SWITCH_RESETSUB:
ret = SWITCH_RESET_SUBSYS(sc->child, *((uint32_t *)kdata));
if (ret) {
- device_printf(sc->sc_dev, "SWITCH_RESET_SUBSYS return error\n");
+ device_printf(sc->sc_dev,
+ "SWITCH_RESET_SUBSYS return error\n");
/* XXX: handle error */
break;
}
@@ -366,23 +369,28 @@
case IOCTL_VLAN_CONFIG:
ret = vlan_config_sub(sc, (struct vlan_config *)kdata);
if (ret) {
- device_printf(sc->sc_dev, "vlan_config_sub return error\n");
+ device_printf(sc->sc_dev,
+ "vlan_config_sub return error\n");
/* XXX: handle error */
break;
}
break;
case IOCTL_VLAN_VLAN_CONFIG:
- ret = vlan_vlan_config_sub(sc, (struct vlan_vlan_config *)kdata);
+ ret = vlan_vlan_config_sub(sc,
+ (struct vlan_vlan_config *)kdata);
if (ret) {
- device_printf(sc->sc_dev, "vlan_vlan_config_sub return error\n");
+ device_printf(sc->sc_dev,
+ "vlan_vlan_config_sub return error\n");
/* XXX: handle error */
break;
}
break;
case IOCTL_VLAN_PORT_CONFIG:
- ret = vlan_port_config_sub(sc, (struct vlan_port_config *)kdata);
+ ret = vlan_port_config_sub(sc,
+ (struct vlan_port_config *)kdata);
if (ret) {
- device_printf(sc->sc_dev, "vlan_port_config_sub return error\n");
+ device_printf(sc->sc_dev,
+ "vlan_port_config_sub return error\n");
/* XXX: handle error */
break;
}
@@ -432,7 +440,7 @@
case IFM_10_T:
case IFM_100_TX:
/* XXX check link here */
- //sc->flags |= 1;
+ /* sc->flags |= 1; */
break;
default:
break;
@@ -552,15 +560,11 @@
sc->ifp = if_alloc(IFT_OTHER);
if_initname(sc->ifp, device_get_name(sc->sc_dev),
device_get_unit(sc->sc_dev));
-// sc->ifp->if_init = rt_init;
-// sc->ifp->if_ioctl = rt_ioctl;
-// sc->ifp->if_start = rt_start;
sc->ifp->if_mtu = 0;
IFQ_SET_MAXLEN(&sc->ifp->if_snd, 0);
sc->ifp->if_snd.ifq_drv_maxlen = 0;
IFQ_SET_READY(&sc->ifp->if_snd);
-
error = mii_attach(sc->sc_dev, &sc->child_miibus, sc->ifp,
switch_ifmedia_upd, switch_ifmedia_sts,
BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
diff -r 7cd2c83e9de7 -r 1f7980008e67 head/sys/dev/switch/switch_if.m
--- a/head/sys/dev/switch/switch_if.m Sat Jan 21 01:20:20 2012 +0100
+++ b/head/sys/dev/switch/switch_if.m Sat Jan 21 17:32:13 2012 +0200
@@ -1,5 +1,5 @@
#-
-# Copyright (c) 2010-2011 Aleksandr Rybalko <ray at ddteam.net>
+# Copyright (c) 2010-2012 Aleksandr Rybalko <ray at ddteam.net>
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -58,7 +58,8 @@
}
static int
- null_mac_write (device_t dev, uint64_t mac, int index, uint32_t port_map, uint8_t age, int *hash_idx)
+ null_mac_write (device_t dev, uint64_t mac, int index,
+ uint32_t port_map, uint8_t age, int *hash_idx)
{
return (0);
}
@@ -129,14 +130,6 @@
return (0);
}
-#ifdef mustbe_rewriten
- static uint32_t
- null_stat (device_t dev, int port)
- {
- return (0);
- }
-#endif
-
static void
null_tick (device_t dev)
{
@@ -341,39 +334,6 @@
uint32_t mode;
} DEFAULT null_force_mode;
-## XXX: must be rewriten
-## #
-## # Get count of good packets on port input
-## #
-## METHOD uint32_t good_in_cnt {
-## device_t dev;
-## int port;
-## } DEFAULT null_stat;
-##
-## #
-## # Get count of good packets on port output
-## #
-## METHOD uint32_t good_out_cnt {
-## device_t dev;
-## int port;
-## } DEFAULT null_stat;
-##
-## #
-## # Get count of bad packets on port input
-## #
-## METHOD uint32_t bad_in_cnt {
-## device_t dev;
-## int port;
-## } DEFAULT null_stat;
-##
-## #
-## # Get count of bad packets on port output
-## #
-## METHOD uint32_t bad_out_cnt {
-## device_t dev;
-## int port;
-## } DEFAULT null_stat;
-
#
# Give a chance to update something
#
diff -r 7cd2c83e9de7 -r 1f7980008e67 head/sys/dev/switch/switch_ioctl.h
--- a/head/sys/dev/switch/switch_ioctl.h Sat Jan 21 01:20:20 2012 +0100
+++ b/head/sys/dev/switch/switch_ioctl.h Sat Jan 21 17:32:13 2012 +0200
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2010-2011, Aleksandr Rybalko <ray at ddteam.net>
+ * Copyright (c) 2010-2012 Aleksandr Rybalko <ray at ddteam.net>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -28,10 +28,10 @@
*/
#ifndef _SWITCH_IOCTL_H_
-#define _SWITCH_IOCTL_H_
+#define _SWITCH_IOCTL_H_
-#define SWITCH_API_VERSION 0
-#define SWITCH_IOCTL_MAIN_BASE 0x00
+#define SWITCH_API_VERSION 0
+#define SWITCH_IOCTL_MAIN_BASE 0x00
/* Main switch configuration */
struct switch_config {
@@ -43,8 +43,8 @@
};
/* Basic switch config */
-#define SWITCH_CONFIG SWITCH_IOCTL_MAIN_BASE+0
-#define IOCTL_SWITCH_CONFIG _IOWR('E', SWITCH_CONFIG, struct switch_config)
+#define SWITCH_CONFIG SWITCH_IOCTL_MAIN_BASE+0
+#define IOCTL_SWITCH_CONFIG _IOWR('E', SWITCH_CONFIG, struct switch_config)
/* Switch capability list */
struct switch_caps {
@@ -54,21 +54,21 @@
uint8_t status; /* Command status */
uint8_t ports; /* Number of ports */
uint32_t main;
-#define SWITCH_CAPS_MAIN_PORT_POWER (1<<0)
-#define SWITCH_CAPS_MAIN_PORT_MIRROR (1<<1) /* Can do port mirror */
-#define SWITCH_CAPS_MAIN_PORT_SECURITY (1<<2) /* Can limit n MACs */
+#define SWITCH_CAPS_MAIN_PORT_POWER (1<<0)
+#define SWITCH_CAPS_MAIN_PORT_MIRROR (1<<1) /* Can do port mirror */
+#define SWITCH_CAPS_MAIN_PORT_SECURITY (1<<2) /* Can limit n MACs */
uint32_t vlan;
-#define SWITCH_CAPS_VLAN_PORT (1<<0) /* Support port based */
-#define SWITCH_CAPS_VLAN_DOT1Q (1<<1) /* 802.1q */
-#define SWITCH_CAPS_VLAN_ISL (1<<2) /* ISL */
-#define SWITCH_CAPS_VLAN_GLBL_UNTG (1<<3) /* Global tag/untag */
-#define SWITCH_CAPS_VLAN_LAN_WAN (1<<4) /* LAN/WAN spliting */
-#define SWITCH_CAPS_VLAN_DOUBLE_TAG (1<<5) /* Q-in-Q */
-#define SWITCH_CAPS_VLAN_MAX_SHIFT_MASK 0x0000fff0 /* max VLAN index */
-#define SWITCH_CAPS_VLAN_MAX_SHIFT_SHIFT 4 /* 4096-full support */
+#define SWITCH_CAPS_VLAN_PORT (1<<0) /* Support port based */
+#define SWITCH_CAPS_VLAN_DOT1Q (1<<1) /* 802.1q */
+#define SWITCH_CAPS_VLAN_ISL (1<<2) /* ISL */
+#define SWITCH_CAPS_VLAN_GLBL_UNTG (1<<3) /* Global tag/untag */
+#define SWITCH_CAPS_VLAN_LAN_WAN (1<<4) /* LAN/WAN spliting */
+#define SWITCH_CAPS_VLAN_DOUBLE_TAG (1<<5) /* Q-in-Q */
+#define SWITCH_CAPS_VLAN_MAX_SHIFT_MASK 0x0000fff0 /* max VLAN index */
+#define SWITCH_CAPS_VLAN_MAX_SHIFT_SHIFT 4 /* 4096-full support */
uint32_t qos;
-#define SWITCH_CAPS_QOS_QUEUES_MASK 0x00000007 /* 2 - 4 queues */
-#define SWITCH_CAPS_QOS_QUEUES_SHIFT 0 /* 3 - 8 queues */
+#define SWITCH_CAPS_QOS_QUEUES_MASK 0x00000007 /* 2 - 4 queues */
+#define SWITCH_CAPS_QOS_QUEUES_SHIFT 0 /* 3 - 8 queues */
uint32_t lacp;
uint32_t stp;
uint32_t acl;
@@ -76,30 +76,30 @@
};
/* List of switch capability */
-#define SWITCH_CAP SWITCH_IOCTL_MAIN_BASE+1
-#define IOCTL_SWITCH_CAP _IOWR('E', SWITCH_CAP, struct switch_caps)
+#define SWITCH_CAP SWITCH_IOCTL_MAIN_BASE+1
+#define IOCTL_SWITCH_CAP _IOWR('E', SWITCH_CAP, struct switch_caps)
struct switch_reg {
uint32_t addr;
uint32_t value;
};
-#define SWITCH_GETREG SWITCH_IOCTL_MAIN_BASE+2
-#define IOCTL_SWITCH_GETREG _IOWR('E', SWITCH_GETREG, struct switch_reg)
-#define SWITCH_SETREG SWITCH_IOCTL_MAIN_BASE+3
-#define IOCTL_SWITCH_SETREG _IOWR('E', SWITCH_SETREG, struct switch_reg)
+#define SWITCH_GETREG SWITCH_IOCTL_MAIN_BASE+2
+#define IOCTL_SWITCH_GETREG _IOWR('E', SWITCH_GETREG, struct switch_reg)
+#define SWITCH_SETREG SWITCH_IOCTL_MAIN_BASE+3
+#define IOCTL_SWITCH_SETREG _IOWR('E', SWITCH_SETREG, struct switch_reg)
-#define SWITCH_RESETSUB SWITCH_IOCTL_MAIN_BASE+4
-#define IOCTL_SWITCH_RESETSUB _IOWR('E', SWITCH_RESETSUB, uint32_t)
-#define SWITCH_RESETSUB_MASK 0x000000ff
-#define SWITCH_RESETSUB_SWITCH 1
-#define SWITCH_RESETSUB_PORT 2
-#define SWITCH_RESETSUB_VLANS 3
-#define SWITCH_RESETSUB_QOS 4
+#define SWITCH_RESETSUB SWITCH_IOCTL_MAIN_BASE+4
+#define IOCTL_SWITCH_RESETSUB _IOWR('E', SWITCH_RESETSUB, uint32_t)
+#define SWITCH_RESETSUB_MASK 0x000000ff
+#define SWITCH_RESETSUB_SWITCH 1
+#define SWITCH_RESETSUB_PORT 2
+#define SWITCH_RESETSUB_VLANS 3
+#define SWITCH_RESETSUB_QOS 4
/* If we doing reset for ports, then store port number at upper location */
-#define SWITCH_RESETSUB_ALLPORTS 0x0000ff00
-#define SWITCH_RESETSUB_PORT_MASK 0x0000ff00
-#define SWITCH_RESETSUB_PORT_SHIFT 8
+#define SWITCH_RESETSUB_ALLPORTS 0x0000ff00
+#define SWITCH_RESETSUB_PORT_MASK 0x0000ff00
+#define SWITCH_RESETSUB_PORT_SHIFT 8
enum vlan_type_e {
@@ -152,13 +152,13 @@
uint16_t vid;
/* Per port config */
uint8_t port_config[32];
-#define DOT1Q_PORT_VLAN_CONFIG_VLAN_NONE (0<<0) /* Not a member */
-#define DOT1Q_PORT_VLAN_CONFIG_VLAN_TAGGED (1<<0) /* Tagged member */
-#define DOT1Q_PORT_VLAN_CONFIG_VLAN_UNTAGGED (2<<0) /* Untagged member */
-#define DOT1Q_PORT_VLAN_CONFIG_VLAN_FORBIDDEN (3<<0) /* Filtered if no
+#define DOT1Q_PORT_VLAN_CONFIG_VLAN_NONE (0<<0) /* Not a member */
+#define DOT1Q_PORT_VLAN_CONFIG_VLAN_TAGGED (1<<0) /* Tagged member */
+#define DOT1Q_PORT_VLAN_CONFIG_VLAN_UNTAGGED (2<<0) /* Untagged member */
+#define DOT1Q_PORT_VLAN_CONFIG_VLAN_FORBIDDEN (3<<0) /* Filtered if no
* ingress checking */
-#define DOT1Q_PORT_VLAN_CONFIG_VLAN_MASK (7<<0)
-#define DOT1Q_PORT_VLAN_CONFIG_VLAN_TXTAG (1<<3) /* Tagging on TX */
+#define DOT1Q_PORT_VLAN_CONFIG_VLAN_MASK (7<<0)
+#define DOT1Q_PORT_VLAN_CONFIG_VLAN_TXTAG (1<<3) /* Tagging on TX */
} dot1q;
} d;
@@ -176,15 +176,15 @@
/* 802.1q based */
struct {
uint32_t flags;
-#define DOT1Q_VLAN_PORT_FLAG_INGRESS (1<<0) /* Ingress checking */
-#define DOT1Q_VLAN_PORT_FLAG_DOUBLE_TAG (1<<1) /* Enable Q-in-Q */
-#define DOT1Q_VLAN_PORT_FLAG_LAN (1<<2) /* Marked as LAN port */
-#define DOT1Q_VLAN_PORT_FLAG_WAN (1<<3) /* Marked as WAN port */
-#define DOT1Q_VLAN_PORT_FLAG_TAGGED (1<<4) /* Port tagged in all VLANs */
-#define DOT1Q_VLAN_PORT_FLAG_UNTAGGED (1<<5) /* Port untagged in all VLANs */
-#define DOT1Q_VLAN_PORT_FLAG_FORCE_UNTAGGED (1<<6) /* Remove tag */
-#define DOT1Q_VLAN_PORT_FLAG_FORCE_PVID (1<<7) /* Reassign tag to PVID */
-#define DOT1Q_VLAN_PORT_FLAG_DROP_UNTAGGED (1<<8) /* Drop untagged frames */
+#define DOT1Q_VLAN_PORT_FLAG_INGRESS (1<<0) /* Ingress checking */
+#define DOT1Q_VLAN_PORT_FLAG_DOUBLE_TAG (1<<1) /* Enable Q-in-Q */
+#define DOT1Q_VLAN_PORT_FLAG_LAN (1<<2) /* Marked as LAN port */
+#define DOT1Q_VLAN_PORT_FLAG_WAN (1<<3) /* Marked as WAN port */
+#define DOT1Q_VLAN_PORT_FLAG_TAGGED (1<<4) /* Port tagged in all VLANs */
+#define DOT1Q_VLAN_PORT_FLAG_UNTAGGED (1<<5) /* Port untagged in all VLANs */
+#define DOT1Q_VLAN_PORT_FLAG_FORCE_UNTAGGED (1<<6) /* Remove tag */
+#define DOT1Q_VLAN_PORT_FLAG_FORCE_PVID (1<<7) /* Reassign tag to PVID */
+#define DOT1Q_VLAN_PORT_FLAG_DROP_UNTAGGED (1<<8) /* Drop untagged frames */
uint16_t vid;
} dot1q;
/* ISL based */
@@ -195,26 +195,26 @@
} d;
};
-#define SWITCH_IOCTL_VLAN_BASE 0x10
+#define SWITCH_IOCTL_VLAN_BASE 0x10
/* get/set switch VLAN basic configuration */
-#define VLAN_CONFIG SWITCH_IOCTL_VLAN_BASE+0
+#define VLAN_CONFIG SWITCH_IOCTL_VLAN_BASE+0
/*
* get/set switch VLAN configuration for
* one port (Port based)
* one VLAN index (!!!not VID!!!) (802.1Q)
* one ISL index (ISL)
*/
-#define VLAN_VLAN_CONFIG SWITCH_IOCTL_VLAN_BASE+1
+#define VLAN_VLAN_CONFIG SWITCH_IOCTL_VLAN_BASE+1
/*
* get/set switch port PVID for
* 802.1q or ISL
*/
-#define VLAN_PORT_CONFIG SWITCH_IOCTL_VLAN_BASE+2
+#define VLAN_PORT_CONFIG SWITCH_IOCTL_VLAN_BASE+2
-#define IOCTL_VLAN_CONFIG _IOWR('E', VLAN_CONFIG, struct vlan_config)
-#define IOCTL_VLAN_VLAN_CONFIG _IOWR('E', VLAN_VLAN_CONFIG, \
+#define IOCTL_VLAN_CONFIG _IOWR('E', VLAN_CONFIG, struct vlan_config)
+#define IOCTL_VLAN_VLAN_CONFIG _IOWR('E', VLAN_VLAN_CONFIG, \
struct vlan_vlan_config)
-#define IOCTL_VLAN_PORT_CONFIG _IOWR('E', VLAN_PORT_CONFIG, \
+#define IOCTL_VLAN_PORT_CONFIG _IOWR('E', VLAN_PORT_CONFIG, \
struct vlan_port_config)
diff -r 7cd2c83e9de7 -r 1f7980008e67 head/sys/dev/switch/switch_mii.c
--- a/head/sys/dev/switch/switch_mii.c Sat Jan 21 01:20:20 2012 +0100
+++ b/head/sys/dev/switch/switch_mii.c Sat Jan 21 17:32:13 2012 +0200
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2011, Aleksandr Rybalko
+ * Copyright (c) 2011,2012 Aleksandr Rybalko
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -72,10 +72,6 @@
DEVMETHOD(switchpub_get_reg, switchpub_get_reg),
DEVMETHOD(switchpub_set_reg, switchpub_set_reg),
- /* Child MDIO bus interface */
-// DEVMETHOD(miibus_readreg, switch_miibus_readreg),
-// DEVMETHOD(miibus_writereg, switch_miibus_writereg),
-// DEVMETHOD(miibus_statchg, switch_miibus_statchg),
{ 0, 0 }
};
@@ -93,7 +89,6 @@
static int switch_mii_service(struct mii_softc *, struct mii_data *, int);
static void switch_mii_status(struct mii_softc *);
-
static const struct mii_phy_funcs switch_mii_funcs = {
switch_mii_service,
switch_mii_status,
@@ -107,7 +102,6 @@
return (BUS_PROBE_NOWILDCARD);
}
-
static int
switch_mii_attach(device_t dev)
{
diff -r 7cd2c83e9de7 -r 1f7980008e67 head/sys/dev/switch/switch_obio.c
--- a/head/sys/dev/switch/switch_obio.c Sat Jan 21 01:20:20 2012 +0100
+++ b/head/sys/dev/switch/switch_obio.c Sat Jan 21 17:32:13 2012 +0200
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2010-2011 Aleksandr Rybalko.
+ * Copyright (c) 2010-2012 Aleksandr Rybalko.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -53,7 +53,6 @@
#define WRITE4(_sc, _reg, _val) \
bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _reg, _val)
-
static int switch_obio_probe(device_t);
static int switch_obio_attach(device_t);
static int switch_obio_detach(device_t);
@@ -211,7 +210,6 @@
DEVMETHOD(device_attach, switch_obio_attach),
DEVMETHOD(device_detach, switch_obio_detach),
-
DEVMETHOD(switchb_read4, switch_obio_read4),
DEVMETHOD(switchb_write4, switch_obio_write4),
DEVMETHOD(switchb_register_isr, switch_obio_register_isr),
diff -r 7cd2c83e9de7 -r 1f7980008e67 head/sys/dev/switch/switchb_if.m
--- a/head/sys/dev/switch/switchb_if.m Sat Jan 21 01:20:20 2012 +0100
+++ b/head/sys/dev/switch/switchb_if.m Sat Jan 21 17:32:13 2012 +0200
@@ -1,5 +1,5 @@
#-
-# Copyright (c) 2010-2011 Aleksandr Rybalko <ray at ddteam.net>
+# Copyright (c) 2010-2012 Aleksandr Rybalko <ray at ddteam.net>
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -119,5 +119,3 @@
device_t dev;
device_t child;
} DEFAULT null_unregister_isr;
-
-
diff -r 7cd2c83e9de7 -r 1f7980008e67 head/sys/dev/switch/switchpub_if.m
--- a/head/sys/dev/switch/switchpub_if.m Sat Jan 21 01:20:20 2012 +0100
+++ b/head/sys/dev/switch/switchpub_if.m Sat Jan 21 17:32:13 2012 +0200
@@ -1,5 +1,5 @@
#-
-# Copyright (c) 2010-2011 Aleksandr Rybalko <ray at ddteam.net>
+# Copyright (c) 2010-2012 Aleksandr Rybalko <ray at ddteam.net>
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
diff -r 7cd2c83e9de7 -r 1f7980008e67 head/sys/dev/switch/switchvar.h
--- a/head/sys/dev/switch/switchvar.h Sat Jan 21 01:20:20 2012 +0100
+++ b/head/sys/dev/switch/switchvar.h Sat Jan 21 17:32:13 2012 +0200
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2010-2011, Aleksandr Rybalko <ray at ddteam.net>
+ * Copyright (c) 2010-2012 Aleksandr Rybalko <ray at ddteam.net>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -38,7 +38,6 @@
#include <net/if.h>
#include <net/if_media.h>
-//#include <dev/mii/mii.h>
#include <dev/mii/miivar.h>
/* Switch capability list */
@@ -55,8 +54,8 @@
};
struct child_res_avl {
- size_t memres_size;
- uint32_t phys;
+ size_t memres_size;
+ uint32_t phys;
uint8_t irqs;
};
@@ -72,14 +71,14 @@
int irq_rid;
uint32_t phys;
void *ihandl;
- driver_filter_t *sc_isr;
+ driver_filter_t *sc_isr;
void *sc_cookie;
- device_t sc_dev;
- device_t sc_miidev;
- device_t child;
- struct cdev *sc_cdev;
- device_t child_miibus;
+ device_t sc_dev;
+ device_t sc_miidev;
+ device_t child;
+ struct cdev *sc_cdev;
+ device_t child_miibus;
struct ifnet *ifp;
int enable;
@@ -93,6 +92,12 @@
int switchpub_get_reg(device_t dev, uint32_t reg, uint32_t *value);
int switchpub_set_reg(device_t dev, uint32_t reg, uint32_t *value);
+#define SWITCH_REG_TYPE_MASK 0xc0000000
+#define SWITCH_REG_TYPE_SHIFT 30
+#define SWITCH_REG_TYPE_SWITCH (0)
+#define SWITCH_REG_TYPE_PHY (1<<SWITCH_REG_TYPE_SHIFT)
+#define SWITCH_REG_TYPE_RAW (2<<SWITCH_REG_TYPE_SHIFT)
+
/* Child MDIO access */
int switch_miibus_writereg(device_t dev, int phy, int reg, int value);
int switch_miibus_readreg(device_t dev, int phy, int reg);
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