[Zrouter-src-freebsd] ZRouter.org: push to FreeBSD HEAD tree

zrouter-src-freebsd at zrouter.org zrouter-src-freebsd at zrouter.org
Thu Dec 15 11:01:37 UTC 2011


details:   http://zrouter.org/hg/FreeBSD/head//rev/820af1e39cd6
changeset: 247:820af1e39cd6
user:      ray at terran.dlink.ua
date:      Thu Dec 15 12:59:38 2011 +0200
description:
FreeBSD HEAD @svn 228526r.

diffstat:

 head/ObsoleteFiles.inc                                                     |     4 +-
 head/bin/chio/chio.c                                                       |     8 +-
 head/bin/stty/modes.c                                                      |    12 +-
 head/cddl/contrib/opensolaris/cmd/zfs/zfs.8                                |    77 +-
 head/contrib/bsnmp/snmpd/snmpmod.h                                         |     1 +
 head/contrib/gcclibs/libcpp/include/cpplib.h                               |     3 +-
 head/contrib/gcclibs/libcpp/init.c                                         |     1 +
 head/contrib/gcclibs/libcpp/internal.h                                     |     2 +
 head/contrib/gcclibs/libcpp/macro.c                                        |     4 +
 head/contrib/groff/tmac/doc-common                                         |    37 +-
 head/contrib/groff/tmac/doc-syms                                           |    36 +
 head/contrib/groff/tmac/doc.tmac                                           |     4 +-
 head/contrib/groff/tmac/groff_mdoc.man                                     |   111 +-
 head/contrib/libstdc++/include/debug/map.h                                 |     2 -
 head/contrib/libstdc++/include/debug/multimap.h                            |     2 -
 head/contrib/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp              |    16 +-
 head/contrib/llvm/lib/CodeGen/LLVMTargetMachine.cpp                        |     3 +-
 head/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp         |    11 +-
 head/contrib/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp             |     8 +-
 head/contrib/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp                   |    15 +-
 head/contrib/llvm/lib/Target/ARM/ARMCallingConv.td                         |    19 +
 head/contrib/llvm/lib/Target/ARM/ARMFastISel.cpp                           |     5 +
 head/contrib/llvm/lib/Target/ARM/ARMFrameLowering.cpp                      |    10 +
 head/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp                       |     2 +
 head/contrib/llvm/lib/Target/ARM/ARMInstrThumb2.td                         |    12 +-
 head/contrib/llvm/lib/Target/CppBackend/CPPBackend.cpp                     |    99 +-
 head/contrib/llvm/lib/Target/Mips/Mips64InstrInfo.td                       |    40 +-
 head/contrib/llvm/lib/Target/Mips/MipsCodeEmitter.cpp                      |    31 +-
 head/contrib/llvm/lib/Target/Mips/MipsInstrFPU.td                          |    56 +-
 head/contrib/llvm/lib/Target/Mips/MipsInstrFormats.td                      |    83 +-
 head/contrib/llvm/lib/Target/Mips/MipsInstrInfo.td                         |    97 +-
 head/contrib/llvm/lib/Target/Mips/MipsJITInfo.cpp                          |    14 +-
 head/contrib/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp                  |     4 +-
 head/contrib/llvm/lib/Target/X86/X86CodeEmitter.cpp                        |    33 +-
 head/contrib/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp      |     7 +-
 head/contrib/llvm/tools/clang/include/clang/Driver/CC1Options.td           |    11 +
 head/contrib/llvm/tools/clang/include/clang/Driver/ToolChain.h             |    12 +-
 head/contrib/llvm/tools/clang/include/clang/Frontend/HeaderSearchOptions.h |    23 +-
 head/contrib/llvm/tools/clang/lib/Basic/Version.cpp                        |     2 +-
 head/contrib/llvm/tools/clang/lib/CodeGen/CGObjCGNU.cpp                    |    42 +-
 head/contrib/llvm/tools/clang/lib/CodeGen/CodeGenModule.cpp                |    59 +-
 head/contrib/llvm/tools/clang/lib/CodeGen/CodeGenModule.h                  |     2 +
 head/contrib/llvm/tools/clang/lib/Driver/ToolChain.cpp                     |    35 +-
 head/contrib/llvm/tools/clang/lib/Driver/ToolChains.cpp                    |  1022 ++-
 head/contrib/llvm/tools/clang/lib/Driver/ToolChains.h                      |    91 +
 head/contrib/llvm/tools/clang/lib/Driver/Tools.cpp                         |    27 +-
 head/contrib/llvm/tools/clang/lib/Frontend/CompilerInvocation.cpp          |    25 +-
 head/contrib/llvm/tools/clang/lib/Frontend/InitHeaderSearch.cpp            |   534 +-
 head/contrib/openpam/lib/openpam_configure.c                               |     7 +
 head/contrib/tzcode/zic/zdump.c                                            |     3 +-
 head/etc/network.subr                                                      |     9 +-
 head/gnu/usr.bin/groff/tmac/mdoc.local                                     |    30 +-
 head/include/netdb.h                                                       |     4 +-
 head/include/regex.h                                                       |     4 +-
 head/include/signal.h                                                      |     8 +-
 head/include/stdbool.h                                                     |     4 +-
 head/include/stdio.h                                                       |     6 +-
 head/include/stdlib.h                                                      |    18 +-
 head/lib/clang/include/MipsGenCodeEmitter.inc                              |     2 +
 head/lib/clang/include/clang/Basic/Version.inc                             |     6 +-
 head/lib/clang/libllvmmipscodegen/Makefile                                 |     3 +-
 head/lib/libc/gen/getosreldate.c                                           |     9 +-
 head/lib/libc/stdlib/Makefile.inc                                          |    10 +-
 head/lib/libc/stdlib/Symbol.map                                            |     4 +-
 head/lib/libc/stdlib/at_quick_exit.3                                       |    61 +
 head/lib/libc/stdlib/atexit.3                                              |     3 +-
 head/lib/libc/stdlib/exit.3                                                |     4 +-
 head/lib/libc/stdlib/quick_exit.3                                          |    57 +
 head/lib/libc/stdlib/quick_exit.c                                          |    78 +
 head/lib/libc/sys/kqueue.2                                                 |     6 +-
 head/lib/libedit/histedit.h                                                |     6 +-
 head/lib/libufs/block.c                                                    |    55 +-
 head/libexec/comsat/comsat.c                                               |    22 +-
 head/libexec/rtld-elf/amd64/reloc.c                                        |   116 +-
 head/libexec/rtld-elf/arm/reloc.c                                          |    18 +-
 head/libexec/rtld-elf/i386/reloc.c                                         |   115 +-
 head/libexec/rtld-elf/ia64/reloc.c                                         |    18 +-
 head/libexec/rtld-elf/mips/reloc.c                                         |    18 +-
 head/libexec/rtld-elf/powerpc/reloc.c                                      |    17 +-
 head/libexec/rtld-elf/powerpc64/reloc.c                                    |    18 +-
 head/libexec/rtld-elf/rtld.c                                               |   113 +-
 head/libexec/rtld-elf/rtld.h                                               |     9 +-
 head/libexec/rtld-elf/sparc64/reloc.c                                      |    18 +-
 head/sbin/bsdlabel/bsdlabel.c                                              |     4 +-
 head/sbin/camcontrol/fwdownload.c                                          |    22 +-
 head/sbin/camcontrol/modeedit.c                                            |     8 +-
 head/sbin/dhclient/dhclient-script                                         |     4 +-
 head/sbin/dumpfs/dumpfs.c                                                  |    42 +-
 head/sbin/rcorder/rcorder.c                                                |    93 +-
 head/sbin/reboot/reboot.c                                                  |     8 +-
 head/share/examples/scsi_target/scsi_cmds.c                                |    14 +-
 head/share/examples/scsi_target/scsi_target.c                              |    18 +-
 head/share/man/man4/Makefile                                               |     5 +-
 head/share/man/man4/altq.4                                                 |     5 +-
 head/share/man/man4/atrtc.4                                                |     4 +-
 head/share/man/man4/attimer.4                                              |     4 +-
 head/share/man/man4/et.4                                                   |     5 +-
 head/share/man/man4/eventtimers.4                                          |   133 +
 head/share/man/man4/hpet.4                                                 |     4 +-
 head/share/man/man4/splash.4                                               |    29 +-
 head/share/man/man4/targ.4                                                 |    20 +-
 head/share/man/man4/viawd.4                                                |    79 +
 head/share/man/man5/make.conf.5                                            |    14 +-
 head/share/man/man5/periodic.conf.5                                        |     6 +-
 head/share/man/man5/rc.conf.5                                              |    12 +-
 head/share/man/man7/Makefile                                               |     3 +-
 head/share/man/man7/eventtimers.7                                          |   133 -
 head/share/man/man8/yp.8                                                   |    18 +-
 head/share/man/man9/Makefile                                               |    10 +-
 head/share/man/man9/rtalloc.9                                              |   265 +-
 head/share/man/man9/sbuf.9                                                 |    17 +-
 head/share/man/man9/shm_map.9                                              |   187 +
 head/share/misc/committers-src.dot                                         |     4 +-
 head/sys/amd64/conf/NOTES                                                  |     3 +-
 head/sys/amd64/include/_types.h                                            |     4 +-
 head/sys/arm/arm/irq_dispatch.S                                            |     5 +-
 head/sys/arm/arm/vm_machdep.c                                              |     6 +-
 head/sys/arm/econa/ehci_ebus.c                                             |    57 +-
 head/sys/arm/econa/ohci_ec.c                                               |    10 +-
 head/sys/arm/include/_types.h                                              |     4 +-
 head/sys/boot/arm/at91/libat91/sd-card.c                                   |     6 +-
 head/sys/cam/scsi/scsi_sa.c                                                |     6 +-
 head/sys/cam/scsi/scsi_target.c                                            |   165 +-
 head/sys/cam/scsi/scsi_xpt.c                                               |    12 +-
 head/sys/cddl/contrib/opensolaris/uts/common/dtrace/dtrace.c               |     5 +-
 head/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/arc.c                  |     3 +
 head/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dbuf.c                 |     4 -
 head/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/txg.c                  |     2 +-
 head/sys/conf/files                                                        |     3 +-
 head/sys/conf/files.amd64                                                  |     3 +-
 head/sys/conf/files.i386                                                   |     3 +-
 head/sys/conf/kmod.mk                                                      |     4 +-
 head/sys/ddb/db_thread.c                                                   |     4 +-
 head/sys/dev/ata/ata-pci.h                                                 |     6 +-
 head/sys/dev/ata/chipsets/ata-intel.c                                      |     6 +-
 head/sys/dev/ath/ath_hal/ar5416/ar2133.c                                   |    10 +-
 head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c                            |     4 +-
 head/sys/dev/ath/ath_hal/ar9002/ar9280.c                                   |    10 +-
 head/sys/dev/ath/ath_hal/ar9002/ar9285.c                                   |    10 +-
 head/sys/dev/ath/ath_hal/ar9002/ar9287.c                                   |    10 +-
 head/sys/dev/ath/if_ath.c                                                  |     4 +-
 head/sys/dev/bce/if_bce.c                                                  |   115 +-
 head/sys/dev/bce/if_bcereg.h                                               |     3 +-
 head/sys/dev/bge/if_bge.c                                                  |    24 +-
 head/sys/dev/bge/if_bgereg.h                                               |     3 +-
 head/sys/dev/bwn/if_bwnvar.h                                               |     4 +-
 head/sys/dev/bxe/bxe_reg.h                                                 |     4 +-
 head/sys/dev/cm/smc90cx6.c                                                 |     4 +-
 head/sys/dev/cpuctl/cpuctl.c                                               |    83 +-
 head/sys/dev/cxgbe/osdep.h                                                 |     4 +-
 head/sys/dev/cxgbe/t4_sge.c                                                |     4 +-
 head/sys/dev/de/if_de.c                                                    |     4 +-
 head/sys/dev/drm/i915_drv.h                                                |     4 +-
 head/sys/dev/e1000/e1000_80003es2lan.c                                     |   229 +-
 head/sys/dev/e1000/e1000_80003es2lan.h                                     |    69 +-
 head/sys/dev/e1000/e1000_82540.c                                           |   107 +-
 head/sys/dev/e1000/e1000_82541.c                                           |    12 +-
 head/sys/dev/e1000/e1000_82543.c                                           |     9 +-
 head/sys/dev/e1000/e1000_82571.c                                           |   185 +-
 head/sys/dev/e1000/e1000_82575.c                                           |  1243 +++-
 head/sys/dev/e1000/e1000_82575.h                                           |   558 +-
 head/sys/dev/e1000/e1000_api.c                                             |    31 +-
 head/sys/dev/e1000/e1000_api.h                                             |   156 +-
 head/sys/dev/e1000/e1000_defines.h                                         |  2847 +++++----
 head/sys/dev/e1000/e1000_hw.h                                              |   372 +-
 head/sys/dev/e1000/e1000_ich8lan.c                                         |   898 +-
 head/sys/dev/e1000/e1000_ich8lan.h                                         |   319 +-
 head/sys/dev/e1000/e1000_mac.c                                             |   114 +-
 head/sys/dev/e1000/e1000_nvm.c                                             |    33 +-
 head/sys/dev/e1000/e1000_nvm.h                                             |    18 +-
 head/sys/dev/e1000/e1000_osdep.h                                           |     8 +-
 head/sys/dev/e1000/e1000_phy.c                                             |   917 ++-
 head/sys/dev/e1000/e1000_phy.h                                             |   262 +-
 head/sys/dev/e1000/e1000_regs.h                                            |  1054 +-
 head/sys/dev/e1000/e1000_vf.c                                              |    62 +-
 head/sys/dev/e1000/if_em.c                                                 |   489 +-
 head/sys/dev/e1000/if_em.h                                                 |     9 +-
 head/sys/dev/e1000/if_igb.c                                                |   703 +-
 head/sys/dev/e1000/if_igb.h                                                |    14 +-
 head/sys/dev/e1000/if_lem.c                                                |    64 +-
 head/sys/dev/e1000/if_lem.h                                                |     6 +-
 head/sys/dev/esp/ncr53c9x.c                                                |     4 +-
 head/sys/dev/et/if_et.c                                                    |  1746 +++--
 head/sys/dev/et/if_etreg.h                                                 |   541 +-
 head/sys/dev/et/if_etvar.h                                                 |   237 +-
 head/sys/dev/fb/splash_txt.c                                               |   135 +
 head/sys/dev/fdc/fdc.c                                                     |     6 +-
 head/sys/dev/hwpmc/hwpmc_core.c                                            |    15 +-
 head/sys/dev/isp/isp_freebsd.c                                             |    32 +-
 head/sys/dev/ixgbe/ixgbe.c                                                 |    10 +-
 head/sys/dev/ixgbe/ixgbe_osdep.h                                           |     4 +-
 head/sys/dev/ixgbe/ixv.c                                                   |    10 +-
 head/sys/dev/md/md.c                                                       |     8 +-
 head/sys/dev/mii/miidevs                                                   |     1 +
 head/sys/dev/pccard/pccardvar.h                                            |    16 +-
 head/sys/dev/pci/isa_pci.c                                                 |     3 +-
 head/sys/dev/sound/usb/uaudio.c                                            |    16 +-
 head/sys/dev/sound/usb/uaudio.h                                            |     7 +-
 head/sys/dev/speaker/spkr.c                                                |     4 +-
 head/sys/dev/spibus/spibusvar.h                                            |     4 +-
 head/sys/dev/switch/switch_mii.c                                           |    26 +-
 head/sys/dev/syscons/syscons.c                                             |     5 +-
 head/sys/dev/syscons/syscons.h                                             |     3 +-
 head/sys/dev/ti/if_ti.c                                                    |     5 +-
 head/sys/dev/twa/tw_osl.h                                                  |     4 +-
 head/sys/dev/tws/tws.h                                                     |     6 +-
 head/sys/dev/uart/uart_subr.c                                              |    14 +-
 head/sys/dev/usb/controller/at91dci.c                                      |    31 +-
 head/sys/dev/usb/controller/at91dci.h                                      |     4 +-
 head/sys/dev/usb/controller/at91dci_atmelarm.c                             |    28 +-
 head/sys/dev/usb/controller/atmegadci.c                                    |    31 +-
 head/sys/dev/usb/controller/atmegadci.h                                    |     4 +-
 head/sys/dev/usb/controller/atmegadci_atmelarm.c                           |    28 +-
 head/sys/dev/usb/controller/avr32dci.c                                     |    88 +-
 head/sys/dev/usb/controller/avr32dci.h                                     |     5 +-
 head/sys/dev/usb/controller/dotg_octeon.c                                  |    17 +-
 head/sys/dev/usb/controller/ehci.c                                         |   260 +-
 head/sys/dev/usb/controller/ehci.h                                         |     7 +-
 head/sys/dev/usb/controller/ehci_ixp4xx.c                                  |    50 +-
 head/sys/dev/usb/controller/ehci_mv.c                                      |    50 +-
 head/sys/dev/usb/controller/ehci_pci.c                                     |    84 +-
 head/sys/dev/usb/controller/ehci_siba.c                                    |    45 +-
 head/sys/dev/usb/controller/musb_otg.c                                     |    31 +-
 head/sys/dev/usb/controller/musb_otg.h                                     |     4 +-
 head/sys/dev/usb/controller/musb_otg_atmelarm.c                            |    28 +-
 head/sys/dev/usb/controller/ohci.c                                         |   102 +-
 head/sys/dev/usb/controller/ohci.h                                         |     6 +-
 head/sys/dev/usb/controller/ohci_atmelarm.c                                |    10 +-
 head/sys/dev/usb/controller/ohci_pci.c                                     |    57 +-
 head/sys/dev/usb/controller/ohci_s3c24x0.c                                 |    10 +-
 head/sys/dev/usb/controller/ohci_siba.c                                    |    58 +-
 head/sys/dev/usb/controller/uhci.c                                         |    60 +-
 head/sys/dev/usb/controller/uhci.h                                         |     6 +-
 head/sys/dev/usb/controller/uhci_pci.c                                     |    56 +-
 head/sys/dev/usb/controller/usb_controller.c                               |   249 +-
 head/sys/dev/usb/controller/uss820dci.c                                    |    31 +-
 head/sys/dev/usb/controller/uss820dci.h                                    |     4 +-
 head/sys/dev/usb/controller/uss820dci_atmelarm.c                           |    52 +-
 head/sys/dev/usb/controller/xhci_pci.c                                     |    61 +-
 head/sys/dev/usb/controller/xhcireg.h                                      |     4 +-
 head/sys/dev/usb/usb_bus.h                                                 |     8 +-
 head/sys/dev/usb/usb_controller.h                                          |    16 +-
 head/sys/dev/usb/usb_if.m                                                  |    12 +-
 head/sys/dev/usb/wlan/if_run.c                                             |    25 +-
 head/sys/dev/viawd/viawd.c                                                 |   248 +
 head/sys/dev/viawd/viawd.h                                                 |    73 +
 head/sys/dev/vxge/vxge-osdep.h                                             |     4 +-
 head/sys/dev/xen/netback/netback.c                                         |     4 +-
 head/sys/fs/devfs/devfs_vnops.c                                            |    12 +-
 head/sys/fs/ext2fs/ext2_readwrite.c                                        |   380 -
 head/sys/fs/ext2fs/ext2_vnops.c                                            |   333 +-
 head/sys/i386/conf/NOTES                                                   |     3 +-
 head/sys/i386/i386/pmap.c                                                  |    40 +-
 head/sys/i386/include/_types.h                                             |     4 +-
 head/sys/i386/include/vmparam.h                                            |     9 +-
 head/sys/i386/xen/mp_machdep.c                                             |     5 +-
 head/sys/ia64/ia64/uma_machdep.c                                           |     5 +-
 head/sys/ia64/include/_types.h                                             |     4 +-
 head/sys/kern/kern_ktrace.c                                                |     4 +-
 head/sys/kern/kern_lock.c                                                  |     5 +-
 head/sys/kern/kern_malloc.c                                                |    17 +-
 head/sys/kern/kern_mutex.c                                                 |    27 +-
 head/sys/kern/kern_ntptime.c                                               |    16 +-
 head/sys/kern/kern_racct.c                                                 |     7 +-
 head/sys/kern/kern_resource.c                                              |    60 +-
 head/sys/kern/kern_rmlock.c                                                |    24 +-
 head/sys/kern/kern_rwlock.c                                                |    30 +-
 head/sys/kern/kern_shutdown.c                                              |    58 +-
 head/sys/kern/kern_sx.c                                                    |    36 +-
 head/sys/kern/kern_synch.c                                                 |     8 +-
 head/sys/kern/kern_thr.c                                                   |    10 +-
 head/sys/kern/subr_kdb.c                                                   |    24 +-
 head/sys/kern/subr_lock.c                                                  |     7 +-
 head/sys/kern/subr_witness.c                                               |    16 +-
 head/sys/kern/sys_pipe.c                                                   |     8 +-
 head/sys/kern/uipc_shm.c                                                   |   121 +-
 head/sys/kern/uipc_sockbuf.c                                               |     4 +-
 head/sys/kern/vfs_cache.c                                                  |     4 +-
 head/sys/kern/vfs_syscalls.c                                               |     5 +-
 head/sys/mips/atheros/ar71xx_chip.c                                        |    56 +-
 head/sys/mips/atheros/ar71xx_ehci.c                                        |    56 +-
 head/sys/mips/atheros/ar71xx_gpio.c                                        |    67 +-
 head/sys/mips/atheros/ar71xx_ohci.c                                        |    10 +-
 head/sys/mips/atheros/ar724x_chip.c                                        |    79 +-
 head/sys/mips/atheros/ar91xx_chip.c                                        |   111 +-
 head/sys/mips/cavium/usb/octusb.c                                          |    31 +-
 head/sys/mips/cavium/usb/octusb.h                                          |     4 +-
 head/sys/mips/cavium/usb/octusb_octeon.c                                   |    27 +-
 head/sys/mips/conf/AR91XX_BASE                                             |     4 +-
 head/sys/mips/conf/AR91XX_BASE.hints                                       |     8 +-
 head/sys/mips/conf/TP-WN1043ND.hints                                       |    43 +-
 head/sys/mips/include/_types.h                                             |     4 +-
 head/sys/mips/rmi/xls_ehci.c                                               |    60 +-
 head/sys/mips/rt305x/rt305x_dotg.c                                         |    28 +-
 head/sys/modules/Makefile                                                  |     5 +-
 head/sys/modules/splash/Makefile                                           |     4 +-
 head/sys/modules/splash/txt/Makefile                                       |     7 +
 head/sys/modules/usb/Makefile                                              |     8 +-
 head/sys/modules/usb/avr32dci/Makefile                                     |    38 +
 head/sys/modules/viawd/Makefile                                            |     8 +
 head/sys/net/if.c                                                          |    47 +-
 head/sys/net/if_var.h                                                      |     3 +-
 head/sys/net80211/ieee80211_acl.c                                          |     5 +-
 head/sys/net80211/ieee80211_hostap.c                                       |    14 +-
 head/sys/net80211/ieee80211_mesh.c                                         |     7 +-
 head/sys/net80211/ieee80211_proto.h                                        |     3 +-
 head/sys/netinet/in.c                                                      |    37 +-
 head/sys/netinet/sctp_constants.h                                          |     4 +-
 head/sys/netinet/sctp_usrreq.c                                             |     3 +-
 head/sys/netinet6/mld6.c                                                   |     3 +-
 head/sys/nfs/bootp_subr.c                                                  |   429 +-
 head/sys/nfsserver/nfs_serv.c                                              |     9 +-
 head/sys/ofed/include/asm/types.h                                          |     8 +-
 head/sys/ofed/include/linux/types.h                                        |     2 +
 head/sys/pc98/cbus/scterm-sck.c                                            |     6 +-
 head/sys/pc98/cbus/scvtb.c                                                 |     4 +-
 head/sys/powerpc/aim/mmu_oea.c                                             |    27 +-
 head/sys/powerpc/aim/mmu_oea64.c                                           |    30 +-
 head/sys/powerpc/aim/uma_machdep.c                                         |     5 +-
 head/sys/powerpc/include/_types.h                                          |     4 +-
 head/sys/powerpc/include/pmap.h                                            |    38 +-
 head/sys/powerpc/include/vmparam.h                                         |    21 +-
 head/sys/powerpc/ps3/ehci_ps3.c                                            |    13 +-
 head/sys/powerpc/ps3/ohci_ps3.c                                            |    13 +-
 head/sys/security/mac/mac_framework.c                                      |     4 +-
 head/sys/security/mac/mac_priv.c                                           |     2 +-
 head/sys/sparc64/include/_types.h                                          |     4 +-
 head/sys/sparc64/sparc64/vm_machdep.c                                      |     5 +-
 head/sys/sys/cdefs.h                                                       |    37 +-
 head/sys/sys/elf_common.h                                                  |     5 +-
 head/sys/sys/lockstat.h                                                    |     2 +-
 head/sys/sys/mman.h                                                        |     7 +-
 head/sys/sys/mutex.h                                                       |     5 +-
 head/sys/sys/param.h                                                       |     4 +-
 head/sys/sys/systm.h                                                       |    17 +-
 head/sys/sys/types.h                                                       |    14 +-
 head/sys/vm/swap_pager.c                                                   |     4 +-
 head/sys/vm/vm_meter.c                                                     |   176 +-
 head/sys/xen/xenstore/xenstore.c                                           |     4 +-
 head/tools/build/mk/OptionalObsoleteFiles.inc                              |    37 +-
 head/tools/regression/pipe/pipe-reverse2.c                                 |    67 +
 head/tools/regression/sockets/unix_passfd/unix_passfd.c                    |    82 +-
 head/tools/regression/usr.bin/make/execution/joberr/Makefile               |    10 +
 head/tools/regression/usr.bin/make/execution/joberr/expected.status.1      |     1 +
 head/tools/regression/usr.bin/make/execution/joberr/expected.stderr.1      |    30 +
 head/tools/regression/usr.bin/make/execution/joberr/expected.stdout.1      |    90 +
 head/tools/regression/usr.bin/make/execution/joberr/test.t                 |    15 +
 head/usr.bin/du/du.1                                                       |    96 +-
 head/usr.bin/du/du.c                                                       |     8 +-
 head/usr.bin/find/main.c                                                   |     4 +-
 head/usr.bin/grep/grep.c                                                   |    10 +-
 head/usr.bin/grep/grep.h                                                   |     4 +-
 head/usr.bin/grep/util.c                                                   |     9 +-
 head/usr.bin/lex/main.c                                                    |     4 +-
 head/usr.bin/mail/extern.h                                                 |     4 +-
 head/usr.bin/mail/lex.c                                                    |     4 +-
 head/usr.bin/make/Makefile                                                 |     2 +-
 head/usr.bin/make/job.c                                                    |     2 +-
 head/usr.bin/procstat/procstat_auxv.c                                      |   109 +-
 head/usr.bin/procstat/procstat_rlimit.c                                    |    63 +-
 head/usr.bin/truss/amd64-linux32.c                                         |     4 +-
 head/usr.bin/truss/i386-linux.c                                            |     4 +-
 head/usr.bin/truss/main.c                                                  |     4 +-
 head/usr.bin/truss/syscalls.c                                              |     6 +-
 head/usr.sbin/cpucontrol/Makefile                                          |     4 +-
 head/usr.sbin/cpucontrol/cpucontrol.c                                      |     4 +-
 head/usr.sbin/cpucontrol/via.c                                             |   222 +
 head/usr.sbin/cpucontrol/via.h                                             |    63 +
 head/usr.sbin/kbdcontrol/kbdcontrol.c                                      |   125 +-
 head/usr.sbin/mount_portalfs/mount_portalfs.c                              |     4 +-
 head/usr.sbin/powerd/powerd.c                                              |     4 +-
 head/usr.sbin/vidcontrol/vidcontrol.c                                      |    26 +-
 372 files changed, 14876 insertions(+), 10243 deletions(-)

diffs (41815 lines):

diff -r 2230520c0499 -r 820af1e39cd6 head/ObsoleteFiles.inc
--- a/head/ObsoleteFiles.inc	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/ObsoleteFiles.inc	Thu Dec 15 12:59:38 2011 +0200
@@ -1,5 +1,5 @@
 #
-# $FreeBSD: head/ObsoleteFiles.inc 227982 2011-11-25 19:29:21Z marius $
+# $FreeBSD: head/ObsoleteFiles.inc 228511 2011-12-14 23:22:40Z delphij $
 #
 # This file lists old files (OLD_FILES), libraries (OLD_LIBS) and
 # directories (OLD_DIRS) which should get removed at an update. Recently
@@ -38,6 +38,8 @@
 #   xargs -n1 | sort | uniq -d;
 # done
 
+# 20111214: eventtimers(7) moved to eventtimers(4)
+OLD_FILES+=usr/share/man/man7/eventtimers.7.gz
 # 20111125: amd(4) removed
 OLD_FILES+=usr/share/man/man4/amd.4.gz
 # 20111125: libodialog removed
diff -r 2230520c0499 -r 820af1e39cd6 head/bin/chio/chio.c
--- a/head/bin/chio/chio.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/bin/chio/chio.c	Thu Dec 15 12:59:38 2011 +0200
@@ -43,7 +43,7 @@
 #endif
 
 #include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: head/bin/chio/chio.c 228423 2011-12-11 20:53:12Z ed $");
 
 #include <sys/param.h>
 #include <sys/chio.h> 
@@ -87,7 +87,7 @@
 #endif
 
 /* Valid changer element types. */
-const struct element_type elements[] = {
+static	const struct element_type elements[] = {
 	{ "drive",		CHET_DT },
 	{ "picker",		CHET_MT },
 	{ "portal",		CHET_IE },
@@ -97,7 +97,7 @@
 };
 
 /* Valid commands. */
-const struct changer_command commands[] = {
+static	const struct changer_command commands[] = {
 	{ "exchange",		do_exchange },
 	{ "getpicker",		do_getpicker },
 	{ "ielem", 		do_ielem },
@@ -112,7 +112,7 @@
 };
 
 /* Valid special words. */
-const struct special_word specials[] = {
+static	const struct special_word specials[] = {
 	{ "inv",		SW_INVERT },
 	{ "inv1",		SW_INVERT1 },
 	{ "inv2",		SW_INVERT2 },
diff -r 2230520c0499 -r 820af1e39cd6 head/bin/stty/modes.c
--- a/head/bin/stty/modes.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/bin/stty/modes.c	Thu Dec 15 12:59:38 2011 +0200
@@ -33,7 +33,7 @@
 #endif
 #endif /* not lint */
 #include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: head/bin/stty/modes.c 228406 2011-12-11 09:56:48Z ed $");
 
 #include <sys/types.h>
 #include <stddef.h>
@@ -52,7 +52,7 @@
  * The code in optlist() depends on minus options following regular
  * options, i.e. "foo" must immediately precede "-foo".
  */
-struct modes cmodes[] = {
+static const struct modes cmodes[] = {
 	{ "cs5",	CS5, CSIZE },
 	{ "cs6",	CS6, CSIZE },
 	{ "cs7",	CS7, CSIZE },
@@ -94,7 +94,7 @@
 	{ NULL,		0, 0 },
 };
 
-struct modes imodes[] = {
+static const struct modes imodes[] = {
 	{ "ignbrk",	IGNBRK, 0 },
 	{ "-ignbrk",	0, IGNBRK },
 	{ "brkint",	BRKINT, 0 },
@@ -130,7 +130,7 @@
 	{ NULL,		0, 0 },
 };
 
-struct modes lmodes[] = {
+static const struct modes lmodes[] = {
 	{ "echo",	ECHO, 0 },
 	{ "-echo",	0, ECHO },
 	{ "echoe",	ECHOE, 0 },
@@ -182,7 +182,7 @@
 	{ NULL,		0, 0 },
 };
 
-struct modes omodes[] = {
+static const struct modes omodes[] = {
 	{ "opost",	OPOST, 0 },
 	{ "-opost",	0, OPOST },
 	{ "litout",	0, OPOST },
@@ -209,7 +209,7 @@
 int
 msearch(char ***argvp, struct info *ip)
 {
-	struct modes *mp;
+	const struct modes *mp;
 	char *name;
 
 	name = **argvp;
diff -r 2230520c0499 -r 820af1e39cd6 head/cddl/contrib/opensolaris/cmd/zfs/zfs.8
--- a/head/cddl/contrib/opensolaris/cmd/zfs/zfs.8	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/cddl/contrib/opensolaris/cmd/zfs/zfs.8	Thu Dec 15 12:59:38 2011 +0200
@@ -22,7 +22,7 @@
 .\" Copyright (c) 2011 by Delphix. All rights reserved.
 .\" Copyright (c) 2011, Pawel Jakub Dawidek <pjd at FreeBSD.org>
 .\"
-.\" $FreeBSD: head/cddl/contrib/opensolaris/cmd/zfs/zfs.8 228206 2011-12-02 19:56:46Z mm $
+.\" $FreeBSD: head/cddl/contrib/opensolaris/cmd/zfs/zfs.8 228353 2011-12-08 19:38:42Z mm $
 .\"
 .Dd November 26, 2011
 .Dt ZFS 8
@@ -377,7 +377,7 @@
 automatically mounts the file system when the
 .Qq Nm Cm mount Fl a
 command is invoked (without editing
-.Pa /etc/fstab Ns ).
+.Pa /etc/fstab ) .
 The
 .Sy mountpoint
 property can be inherited, so if
@@ -409,7 +409,7 @@
 dataset can be attached to a jail by using the
 .Qq Nm Cm jail
 subcommand. You cannot attach a dataset to one jail and the children of the
-same dataset to another jails. To allow managment of the dataset from within
+same dataset to another jails. To allow management of the dataset from within
 a jail, the
 .Sy jailed
 property has to be set. The
@@ -624,10 +624,10 @@
 .Bl -bullet -offset 2n
 .It
 POSIX name (for example,
-.Em joe Ns )
+.Em joe )
 .It
 POSIX numeric ID (for example,
-.Em 1001 Ns )
+.Em 1001 )
 .El
 .It Sy userrefs
 This property is set to the number of user holds on this snapshot. User holds
@@ -673,7 +673,7 @@
 The
 .Ar snapshot
 may be specified as a short snapshot name (just the part after the
-.Sy @ Ns ),
+.Sy @ ) ,
 in which case it will be interpreted as a snapshot in the same filesystem as
 this dataset. The
 .Ar snapshot
@@ -847,7 +847,7 @@
 is equivalent to
 .Cm gzip-6
 (which is also the default for
-.Xr gzip 1 Ns ).
+.Xr gzip 1 ) .
 The
 .Cm zle
 compression algorithm compresses runs of zeros.
@@ -952,7 +952,7 @@
 such as snapshots and clones. User space consumption is identified by the
 .Sy [email protected] Ns Ar user
 property.
-.sp
+.Pp
 Enforcement of user quotas may be delayed by several seconds. This delay means
 that a user might exceed their quota before the system notices that they are
 over quota and begins to refuse additional writes with the
@@ -960,14 +960,14 @@
 error message. See the
 .Cm userspace
 subcommand for more information.
-.sp
+.Pp
 Unprivileged users can only access their own groups' space usage. The root
 user, or a user who has been granted the
 .Sy userquota
 privilege with
 .Qq Nm Cm allow ,
 can get and set everyone's quota.
-.sp
+.Pp
 This property is not available on volumes, on file systems before version 4, or
 on pools before version 15. The
 .Sy [email protected] Ns ...
@@ -979,17 +979,17 @@
 .Bl -bullet -offset 2n
 .It
 POSIX name (for example,
-.Em joe Ns )
+.Em joe )
 .It
 POSIX numeric ID (for example,
-.Em 1001 Ns )
+.Em 1001 )
 .El
 .It Sy [email protected] Ns Ar group Ns = Ns Ar size | Cm none
 Limits the amount of space consumed by the specified group. Group space
 consumption is identified by the
 .Sy [email protected] Ns Ar user
 property.
-.sp
+.Pp
 Unprivileged users can access only their own groups' space usage. The root
 user, or a user who has been granted the
 .Sy groupquota
@@ -1020,7 +1020,7 @@
 Changing the file system's
 .Sy recordsize
 affects only files created afterward; existing files are unaffected.
-.sp
+.Pp
 This property can also be referred to by its shortened column name,
 .Sy recsize .
 .It Sy refquota Ns = Ns Ar size | Cm none
@@ -1036,13 +1036,13 @@
 .Sy refreservation
 reservation is accounted for in the parent datasets' space used, and counts
 against the parent datasets' quotas and reservations.
-.sp
+.Pp
 If
 .Sy refreservation
 is set, a snapshot is only allowed if there is enough free pool space outside
 of this reservation to accommodate the current number of "referenced" bytes in
 the dataset.
-.sp
+.Pp
 This property can also be referred to by its shortened column name,
 .Sy refreserv .
 .It Sy reservation Ns = Ns Ar size | Cm none
@@ -1161,7 +1161,7 @@
 is set instead. Any changes to
 .Sy volsize
 are reflected in an equivalent change to the reservation (or
-.Sy refreservation Ns ).
+.Sy refreservation ) .
 The
 .Sy volsize
 can only be set to a multiple of
@@ -1174,7 +1174,7 @@
 on how the volume is used. These effects can also occur when the volume size is
 changed while it is in use (particularly when shrinking the size). Extreme care
 should be used when adjusting the volume size.
-.sp
+.Pp
 Though not recommended, a "sparse volume" (also known as "thin provisioning")
 can be created by specifying the
 .Fl s
@@ -1708,7 +1708,7 @@
 property is
 .Cm on
 (the default is
-.Cm off Ns ).
+.Cm off ) .
 The following fields are displayed,
 .Sy name , used , available , referenced , mountpoint .
 .Bl -tag -width indent
@@ -2168,10 +2168,10 @@
 argument (not part of
 .Fl i
 or
-.Fl I Ns )
+.Fl I )
 which is written to standard output. The output can be redirected to
 a file or to a different system (for example, using
-.Xr ssh 1 Ns ).
+.Xr ssh 1 ) .
 By default, a full stream is generated.
 .Bl -tag -width indent
 .It Fl i Ar snapshot
@@ -2180,10 +2180,10 @@
 to the last
 .Ar snapshot .
 The incremental source (the
-.Fl i Ar snapshot Ns )
+.Fl i Ar snapshot )
 can be specified as the last component of the snapshot name (for example, the
 part after the
-.Sy @ Ns ),
+.Sy @ ) ,
 and it is assumed to be from the same file system as the last
 .Ar snapshot .
 .Pp
@@ -2191,11 +2191,13 @@
 must be fully specified (for example, 
 .Cm pool/fs at origin ,
 not just
-.Cm @origin Ns ).
+.Cm @origin ) .
 .It Fl I Ar snapshot
 Generate a stream package that sends all intermediary snapshots from the
-.Fl I Ar snapshot to the last
-.Ar snapshot . For example,
+.Fl I Ar snapshot
+to the last
+.Ar snapshot .
+For example,
 .Ic -I @a fs at d
 is similar to
 .Ic -i @a fs at b; -i @b fs at c; -i @c fs at d .
@@ -2223,12 +2225,12 @@
 .It Fl D
 Generate a deduplicated stream. Blocks which would have been sent multiple
 times in the send stream will only be sent once.  The receiving system must
-also support this feature to recieve a deduplicated stream.  This flag can
+also support this feature to receive a deduplicated stream.  This flag can
 be used regardless of the dataset's
 .Sy dedup
 property, but performance will be much better if the filesystem uses a
 dedup-capable checksum (eg.
-.Sy sha256 Ns ).
+.Sy sha256 ) .
 .It Fl r
 Recursively send all descendant snapshots.  This is similar to the
 .Fl R
@@ -2323,14 +2325,14 @@
 appended (for example,
 .Sy b/c at 1
 appended from sent snapshot
-.Sy a/b/c at 1 Ns ),
+.Sy a/b/c at 1 ) ,
 and if the
 .Fl e
 option is specified, only the tail of the sent snapshot path is appended (for
 example,
 .Sy c at 1
 appended from sent snapshot
-.Sy a/b/c at 1 Ns ).
+.Sy a/b/c at 1 ) .
 In the case of
 .Fl d ,
 any file systems needed to replicate the path of the sent snapshot are created
@@ -2349,13 +2351,13 @@
 receive operation.
 .It Fl n
 Do not actually receive the stream. This can be useful in conjunction with the
-.It Fl v
+.Fl v
 option to verify the name the receive operation would use.
 .It Fl F
 Force a rollback of the file system to the most recent snapshot before
 performing the receive operation. If receiving an incremental replication
 stream (for example, one generated by
-.Qq Nm Cm send Fl R Fi iI Ns ) ,
+.Qq Nm Cm send Fl R Fi iI ) ,
 destroy snapshots and file systems that do not exist on the sending side.
 .El
 .It Xo
@@ -2409,7 +2411,8 @@
 .Op Fl e
 .Ar perm Ns | Ns Ar @setname Ns Op , Ns Ar ...
 .Xc
-Specifies that the permissions be delegated to "everyone." Multiple permissions
+Specifies that the permissions be delegated to "everyone".
+Multiple permissions
 may be specified as a comma-separated list. Permission names are the same as
 .Tn ZFS
 subcommand and property names. See the property list below. Property set names,
@@ -2655,7 +2658,7 @@
 successor dataset can be a later snapshot or the current filesystem.
 .Pp
 The changed files are displayed including the change type. The change type
-is displayed ussing a single character. If a file or directory was renamed,
+is displayed useing a single character. If a file or directory was renamed,
 the old and the new names are displayed.
 .Pp
 The following change types can be displayed:
@@ -2680,9 +2683,9 @@
 .It \&B Ta block device
 .It \&@ Ta symbolic link
 .It \&= Ta socket
-.It \&> Ta door (not supported on Fx Ns )
-.It \&| Ta FIFO (not supported on Fx Ns )
-.It \&P Ta event portal (not supported on Fx Ns )
+.It \&> Ta door (not supported on Fx )
+.It \&| Ta FIFO (not supported on Fx )
+.It \&P Ta event portal (not supported on Fx )
 .El
 .It Fl H
 Machine-parseable output, fields separated a tab character.
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/bsnmp/snmpd/snmpmod.h
--- a/head/contrib/bsnmp/snmpd/snmpmod.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/bsnmp/snmpd/snmpmod.h	Thu Dec 15 12:59:38 2011 +0200
@@ -40,6 +40,7 @@
 #define snmpmod_h_
 
 #include <sys/types.h>
+#include <sys/queue.h>
 #include <sys/socket.h>
 #include <net/if.h>
 #include <netinet/in.h>
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/gcclibs/libcpp/include/cpplib.h
--- a/head/contrib/gcclibs/libcpp/include/cpplib.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/gcclibs/libcpp/include/cpplib.h	Thu Dec 15 12:59:38 2011 +0200
@@ -555,7 +555,8 @@
   BT_TIME,			/* `__TIME__' */
   BT_STDC,			/* `__STDC__' */
   BT_PRAGMA,			/* `_Pragma' operator */
-  BT_TIMESTAMP			/* `__TIMESTAMP__' */
+  BT_TIMESTAMP,			/* `__TIMESTAMP__' */
+  BT_COUNTER			/* `__COUNTER__' */
 };
 
 #define CPP_HASHNODE(HNODE)	((cpp_hashnode *) (HNODE))
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/gcclibs/libcpp/init.c
--- a/head/contrib/gcclibs/libcpp/init.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/gcclibs/libcpp/init.c	Thu Dec 15 12:59:38 2011 +0200
@@ -308,6 +308,7 @@
   B("__BASE_FILE__",	 BT_BASE_FILE),
   B("__LINE__",		 BT_SPECLINE),
   B("__INCLUDE_LEVEL__", BT_INCLUDE_LEVEL),
+  B("__COUNTER__",	 BT_COUNTER),
   /* Keep builtins not used for -traditional-cpp at the end, and
      update init_builtins() if any more are added.  */
   B("_Pragma",		 BT_PRAGMA),
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/gcclibs/libcpp/internal.h
--- a/head/contrib/gcclibs/libcpp/internal.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/gcclibs/libcpp/internal.h	Thu Dec 15 12:59:38 2011 +0200
@@ -448,6 +448,8 @@
   /* A saved list of the defined macros, for dependency checking
      of precompiled headers.  */
   struct cpp_savedstate *savedstate;
+
+  unsigned int nextcounter;
 };
 
 /* Character classes.  Based on the more primitive macros in safe-ctype.h.
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/gcclibs/libcpp/macro.c
--- a/head/contrib/gcclibs/libcpp/macro.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/gcclibs/libcpp/macro.c	Thu Dec 15 12:59:38 2011 +0200
@@ -262,6 +262,10 @@
       else
 	result = pfile->time;
       break;
+
+    case BT_COUNTER:
+      number = pfile->nextcounter++;
+      break;
     }
 
   if (result == NULL)
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/groff/tmac/doc-common
--- a/head/contrib/groff/tmac/doc-common	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/groff/tmac/doc-common	Thu Dec 15 12:59:38 2011 +0200
@@ -264,50 +264,72 @@
 .ds doc-volume-as-algor        algor
 .ds doc-volume-as-amd64        amd64
 .ds doc-volume-as-amiga        amiga
+.ds doc-volume-as-amigappc     amigappc
 .ds doc-volume-as-arc          arc
+.ds doc-volume-as-arm          arm
 .ds doc-volume-as-arm26        arm26
 .ds doc-volume-as-arm32        arm32
+.ds doc-volume-as-armish       armish
 .ds doc-volume-as-atari        atari
+.ds doc-volume-as-aviion       aviion
+.ds doc-volume-as-beagle       beagle
 .ds doc-volume-as-bebox        bebox
 .ds doc-volume-as-cats         cats
 .ds doc-volume-as-cesfic       cesfic
 .ds doc-volume-as-cobalt       cobalt
 .ds doc-volume-as-dreamcast    dreamcast
+.ds doc-volume-as-emips        emips
 .ds doc-volume-as-evbarm       evbarm
 .ds doc-volume-as-evbmips      evbmips
 .ds doc-volume-as-evbppc       evbppc
 .ds doc-volume-as-evbsh3       evbsh3
+.ds doc-volume-as-ews4800mips  ews4800mips
 .ds doc-volume-as-hp300        hp300
 .ds doc-volume-as-hp700        hp700
 .ds doc-volume-as-hpcarm       hpcarm
 .ds doc-volume-as-hpcmips      hpcmips
 .ds doc-volume-as-hpcsh        hpcsh
+.ds doc-volume-as-hppa         hppa
+.ds doc-volume-as-hppa64       hppa64
 .ds doc-volume-as-i386         i386
+.ds doc-volume-as-ia64         ia64
+.ds doc-volume-as-ibmnws       ibmnws
+.ds doc-volume-as-iyonix       iyonix
+.ds doc-volume-as-landisk      landisk
+.ds doc-volume-as-loongson     loongson
 .ds doc-volume-as-luna68k      luna68k
+.ds doc-volume-as-luna88k      luna88k
 .ds doc-volume-as-m68k         m68k
 .ds doc-volume-as-mac68k       mac68k
 .ds doc-volume-as-macppc       macppc
 .ds doc-volume-as-mips         mips
+.ds doc-volume-as-mips64       mips64
 .ds doc-volume-as-mipsco       mipsco
 .ds doc-volume-as-mmeye        mmeye
 .ds doc-volume-as-mvme68k      mvme68k
+.ds doc-volume-as-mvme88k      mvme88k
 .ds doc-volume-as-mvmeppc      mvmeppc
 .ds doc-volume-as-netwinder    netwinder
 .ds doc-volume-as-news68k      news68k
 .ds doc-volume-as-newsmips     newsmips
 .ds doc-volume-as-next68k      next68k
 .ds doc-volume-as-ofppc        ofppc
+.ds doc-volume-as-palm         palm
 .ds doc-volume-as-pc532        pc532
 .ds doc-volume-as-playstation2 playstation2
 .ds doc-volume-as-pmax         pmax
 .ds doc-volume-as-pmppc        pmppc
 .ds doc-volume-as-powerpc      powerpc
 .ds doc-volume-as-prep         prep
+.ds doc-volume-as-rs6000       rs6000
 .ds doc-volume-as-sandpoint    sandpoint
 .ds doc-volume-as-sbmips       sbmips
+.ds doc-volume-as-sgi          sgi
 .ds doc-volume-as-sgimips      sgimips
 .ds doc-volume-as-sh3          sh3
 .ds doc-volume-as-shark        shark
+.ds doc-volume-as-socppc       socppc
+.ds doc-volume-as-solbourne    solbourne
 .ds doc-volume-as-sparc        sparc
 .ds doc-volume-as-sparc64      sparc64
 .ds doc-volume-as-sun2         sun2
@@ -316,6 +338,8 @@
 .ds doc-volume-as-vax          vax
 .ds doc-volume-as-x68k         x68k
 .ds doc-volume-as-x86_64       x86_64
+.ds doc-volume-as-xen          xen
+.ds doc-volume-as-zaurus       zaurus
 .
 .de Dt
 .  \" reset default arguments
@@ -451,12 +475,16 @@
 .ds doc-operating-system-NetBSD-3.0   3.0
 .ds doc-operating-system-NetBSD-3.0.1 3.0.1
 .ds doc-operating-system-NetBSD-3.0.2 3.0.2
+.ds doc-operating-system-NetBSD-3.0.3 3.0.3
 .ds doc-operating-system-NetBSD-3.1   3.1
+.ds doc-operating-system-NetBSD-3.1.1 3.1.1
 .ds doc-operating-system-NetBSD-4.0   4.0
 .ds doc-operating-system-NetBSD-4.0.1 4.0.1
 .ds doc-operating-system-NetBSD-5.0   5.0
 .ds doc-operating-system-NetBSD-5.0.1 5.0.1
 .ds doc-operating-system-NetBSD-5.0.2 5.0.2
+.ds doc-operating-system-NetBSD-5.1   5.1
+.ds doc-operating-system-NetBSD-6.0   6.0
 .
 .ds doc-operating-system-OpenBSD-2.0  2.0
 .ds doc-operating-system-OpenBSD-2.1  2.1
@@ -487,6 +515,8 @@
 .ds doc-operating-system-OpenBSD-4.6  4.6
 .ds doc-operating-system-OpenBSD-4.7  4.7
 .ds doc-operating-system-OpenBSD-4.8  4.8
+.ds doc-operating-system-OpenBSD-4.9  4.9
+.ds doc-operating-system-OpenBSD-5.0  5.0
 .
 .ds doc-operating-system-FreeBSD-1.0     1.0
 .ds doc-operating-system-FreeBSD-1.1     1.1
@@ -544,6 +574,7 @@
 .ds doc-operating-system-FreeBSD-8.0     8.0
 .ds doc-operating-system-FreeBSD-8.1     8.1
 .ds doc-operating-system-FreeBSD-8.2     8.2
+.ds doc-operating-system-FreeBSD-9.0     9.0
 .
 .ds doc-operating-system-Darwin-8.0.0  8.0.0
 .ds doc-operating-system-Darwin-8.1.0  8.1.0
@@ -566,7 +597,6 @@
 .ds doc-operating-system-Darwin-9.6.0  9.6.0
 .ds doc-operating-system-Darwin-9.7.0  9.7.0
 .ds doc-operating-system-Darwin-9.8.0  9.8.0
-.ds doc-operating-system-Darwin-10.6.0 10.6.0
 .ds doc-operating-system-Darwin-10.1.0 10.1.0
 .ds doc-operating-system-Darwin-10.2.0 10.2.0
 .ds doc-operating-system-Darwin-10.3.0 10.3.0
@@ -593,6 +623,11 @@
 .ds doc-operating-system-DragonFly-2.4    2.4
 .ds doc-operating-system-DragonFly-2.6    2.6
 .ds doc-operating-system-DragonFly-2.8    2.8
+.ds doc-operating-system-DragonFly-2.9    2.9
+.ds doc-operating-system-DragonFly-2.9.1  2.9.1
+.ds doc-operating-system-DragonFly-2.10   2.10
+.ds doc-operating-system-DragonFly-2.10.1 2.10.1
+.ds doc-operating-system-DragonFly-2.11   2.11
 .
 .de Os
 .  ds doc-command-name
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/groff/tmac/doc-syms
--- a/head/contrib/groff/tmac/doc-syms	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/groff/tmac/doc-syms	Thu Dec 15 12:59:38 2011 +0200
@@ -754,38 +754,74 @@
 .\" NS
 .\" NS width register `Lb' defined in doc-common
 .
+.ds doc-str-Lb-libarchive  Reading and Writing Streaming Archives Library (libarchive, \-larchive)
 .ds doc-str-Lb-libarm      ARM Architecture Library (libarm, \-larm)
 .ds doc-str-Lb-libarm32    ARM32 Architecture Library (libarm32, \-larm32)
+.ds doc-str-Lb-libbluetooth Bluetooth Library (libbluetooth, \-lbluetooth)
 .ds doc-str-Lb-libbsm      Basic Security Module Library (libbsm, \-lbsm)
 .ds doc-str-Lb-libc        Standard C\~Library (libc, \-lc)
+.ds doc-str-Lb-libc_r      Reentrant C\~Library (libc_r, \-lc_r)
+.ds doc-str-Lb-libcalendar Calendar Arithmetic Library (libcalendar, \-lcalendar)
+.ds doc-str-Lb-libcam      Common Access Method User Library (libcam, \-lcam)
 .ds doc-str-Lb-libcdk      Curses Development Kit Library (libcdk, \-lcdk)
+.ds doc-str-Lb-libcipher   FreeSec Crypt Library (libcipher, \-lcipher)
 .ds doc-str-Lb-libcompat   Compatibility Library (libcompat, \-lcompat)
 .ds doc-str-Lb-libcrypt    Crypt Library (libcrypt, \-lcrypt)
 .ds doc-str-Lb-libcurses   Curses Library (libcurses, \-lcurses)
+.ds doc-str-Lb-libdevinfo  Device and Resource Information Utility Library (libdevinfo, \-ldevinfo)
+.ds doc-str-Lb-libdevstat  Device Statistics Library (libdevstat, \-ldevstat)
+.ds doc-str-Lb-libdisk     Interface to Slice and Partition Labels Library (libdisk, \-ldisk)
+.ds doc-str-Lb-libdwarf    DWARF Access Library (libdwarf, \-ldwarf)
 .ds doc-str-Lb-libedit     Command Line Editor Library (libedit, \-ledit)
+.ds doc-str-Lb-libelf      ELF Access Library (libelf, \-lelf)
 .ds doc-str-Lb-libevent    Event Notification Library (libevent, \-levent)
+.ds doc-str-Lb-libfetch    File Transfer Library for URLs (libfetch, \-lfetch)
 .ds doc-str-Lb-libform     Curses Form Library (libform, \-lform)
+.ds doc-str-Lb-libgeom     Userland API Library for kernel GEOM subsystem (libgeom, \-lgeom)
+.ds doc-str-Lb-libgpib     General-Purpose Instrument Bus (GPIB) library (libgpib, \-lgpib)
 .ds doc-str-Lb-libi386     i386 Architecture Library (libi386, \-li386)
 .ds doc-str-Lb-libintl     Internationalized Message Handling Library (libintl, \-lintl)
 .ds doc-str-Lb-libipsec    IPsec Policy Control Library (libipsec, \-lipsec)
+.ds doc-str-Lb-libipx      IPX Address Conversion Support Library (libipx, \-lipx)
+.ds doc-str-Lb-libiscsi    iSCSI protocol library (libiscsi, \-liscsi)
+.ds doc-str-Lb-libjail     Jail Library (libjail, \-ljail)
+.ds doc-str-Lb-libkiconv   Kernel side iconv library (libkiconv, \-lkiconv)
+.ds doc-str-Lb-libkse      N:M Threading Library (libkse, \-lkse)
 .ds doc-str-Lb-libkvm      Kernel Data Access Library (libkvm, \-lkvm)
 .ds doc-str-Lb-libm        Math Library (libm, \-lm)
 .ds doc-str-Lb-libm68k     m68k Architecture Library (libm68k, \-lm68k)
 .ds doc-str-Lb-libmagic    Magic Number Recognition Library (libmagic, \-lmagic)
+.ds doc-str-Lb-libmd       Message Digest (MD4, MD5, etc.) Support Library (libmd, \-lmd)
+.ds doc-str-Lb-libmemstat  Kernel Memory Allocator Statistics Library (libmemstat, \-lmemstat)
 .ds doc-str-Lb-libmenu     Curses Menu Library (libmenu, \-lmenu)
+.ds doc-str-Lb-libnetgraph Netgraph User Library (libnetgraph, \-lnetgraph)
+.ds doc-str-Lb-libnetpgp   Netpgp signing, verification, encryption and decryption (libnetpgp, \-lnetpgp)
 .ds doc-str-Lb-libossaudio OSS Audio Emulation Library (libossaudio, \-lossaudio)
 .ds doc-str-Lb-libpam      Pluggable Authentication Module Library (libpam, \-lpam)
 .ds doc-str-Lb-libpcap     Packet Capture Library (libpcap, \-lpcap)
 .ds doc-str-Lb-libpci      PCI Bus Access Library (libpci, \-lpci)
 .ds doc-str-Lb-libpmc      Performance Counters Library (libpmc, \-lpmc)
 .ds doc-str-Lb-libposix    \*[Px] \*[doc-str-Lb]Compatibility Library (libposix, \-lposix)
+.ds doc-str-Lb-libprop     Property Container Object Library (libprop, \-lprop)
 .ds doc-str-Lb-libpthread  \*[Px] \*[doc-str-Lb]Threads Library (libpthread, \-lpthread)
+.ds doc-str-Lb-libpuffs    puffs Convenience Library (libpuffs, \-lpuffs)
+.ds doc-str-Lb-librefuse   File System in Userspace Convenience Library (librefuse, \-lrefuse)
 .ds doc-str-Lb-libresolv   DNS Resolver Library (libresolv, \-lresolv)
+.ds doc-str-Lb-librpcsec_gss RPC GSS-API Authentication Library (librpcsec_gss, \-lrpcsec_gss)
+.ds doc-str-Lb-librpcsvc   RPC Service Library (librpcsvc, \-lrpcsvc)
 .ds doc-str-Lb-librt       \*[Px] \*[doc-str-Lb]Real-time Library (librt, \-lrt)
+.ds doc-str-Lb-libsdp      Bluetooth Service Discovery Protocol User Library (libsdp, \-lsdp)
+.ds doc-str-Lb-libssp      Buffer Overflow Protection Library (libssp, \-lssp)
 .ds doc-str-Lb-libSystem   System Library (libSystem, \-lSystem)
 .ds doc-str-Lb-libtermcap  Termcap Access Library (libtermcap, \-ltermcap)
+.ds doc-str-Lb-libterminfo Terminal Information Library (libterminfo, \-lterminfo)
+.ds doc-str-Lb-libthr      1:1 Threading Library (libthr, \-lthr)
+.ds doc-str-Lb-libufs      UFS File System Access Library (libufs, \-lufs)
+.ds doc-str-Lb-libugidfw   File System Firewall Interface Library (libugidfw, \-lugidfw)
+.ds doc-str-Lb-libulog     User Login Record Library (libulog, \-lulog)
 .ds doc-str-Lb-libusbhid   USB Human Interface Devices Library (libusbhid, \-lusbhid)
 .ds doc-str-Lb-libutil     System Utilities Library (libutil, \-lutil)
+.ds doc-str-Lb-libvgl      Video Graphics Library (libvgl, \-lvgl)
 .ds doc-str-Lb-libx86_64   x86_64 Architecture Library (libx86_64, \-lx86_64)
 .ds doc-str-Lb-libz        Compression Library (libz, \-lz)
 .
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/groff/tmac/doc.tmac
--- a/head/contrib/groff/tmac/doc.tmac	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/groff/tmac/doc.tmac	Thu Dec 15 12:59:38 2011 +0200
@@ -4268,7 +4268,7 @@
 .      if (\n[doc-arg-limit] > \n[doc-arg-ptr]) \{\
 .        nr doc-reg-Xr (\n[doc-arg-ptr] + 1)
 .        \" modify second argument if it is a string and
-.        \" remove space inbetween
+.        \" remove space in between
 .        if (\n[doc-type\n[doc-reg-Xr]] == 2) \{\
 .          ds doc-arg\n[doc-reg-Xr] \*[lp]\*[doc-arg\n[doc-reg-Xr]]\*[rp]
 .          ds doc-space\n[doc-arg-ptr]
@@ -5091,7 +5091,7 @@
 .
 .
 .\" NS doc-build-func-string macro
-.\" NS   collect function arguments and set hard spaces inbetween
+.\" NS   collect function arguments and set hard spaces in between
 .\" NS
 .\" NS modifies:
 .\" NS   doc-func-arg
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/groff/tmac/groff_mdoc.man
--- a/head/contrib/groff/tmac/groff_mdoc.man	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/groff/tmac/groff_mdoc.man	Thu Dec 15 12:59:38 2011 +0200
@@ -769,13 +769,18 @@
 .
 \# we use `No' to avoid hyphenation
 .Bd -ragged -offset indent
-.No alpha , acorn26 , acorn32 , algor , amd64 , amiga , arc , arm26 ,
-.No arm32 , atari , bebox , cats , cesfic , cobalt , dreamcast , evbarm ,
-.No evbmips , evbppc , evbsh3 , hp300 , hp700 , hpcmips , i386 , luna68k ,
-.No m68k , mac68k , macppc , mips , mmeye , mvme68k , mvmeppc , netwinder ,
-.No news68k , newsmips , next68k , ofppc , pc532 , pmax , pmppc , powerpc ,
-.No prep , sandpoint , sgimips , sh3 , shark , sparc , sparc64 , sun3 ,
-.No tahoe , vax , x68k , x86_64
+.No acorn26 , acorn32 , algor , alpha , amd64 , amiga , amigappc ,
+.No arc , arm , arm26 , arm32 , armish , atari , aviion ,
+.No beagle , bebox , cats , cesfic , cobalt , dreamcast ,
+.No emips , evbarm , evbmips , evbppc , evbsh3 , ews4800mips ,
+.No hp300 , hp700 , hpcarm , hpcmips , hpcsh , hppa , hppa64 ,
+.No i386 , ia64 , ibmnws , iyonix , landisk , loongson , luna68k , luna88k ,
+.No m68k , mac68k , macppc , mips , mips64 , mipsco , mmeye ,
+.No mvme68k , mvme88k , mvmeppc , netwinder , news68k , newsmips , next68k ,
+.No ofppc , palm , pc532 , playstation2 , pmax , pmppc , powerpc , prep ,
+.No rs6000 , sandpoint , sbmips , sgi , sgimips , sh3 , shark ,
+.No socppc , solbourne , sparc , sparc64 , sun2 , sun3 ,
+.No tahoe , vax , x68k , x86_64 , xen , zaurus
 .Ed
 .Pp
 .
@@ -864,23 +869,25 @@
 .It NetBSD
 0.8, 0.8a, 0.9, 0.9a, 1.0, 1.0a, 1.1, 1.2, 1.2a, 1.2b, 1.2c, 1.2d, 1.2e,
 1.3, 1.3a, 1.4, 1.4.1, 1.4.2, 1.4.3, 1.5, 1.5.1, 1.5.2, 1.5.3, 1.6, 1.6.1,
-1.6.2, 1.6.3, 2.0, 2.0.1, 2.0.2, 2.0.3, 2.1, 3.0, 3.0.1, 3.0.2, 3.1, 4.0,
-4.0.1, 5.0, 5.0.1, 5.0.2
+1.6.2, 1.6.3, 2.0, 2.0.1, 2.0.2, 2.0.3, 2.1, 3.0, 3.0.1, 3.0.2, 3.0.3,
+3.1, 3.1.1, 4.0, 4.0.1, 5.0, 5.0.1, 5.0.2, 5.1, 6.0
 .It FreeBSD
 1.0, 1.1, 1.1.5, 1.1.5.1, 2.0, 2.0.5, 2.1, 2.1.5, 2.1.6, 2.1.7, 2.2, 2.2.1,
 2.2.2, 2.2.5, 2.2.6, 2.2.7, 2.2.8, 3.0, 3.1, 3.2, 3.3, 3.4, 3.5, 4.0, 4.1,
 4.1.1, 4.2, 4.3, 4.4, 4.5, 4.6, 4.6.2, 4.7, 4.8, 4.9, 4.10, 4.11, 5.0, 5.1,
 5.2, 5.2.1, 5.3, 5.4, 5.5, 6.0, 6.1, 6.2, 6.3, 6.4, 7.0, 7.1, 7.2, 7.3, 8.0,
-8.1
+8.1, 8.2, 9.0
 .It OpenBSD
 2.0, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 2.7, 2.8, 2.9, 3.0, 3.1, 3.2, 3.3, 3.4,
-3.5, 3.6, 3.7, 3.8, 3.9, 4.0, 4.1, 4.2, 4.3, 4.4, 4.5, 4.6, 4.7, 4.8
+3.5, 3.6, 3.7, 3.8, 3.9, 4.0, 4.1, 4.2, 4.3, 4.4, 4.5, 4.6, 4.7, 4.8, 4.9,
+5.0
 .It DragonFly
 1.0, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.8, 1.8.1, 1.10, 1.12, 1.12.2, 2.0, 2.2,
-2.4, 2.6, 2.8
+2.4, 2.6, 2.8, 2.9, 2.9.1, 2.10, 2.10.1, 2.11
 .It Darwin
 8.0.0, 8.1.0, 8.2.0, 8.3.0, 8.4.0, 8.5.0, 8.6.0, 8.7.0, 8.8.0, 8.9.0,
-8.10.0, 8.11.0, 9.0.0, 9.1.0, 9.2.0, 9.3.0, 9.4.0, 9.5.0, 9.6.0
+8.10.0, 8.11.0, 9.0.0, 9.1.0, 9.2.0, 9.3.0, 9.4.0, 9.5.0, 9.6.0, 9.7.0,
+9.8.0, 10.1.0, 10.2.0, 10.3.0, 10.4.0, 10.5.0, 10.6.0, 10.7.0, 11.0.0
 .El
 .Ed
 .Pp
@@ -1673,33 +1680,73 @@
 and their results are:
 .
 .Pp
-.Bl -tag -width ".Li libossaudio" -compact -offset indent
+.Bl -tag -width ".Li librpcsec_gss" -compact -offset indent
+.It Li libarchive
+.Lb libarchive
 .It Li libarm
 .Lb libarm
 .It Li libarm32
 .Lb libarm32
+.It Li libbluetooth
+.Lb libbluetooth
+.It Li libbsm
+.Lb libbsm
 .It Li libc
 .Lb libc
+.It Li libc_r
+.Lb libc_r
+.It Li libcalendar
+.Lb libcalendar
+.It Li libcam
+.Lb libcam
 .It Li libcdk
 .Lb libcdk
+.It Li libcipher
+.Lb libcipher
 .It Li libcompat
 .Lb libcompat
 .It Li libcrypt
 .Lb libcrypt
 .It Li libcurses
 .Lb libcurses
+.It Li libdevinfo
+.Lb libdevinfo
+.It Li libdevstat
+.Lb libdevstat
+.It Li libdisk
+.Lb libdisk
+.It Li libdwarf
+.Lb libdwarf
 .It Li libedit
 .Lb libedit
+.It Li libelf
+.Lb libelf
 .It Li libevent
 .Lb libevent
+.It Li libfetch
+.Lb libfetch
 .It Li libform
 .Lb libform
+.It Li libgeom
+.Lb libgeom
+.It Li libgpib
+.Lb libgpib
 .It Li libi386
 .Lb libi386
 .It Li libintl
 .Lb libintl
 .It Li libipsec
 .Lb libipsec
+.It Li libipx
+.Lb libipx
+.It Li libiscsi
+.Lb libiscsi
+.It Li libjail
+.Lb libjail
+.It Li libkiconv
+.Lb libkiconv
+.It Li libkse
+.Lb libkse
 .It Li libkvm
 .Lb libkvm
 .It Li libm
@@ -1708,8 +1755,16 @@
 .Lb libm68k
 .It Li libmagic
 .Lb libmagic
+.It Li libmd
+.Lb libmd
+.It Li libmemstat
+.Lb libmemstat
 .It Li libmenu
 .Lb libmenu
+.It Li libnetgraph
+.Lb libnetgraph
+.It Li libnetpgp
+.Lb libnetpgp
 .It Li libossaudio
 .Lb libossaudio
 .It Li libpam
@@ -1722,18 +1777,46 @@
 .Lb libpmc
 .It Li libposix
 .Lb libposix
+.It Li libprop
+.Lb libprop
 .It Li libpthread
 .Lb libpthread
+.It Li libpuffs
+.Lb libpuffs
+.It Li librefuse
+.Lb librefuse
 .It Li libresolv
 .Lb libresolv
+.It Li librpcsec_gss
+.Lb librpcsec_gss
+.It Li librpcsvc
+.Lb librpcsvc
 .It Li librt
 .Lb librt
+.It Li libsdp
+.Lb libsdp
+.It Li libssp
+.Lb libssp
+.It Li libSystem
+.Lb libSystem
 .It Li libtermcap
 .Lb libtermcap
+.It Li libterminfo
+.Lb libterminfo
+.It Li libthr
+.Lb libthr
+.It Li libufs
+.Lb libufs
+.It Li libugidfw
+.Lb libugidfw
+.It Li libulog
+.Lb libulog
 .It Li libusbhid
 .Lb libusbhid
 .It Li libutil
 .Lb libutil
+.It Li libvgl
+.Lb libvgl
 .It Li libx86_64
 .Lb libx86_64
 .It Li libz
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/libstdc++/include/debug/map.h
--- a/head/contrib/libstdc++/include/debug/map.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/libstdc++/include/debug/map.h	Thu Dec 15 12:59:38 2011 +0200
@@ -74,8 +74,6 @@
       typedef std::reverse_iterator<iterator>       reverse_iterator;
       typedef std::reverse_iterator<const_iterator> const_reverse_iterator;
 
-      using _Base::value_compare;
-
       // 23.3.1.1 construct/copy/destroy:
       explicit map(const _Compare& __comp = _Compare(),
 		   const _Allocator& __a = _Allocator())
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/libstdc++/include/debug/multimap.h
--- a/head/contrib/libstdc++/include/debug/multimap.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/libstdc++/include/debug/multimap.h	Thu Dec 15 12:59:38 2011 +0200
@@ -74,8 +74,6 @@
       typedef std::reverse_iterator<iterator>        reverse_iterator;
       typedef std::reverse_iterator<const_iterator>  const_reverse_iterator;
 
-      using _Base::value_compare;
-
       // 23.3.1.1 construct/copy/destroy:
       explicit multimap(const _Compare& __comp = _Compare(),
 			const _Allocator& __a = _Allocator())
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
--- a/head/contrib/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp	Thu Dec 15 12:59:38 2011 +0200
@@ -527,18 +527,20 @@
 
   // Get the raw data form of the large APInt.
   const APInt Val = CI->getValue();
-  const char *Ptr = (const char*)Val.getRawData();
+  const uint64_t *Ptr64 = Val.getRawData();
 
   int NumBytes = Val.getBitWidth() / 8; // 8 bits per byte.
   bool LittleEndian = Asm->getTargetData().isLittleEndian();
-  int Incr = (LittleEndian ? 1 : -1);
-  int Start = (LittleEndian ? 0 : NumBytes - 1);
-  int Stop = (LittleEndian ? NumBytes : -1);
 
   // Output the constant to DWARF one byte at a time.
-  for (; Start != Stop; Start += Incr)
-    addUInt(Block, 0, dwarf::DW_FORM_data1,
-            (unsigned char)0xFF & Ptr[Start]);
+  for (int i = 0; i < NumBytes; i++) {
+    uint8_t c;
+    if (LittleEndian)
+      c = Ptr64[i / 8] >> (8 * (i & 7));
+    else
+      c = Ptr64[(NumBytes - 1 - i) / 8] >> (8 * ((NumBytes - 1 - i) & 7));
+    addUInt(Block, 0, dwarf::DW_FORM_data1, c);
+  }
 
   addBlock(Die, dwarf::DW_AT_const_value, 0, Block);
   return true;
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/lib/CodeGen/LLVMTargetMachine.cpp
--- a/head/contrib/llvm/lib/CodeGen/LLVMTargetMachine.cpp	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/lib/CodeGen/LLVMTargetMachine.cpp	Thu Dec 15 12:59:38 2011 +0200
@@ -119,7 +119,8 @@
   // we'll crash later.
   // Provide the user with a useful error message about what's wrong.
   assert(AsmInfo && "MCAsmInfo not initialized."
-	 "Make sure you include the correct TargetSelect.h!");
+         "Make sure you include the correct TargetSelect.h"
+         "and that InitializeAllTargetMCs() is being invoked!");
 }
 
 bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
--- a/head/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp	Thu Dec 15 12:59:38 2011 +0200
@@ -2034,14 +2034,17 @@
     return false;
 
   APInt Range = ComputeRange(First, Last);
-  double Density = TSize.roundToDouble() / Range.roundToDouble();
-  if (Density < 0.4)
+  // The density is TSize / Range. Require at least 40%.
+  // It should not be possible for IntTSize to saturate for sane code, but make
+  // sure we handle Range saturation correctly.
+  uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
+  uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
+  if (IntTSize * 10 < IntRange * 4)
     return false;
 
   DEBUG(dbgs() << "Lowering jump table\n"
                << "First entry: " << First << ". Last entry: " << Last << '\n'
-               << "Range: " << Range
-               << ". Size: " << TSize << ". Density: " << Density << "\n\n");
+               << "Range: " << Range << ". Size: " << TSize << ".\n\n");
 
   // Get the MachineFunction which holds the current MBB.  This is used when
   // inserting any additional MBBs necessary to represent the switch.
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
--- a/head/contrib/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp	Thu Dec 15 12:59:38 2011 +0200
@@ -506,7 +506,9 @@
     // Add information about the stub reference to MachOMMI so that the stub
     // gets emitted by the asmprinter.
     MCSymbol *SSym = getContext().GetOrCreateSymbol(Name.str());
-    MachineModuleInfoImpl::StubValueTy &StubSym = MachOMMI.getGVStubEntry(SSym);
+    MachineModuleInfoImpl::StubValueTy &StubSym =
+      GV->hasHiddenVisibility() ? MachOMMI.getHiddenGVStubEntry(SSym) :
+                                  MachOMMI.getGVStubEntry(SSym);
     if (StubSym.getPointer() == 0) {
       MCSymbol *Sym = Mang->getSymbol(GV);
       StubSym = MachineModuleInfoImpl::StubValueTy(Sym, !GV->hasLocalLinkage());
@@ -534,7 +536,9 @@
   // Add information about the stub reference to MachOMMI so that the stub
   // gets emitted by the asmprinter.
   MCSymbol *SSym = getContext().GetOrCreateSymbol(Name.str());
-  MachineModuleInfoImpl::StubValueTy &StubSym = MachOMMI.getGVStubEntry(SSym);
+  MachineModuleInfoImpl::StubValueTy &StubSym =
+      GV->hasHiddenVisibility() ? MachOMMI.getHiddenGVStubEntry(SSym) :
+                                  MachOMMI.getGVStubEntry(SSym);
   if (StubSym.getPointer() == 0) {
     MCSymbol *Sym = Mang->getSymbol(GV);
     StubSym = MachineModuleInfoImpl::StubValueTy(Sym, !GV->hasLocalLinkage());
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
--- a/head/contrib/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp	Thu Dec 15 12:59:38 2011 +0200
@@ -63,6 +63,13 @@
 
 const unsigned*
 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
+  bool ghcCall = false;
+
+  if (MF) {
+    const Function *F = MF->getFunction();
+    ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
+  }
+
   static const unsigned CalleeSavedRegs[] = {
     ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
     ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
@@ -82,7 +89,13 @@
     ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
     0
   };
-  return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
+
+  static const unsigned GhcCalleeSavedRegs[] = {
+    0
+  };
+
+  return ghcCall ? GhcCalleeSavedRegs :
+         STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
 }
 
 BitVector ARMBaseRegisterInfo::
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/lib/Target/ARM/ARMCallingConv.td
--- a/head/contrib/llvm/lib/Target/ARM/ARMCallingConv.td	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/lib/Target/ARM/ARMCallingConv.td	Thu Dec 15 12:59:38 2011 +0200
@@ -82,6 +82,25 @@
   CCDelegateTo<RetCC_ARM_APCS>
 ]>;
 
+//===----------------------------------------------------------------------===//
+// ARM APCS Calling Convention for GHC
+//===----------------------------------------------------------------------===//
+
+def CC_ARM_APCS_GHC : CallingConv<[
+  // Handle all vector types as either f64 or v2f64.
+  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
+  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
+
+  CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>,
+  CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>,
+  CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>,
+
+  // Promote i8/i16 arguments to i32.
+  CCIfType<[i8, i16], CCPromoteToType<i32>>,
+
+  // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, SpLim
+  CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
+]>;
 
 //===----------------------------------------------------------------------===//
 // ARM AAPCS (EABI) Calling Convention, common parts
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/lib/Target/ARM/ARMFastISel.cpp
--- a/head/contrib/llvm/lib/Target/ARM/ARMFastISel.cpp	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/lib/Target/ARM/ARMFastISel.cpp	Thu Dec 15 12:59:38 2011 +0200
@@ -1548,6 +1548,11 @@
     return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
   case CallingConv::ARM_APCS:
     return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
+  case CallingConv::GHC:
+    if (Return)
+      llvm_unreachable("Can't return in GHC call convention");
+    else
+      return CC_ARM_APCS_GHC;
   }
 }
 
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/lib/Target/ARM/ARMFrameLowering.cpp
--- a/head/contrib/llvm/lib/Target/ARM/ARMFrameLowering.cpp	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/lib/Target/ARM/ARMFrameLowering.cpp	Thu Dec 15 12:59:38 2011 +0200
@@ -15,6 +15,8 @@
 #include "ARMBaseInstrInfo.h"
 #include "ARMBaseRegisterInfo.h"
 #include "ARMMachineFunctionInfo.h"
+#include "llvm/CallingConv.h"
+#include "llvm/Function.h"
 #include "MCTargetDesc/ARMAddressingModes.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
@@ -139,6 +141,10 @@
   unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
   int FramePtrSpillFI = 0;
 
+  // All calls are tail calls in GHC calling conv, and functions have no prologue/epilogue.
+  if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
+    return;
+
   // Allocate the vararg register save area. This is not counted in NumBytes.
   if (VARegSaveSize)
     emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize,
@@ -326,6 +332,10 @@
   int NumBytes = (int)MFI->getStackSize();
   unsigned FramePtr = RegInfo->getFrameRegister(MF);
 
+  // All calls are tail calls in GHC calling conv, and functions have no prologue/epilogue.
+  if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
+    return;
+
   if (!AFI->hasStackFrame()) {
     if (NumBytes != 0)
       emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp
--- a/head/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp	Thu Dec 15 12:59:38 2011 +0200
@@ -1091,6 +1091,8 @@
     return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
   case CallingConv::ARM_APCS:
     return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
+  case CallingConv::GHC:
+    return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
   }
 }
 
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/lib/Target/ARM/ARMInstrThumb2.td
--- a/head/contrib/llvm/lib/Target/ARM/ARMInstrThumb2.td	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/lib/Target/ARM/ARMInstrThumb2.td	Thu Dec 15 12:59:38 2011 +0200
@@ -1538,8 +1538,7 @@
     let Inst{21}    = 0;        // No writeback
     let Inst{20}    = L_bit;
     let Inst{19-16} = Rn;
-    let Inst{15}    = 0;
-    let Inst{14-0}  = regs{14-0};
+    let Inst{15-0}  = regs;
   }
   def IA_UPD :
     T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
@@ -1554,8 +1553,7 @@
     let Inst{21}    = 1;        // Writeback
     let Inst{20}    = L_bit;
     let Inst{19-16} = Rn;
-    let Inst{15}    = 0;
-    let Inst{14-0}  = regs{14-0};
+    let Inst{15-0}  = regs;
   }
   def DB :
     T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
@@ -1570,8 +1568,7 @@
     let Inst{21}    = 0;        // No writeback
     let Inst{20}    = L_bit;
     let Inst{19-16} = Rn;
-    let Inst{15}    = 0;
-    let Inst{14-0}  = regs{14-0};
+    let Inst{15-0}  = regs;
   }
   def DB_UPD :
     T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
@@ -1586,8 +1583,7 @@
     let Inst{21}    = 1;        // Writeback
     let Inst{20}    = L_bit;
     let Inst{19-16} = Rn;
-    let Inst{15}    = 0;
-    let Inst{14-0}  = regs{14-0};
+    let Inst{15-0}  = regs;
   }
 }
 
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/lib/Target/CppBackend/CPPBackend.cpp
--- a/head/contrib/llvm/lib/Target/CppBackend/CPPBackend.cpp	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/lib/Target/CppBackend/CPPBackend.cpp	Thu Dec 15 12:59:38 2011 +0200
@@ -1016,6 +1016,27 @@
   return result;
 }
 
+static StringRef ConvertAtomicOrdering(AtomicOrdering Ordering) {
+  switch (Ordering) {
+    case NotAtomic: return "NotAtomic";
+    case Unordered: return "Unordered";
+    case Monotonic: return "Monotonic";
+    case Acquire: return "Acquire";
+    case Release: return "Release";
+    case AcquireRelease: return "AcquireRelease";
+    case SequentiallyConsistent: return "SequentiallyConsistent";
+  }
+  llvm_unreachable("Unknown ordering");
+}
+
+static StringRef ConvertAtomicSynchScope(SynchronizationScope SynchScope) {
+  switch (SynchScope) {
+    case SingleThread: return "SingleThread";
+    case CrossThread: return "CrossThread";
+  }
+  llvm_unreachable("Unknown synch scope");
+}
+
 // printInstruction - This member is called for each Instruction in a function.
 void CppWriter::printInstruction(const Instruction *I,
                                  const std::string& bbname) {
@@ -1237,15 +1258,33 @@
     printEscapedString(load->getName());
     Out << "\", " << (load->isVolatile() ? "true" : "false" )
         << ", " << bbname << ");";
+    if (load->getAlignment())
+      nl(Out) << iName << "->setAlignment("
+              << load->getAlignment() << ");";
+    if (load->isAtomic()) {
+      StringRef Ordering = ConvertAtomicOrdering(load->getOrdering());
+      StringRef CrossThread = ConvertAtomicSynchScope(load->getSynchScope());
+      nl(Out) << iName << "->setAtomic("
+              << Ordering << ", " << CrossThread << ");";
+    }
     break;
   }
   case Instruction::Store: {
     const StoreInst* store = cast<StoreInst>(I);
-    Out << " new StoreInst("
+    Out << "StoreInst* " << iName << " = new StoreInst("
         << opNames[0] << ", "
         << opNames[1] << ", "
         << (store->isVolatile() ? "true" : "false")
         << ", " << bbname << ");";
+    if (store->getAlignment())
+      nl(Out) << iName << "->setAlignment("
+              << store->getAlignment() << ");";
+    if (store->isAtomic()) {
+      StringRef Ordering = ConvertAtomicOrdering(store->getOrdering());
+      StringRef CrossThread = ConvertAtomicSynchScope(store->getSynchScope());
+      nl(Out) << iName << "->setAtomic("
+              << Ordering << ", " << CrossThread << ");";
+    }
     break;
   }
   case Instruction::GetElementPtr: {
@@ -1447,6 +1486,60 @@
     Out << "\", " << bbname << ");";
     break;
   }
+  case Instruction::Fence: {
+    const FenceInst *fi = cast<FenceInst>(I);
+    StringRef Ordering = ConvertAtomicOrdering(fi->getOrdering());
+    StringRef CrossThread = ConvertAtomicSynchScope(fi->getSynchScope());
+    Out << "FenceInst* " << iName
+        << " = new FenceInst(mod->getContext(), "
+        << Ordering << ", " << CrossThread << ", " << bbname
+        << ");";
+    break;
+  }
+  case Instruction::AtomicCmpXchg: {
+    const AtomicCmpXchgInst *cxi = cast<AtomicCmpXchgInst>(I);
+    StringRef Ordering = ConvertAtomicOrdering(cxi->getOrdering());
+    StringRef CrossThread = ConvertAtomicSynchScope(cxi->getSynchScope());
+    Out << "AtomicCmpXchgInst* " << iName
+        << " = new AtomicCmpXchgInst("
+        << opNames[0] << ", " << opNames[1] << ", " << opNames[2] << ", "
+        << Ordering << ", " << CrossThread << ", " << bbname
+        << ");";
+    nl(Out) << iName << "->setName(\"";
+    printEscapedString(cxi->getName());
+    Out << "\");";
+    break;
+  }
+  case Instruction::AtomicRMW: {
+    const AtomicRMWInst *rmwi = cast<AtomicRMWInst>(I);
+    StringRef Ordering = ConvertAtomicOrdering(rmwi->getOrdering());
+    StringRef CrossThread = ConvertAtomicSynchScope(rmwi->getSynchScope());
+    StringRef Operation;
+    switch (rmwi->getOperation()) {
+      case AtomicRMWInst::Xchg: Operation = "AtomicRMWInst::Xchg"; break;
+      case AtomicRMWInst::Add:  Operation = "AtomicRMWInst::Add"; break;
+      case AtomicRMWInst::Sub:  Operation = "AtomicRMWInst::Sub"; break;
+      case AtomicRMWInst::And:  Operation = "AtomicRMWInst::And"; break;
+      case AtomicRMWInst::Nand: Operation = "AtomicRMWInst::Nand"; break;
+      case AtomicRMWInst::Or:   Operation = "AtomicRMWInst::Or"; break;
+      case AtomicRMWInst::Xor:  Operation = "AtomicRMWInst::Xor"; break;
+      case AtomicRMWInst::Max:  Operation = "AtomicRMWInst::Max"; break;
+      case AtomicRMWInst::Min:  Operation = "AtomicRMWInst::Min"; break;
+      case AtomicRMWInst::UMax: Operation = "AtomicRMWInst::UMax"; break;
+      case AtomicRMWInst::UMin: Operation = "AtomicRMWInst::UMin"; break;
+      case AtomicRMWInst::BAD_BINOP: llvm_unreachable("Bad atomic operation");
+    }
+    Out << "AtomicRMWInst* " << iName
+        << " = new AtomicRMWInst("
+        << Operation << ", "
+        << opNames[0] << ", " << opNames[1] << ", "
+        << Ordering << ", " << CrossThread << ", " << bbname
+        << ");";
+    nl(Out) << iName << "->setName(\"";
+    printEscapedString(rmwi->getName());
+    Out << "\");";
+    break;
+  }
   }
   DefinedValues.insert(I);
   nl(Out);
@@ -1623,7 +1716,9 @@
       Out << "Value* " << getCppName(AI) << " = args++;";
       nl(Out);
       if (AI->hasName()) {
-        Out << getCppName(AI) << "->setName(\"" << AI->getName() << "\");";
+        Out << getCppName(AI) << "->setName(\"";
+        printEscapedString(AI->getName());
+        Out << "\");";
         nl(Out);
       }
     }
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/lib/Target/Mips/Mips64InstrInfo.td
--- a/head/contrib/llvm/lib/Target/Mips/Mips64InstrInfo.td	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/lib/Target/Mips/Mips64InstrInfo.td	Thu Dec 15 12:59:38 2011 +0200
@@ -39,51 +39,51 @@
 // Shifts
 class LogicR_shift_rotate_imm64<bits<6> func, bits<5> _rs, string instr_asm,
                                 SDNode OpNode, PatFrag PF>:
-  FR<0x00, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, shamt_64:$c),
-     !strconcat(instr_asm, "\t$dst, $b, $c"),
-     [(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, (i64 PF:$c)))],
+  FR<0x00, func, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt, shamt_64:$shamt),
+     !strconcat(instr_asm, "\t$rd, $rt, $shamt"),
+     [(set CPU64Regs:$rd, (OpNode CPU64Regs:$rt, (i64 PF:$shamt)))],
      IIAlu> {
   let rs = _rs;
 }
 
 class LogicR_shift_rotate_reg64<bits<6> func, bits<5> _shamt, string instr_asm,
                                 SDNode OpNode>:
-  FR<0x00, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$c, CPU64Regs:$b),
-     !strconcat(instr_asm, "\t$dst, $b, $c"),
-     [(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, CPU64Regs:$c))], IIAlu> {
+  FR<0x00, func, (outs CPU64Regs:$rd), (ins CPU64Regs:$rs, CPU64Regs:$rt),
+     !strconcat(instr_asm, "\t$rd, $rt, $rs"),
+     [(set CPU64Regs:$rd, (OpNode CPU64Regs:$rt, CPU64Regs:$rs))], IIAlu> {
   let shamt = _shamt;
 }
 
 // Mul, Div
-let Defs = [HI64, LO64] in {
+let rd = 0, shamt = 0, Defs = [HI64, LO64] in {
   let isCommutable = 1 in
   class Mul64<bits<6> func, string instr_asm, InstrItinClass itin>:
-    FR<0x00, func, (outs), (ins CPU64Regs:$a, CPU64Regs:$b),
-       !strconcat(instr_asm, "\t$a, $b"), [], itin>;
+    FR<0x00, func, (outs), (ins CPU64Regs:$rs, CPU64Regs:$rt),
+       !strconcat(instr_asm, "\t$rs, $rt"), [], itin>;
 
   class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
-              FR<0x00, func, (outs), (ins CPU64Regs:$a, CPU64Regs:$b),
-              !strconcat(instr_asm, "\t$$zero, $a, $b"),
-              [(op CPU64Regs:$a, CPU64Regs:$b)], itin>;
+              FR<0x00, func, (outs), (ins CPU64Regs:$rs, CPU64Regs:$rt),
+              !strconcat(instr_asm, "\t$$zero, $rs, $rt"),
+              [(op CPU64Regs:$rs, CPU64Regs:$rt)], itin>;
 }
 
 // Move from Hi/Lo
 let shamt = 0 in {
 let rs = 0, rt = 0 in
 class MoveFromLOHI64<bits<6> func, string instr_asm>:
-  FR<0x00, func, (outs CPU64Regs:$dst), (ins),
-     !strconcat(instr_asm, "\t$dst"), [], IIHiLo>;
+  FR<0x00, func, (outs CPU64Regs:$rd), (ins),
+     !strconcat(instr_asm, "\t$rd"), [], IIHiLo>;
 
 let rt = 0, rd = 0 in
 class MoveToLOHI64<bits<6> func, string instr_asm>:
-  FR<0x00, func, (outs), (ins CPU64Regs:$src),
-     !strconcat(instr_asm, "\t$src"), [], IIHiLo>;
+  FR<0x00, func, (outs), (ins CPU64Regs:$rs),
+     !strconcat(instr_asm, "\t$rs"), [], IIHiLo>;
 }
 
 // Count Leading Ones/Zeros in Word
 class CountLeading64<bits<6> func, string instr_asm, list<dag> pattern>:
-  FR<0x1c, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$src),
-     !strconcat(instr_asm, "\t$dst, $src"), pattern, IIAlu>,
+  FR<0x1c, func, (outs CPU64Regs:$rd), (ins CPU64Regs:$rs),
+     !strconcat(instr_asm, "\t$rd, $rs"), pattern, IIAlu>,
      Requires<[HasBitCount]> {
   let shamt = 0;
   let rt = rd;
@@ -180,9 +180,9 @@
 
 /// Count Leading
 def DCLZ : CountLeading64<0x24, "dclz",
-                          [(set CPU64Regs:$dst, (ctlz CPU64Regs:$src))]>;
+                          [(set CPU64Regs:$rd, (ctlz CPU64Regs:$rs))]>;
 def DCLO : CountLeading64<0x25, "dclo",
-                          [(set CPU64Regs:$dst, (ctlz (not CPU64Regs:$src)))]>;
+                          [(set CPU64Regs:$rd, (ctlz (not CPU64Regs:$rs)))]>;
 
 //===----------------------------------------------------------------------===//
 //  Arbitrary patterns that map to one or more instructions
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/lib/Target/Mips/MipsCodeEmitter.cpp
--- a/head/contrib/llvm/lib/Target/Mips/MipsCodeEmitter.cpp	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/lib/Target/Mips/MipsCodeEmitter.cpp	Thu Dec 15 12:59:38 2011 +0200
@@ -105,6 +105,9 @@
     unsigned getRelocation(const MachineInstr &MI,
                            const MachineOperand &MO) const;
 
+    unsigned getMemEncoding(const MachineInstr &MI, unsigned OpNo) const;
+    unsigned getSizeExtEncoding(const MachineInstr &MI, unsigned OpNo) const;
+    unsigned getSizeInsEncoding(const MachineInstr &MI, unsigned OpNo) const;
   };
 }
 
@@ -153,6 +156,28 @@
   return Mips::reloc_mips_lo;
 }
 
+unsigned MipsCodeEmitter::getMemEncoding(const MachineInstr &MI,
+                                          unsigned OpNo) const {
+  // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
+  assert(MI.getOperand(OpNo).isReg());
+  unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo)) << 16;
+  return
+    (getMachineOpValue(MI, MI.getOperand(OpNo+1)) & 0xFFFF) | RegBits;
+}
+
+unsigned MipsCodeEmitter::getSizeExtEncoding(const MachineInstr &MI,
+                                          unsigned OpNo) const {
+  // size is encoded as size-1.
+  return getMachineOpValue(MI, MI.getOperand(OpNo)) - 1;
+}
+
+unsigned MipsCodeEmitter::getSizeInsEncoding(const MachineInstr &MI,
+                                          unsigned OpNo) const {
+  // size is encoded as pos+size-1.
+  return getMachineOpValue(MI, MI.getOperand(OpNo-1)) +
+         getMachineOpValue(MI, MI.getOperand(OpNo)) - 1;
+}
+
 /// getMachineOpValue - Return binary encoding of operand. If the machine
 /// operand requires relocation, record the relocation and return zero.
 unsigned MipsCodeEmitter::getMachineOpValue(const MachineInstr &MI,
@@ -238,8 +263,4 @@
   return new MipsCodeEmitter(TM, JCE);
 }
 
-unsigned MipsCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) const {
- // this function will be automatically generated by the CodeEmitterGenerator
- // using TableGen
- return 0;
-}
+#include "MipsGenCodeEmitter.inc"
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/lib/Target/Mips/MipsInstrFPU.td
--- a/head/contrib/llvm/lib/Target/Mips/MipsInstrFPU.td	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/lib/Target/Mips/MipsInstrFPU.td	Thu Dec 15 12:59:38 2011 +0200
@@ -76,14 +76,16 @@
 // FP load.
 class FPLoad<bits<6> op, string opstr, PatFrag FOp, RegisterClass RC,
              Operand MemOpnd>:
-  FFI<op, (outs RC:$ft), (ins MemOpnd:$base),
-      !strconcat(opstr, "\t$ft, $base"), [(set RC:$ft, (FOp addr:$base))]>;
+  FMem<op, (outs RC:$ft), (ins MemOpnd:$addr),
+      !strconcat(opstr, "\t$ft, $addr"), [(set RC:$ft, (FOp addr:$addr))],
+      IILoad>;
 
 // FP store.
 class FPStore<bits<6> op, string opstr, PatFrag FOp, RegisterClass RC,
               Operand MemOpnd>:
-  FFI<op, (outs), (ins RC:$ft, MemOpnd:$base),
-      !strconcat(opstr, "\t$ft, $base"), [(store RC:$ft, addr:$base)]>;
+  FMem<op, (outs), (ins RC:$ft, MemOpnd:$addr),
+      !strconcat(opstr, "\t$ft, $addr"), [(store RC:$ft, addr:$addr)],
+      IIStore>;
 
 // Instructions that convert an FP value to 32-bit fixed point.
 multiclass FFR1_W_M<bits<6> funct, string opstr> {
@@ -158,22 +160,28 @@
 // stores, and moves between floating-point and integer registers.
 // When defining instructions, we reference all 32-bit registers,
 // regardless of register aliasing.
-let fd = 0 in {
-  /// Move Control Registers From/To CPU Registers
-  def CFC1  : FFR<0x11, 0x0, 0x2, (outs CPURegs:$rt), (ins CCR:$fs),
+
+class FFRGPR<bits<5> _fmt, dag outs, dag ins, string asmstr, list<dag> pattern>:
+             FFR<0x11, 0x0, _fmt, outs, ins, asmstr, pattern> {
+  bits<5> rt;
+  let ft = rt;
+  let fd = 0;
+}
+
+/// Move Control Registers From/To CPU Registers
+def CFC1  : FFRGPR<0x2, (outs CPURegs:$rt), (ins CCR:$fs),
                   "cfc1\t$rt, $fs", []>;
 
-  def CTC1  : FFR<0x11, 0x0, 0x6, (outs CCR:$rt), (ins CPURegs:$fs),
-                  "ctc1\t$fs, $rt", []>;
+def CTC1  : FFRGPR<0x6, (outs CCR:$fs), (ins CPURegs:$rt),
+                  "ctc1\t$rt, $fs", []>;
 
-  def MFC1  : FFR<0x11, 0x00, 0x00, (outs CPURegs:$rt), (ins FGR32:$fs),
+def MFC1  : FFRGPR<0x00, (outs CPURegs:$rt), (ins FGR32:$fs),
                   "mfc1\t$rt, $fs",
                   [(set CPURegs:$rt, (bitconvert FGR32:$fs))]>;
 
-  def MTC1  : FFR<0x11, 0x00, 0x04, (outs FGR32:$fs), (ins CPURegs:$rt),
+def MTC1  : FFRGPR<0x04, (outs FGR32:$fs), (ins CPURegs:$rt),
                   "mtc1\t$rt, $fs",
                   [(set FGR32:$fs, (bitconvert CPURegs:$rt))]>;
-}
 
 def FMOV_S   : FFR1<0x6, 16, "mov", "s", FGR32, FGR32>;
 def FMOV_D32 : FFR1<0x6, 17, "mov", "d", AFGR64, AFGR64>,
@@ -203,7 +211,7 @@
 }
 
 /// Floating-point Aritmetic
-defm FADD : FFR2P_M<0x10, "add", fadd, 1>;
+defm FADD : FFR2P_M<0x00, "add", fadd, 1>;
 defm FDIV : FFR2P_M<0x03, "div", fdiv>;
 defm FMUL : FFR2P_M<0x02, "mul", fmul, 1>;
 defm FSUB : FFR2P_M<0x01, "sub", fsub>;
@@ -218,12 +226,16 @@
 
 /// Floating Point Branch of False/True (Likely)
 let isBranch=1, isTerminator=1, hasDelaySlot=1, base=0x8, Uses=[FCR31] in
-  class FBRANCH<PatLeaf op, string asmstr> : FFI<0x11, (outs),
-        (ins brtarget:$dst), !strconcat(asmstr, "\t$dst"),
-        [(MipsFPBrcond op, bb:$dst)]>;
+  class FBRANCH<bits<1> nd, bits<1> tf, PatLeaf op, string asmstr> :
+      FFI<0x11, (outs), (ins brtarget:$dst), !strconcat(asmstr, "\t$dst"),
+        [(MipsFPBrcond op, bb:$dst)]> {
+  let Inst{20-18} = 0;
+  let Inst{17} = nd;
+  let Inst{16} = tf;
+}
 
-def BC1F  : FBRANCH<MIPS_BRANCH_F,  "bc1f">;
-def BC1T  : FBRANCH<MIPS_BRANCH_T,  "bc1t">;
+def BC1F  : FBRANCH<0, 0, MIPS_BRANCH_F,  "bc1f">;
+def BC1T  : FBRANCH<0, 1, MIPS_BRANCH_T,  "bc1t">;
 
 //===----------------------------------------------------------------------===//
 // Floating Point Flag Conditions
@@ -249,11 +261,11 @@
 
 /// Floating Point Compare
 let Defs=[FCR31] in {
-  def FCMP_S32 : FCC<0x0, (outs), (ins FGR32:$fs, FGR32:$ft, condcode:$cc),
+  def FCMP_S32 : FCC<0x10, (outs), (ins FGR32:$fs, FGR32:$ft, condcode:$cc),
                      "c.$cc.s\t$fs, $ft",
                      [(MipsFPCmp FGR32:$fs, FGR32:$ft, imm:$cc)]>;
 
-  def FCMP_D32 : FCC<0x1, (outs), (ins AFGR64:$fs, AFGR64:$ft, condcode:$cc),
+  def FCMP_D32 : FCC<0x11, (outs), (ins AFGR64:$fs, AFGR64:$ft, condcode:$cc),
                      "c.$cc.d\t$fs, $ft",
                      [(MipsFPCmp AFGR64:$fs, AFGR64:$ft, imm:$cc)]>,
                      Requires<[NotFP64bit]>;
@@ -287,7 +299,8 @@
   defm : MovnPats<AFGR64, MOVN_D>;
 }
 
-let usesCustomInserter = 1, Uses = [FCR31], Constraints = "$F = $dst" in {
+let cc = 0, usesCustomInserter = 1, Uses = [FCR31],
+    Constraints = "$F = $dst" in {
 // flag:float, data:int
 class CondMovFPInt<SDNode cmov, bits<1> tf, string instr_asm> :
   FCMOV<tf, (outs CPURegs:$dst), (ins CPURegs:$T, CPURegs:$F),
@@ -295,6 +308,7 @@
         [(set CPURegs:$dst, (cmov CPURegs:$T, CPURegs:$F))]>;
 
 // flag:float, data:float
+let cc = 0 in
 class CondMovFPFP<RegisterClass RC, SDNode cmov, bits<5> fmt, bits<1> tf,
                   string instr_asm> :
   FFCMOV<fmt, tf, (outs RC:$dst), (ins RC:$T, RC:$F),
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/lib/Target/Mips/MipsInstrFormats.td
--- a/head/contrib/llvm/lib/Target/Mips/MipsInstrFormats.td	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/lib/Target/Mips/MipsInstrFormats.td	Thu Dec 15 12:59:38 2011 +0200
@@ -21,30 +21,55 @@
 //
 //===----------------------------------------------------------------------===//
 
+// Format specifies the encoding used by the instruction.  This is part of the
+// ad-hoc solution used to emit machine instruction encodings by our machine
+// code emitter.
+class Format<bits<4> val> {
+  bits<4> Value = val;
+}
+
+def Pseudo    : Format<0>;
+def FrmR      : Format<1>;
+def FrmI      : Format<2>;
+def FrmJ      : Format<3>;
+def FrmFR     : Format<4>;
+def FrmFI     : Format<5>;
+def FrmOther  : Format<6>; // Instruction w/ a custom format
+
 // Generic Mips Format
 class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
-               InstrItinClass itin>: Instruction
+               InstrItinClass itin, Format f>: Instruction
 {
   field bits<32> Inst;
+  Format Form = f;
 
   let Namespace = "Mips";
 
-  bits<6> opcode;
+  bits<6> Opcode = 0;
 
-  // Top 5 bits are the 'opcode' field
-  let Inst{31-26} = opcode;
+  // Top 6 bits are the 'opcode' field
+  let Inst{31-26} = Opcode;
 
-  dag OutOperandList = outs;
-  dag InOperandList  = ins;
+  let OutOperandList = outs;
+  let InOperandList  = ins;
 
   let AsmString   = asmstr;
   let Pattern     = pattern;
   let Itinerary   = itin;
+
+  //
+  // Attributes specific to Mips instructions...
+  //
+  bits<4> FormBits = Form.Value;
+
+  // TSFlags layout should be kept in sync with MipsInstrInfo.h.
+  let TSFlags{3-0}   = FormBits;
 }
 
 // Mips Pseudo Instructions Format
 class MipsPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>:
-      MipsInst<outs, ins, asmstr, pattern, IIPseudo> {
+      MipsInst<outs, ins, asmstr, pattern, IIPseudo, Pseudo> {
+  let isCodeGenOnly = 1;
   let isPseudo = 1;
 }
 
@@ -54,7 +79,7 @@
 
 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
          list<dag> pattern, InstrItinClass itin>:
-      MipsInst<outs, ins, asmstr, pattern, itin>
+      MipsInst<outs, ins, asmstr, pattern, itin, FrmR>
 {
   bits<5>  rd;
   bits<5>  rs;
@@ -62,7 +87,7 @@
   bits<5>  shamt;
   bits<6>  funct;
 
-  let opcode = op;
+  let Opcode = op;
   let funct  = _funct;
 
   let Inst{25-21} = rs;
@@ -77,13 +102,13 @@
 //===----------------------------------------------------------------------===//
 
 class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
-         InstrItinClass itin>: MipsInst<outs, ins, asmstr, pattern, itin>
+         InstrItinClass itin>: MipsInst<outs, ins, asmstr, pattern, itin, FrmI>
 {
   bits<5>  rt;
   bits<5>  rs;
   bits<16> imm16;
 
-  let opcode = op;
+  let Opcode = op;
 
   let Inst{25-21} = rs;
   let Inst{20-16} = rt;
@@ -92,13 +117,13 @@
 
 class CBranchBase<bits<6> op, dag outs, dag ins, string asmstr,
                   list<dag> pattern, InstrItinClass itin>:
-  MipsInst<outs, ins, asmstr, pattern, itin>
+  MipsInst<outs, ins, asmstr, pattern, itin, FrmI>
 {
   bits<5>  rs;
   bits<5>  rt;
   bits<16> imm16;
 
-  let opcode = op;
+  let Opcode = op;
 
   let Inst{25-21} = rs;
   let Inst{20-16} = rt;
@@ -110,11 +135,11 @@
 //===----------------------------------------------------------------------===//
 
 class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
-         InstrItinClass itin>: MipsInst<outs, ins, asmstr, pattern, itin>
+         InstrItinClass itin>: MipsInst<outs, ins, asmstr, pattern, itin, FrmJ>
 {
   bits<26> addr;
 
-  let opcode = op;
+  let Opcode = op;
 
   let Inst{25-0} = addr;
 }
@@ -138,7 +163,7 @@
 
 class FFR<bits<6> op, bits<6> _funct, bits<5> _fmt, dag outs, dag ins,
           string asmstr, list<dag> pattern> :
-          MipsInst<outs, ins, asmstr, pattern, NoItinerary>
+          MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmFR>
 {
   bits<5>  fd;
   bits<5>  fs;
@@ -146,7 +171,7 @@
   bits<5>  fmt;
   bits<6>  funct;
 
-  let opcode = op;
+  let Opcode = op;
   let funct  = _funct;
   let fmt    = _fmt;
 
@@ -162,13 +187,13 @@
 //===----------------------------------------------------------------------===//
 
 class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
-          MipsInst<outs, ins, asmstr, pattern, NoItinerary>
+          MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
 {
   bits<5>  ft;
   bits<5>  base;
   bits<16> imm16;
 
-  let opcode = op;
+  let Opcode = op;
 
   let Inst{25-21} = base;
   let Inst{20-16} = ft;
@@ -180,14 +205,14 @@
 //===----------------------------------------------------------------------===//
 
 class FCC<bits<5> _fmt, dag outs, dag ins, string asmstr, list<dag> pattern> :
-          MipsInst<outs, ins, asmstr, pattern, NoItinerary>
+          MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmOther>
 {
   bits<5>  fs;
   bits<5>  ft;
   bits<4>  cc;
   bits<5>  fmt;
 
-  let opcode = 0x11;
+  let Opcode = 0x11;
   let fmt    = _fmt;
 
   let Inst{25-21} = fmt;
@@ -201,18 +226,18 @@
 
 class FCMOV<bits<1> _tf, dag outs, dag ins, string asmstr,
             list<dag> pattern> :
-  MipsInst<outs, ins, asmstr, pattern, NoItinerary>
+  MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmOther>
 {
   bits<5>  rd;
   bits<5>  rs;
-  bits<3>  N;
+  bits<3>  cc;
   bits<1>  tf;
 
-  let opcode = 0;
+  let Opcode = 0;
   let tf = _tf;
 
   let Inst{25-21} = rs;
-  let Inst{20-18} = N;
+  let Inst{20-18} = cc;
   let Inst{17} = 0;
   let Inst{16} = tf;
   let Inst{15-11} = rd;
@@ -222,20 +247,20 @@
 
 class FFCMOV<bits<5> _fmt, bits<1> _tf, dag outs, dag ins, string asmstr,
              list<dag> pattern> :
-  MipsInst<outs, ins, asmstr, pattern, NoItinerary>
+  MipsInst<outs, ins, asmstr, pattern, NoItinerary, FrmOther>
 {
   bits<5>  fd;
   bits<5>  fs;
-  bits<3>  N;
+  bits<3>  cc;
   bits<5>  fmt;
   bits<1>  tf;
 
-  let opcode = 17;
+  let Opcode = 17;
   let fmt = _fmt;
   let tf = _tf;
 
   let Inst{25-21} = fmt;
-  let Inst{20-18} = N;
+  let Inst{20-18} = cc;
   let Inst{17} = 0;
   let Inst{16} = tf;
   let Inst{15-11} = fs;
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/lib/Target/Mips/MipsInstrInfo.td
--- a/head/contrib/llvm/lib/Target/Mips/MipsInstrInfo.td	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/lib/Target/Mips/MipsInstrInfo.td	Thu Dec 15 12:59:38 2011 +0200
@@ -153,6 +153,7 @@
 def mem : Operand<i32> {
   let PrintMethod = "printMemOperand";
   let MIOperandInfo = (ops CPURegs, simm16);
+  let EncoderMethod = "getMemEncoding";
 }
 
 def mem64 : Operand<i64> {
@@ -163,6 +164,17 @@
 def mem_ea : Operand<i32> {
   let PrintMethod = "printMemOperandEA";
   let MIOperandInfo = (ops CPURegs, simm16);
+  let EncoderMethod = "getMemEncoding";
+}
+
+// size operand of ext instruction
+def size_ext : Operand<i32> {
+  let EncoderMethod = "getSizeExtEncoding";
+}
+
+// size operand of ins instruction
+def size_ins : Operand<i32> {
+  let EncoderMethod = "getSizeInsEncoding";
 }
 
 // Transformation Function - get the lower 16 bits.
@@ -271,14 +283,14 @@
 // Arithmetic and logical instructions with 2 register operands.
 class ArithLogicI<bits<6> op, string instr_asm, SDNode OpNode,
                   Operand Od, PatLeaf imm_type, RegisterClass RC> :
-  FI<op, (outs RC:$rt), (ins RC:$rs, Od:$i),
-     !strconcat(instr_asm, "\t$rt, $rs, $i"),
-     [(set RC:$rt, (OpNode RC:$rs, imm_type:$i))], IIAlu>;
+  FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16),
+     !strconcat(instr_asm, "\t$rt, $rs, $imm16"),
+     [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu>;
 
 class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode,
                      Operand Od, PatLeaf imm_type, RegisterClass RC> :
-  FI<op, (outs RC:$rt), (ins RC:$rs, Od:$i),
-     !strconcat(instr_asm, "\t$rt, $rs, $i"), [], IIAlu>;
+  FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16),
+     !strconcat(instr_asm, "\t$rt, $rs, $imm16"), [], IIAlu>;
 
 // Arithmetic Multiply ADD/SUB
 let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in
@@ -319,16 +331,23 @@
 
 // Load Upper Imediate
 class LoadUpper<bits<6> op, string instr_asm>:
-  FI<op, (outs CPURegs:$rt), (ins uimm16:$imm),
-     !strconcat(instr_asm, "\t$rt, $imm"), [], IIAlu> {
+  FI<op, (outs CPURegs:$rt), (ins uimm16:$imm16),
+     !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu> {
   let rs = 0;
 }
 
+class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
+          InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
+  bits<21> addr;
+  let Inst{25-21} = addr{20-16};
+  let Inst{15-0}  = addr{15-0};
+}
+
 // Memory Load/Store
 let canFoldAsLoad = 1 in
 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
             Operand MemOpnd, bit Pseudo>:
-  FI<op, (outs RC:$rt), (ins MemOpnd:$addr),
+  FMem<op, (outs RC:$rt), (ins MemOpnd:$addr),
      !strconcat(instr_asm, "\t$rt, $addr"),
      [(set RC:$rt, (OpNode addr:$addr))], IILoad> {
   let isPseudo = Pseudo;
@@ -336,7 +355,7 @@
 
 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
              Operand MemOpnd, bit Pseudo>:
-  FI<op, (outs), (ins RC:$rt, MemOpnd:$addr),
+  FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr),
      !strconcat(instr_asm, "\t$rt, $addr"),
      [(OpNode RC:$rt, addr:$addr)], IIStore> {
   let isPseudo = Pseudo;
@@ -380,9 +399,9 @@
 
 // Conditional Branch
 class CBranch<bits<6> op, string instr_asm, PatFrag cond_op, RegisterClass RC>:
-  CBranchBase<op, (outs), (ins RC:$rs, RC:$rt, brtarget:$offset),
-              !strconcat(instr_asm, "\t$rs, $rt, $offset"),
-              [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch> {
+  CBranchBase<op, (outs), (ins RC:$rs, RC:$rt, brtarget:$imm16),
+              !strconcat(instr_asm, "\t$rs, $rt, $imm16"),
+              [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> {
   let isBranch = 1;
   let isTerminator = 1;
   let hasDelaySlot = 1;
@@ -390,9 +409,9 @@
 
 class CBranchZero<bits<6> op, bits<5> _rt, string instr_asm, PatFrag cond_op,
                   RegisterClass RC>:
-  CBranchBase<op, (outs), (ins RC:$rs, brtarget:$offset),
-              !strconcat(instr_asm, "\t$rs, $offset"),
-              [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch> {
+  CBranchBase<op, (outs), (ins RC:$rs, brtarget:$imm16),
+              !strconcat(instr_asm, "\t$rs, $imm16"),
+              [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> {
   let rt = _rt;
   let isBranch = 1;
   let isTerminator = 1;
@@ -411,9 +430,9 @@
 
 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od,
               PatLeaf imm_type, RegisterClass RC>:
-  FI<op, (outs CPURegs:$rd), (ins RC:$rs, Od:$i),
-     !strconcat(instr_asm, "\t$rd, $rs, $i"),
-     [(set CPURegs:$rd, (cond_op RC:$rs, imm_type:$i))],
+  FI<op, (outs CPURegs:$rt), (ins RC:$rs, Od:$imm16),
+     !strconcat(instr_asm, "\t$rt, $rs, $imm16"),
+     [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))],
      IIAlu>;
 
 // Unconditional branch
@@ -450,10 +469,8 @@
   }
 
   class BranchLink<string instr_asm>:
-    FI<0x1, (outs), (ins CPURegs:$rs, brtarget:$target, variable_ops),
-       !strconcat(instr_asm, "\t$rs, $target"), [], IIBranch> {
-    let rt = 0;
-  }
+    FI<0x1, (outs), (ins CPURegs:$rs, brtarget:$imm16, variable_ops),
+       !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch>;
 }
 
 // Mul, Div
@@ -493,7 +510,7 @@
 }
 
 class EffectiveAddress<string instr_asm> :
-  FI<0x09, (outs CPURegs:$rt), (ins mem_ea:$addr),
+  FMem<0x09, (outs CPURegs:$rt), (ins mem_ea:$addr),
      instr_asm, [(set CPURegs:$rt, addr:$addr)], IIAlu>;
 
 // Count Leading Ones/Zeros in Word
@@ -507,7 +524,7 @@
 
 // Sign Extend in Register.
 class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt>:
-  FR<0x3f, 0x20, (outs CPURegs:$rd), (ins CPURegs:$rt),
+  FR<0x1f, 0x20, (outs CPURegs:$rd), (ins CPURegs:$rt),
      !strconcat(instr_asm, "\t$rd, $rt"),
      [(set CPURegs:$rd, (sext_inreg CPURegs:$rt, vt))], NoItinerary> {
   let rs = 0;
@@ -685,20 +702,22 @@
 
 let hasSideEffects = 1 in
 def SYNC : MipsInst<(outs), (ins i32imm:$stype), "sync $stype",
-                    [(MipsSync imm:$stype)], NoItinerary>
+                    [(MipsSync imm:$stype)], NoItinerary, FrmOther>
 {
-  let opcode = 0;
+  bits<5> stype;
+  let Opcode = 0;
   let Inst{25-11} = 0;
+  let Inst{10-6} = stype;
   let Inst{5-0} = 15;
 }
 
 /// Load-linked, Store-conditional
 let mayLoad = 1 in
-  def LL    : FI<0x30, (outs CPURegs:$dst), (ins mem:$addr),
-              "ll\t$dst, $addr", [], IILoad>;
-let mayStore = 1, Constraints = "$src = $dst" in
-  def SC    : FI<0x38, (outs CPURegs:$dst), (ins CPURegs:$src, mem:$addr),
-              "sc\t$src, $addr", [], IIStore>;
+  def LL    : FMem<0x30, (outs CPURegs:$rt), (ins mem:$addr),
+              "ll\t$rt, $addr", [], IILoad>;
+let mayStore = 1, Constraints = "$rt = $dst" in
+  def SC    : FMem<0x38, (outs CPURegs:$dst), (ins CPURegs:$rt, mem:$addr),
+              "sc\t$rt, $addr", [], IIStore>;
 
 /// Jump and Branch Instructions
 def J       : JumpFJ<0x02, "j">;
@@ -710,15 +729,17 @@
 def BNE     : CBranch<0x05, "bne", setne, CPURegs>;
 def BGEZ    : CBranchZero<0x01, 1, "bgez", setge, CPURegs>;
 def BGTZ    : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>;
-def BLEZ    : CBranchZero<0x07, 0, "blez", setle, CPURegs>;
+def BLEZ    : CBranchZero<0x06, 0, "blez", setle, CPURegs>;
 def BLTZ    : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>;
 
-def BGEZAL  : BranchLink<"bgezal">;
-def BLTZAL  : BranchLink<"bltzal">;
+let rt=0x11 in
+  def BGEZAL  : BranchLink<"bgezal">;
+let rt=0x10 in
+  def BLTZAL  : BranchLink<"bltzal">;
 
 let isReturn=1, isTerminator=1, hasDelaySlot=1,
-    isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
-  def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target),
+    isBarrier=1, hasCtrlDep=1, rd=0, rt=0, shamt=0 in
+  def RET : FR <0x00, 0x08, (outs), (ins CPURegs:$target),
                 "jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>;
 
 /// Multiply and Divide Instructions.
@@ -797,14 +818,14 @@
 def RDHWR : ReadHardware;
 
 def EXT : ExtIns<0, "ext", (outs CPURegs:$rt),
-                 (ins CPURegs:$rs, uimm16:$pos, uimm16:$sz),
+                 (ins CPURegs:$rs, uimm16:$pos, size_ext:$sz),
                  [(set CPURegs:$rt,
                    (MipsExt CPURegs:$rs, immZExt5:$pos, immZExt5:$sz))],
                  NoItinerary>;
 
 let Constraints = "$src = $rt" in
 def INS : ExtIns<4, "ins", (outs CPURegs:$rt),
-                 (ins CPURegs:$rs, uimm16:$pos, uimm16:$sz, CPURegs:$src),
+                 (ins CPURegs:$rs, uimm16:$pos, size_ins:$sz, CPURegs:$src),
                  [(set CPURegs:$rt,
                    (MipsIns CPURegs:$rs, immZExt5:$pos, immZExt5:$sz,
                     CPURegs:$src))],
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/lib/Target/Mips/MipsJITInfo.cpp
--- a/head/contrib/llvm/lib/Target/Mips/MipsJITInfo.cpp	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/lib/Target/Mips/MipsJITInfo.cpp	Thu Dec 15 12:59:38 2011 +0200
@@ -57,11 +57,11 @@
     ".globl " ASMPREFIX "MipsCompilationCallback\n"
     ASMPREFIX "MipsCompilationCallback:\n"
     ".ent " ASMPREFIX "MipsCompilationCallback\n"
-    ".frame  $29, 32, $31\n"
+    ".frame  $sp, 32, $ra\n"
     ".set  noreorder\n"
     ".cpload $t9\n"
 
-    "addiu $sp, $sp, -60\n"
+    "addiu $sp, $sp, -64\n"
     ".cprestore 16\n"
 
     // Save argument registers a0, a1, a2, a3, f12, f14 since they may contain
@@ -76,8 +76,8 @@
     "sw $a3, 32($sp)\n"
     "sw $ra, 36($sp)\n"
     "sw $t8, 40($sp)\n"
-    "sdc1 $f12, 44($sp)\n"
-    "sdc1 $f14, 52($sp)\n"
+    "sdc1 $f12, 48($sp)\n"
+    "sdc1 $f14, 56($sp)\n"
 
     // t8 points at the end of function stub. Pass the beginning of the stub
     // to the MipsCompilationCallbackC.
@@ -92,9 +92,9 @@
     "lw $a3, 32($sp)\n"
     "lw $ra, 36($sp)\n"
     "lw $t8, 40($sp)\n"
-    "ldc1 $f12, 44($sp)\n"
-    "ldc1 $f14, 52($sp)\n"
-    "addiu $sp, $sp, 60\n"
+    "ldc1 $f12, 48($sp)\n"
+    "ldc1 $f14, 56($sp)\n"
+    "addiu $sp, $sp, 64\n"
 
     // Jump to the (newly modified) stub to invoke the real function.
     "addiu $t8, $t8, -16\n"
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
--- a/head/contrib/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp	Thu Dec 15 12:59:38 2011 +0200
@@ -490,10 +490,8 @@
 
       // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
       // subregisters of CR2. We just need to emit a move of CR2.
-      if (Reg == PPC::CR2LT || Reg == PPC::CR2GT || Reg == PPC::CR2EQ)
+      if (PPC::CRBITRCRegisterClass->contains(Reg))
         continue;
-      if (Reg == PPC::CR2UN)
-        Reg = PPC::CR2;
 
       MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
       MachineLocation CSSrc(Reg);
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/lib/Target/X86/X86CodeEmitter.cpp
--- a/head/contrib/llvm/lib/Target/X86/X86CodeEmitter.cpp	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/lib/Target/X86/X86CodeEmitter.cpp	Thu Dec 15 12:59:38 2011 +0200
@@ -589,6 +589,13 @@
   }
 }
 
+static const MCInstrDesc *UpdateOp(MachineInstr &MI, const X86InstrInfo *II,
+                                   unsigned Opcode) {
+  const MCInstrDesc *Desc = &II->get(Opcode);
+  MI.setDesc(*Desc);
+  return Desc;
+}
+
 template<class CodeEmitter>
 void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
                                            const MCInstrDesc *Desc) {
@@ -596,15 +603,23 @@
   
   // If this is a pseudo instruction, lower it.
   switch (Desc->getOpcode()) {
-  case X86::ADD16rr_DB:   Desc = &II->get(X86::OR16rr); MI.setDesc(*Desc);break;
-  case X86::ADD32rr_DB:   Desc = &II->get(X86::OR32rr); MI.setDesc(*Desc);break;
-  case X86::ADD64rr_DB:   Desc = &II->get(X86::OR64rr); MI.setDesc(*Desc);break;
-  case X86::ADD16ri_DB:   Desc = &II->get(X86::OR16ri); MI.setDesc(*Desc);break;
-  case X86::ADD32ri_DB:   Desc = &II->get(X86::OR32ri); MI.setDesc(*Desc);break;
-  case X86::ADD64ri32_DB:Desc = &II->get(X86::OR64ri32);MI.setDesc(*Desc);break;
-  case X86::ADD16ri8_DB:  Desc = &II->get(X86::OR16ri8);MI.setDesc(*Desc);break;
-  case X86::ADD32ri8_DB:  Desc = &II->get(X86::OR32ri8);MI.setDesc(*Desc);break;
-  case X86::ADD64ri8_DB:  Desc = &II->get(X86::OR64ri8);MI.setDesc(*Desc);break;
+  case X86::ADD16rr_DB:      Desc = UpdateOp(MI, II, X86::OR16rr); break;
+  case X86::ADD32rr_DB:      Desc = UpdateOp(MI, II, X86::OR32rr); break;
+  case X86::ADD64rr_DB:      Desc = UpdateOp(MI, II, X86::OR64rr); break;
+  case X86::ADD16ri_DB:      Desc = UpdateOp(MI, II, X86::OR16ri); break;
+  case X86::ADD32ri_DB:      Desc = UpdateOp(MI, II, X86::OR32ri); break;
+  case X86::ADD64ri32_DB:    Desc = UpdateOp(MI, II, X86::OR64ri32); break;
+  case X86::ADD16ri8_DB:     Desc = UpdateOp(MI, II, X86::OR16ri8); break;
+  case X86::ADD32ri8_DB:     Desc = UpdateOp(MI, II, X86::OR32ri8); break;
+  case X86::ADD64ri8_DB:     Desc = UpdateOp(MI, II, X86::OR64ri8); break;
+  case X86::ACQUIRE_MOV8rm:  Desc = UpdateOp(MI, II, X86::MOV8rm); break;
+  case X86::ACQUIRE_MOV16rm: Desc = UpdateOp(MI, II, X86::MOV16rm); break;
+  case X86::ACQUIRE_MOV32rm: Desc = UpdateOp(MI, II, X86::MOV32rm); break;
+  case X86::ACQUIRE_MOV64rm: Desc = UpdateOp(MI, II, X86::MOV64rm); break;
+  case X86::RELEASE_MOV8mr:  Desc = UpdateOp(MI, II, X86::MOV8mr); break;
+  case X86::RELEASE_MOV16mr: Desc = UpdateOp(MI, II, X86::MOV16mr); break;
+  case X86::RELEASE_MOV32mr: Desc = UpdateOp(MI, II, X86::MOV32mr); break;
+  case X86::RELEASE_MOV64mr: Desc = UpdateOp(MI, II, X86::MOV64mr); break;
   }
   
 
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
--- a/head/contrib/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp	Thu Dec 15 12:59:38 2011 +0200
@@ -2025,9 +2025,10 @@
         BasicBlock *InstParent = I->getParent();
         BasicBlock::iterator InsertPos = I;
 
-        if (!isa<PHINode>(Result))        // If combining a PHI, don't insert
-          while (isa<PHINode>(InsertPos)) // middle of a block of PHIs.
-            ++InsertPos;
+        // If we replace a PHI with something that isn't a PHI, fix up the
+        // insertion point.
+        if (!isa<PHINode>(Result) && isa<PHINode>(InsertPos))
+          InsertPos = InstParent->getFirstInsertionPt();
 
         InstParent->getInstList().insert(InsertPos, Result);
 
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/tools/clang/include/clang/Driver/CC1Options.td
--- a/head/contrib/llvm/tools/clang/include/clang/Driver/CC1Options.td	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/tools/clang/include/clang/Driver/CC1Options.td	Thu Dec 15 12:59:38 2011 +0200
@@ -644,6 +644,17 @@
 def iwithsysroot : JoinedOrSeparate<"-iwithsysroot">,MetaVarName<"<directory>">,
   HelpText<"Add directory to SYSTEM include search path, "
            "absolute paths are relative to -isysroot">;
+def internal_isystem : JoinedOrSeparate<"-internal-isystem">,
+  MetaVarName<"<directory>">,
+  HelpText<"Add directory to the internal system include search path; these "
+           "are assumed to not be user-provided and are used to model system "
+           "and standard headers' paths.">;
+def internal_externc_isystem : JoinedOrSeparate<"-internal-externc-isystem">,
+  MetaVarName<"<directory>">,
+  HelpText<"Add directory to the internal system include search path with "
+           "implicit extern \"C\" semantics; these are assumed to not be "
+           "user-provided and are used to model system and standard headers' "
+           "paths.">;
 def iprefix : JoinedOrSeparate<"-iprefix">, MetaVarName<"<prefix>">,
   HelpText<"Set the -iwithprefix/-iwithprefixbefore prefix">;
 def iwithprefix : JoinedOrSeparate<"-iwithprefix">, MetaVarName<"<dir>">,
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/tools/clang/include/clang/Driver/ToolChain.h
--- a/head/contrib/llvm/tools/clang/include/clang/Driver/ToolChain.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/tools/clang/include/clang/Driver/ToolChain.h	Thu Dec 15 12:59:38 2011 +0200
@@ -195,15 +195,21 @@
   /// FIXME: this really belongs on some sort of DeploymentTarget abstraction
   virtual bool hasBlocksRuntime() const { return true; }
 
+  /// \brief Add the clang cc1 arguments for system include paths.
+  ///
+  /// This routine is responsible for adding the necessary cc1 arguments to
+  /// include headers from standard system header directories.
+  virtual void AddClangSystemIncludeArgs(const ArgList &DriverArgs,
+                                         ArgStringList &CC1Args) const;
+
   // GetCXXStdlibType - Determine the C++ standard library type to use with the
   // given compilation arguments.
   virtual CXXStdlibType GetCXXStdlibType(const ArgList &Args) const;
 
   /// AddClangCXXStdlibIncludeArgs - Add the clang -cc1 level arguments to set
   /// the include paths to use for the given C++ standard library type.
-  virtual void AddClangCXXStdlibIncludeArgs(const ArgList &Args,
-                                            ArgStringList &CmdArgs,
-                                            bool ObjCXXAutoRefCount) const;
+  virtual void AddClangCXXStdlibIncludeArgs(const ArgList &DriverArgs,
+                                            ArgStringList &CC1Args) const;
 
   /// AddCXXStdlibLibArgs - Add the system specific linker arguments to use
   /// for the given C++ standard library type.
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/tools/clang/include/clang/Frontend/HeaderSearchOptions.h
--- a/head/contrib/llvm/tools/clang/include/clang/Frontend/HeaderSearchOptions.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/tools/clang/include/clang/Frontend/HeaderSearchOptions.h	Thu Dec 15 12:59:38 2011 +0200
@@ -49,10 +49,24 @@
     /// path.
     unsigned IgnoreSysRoot : 1;
 
+    /// \brief True if this entry is an internal search path.
+    ///
+    /// This typically indicates that users didn't directly provide it, but
+    /// instead it was provided by a compatibility layer for a particular
+    /// system. This isn't redundant with IsUserSupplied (even though perhaps
+    /// it should be) because that is false for user provided '-iwithprefix'
+    /// header search entries.
+    unsigned IsInternal : 1;
+
+    /// \brief True if this entry's headers should be wrapped in extern "C".
+    unsigned ImplicitExternC : 1;
+
     Entry(StringRef path, frontend::IncludeDirGroup group,
-          bool isUserSupplied, bool isFramework, bool ignoreSysRoot)
+          bool isUserSupplied, bool isFramework, bool ignoreSysRoot,
+          bool isInternal, bool implicitExternC)
       : Path(path), Group(group), IsUserSupplied(isUserSupplied),
-        IsFramework(isFramework), IgnoreSysRoot(ignoreSysRoot) {}
+        IsFramework(isFramework), IgnoreSysRoot(ignoreSysRoot),
+        IsInternal(isInternal), ImplicitExternC(implicitExternC) {}
   };
 
   /// If non-empty, the directory to use as a "virtual system root" for include
@@ -98,9 +112,10 @@
 
   /// AddPath - Add the \arg Path path to the specified \arg Group list.
   void AddPath(StringRef Path, frontend::IncludeDirGroup Group,
-               bool IsUserSupplied, bool IsFramework, bool IgnoreSysRoot) {
+               bool IsUserSupplied, bool IsFramework, bool IgnoreSysRoot,
+               bool IsInternal = false, bool ImplicitExternC = false) {
     UserEntries.push_back(Entry(Path, Group, IsUserSupplied, IsFramework,
-                                IgnoreSysRoot));
+                                IgnoreSysRoot, IsInternal, ImplicitExternC));
   }
 };
 
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/tools/clang/lib/Basic/Version.cpp
--- a/head/contrib/llvm/tools/clang/lib/Basic/Version.cpp	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/tools/clang/lib/Basic/Version.cpp	Thu Dec 15 12:59:38 2011 +0200
@@ -32,7 +32,7 @@
 
   // If the SVN_REPOSITORY is empty, try to use the SVN keyword. This helps us
   // pick up a tag in an SVN export, for example.
-  static StringRef SVNRepository("$URL: http://llvm.org/svn/llvm-project/cfe/branches/release_30/lib/Basic/Version.cpp $");
+  static StringRef SVNRepository("$URL: http://llvm.org/svn/llvm-project/cfe/tags/RELEASE_30/final/lib/Basic/Version.cpp $");
   if (URL.empty()) {
     URL = SVNRepository.slice(SVNRepository.find(':'),
                               SVNRepository.find("/lib/Basic"));
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/tools/clang/lib/CodeGen/CGObjCGNU.cpp
--- a/head/contrib/llvm/tools/clang/lib/CodeGen/CGObjCGNU.cpp	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/tools/clang/lib/CodeGen/CGObjCGNU.cpp	Thu Dec 15 12:59:38 2011 +0200
@@ -538,11 +538,12 @@
                                  llvm::Value *cmd,
                                  llvm::MDNode *node) {
     CGBuilderTy &Builder = CGF.Builder;
-    llvm::Value *imp = Builder.CreateCall2(MsgLookupFn, 
-            EnforceType(Builder, Receiver, IdTy),
-            EnforceType(Builder, cmd, SelectorTy));
-    cast<llvm::CallInst>(imp)->setMetadata(msgSendMDKind, node);
-    return imp;
+    llvm::Value *args[] = {
+      EnforceType(Builder, Receiver, IdTy),
+      EnforceType(Builder, cmd, SelectorTy) };
+    llvm::CallSite imp = CGF.EmitCallOrInvoke(MsgLookupFn, args);
+    imp->setMetadata(msgSendMDKind, node);
+    return imp.getInstruction();
   }
   virtual llvm::Value *LookupIMPSuper(CodeGenFunction &CGF,
                                       llvm::Value *ObjCSuper,
@@ -597,16 +598,17 @@
       // The lookup function is guaranteed not to capture the receiver pointer.
       LookupFn->setDoesNotCapture(1);
 
-      llvm::CallInst *slot =
-          Builder.CreateCall3(LookupFn,
-              EnforceType(Builder, ReceiverPtr, PtrToIdTy),
-              EnforceType(Builder, cmd, SelectorTy),
-              EnforceType(Builder, self, IdTy));
-      slot->setOnlyReadsMemory();
+      llvm::Value *args[] = {
+        EnforceType(Builder, ReceiverPtr, PtrToIdTy),
+        EnforceType(Builder, cmd, SelectorTy),
+        EnforceType(Builder, self, IdTy) };
+      llvm::CallSite slot = CGF.EmitCallOrInvoke(LookupFn, args);
+      slot.setOnlyReadsMemory();
       slot->setMetadata(msgSendMDKind, node);
 
       // Load the imp from the slot
-      llvm::Value *imp = Builder.CreateLoad(Builder.CreateStructGEP(slot, 4));
+      llvm::Value *imp =
+        Builder.CreateLoad(Builder.CreateStructGEP(slot.getInstruction(), 4));
 
       // The lookup function may have changed the receiver, so make sure we use
       // the new one.
@@ -1361,8 +1363,8 @@
       LongTy,                 // abi_version
       IvarOffsets->getType(), // ivar_offsets
       Properties->getType(),  // properties
-      Int64Ty,                // strong_pointers
-      Int64Ty,                // weak_pointers
+      IntPtrTy,               // strong_pointers
+      IntPtrTy,               // weak_pointers
       NULL);
   llvm::Constant *Zero = llvm::ConstantInt::get(LongTy, 0);
   // Fill in the structure
@@ -1723,12 +1725,14 @@
 /// bitfield / with the 63rd bit set will be 1<<64.
 llvm::Constant *CGObjCGNU::MakeBitField(llvm::SmallVectorImpl<bool> &bits) {
   int bitCount = bits.size();
-  if (bitCount < 64) {
+  int ptrBits =
+        (TheModule.getPointerSize() == llvm::Module::Pointer32) ? 32 : 64;
+  if (bitCount < ptrBits) {
     uint64_t val = 1;
     for (int i=0 ; i<bitCount ; ++i) {
       if (bits[i]) val |= 1ULL<<(i+1);
     }
-    return llvm::ConstantInt::get(Int64Ty, val);
+    return llvm::ConstantInt::get(IntPtrTy, val);
   }
   llvm::SmallVector<llvm::Constant*, 8> values;
   int v=0;
@@ -1748,8 +1752,6 @@
   llvm::Constant *GS = MakeGlobal(llvm::StructType::get(Int32Ty, arrayTy,
         NULL), fields);
   llvm::Constant *ptr = llvm::ConstantExpr::getPtrToInt(GS, IntPtrTy);
-  if (IntPtrTy != Int64Ty)
-    ptr = llvm::ConstantExpr::getZExt(ptr, Int64Ty);
   return ptr;
 }
 
@@ -2073,12 +2075,12 @@
       }
       ++ivarIndex;
   }
-  llvm::Constant *Zero64 = llvm::ConstantInt::get(Int64Ty, 0);
+  llvm::Constant *ZeroPtr = llvm::ConstantInt::get(IntPtrTy, 0);
   //Generate metaclass for class methods
   llvm::Constant *MetaClassStruct = GenerateClassStructure(NULLPtr,
       NULLPtr, 0x12L, ClassName.c_str(), 0, Zeros[0], GenerateIvarList(
         empty, empty, empty), ClassMethodList, NULLPtr,
-      NULLPtr, NULLPtr, Zero64, Zero64, true);
+      NULLPtr, NULLPtr, ZeroPtr, ZeroPtr, true);
 
   // Generate the class structure
   llvm::Constant *ClassStruct =
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/tools/clang/lib/CodeGen/CodeGenModule.cpp
--- a/head/contrib/llvm/tools/clang/lib/CodeGen/CodeGenModule.cpp	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/tools/clang/lib/CodeGen/CodeGenModule.cpp	Thu Dec 15 12:59:38 2011 +0200
@@ -29,6 +29,7 @@
 #include "clang/AST/DeclTemplate.h"
 #include "clang/AST/Mangle.h"
 #include "clang/AST/RecordLayout.h"
+#include "clang/AST/RecursiveASTVisitor.h"
 #include "clang/Basic/Diagnostic.h"
 #include "clang/Basic/SourceManager.h"
 #include "clang/Basic/TargetInfo.h"
@@ -858,6 +859,59 @@
   }
 }
 
+namespace {
+  struct FunctionIsDirectlyRecursive :
+    public RecursiveASTVisitor<FunctionIsDirectlyRecursive> {
+    const StringRef Name;
+    bool Result;
+    FunctionIsDirectlyRecursive(const FunctionDecl *F) :
+      Name(F->getName()), Result(false) {
+    }
+    typedef RecursiveASTVisitor<FunctionIsDirectlyRecursive> Base;
+
+    bool TraverseCallExpr(CallExpr *E) {
+      const Decl *D = E->getCalleeDecl();
+      if (!D)
+        return true;
+      AsmLabelAttr *Attr = D->getAttr<AsmLabelAttr>();
+      if (!Attr)
+        return true;
+      if (Name == Attr->getLabel()) {
+        Result = true;
+        return false;
+      }
+      return true;
+    }
+  };
+}
+
+// isTriviallyRecursiveViaAsm - Check if this function calls another
+// decl that, because of the asm attribute, ends up pointing to itself.
+bool
+CodeGenModule::isTriviallyRecursiveViaAsm(const FunctionDecl *F) {
+  if (getCXXABI().getMangleContext().shouldMangleDeclName(F))
+    return false;
+
+  FunctionIsDirectlyRecursive Walker(F);
+  Walker.TraverseFunctionDecl(const_cast<FunctionDecl*>(F));
+  return Walker.Result;
+}
+
+bool
+CodeGenModule::shouldEmitFunction(const FunctionDecl *F) {
+  if (getFunctionLinkage(F) != llvm::Function::AvailableExternallyLinkage)
+    return true;
+  if (CodeGenOpts.OptimizationLevel == 0 &&
+      !F->hasAttr<AlwaysInlineAttr>())
+    return false;
+  // PR9614. Avoid cases where the source code is lying to us. An available
+  // externally function should have an equivalent function somewhere else,
+  // but a function that calls itself is clearly not equivalent to the real
+  // implementation.
+  // This happens in glibc's btowc and in some configure checks.
+  return !isTriviallyRecursiveViaAsm(F);
+}
+
 void CodeGenModule::EmitGlobalDefinition(GlobalDecl GD) {
   const ValueDecl *D = cast<ValueDecl>(GD.getDecl());
 
@@ -868,10 +922,7 @@
   if (const FunctionDecl *Function = dyn_cast<FunctionDecl>(D)) {
     // At -O0, don't generate IR for functions with available_externally 
     // linkage.
-    if (CodeGenOpts.OptimizationLevel == 0 && 
-        !Function->hasAttr<AlwaysInlineAttr>() &&
-        getFunctionLinkage(Function) 
-                                  == llvm::Function::AvailableExternallyLinkage)
+    if (!shouldEmitFunction(Function))
       return;
 
     if (const CXXMethodDecl *Method = dyn_cast<CXXMethodDecl>(D)) {
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/tools/clang/lib/CodeGen/CodeGenModule.h
--- a/head/contrib/llvm/tools/clang/lib/CodeGen/CodeGenModule.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/tools/clang/lib/CodeGen/CodeGenModule.h	Thu Dec 15 12:59:38 2011 +0200
@@ -324,6 +324,8 @@
   void createOpenCLRuntime();
   void createCUDARuntime();
 
+  bool isTriviallyRecursiveViaAsm(const FunctionDecl *F);
+  bool shouldEmitFunction(const FunctionDecl *F);
   llvm::LLVMContext &VMContext;
 
   /// @name Cache for Blocks Runtime Globals
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/tools/clang/lib/Driver/ToolChain.cpp
--- a/head/contrib/llvm/tools/clang/lib/Driver/ToolChain.cpp	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/tools/clang/lib/Driver/ToolChain.cpp	Thu Dec 15 12:59:38 2011 +0200
@@ -211,6 +211,11 @@
   return ComputeLLVMTriple(Args, InputType);
 }
 
+void ToolChain::AddClangSystemIncludeArgs(const ArgList &DriverArgs,
+                                          ArgStringList &CC1Args) const {
+  // Each toolchain should provide the appropriate include flags.
+}
+
 ToolChain::CXXStdlibType ToolChain::GetCXXStdlibType(const ArgList &Args) const{
   if (Arg *A = Args.getLastArg(options::OPT_stdlib_EQ)) {
     StringRef Value = A->getValue(Args);
@@ -225,24 +230,18 @@
   return ToolChain::CST_Libstdcxx;
 }
 
-void ToolChain::AddClangCXXStdlibIncludeArgs(const ArgList &Args,
-                                             ArgStringList &CmdArgs,
-                                             bool ObjCXXAutoRefCount) const {
-  CXXStdlibType Type = GetCXXStdlibType(Args);
-
-  // Header search paths are handled by the mass of goop in InitHeaderSearch.
-
-  switch (Type) {
-  case ToolChain::CST_Libcxx:
-    if (ObjCXXAutoRefCount)
-      CmdArgs.push_back("-fobjc-arc-cxxlib=libc++");
-    break;
-
-  case ToolChain::CST_Libstdcxx:
-    if (ObjCXXAutoRefCount)
-      CmdArgs.push_back("-fobjc-arc-cxxlib=libstdc++");
-    break;
-  }
+void ToolChain::AddClangCXXStdlibIncludeArgs(const ArgList &DriverArgs,
+                                             ArgStringList &CC1Args) const {
+  // Header search paths should be handled by each of the subclasses.
+  // Historically, they have not been, and instead have been handled inside of
+  // the CC1-layer frontend. As the logic is hoisted out, this generic function
+  // will slowly stop being called.
+  //
+  // While it is being called, replicate a bit of a hack to propagate the
+  // '-stdlib=' flag down to CC1 so that it can in turn customize the C++
+  // header search paths with it. Once all systems are overriding this
+  // function, the CC1 flag and this line can be removed.
+  DriverArgs.AddAllArgs(CC1Args, options::OPT_stdlib_EQ);
 }
 
 void ToolChain::AddCXXStdlibLibArgs(const ArgList &Args,
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/tools/clang/lib/Driver/ToolChains.cpp
--- a/head/contrib/llvm/tools/clang/lib/Driver/ToolChains.cpp	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/tools/clang/lib/Driver/ToolChains.cpp	Thu Dec 15 12:59:38 2011 +0200
@@ -40,6 +40,15 @@
 
 #include "llvm/Config/config.h" // for CXX_INCLUDE_ROOT
 
+// Include the necessary headers to interface with the Windows registry and
+// environment.
+#ifdef _MSC_VER
+  #define WIN32_LEAN_AND_MEAN 1
+  #include <Windows.h>
+  #undef min
+  #undef max
+#endif
+
 #ifndef CLANG_PREFIX
 #define CLANG_PREFIX
 #endif
@@ -48,6 +57,38 @@
 using namespace clang::driver::toolchains;
 using namespace clang;
 
+/// \brief Utility function to add a system include directory to CC1 arguments.
+static void addSystemInclude(const ArgList &DriverArgs, ArgStringList &CC1Args,
+                             const Twine &Path) {
+  CC1Args.push_back("-internal-isystem");
+  CC1Args.push_back(DriverArgs.MakeArgString(Path));
+}
+
+/// \brief Utility function to add a system include directory with extern "C"
+/// semantics to CC1 arguments.
+///
+/// Note that this should be used rarely, and only for directories that
+/// historically and for legacy reasons are treated as having implicit extern
+/// "C" semantics. These semantics are *ignored* by and large today, but its
+/// important to preserve the preprocessor changes resulting from the
+/// classification.
+static void addExternCSystemInclude(const ArgList &DriverArgs,
+                                    ArgStringList &CC1Args, const Twine &Path) {
+  CC1Args.push_back("-internal-externc-isystem");
+  CC1Args.push_back(DriverArgs.MakeArgString(Path));
+}
+
+/// \brief Utility function to add a list of system include directories to CC1.
+static void addSystemIncludes(const ArgList &DriverArgs,
+                              ArgStringList &CC1Args,
+                              ArrayRef<StringRef> Paths) {
+  for (ArrayRef<StringRef>::iterator I = Paths.begin(), E = Paths.end();
+       I != E; ++I) {
+    CC1Args.push_back("-internal-isystem");
+    CC1Args.push_back(DriverArgs.MakeArgString(*I));
+  }
+}
+
 /// Darwin - Darwin tool chain for i386 and x86_64.
 
 Darwin::Darwin(const HostInfo &Host, const llvm::Triple& Triple)
@@ -1389,19 +1430,6 @@
          Distro == UbuntuNatty  || Distro == UbuntuOneiric;
 }
 
-// FIXME: This should be deleted. We should assume a multilib environment, and
-// fallback gracefully if any parts of it are absent.
-static bool HasMultilib(llvm::Triple::ArchType Arch, enum LinuxDistro Distro) {
-  if (Arch == llvm::Triple::x86_64) {
-    bool Exists;
-    if (Distro == Exherbo &&
-        (llvm::sys::fs::exists("/usr/lib32/libc.so", Exists) || !Exists))
-      return false;
-  }
-
-  return true;
-}
-
 static LinuxDistro DetectLinuxDistro(llvm::Triple::ArchType Arch) {
   llvm::OwningPtr<llvm::MemoryBuffer> File;
   if (!llvm::MemoryBuffer::getFile("/etc/lsb-release", File)) {
@@ -1486,280 +1514,293 @@
   return UnknownDistro;
 }
 
-/// \brief Trivial helper function to simplify code checking path existence.
-static bool PathExists(StringRef Path) {
-  bool Exists;
-  if (!llvm::sys::fs::exists(Path, Exists))
-    return Exists;
+/// \brief Parse a GCCVersion object out of a string of text.
+///
+/// This is the primary means of forming GCCVersion objects.
+/*static*/ Linux::GCCVersion Linux::GCCVersion::Parse(StringRef VersionText) {
+  const GCCVersion BadVersion = { VersionText.str(), -1, -1, -1, "" };
+  std::pair<StringRef, StringRef> First = VersionText.split('.');
+  std::pair<StringRef, StringRef> Second = First.second.split('.');
+
+  GCCVersion GoodVersion = { VersionText.str(), -1, -1, -1, "" };
+  if (First.first.getAsInteger(10, GoodVersion.Major) ||
+      GoodVersion.Major < 0)
+    return BadVersion;
+  if (Second.first.getAsInteger(10, GoodVersion.Minor) ||
+      GoodVersion.Minor < 0)
+    return BadVersion;
+
+  // First look for a number prefix and parse that if present. Otherwise just
+  // stash the entire patch string in the suffix, and leave the number
+  // unspecified. This covers versions strings such as:
+  //   4.4
+  //   4.4.0
+  //   4.4.x
+  //   4.4.2-rc4
+  //   4.4.x-patched
+  // And retains any patch number it finds.
+  StringRef PatchText = GoodVersion.PatchSuffix = Second.second.str();
+  if (!PatchText.empty()) {
+    if (unsigned EndNumber = PatchText.find_first_not_of("0123456789")) {
+      // Try to parse the number and any suffix.
+      if (PatchText.slice(0, EndNumber).getAsInteger(10, GoodVersion.Patch) ||
+          GoodVersion.Patch < 0)
+        return BadVersion;
+      GoodVersion.PatchSuffix = PatchText.substr(EndNumber).str();
+    }
+  }
+
+  return GoodVersion;
+}
+
+/// \brief Less-than for GCCVersion, implementing a Strict Weak Ordering.
+bool Linux::GCCVersion::operator<(const GCCVersion &RHS) const {
+  if (Major < RHS.Major) return true; if (Major > RHS.Major) return false;
+  if (Minor < RHS.Minor) return true; if (Minor > RHS.Minor) return false;
+
+  // Note that we rank versions with *no* patch specified is better than ones
+  // hard-coding a patch version. Thus if the RHS has no patch, it always
+  // wins, and the LHS only wins if it has no patch and the RHS does have
+  // a patch.
+  if (RHS.Patch == -1) return true;   if (Patch == -1) return false;
+  if (Patch < RHS.Patch) return true; if (Patch > RHS.Patch) return false;
+
+  // Finally, between completely tied version numbers, the version with the
+  // suffix loses as we prefer full releases.
+  if (RHS.PatchSuffix.empty()) return true;
   return false;
 }
 
-namespace {
-/// \brief This is a class to find a viable GCC installation for Clang to use.
+/// \brief Construct a GCCInstallationDetector from the driver.
 ///
-/// This class tries to find a GCC installation on the system, and report
-/// information about it. It starts from the host information provided to the
-/// Driver, and has logic for fuzzing that where appropriate.
-class GCCInstallationDetector {
-  /// \brief Struct to store and manipulate GCC versions.
-  ///
-  /// We rely on assumptions about the form and structure of GCC version
-  /// numbers: they consist of at most three '.'-separated components, and each
-  /// component is a non-negative integer.
-  struct GCCVersion {
-    unsigned Major, Minor, Patch;
+/// This performs all of the autodetection and sets up the various paths.
+/// Once constructed, a GCCInstallation is esentially immutable.
+Linux::GCCInstallationDetector::GCCInstallationDetector(const Driver &D)
+  : IsValid(false),
+    GccTriple(D.DefaultHostTriple) {
+  // FIXME: Using CXX_INCLUDE_ROOT is here is a bit of a hack, but
+  // avoids adding yet another option to configure/cmake.
+  // It would probably be cleaner to break it in two variables
+  // CXX_GCC_ROOT with just /foo/bar
+  // CXX_GCC_VER with 4.5.2
+  // Then we would have
+  // CXX_INCLUDE_ROOT = CXX_GCC_ROOT/include/c++/CXX_GCC_VER
+  // and this function would return
+  // CXX_GCC_ROOT/lib/gcc/CXX_INCLUDE_ARCH/CXX_GCC_VER
+  llvm::SmallString<128> CxxIncludeRoot(CXX_INCLUDE_ROOT);
+  if (CxxIncludeRoot != "") {
+    // This is of the form /foo/bar/include/c++/4.5.2/
+    if (CxxIncludeRoot.back() == '/')
+      llvm::sys::path::remove_filename(CxxIncludeRoot); // remove the /
+    StringRef Version = llvm::sys::path::filename(CxxIncludeRoot);
+    llvm::sys::path::remove_filename(CxxIncludeRoot); // remove the version
+    llvm::sys::path::remove_filename(CxxIncludeRoot); // remove the c++
+    llvm::sys::path::remove_filename(CxxIncludeRoot); // remove the include
+    GccInstallPath = CxxIncludeRoot.str();
+    GccInstallPath.append("/lib/gcc/");
+    GccInstallPath.append(CXX_INCLUDE_ARCH);
+    GccInstallPath.append("/");
+    GccInstallPath.append(Version);
+    GccParentLibPath = GccInstallPath + "/../../..";
+    IsValid = true;
+    return;
+  }
 
-    static GCCVersion Parse(StringRef VersionText) {
-      const GCCVersion BadVersion = {0, 0, 0};
-      std::pair<StringRef, StringRef> First = VersionText.split('.');
-      std::pair<StringRef, StringRef> Second = First.second.split('.');
+  llvm::Triple::ArchType HostArch = llvm::Triple(GccTriple).getArch();
+  // The library directories which may contain GCC installations.
+  SmallVector<StringRef, 4> CandidateLibDirs;
+  // The compatible GCC triples for this particular architecture.
+  SmallVector<StringRef, 10> CandidateTriples;
+  CollectLibDirsAndTriples(HostArch, CandidateLibDirs, CandidateTriples);
 
-      GCCVersion GoodVersion = {0, 0, 0};
-      if (First.first.getAsInteger(10, GoodVersion.Major))
-        return BadVersion;
-      if (Second.first.getAsInteger(10, GoodVersion.Minor))
-        return BadVersion;
-      // We accept a number, or a string for the patch version, in case there
-      // is a strang suffix, or other mangling: '4.1.x', '4.1.2-rc3'. When it
-      // isn't a number, we just use '0' as the number but accept it.
-      if (Second.first.getAsInteger(10, GoodVersion.Patch))
-        GoodVersion.Patch = 0;
-      return GoodVersion;
-    }
+  // Always include the default host triple as the final fallback if no
+  // specific triple is detected.
+  CandidateTriples.push_back(D.DefaultHostTriple);
 
-    bool operator<(const GCCVersion &RHS) const {
-      if (Major < RHS.Major) return true;
-      if (Major > RHS.Major) return false;
-      if (Minor < RHS.Minor) return true;
-      if (Minor > RHS.Minor) return false;
-      return Patch < RHS.Patch;
-    }
-    bool operator>(const GCCVersion &RHS) const { return RHS < *this; }
-    bool operator<=(const GCCVersion &RHS) const { return !(*this > RHS); }
-    bool operator>=(const GCCVersion &RHS) const { return !(*this < RHS); }
-  };
+  // Compute the set of prefixes for our search.
+  SmallVector<std::string, 8> Prefixes(D.PrefixDirs.begin(),
+                                       D.PrefixDirs.end());
+  Prefixes.push_back(D.SysRoot);
+  Prefixes.push_back(D.SysRoot + "/usr");
+  Prefixes.push_back(D.InstalledDir + "/..");
 
-  bool IsValid;
-  std::string GccTriple;
-
-  // FIXME: These might be better as path objects.
-  std::string GccInstallPath;
-  std::string GccParentLibPath;
-
-  llvm::SmallString<128> CxxIncludeRoot;
-
-public:
-  /// \brief Construct a GCCInstallationDetector from the driver.
-  ///
-  /// This performs all of the autodetection and sets up the various paths.
-  /// Once constructed, a GCCInstallation is esentially immutable.
-  GCCInstallationDetector(const Driver &D)
-    : IsValid(false),
-      GccTriple(D.DefaultHostTriple),
-      CxxIncludeRoot(CXX_INCLUDE_ROOT) {
-    // FIXME: Using CXX_INCLUDE_ROOT is here is a bit of a hack, but
-    // avoids adding yet another option to configure/cmake.
-    // It would probably be cleaner to break it in two variables
-    // CXX_GCC_ROOT with just /foo/bar
-    // CXX_GCC_VER with 4.5.2
-    // Then we would have
-    // CXX_INCLUDE_ROOT = CXX_GCC_ROOT/include/c++/CXX_GCC_VER
-    // and this function would return
-    // CXX_GCC_ROOT/lib/gcc/CXX_INCLUDE_ARCH/CXX_GCC_VER
-    if (CxxIncludeRoot != "") {
-      // This is of the form /foo/bar/include/c++/4.5.2/
-      if (CxxIncludeRoot.back() == '/')
-        llvm::sys::path::remove_filename(CxxIncludeRoot); // remove the /
-      StringRef Version = llvm::sys::path::filename(CxxIncludeRoot);
-      llvm::sys::path::remove_filename(CxxIncludeRoot); // remove the version
-      llvm::sys::path::remove_filename(CxxIncludeRoot); // remove the c++
-      llvm::sys::path::remove_filename(CxxIncludeRoot); // remove the include
-      GccInstallPath = CxxIncludeRoot.str();
-      GccInstallPath.append("/lib/gcc/");
-      GccInstallPath.append(CXX_INCLUDE_ARCH);
-      GccInstallPath.append("/");
-      GccInstallPath.append(Version);
-      GccParentLibPath = GccInstallPath + "/../../..";
-      IsValid = true;
-      return;
-    }
-
-    llvm::Triple::ArchType HostArch = llvm::Triple(GccTriple).getArch();
-    // The library directories which may contain GCC installations.
-    SmallVector<StringRef, 4> CandidateLibDirs;
-    // The compatible GCC triples for this particular architecture.
-    SmallVector<StringRef, 10> CandidateTriples;
-    CollectLibDirsAndTriples(HostArch, CandidateLibDirs, CandidateTriples);
-
-    // Always include the default host triple as the final fallback if no
-    // specific triple is detected.
-    CandidateTriples.push_back(D.DefaultHostTriple);
-
-    // Compute the set of prefixes for our search.
-    SmallVector<std::string, 8> Prefixes(D.PrefixDirs.begin(),
-                                         D.PrefixDirs.end());
-    Prefixes.push_back(D.SysRoot);
-    Prefixes.push_back(D.SysRoot + "/usr");
-    Prefixes.push_back(D.InstalledDir + "/..");
-
-    // Loop over the various components which exist and select the best GCC
-    // installation available. GCC installs are ranked by version number.
-    GCCVersion BestVersion = {0, 0, 0};
-    for (unsigned i = 0, ie = Prefixes.size(); i < ie; ++i) {
-      if (!PathExists(Prefixes[i]))
+  // Loop over the various components which exist and select the best GCC
+  // installation available. GCC installs are ranked by version number.
+  Version = GCCVersion::Parse("0.0.0");
+  for (unsigned i = 0, ie = Prefixes.size(); i < ie; ++i) {
+    if (!llvm::sys::fs::exists(Prefixes[i]))
+      continue;
+    for (unsigned j = 0, je = CandidateLibDirs.size(); j < je; ++j) {
+      const std::string LibDir = Prefixes[i] + CandidateLibDirs[j].str();
+      if (!llvm::sys::fs::exists(LibDir))
         continue;
-      for (unsigned j = 0, je = CandidateLibDirs.size(); j < je; ++j) {
-        const std::string LibDir = Prefixes[i] + CandidateLibDirs[j].str();
-        if (!PathExists(LibDir))
-          continue;
-        for (unsigned k = 0, ke = CandidateTriples.size(); k < ke; ++k)
-          ScanLibDirForGCCTriple(LibDir, CandidateTriples[k], BestVersion);
-      }
+      for (unsigned k = 0, ke = CandidateTriples.size(); k < ke; ++k)
+        ScanLibDirForGCCTriple(HostArch, LibDir, CandidateTriples[k]);
     }
   }
+}
 
-  /// \brief Check whether we detected a valid GCC install.
-  bool isValid() const { return IsValid; }
+/*static*/ void Linux::GCCInstallationDetector::CollectLibDirsAndTriples(
+    llvm::Triple::ArchType HostArch, SmallVectorImpl<StringRef> &LibDirs,
+    SmallVectorImpl<StringRef> &Triples) {
+  if (HostArch == llvm::Triple::arm || HostArch == llvm::Triple::thumb) {
+    static const char *const ARMLibDirs[] = { "/lib" };
+    static const char *const ARMTriples[] = { "arm-linux-gnueabi" };
+    LibDirs.append(ARMLibDirs, ARMLibDirs + llvm::array_lengthof(ARMLibDirs));
+    Triples.append(ARMTriples, ARMTriples + llvm::array_lengthof(ARMTriples));
+  } else if (HostArch == llvm::Triple::x86_64) {
+    static const char *const X86_64LibDirs[] = { "/lib64", "/lib" };
+    static const char *const X86_64Triples[] = {
+      "x86_64-linux-gnu",
+      "x86_64-unknown-linux-gnu",
+      "x86_64-pc-linux-gnu",
+      "x86_64-redhat-linux6E",
+      "x86_64-redhat-linux",
+      "x86_64-suse-linux",
+      "x86_64-manbo-linux-gnu",
+      "x86_64-linux-gnu",
+      "x86_64-slackware-linux"
+    };
+    LibDirs.append(X86_64LibDirs,
+                   X86_64LibDirs + llvm::array_lengthof(X86_64LibDirs));
+    Triples.append(X86_64Triples,
+                   X86_64Triples + llvm::array_lengthof(X86_64Triples));
+  } else if (HostArch == llvm::Triple::x86) {
+    static const char *const X86LibDirs[] = { "/lib32", "/lib" };
+    static const char *const X86Triples[] = {
+      "i686-linux-gnu",
+      "i686-pc-linux-gnu",
+      "i486-linux-gnu",
+      "i386-linux-gnu",
+      "i686-redhat-linux",
+      "i586-redhat-linux",
+      "i386-redhat-linux",
+      "i586-suse-linux",
+      "i486-slackware-linux"
+    };
+    LibDirs.append(X86LibDirs, X86LibDirs + llvm::array_lengthof(X86LibDirs));
+    Triples.append(X86Triples, X86Triples + llvm::array_lengthof(X86Triples));
+  } else if (HostArch == llvm::Triple::ppc) {
+    static const char *const PPCLibDirs[] = { "/lib32", "/lib" };
+    static const char *const PPCTriples[] = {
+      "powerpc-linux-gnu",
+      "powerpc-unknown-linux-gnu"
+    };
+    LibDirs.append(PPCLibDirs, PPCLibDirs + llvm::array_lengthof(PPCLibDirs));
+    Triples.append(PPCTriples, PPCTriples + llvm::array_lengthof(PPCTriples));
+  } else if (HostArch == llvm::Triple::ppc64) {
+    static const char *const PPC64LibDirs[] = { "/lib64", "/lib" };
+    static const char *const PPC64Triples[] = {
+      "powerpc64-unknown-linux-gnu"
+    };
+    LibDirs.append(PPC64LibDirs,
+                   PPC64LibDirs + llvm::array_lengthof(PPC64LibDirs));
+    Triples.append(PPC64Triples,
+                   PPC64Triples + llvm::array_lengthof(PPC64Triples));
+  }
+}
 
-  /// \brief Get the GCC triple for the detected install.
-  const std::string &getTriple() const { return GccTriple; }
+void Linux::GCCInstallationDetector::ScanLibDirForGCCTriple(
+    llvm::Triple::ArchType HostArch, const std::string &LibDir,
+    StringRef CandidateTriple) {
+  // There are various different suffixes involving the triple we
+  // check for. We also record what is necessary to walk from each back
+  // up to the lib directory.
+  const std::string Suffixes[] = {
+    "/gcc/" + CandidateTriple.str(),
+    "/" + CandidateTriple.str() + "/gcc/" + CandidateTriple.str(),
 
-  /// \brief Get the detected GCC installation path.
-  const std::string &getInstallPath() const { return GccInstallPath; }
+    // Ubuntu has a strange mis-matched pair of triples that this happens to
+    // match.
+    // FIXME: It may be worthwhile to generalize this and look for a second
+    // triple.
+    "/i386-linux-gnu/gcc/" + CandidateTriple.str()
+  };
+  const std::string InstallSuffixes[] = {
+    "/../../..",
+    "/../../../..",
+    "/../../../.."
+  };
+  // Only look at the final, weird Ubuntu suffix for i386-linux-gnu.
+  const unsigned NumSuffixes = (llvm::array_lengthof(Suffixes) -
+                                (HostArch != llvm::Triple::x86));
+  for (unsigned i = 0; i < NumSuffixes; ++i) {
+    StringRef Suffix = Suffixes[i];
+    llvm::error_code EC;
+    for (llvm::sys::fs::directory_iterator LI(LibDir + Suffix, EC), LE;
+         !EC && LI != LE; LI = LI.increment(EC)) {
+      StringRef VersionText = llvm::sys::path::filename(LI->path());
+      GCCVersion CandidateVersion = GCCVersion::Parse(VersionText);
+      static const GCCVersion MinVersion = { "4.1.1", 4, 1, 1, "" };
+      if (CandidateVersion < MinVersion)
+        continue;
+      if (CandidateVersion <= Version)
+        continue;
+      if (!llvm::sys::fs::exists(LI->path() + "/crtbegin.o"))
+        continue;
 
-  /// \brief Get the detected GCC parent lib path.
-  const std::string &getParentLibPath() const { return GccParentLibPath; }
-
-private:
-  static void CollectLibDirsAndTriples(llvm::Triple::ArchType HostArch,
-                                       SmallVectorImpl<StringRef> &LibDirs,
-                                       SmallVectorImpl<StringRef> &Triples) {
-    if (HostArch == llvm::Triple::arm || HostArch == llvm::Triple::thumb) {
-      static const char *const ARMLibDirs[] = { "/lib" };
-      static const char *const ARMTriples[] = { "arm-linux-gnueabi" };
-      LibDirs.append(ARMLibDirs, ARMLibDirs + llvm::array_lengthof(ARMLibDirs));
-      Triples.append(ARMTriples, ARMTriples + llvm::array_lengthof(ARMTriples));
-    } else if (HostArch == llvm::Triple::x86_64) {
-      static const char *const X86_64LibDirs[] = { "/lib64", "/lib" };
-      static const char *const X86_64Triples[] = {
-        "x86_64-linux-gnu",
-        "x86_64-unknown-linux-gnu",
-        "x86_64-pc-linux-gnu",
-        "x86_64-redhat-linux6E",
-        "x86_64-redhat-linux",
-        "x86_64-suse-linux",
-        "x86_64-manbo-linux-gnu",
-        "x86_64-linux-gnu",
-        "x86_64-slackware-linux"
-      };
-      LibDirs.append(X86_64LibDirs,
-                     X86_64LibDirs + llvm::array_lengthof(X86_64LibDirs));
-      Triples.append(X86_64Triples,
-                     X86_64Triples + llvm::array_lengthof(X86_64Triples));
-    } else if (HostArch == llvm::Triple::x86) {
-      static const char *const X86LibDirs[] = { "/lib32", "/lib" };
-      static const char *const X86Triples[] = {
-        "i686-linux-gnu",
-        "i386-linux-gnu",
-        "i686-pc-linux-gnu",
-        "i486-linux-gnu",
-        "i686-redhat-linux",
-        "i386-redhat-linux",
-        "i586-suse-linux",
-        "i486-slackware-linux"
-      };
-      LibDirs.append(X86LibDirs, X86LibDirs + llvm::array_lengthof(X86LibDirs));
-      Triples.append(X86Triples, X86Triples + llvm::array_lengthof(X86Triples));
-    } else if (HostArch == llvm::Triple::ppc) {
-      static const char *const PPCLibDirs[] = { "/lib32", "/lib" };
-      static const char *const PPCTriples[] = {
-        "powerpc-linux-gnu",
-        "powerpc-unknown-linux-gnu"
-      };
-      LibDirs.append(PPCLibDirs, PPCLibDirs + llvm::array_lengthof(PPCLibDirs));
-      Triples.append(PPCTriples, PPCTriples + llvm::array_lengthof(PPCTriples));
-    } else if (HostArch == llvm::Triple::ppc64) {
-      static const char *const PPC64LibDirs[] = { "/lib64", "/lib" };
-      static const char *const PPC64Triples[] = {
-        "powerpc64-unknown-linux-gnu"
-      };
-      LibDirs.append(PPC64LibDirs,
-                     PPC64LibDirs + llvm::array_lengthof(PPC64LibDirs));
-      Triples.append(PPC64Triples,
-                     PPC64Triples + llvm::array_lengthof(PPC64Triples));
+      Version = CandidateVersion;
+      GccTriple = CandidateTriple.str();
+      // FIXME: We hack together the directory name here instead of
+      // using LI to ensure stable path separators across Windows and
+      // Linux.
+      GccInstallPath = LibDir + Suffixes[i] + "/" + VersionText.str();
+      GccParentLibPath = GccInstallPath + InstallSuffixes[i];
+      IsValid = true;
     }
   }
-
-  void ScanLibDirForGCCTriple(const std::string &LibDir,
-                              StringRef CandidateTriple,
-                              GCCVersion &BestVersion) {
-    // There are various different suffixes involving the triple we
-    // check for. We also record what is necessary to walk from each back
-    // up to the lib directory.
-    const std::string Suffixes[] = {
-      "/gcc/" + CandidateTriple.str(),
-      "/" + CandidateTriple.str() + "/gcc/" + CandidateTriple.str(),
-
-      // Ubuntu has a strange mis-matched pair of triples that this happens to
-      // match.
-      // FIXME: It may be worthwhile to generalize this and look for a second
-      // triple.
-      "/" + CandidateTriple.str() + "/gcc/i686-linux-gnu"
-    };
-    const std::string InstallSuffixes[] = {
-      "/../../..",
-      "/../../../..",
-      "/../../../.."
-    };
-    // Only look at the final, weird Ubuntu suffix for i386-linux-gnu.
-    const unsigned NumSuffixes = (llvm::array_lengthof(Suffixes) -
-                                  (CandidateTriple != "i386-linux-gnu"));
-    for (unsigned i = 0; i < NumSuffixes; ++i) {
-      StringRef Suffix = Suffixes[i];
-      llvm::error_code EC;
-      for (llvm::sys::fs::directory_iterator LI(LibDir + Suffix, EC), LE;
-           !EC && LI != LE; LI = LI.increment(EC)) {
-        StringRef VersionText = llvm::sys::path::filename(LI->path());
-        GCCVersion CandidateVersion = GCCVersion::Parse(VersionText);
-        static const GCCVersion MinVersion = { 4, 1, 1 };
-        if (CandidateVersion < MinVersion)
-          continue;
-        if (CandidateVersion <= BestVersion)
-          continue;
-        if (!PathExists(LI->path() + "/crtbegin.o"))
-          continue;
-
-        BestVersion = CandidateVersion;
-        GccTriple = CandidateTriple.str();
-        // FIXME: We hack together the directory name here instead of
-        // using LI to ensure stable path separators across Windows and
-        // Linux.
-        GccInstallPath = LibDir + Suffixes[i] + "/" + VersionText.str();
-        GccParentLibPath = GccInstallPath + InstallSuffixes[i];
-        IsValid = true;
-      }
-    }
-  }
-};
 }
 
-static void addPathIfExists(const std::string &Path,
-                            ToolChain::path_list &Paths) {
-  if (PathExists(Path)) Paths.push_back(Path);
+static void addPathIfExists(Twine Path, ToolChain::path_list &Paths) {
+  if (llvm::sys::fs::exists(Path)) Paths.push_back(Path.str());
+}
+
+/// \brief Get our best guess at the multiarch triple for a target.
+///
+/// Debian-based systems are starting to use a multiarch setup where they use
+/// a target-triple directory in the library and header search paths.
+/// Unfortunately, this triple does not align with the vanilla target triple,
+/// so we provide a rough mapping here.
+static std::string getMultiarchTriple(const llvm::Triple TargetTriple,
+                                      StringRef SysRoot) {
+  // For most architectures, just use whatever we have rather than trying to be
+  // clever.
+  switch (TargetTriple.getArch()) {
+  default:
+    return TargetTriple.str();
+
+    // We use the existence of '/lib/<triple>' as a directory to detect some
+    // common linux triples that don't quite match the Clang triple for both
+    // 32-bit and 64-bit targets. This works around annoying discrepancies on
+    // Debian-based systems.
+  case llvm::Triple::x86:
+    if (llvm::sys::fs::exists(SysRoot + "/lib/i686-linux-gnu"))
+      return "i686-linux-gnu";
+    if (llvm::sys::fs::exists(SysRoot + "/lib/i386-linux-gnu"))
+      return "i386-linux-gnu";
+    return TargetTriple.str();
+  case llvm::Triple::x86_64:
+    if (llvm::sys::fs::exists(SysRoot + "/lib/x86_64-linux-gnu"))
+      return "x86_64-linux-gnu";
+    if (llvm::sys::fs::exists(SysRoot + "/lib/x86_64-pc-linux-gnu"))
+      return "x86_64-pc-linux-gnu";
+    if (llvm::sys::fs::exists(SysRoot + "/lib/x86_64-unknown-linux-gnu"))
+      return "x86_64-unknown-linux-gnu";
+    return TargetTriple.str();
+  }
 }
 
 Linux::Linux(const HostInfo &Host, const llvm::Triple &Triple)
-  : Generic_ELF(Host, Triple) {
+  : Generic_ELF(Host, Triple), GCCInstallation(getDriver()) {
   llvm::Triple::ArchType Arch =
     llvm::Triple(getDriver().DefaultHostTriple).getArch();
   const std::string &SysRoot = getDriver().SysRoot;
-  GCCInstallationDetector GCCInstallation(getDriver());
 
   // OpenSuse stores the linker with the compiler, add that to the search
   // path.
   ToolChain::path_list &PPaths = getProgramPaths();
-  PPaths.push_back(GCCInstallation.getParentLibPath() + "/../" +
-                   GCCInstallation.getTriple() + "/bin");
+  PPaths.push_back(Twine(GCCInstallation.getParentLibPath() + "/../" +
+                         GCCInstallation.getTriple() + "/bin").str());
 
   Linker = GetProgramPath("ld");
 
@@ -1808,50 +1849,43 @@
   const std::string Suffix64 = Arch == llvm::Triple::x86_64 ? "" : "/64";
   const std::string Suffix = Is32Bits ? Suffix32 : Suffix64;
   const std::string Multilib = Is32Bits ? "lib32" : "lib64";
+  const std::string MultiarchTriple = getMultiarchTriple(Triple, SysRoot);
 
-  // FIXME: Because we add paths only when they exist on the system, I think we
-  // should remove the concept of 'HasMultilib'. It's more likely to break the
-  // behavior than to preserve any useful invariant on the system.
-  if (HasMultilib(Arch, Distro)) {
-    // Add the multilib suffixed paths.
-    if (GCCInstallation.isValid()) {
-      const std::string &LibPath = GCCInstallation.getParentLibPath();
-      const std::string &GccTriple = GCCInstallation.getTriple();
-      // FIXME: This OpenSuse-specific path shouldn't be needed any more, but
-      // I don't want to remove it without finding someone to test.
-      if (IsOpenSuse(Distro) && Is32Bits)
-        Paths.push_back(LibPath + "/../" + GccTriple + "/lib/../lib");
+  // Add the multilib suffixed paths where they are available.
+  if (GCCInstallation.isValid()) {
+    const std::string &LibPath = GCCInstallation.getParentLibPath();
+    const std::string &GccTriple = GCCInstallation.getTriple();
+    addPathIfExists(GCCInstallation.getInstallPath() + Suffix, Paths);
+    addPathIfExists(LibPath + "/../" + GccTriple + "/lib/../" + Multilib,
+                    Paths);
+    addPathIfExists(LibPath + "/" + MultiarchTriple, Paths);
+    addPathIfExists(LibPath + "/../" + Multilib, Paths);
+  }
+  addPathIfExists(SysRoot + "/lib/" + MultiarchTriple, Paths);
+  addPathIfExists(SysRoot + "/lib/../" + Multilib, Paths);
+  addPathIfExists(SysRoot + "/usr/lib/" + MultiarchTriple, Paths);
+  addPathIfExists(SysRoot + "/usr/lib/../" + Multilib, Paths);
 
-      addPathIfExists(GCCInstallation.getInstallPath() + Suffix, Paths);
-      addPathIfExists(LibPath + "/../" + GccTriple + "/lib/../" + Multilib,
-                      Paths);
-      addPathIfExists(LibPath + "/../" + Multilib, Paths);
-    }
-    addPathIfExists(SysRoot + "/lib/../" + Multilib, Paths);
-    addPathIfExists(SysRoot + "/usr/lib/../" + Multilib, Paths);
-
-    // Try walking via the GCC triple path in case of multiarch GCC
-    // installations with strange symlinks.
-    if (GCCInstallation.isValid())
-      addPathIfExists(SysRoot + "/usr/lib/" + GCCInstallation.getTriple() +
-                      "/../../" + Multilib, Paths);
-  }
+  // Try walking via the GCC triple path in case of multiarch GCC
+  // installations with strange symlinks.
+  if (GCCInstallation.isValid())
+    addPathIfExists(SysRoot + "/usr/lib/" + GCCInstallation.getTriple() +
+                    "/../../" + Multilib, Paths);
 
   // Add the non-multilib suffixed paths (if potentially different).
   if (GCCInstallation.isValid()) {
     const std::string &LibPath = GCCInstallation.getParentLibPath();
     const std::string &GccTriple = GCCInstallation.getTriple();
-    if (!Suffix.empty() || !HasMultilib(Arch, Distro))
+    if (!Suffix.empty())
       addPathIfExists(GCCInstallation.getInstallPath(), Paths);
     addPathIfExists(LibPath + "/../" + GccTriple + "/lib", Paths);
+    addPathIfExists(LibPath + "/" + MultiarchTriple, Paths);
     addPathIfExists(LibPath, Paths);
   }
+  addPathIfExists(SysRoot + "/lib/" + MultiarchTriple, Paths);
   addPathIfExists(SysRoot + "/lib", Paths);
+  addPathIfExists(SysRoot + "/usr/lib/" + MultiarchTriple, Paths);
   addPathIfExists(SysRoot + "/usr/lib", Paths);
-
-  // Add a multiarch lib directory whenever it exists and is plausible.
-  if (GCCInstallation.isValid() && Arch == getArch())
-    addPathIfExists(SysRoot + "/usr/lib/" + GCCInstallation.getTriple(), Paths);
 }
 
 bool Linux::HasNativeLLVMSupport() const {
@@ -1889,6 +1923,161 @@
   return *T;
 }
 
+void Linux::AddClangSystemIncludeArgs(const ArgList &DriverArgs,
+                                      ArgStringList &CC1Args) const {
+  const Driver &D = getDriver();
+
+  if (DriverArgs.hasArg(options::OPT_nostdinc))
+    return;
+
+  if (!DriverArgs.hasArg(options::OPT_nostdlibinc))
+    addSystemInclude(DriverArgs, CC1Args, D.SysRoot + "/usr/local/include");
+
+  if (!DriverArgs.hasArg(options::OPT_nobuiltininc)) {
+    llvm::sys::Path P(D.ResourceDir);
+    P.appendComponent("include");
+    addSystemInclude(DriverArgs, CC1Args, P.str());
+  }
+
+  if (DriverArgs.hasArg(options::OPT_nostdlibinc))
+    return;
+
+  // Check for configure-time C include directories.
+  StringRef CIncludeDirs(C_INCLUDE_DIRS);
+  if (CIncludeDirs != "") {
+    SmallVector<StringRef, 5> dirs;
+    CIncludeDirs.split(dirs, ":");
+    for (SmallVectorImpl<StringRef>::iterator I = dirs.begin(), E = dirs.end();
+         I != E; ++I) {
+      StringRef Prefix = llvm::sys::path::is_absolute(*I) ? D.SysRoot : "";
+      addExternCSystemInclude(DriverArgs, CC1Args, Prefix + *I);
+    }
+    return;
+  }
+
+  // Lacking those, try to detect the correct set of system includes for the
+  // target triple.
+
+  // Implement generic Debian multiarch support.
+  const StringRef X86_64MultiarchIncludeDirs[] = {
+    "/usr/include/x86_64-linux-gnu",
+
+    // FIXME: These are older forms of multiarch. It's not clear that they're
+    // in use in any released version of Debian, so we should consider
+    // removing them.
+    "/usr/include/i686-linux-gnu/64",
+    "/usr/include/i486-linux-gnu/64"
+  };
+  const StringRef X86MultiarchIncludeDirs[] = {
+    "/usr/include/i386-linux-gnu",
+
+    // FIXME: These are older forms of multiarch. It's not clear that they're
+    // in use in any released version of Debian, so we should consider
+    // removing them.
+    "/usr/include/x86_64-linux-gnu/32",
+    "/usr/include/i686-linux-gnu",
+    "/usr/include/i486-linux-gnu"
+  };
+  const StringRef ARMMultiarchIncludeDirs[] = {
+    "/usr/include/arm-linux-gnueabi"
+  };
+  ArrayRef<StringRef> MultiarchIncludeDirs;
+  if (getTriple().getArch() == llvm::Triple::x86_64) {
+    MultiarchIncludeDirs = X86_64MultiarchIncludeDirs;
+  } else if (getTriple().getArch() == llvm::Triple::x86) {
+    MultiarchIncludeDirs = X86MultiarchIncludeDirs;
+  } else if (getTriple().getArch() == llvm::Triple::arm) {
+    MultiarchIncludeDirs = ARMMultiarchIncludeDirs;
+  }
+  for (ArrayRef<StringRef>::iterator I = MultiarchIncludeDirs.begin(),
+                                     E = MultiarchIncludeDirs.end();
+       I != E; ++I) {
+    if (llvm::sys::fs::exists(*I)) {
+      addExternCSystemInclude(DriverArgs, CC1Args, D.SysRoot + *I);
+      break;
+    }
+  }
+
+  if (getTriple().getOS() == llvm::Triple::RTEMS)
+    return;
+
+  addExternCSystemInclude(DriverArgs, CC1Args, D.SysRoot + "/usr/include");
+}
+
+static bool addLibStdCXXIncludePaths(Twine Base, Twine TargetArchDir,
+                                     const ArgList &DriverArgs,
+                                     ArgStringList &CC1Args) {
+  if (!llvm::sys::fs::exists(Base))
+    return false;
+  addSystemInclude(DriverArgs, CC1Args, Base);
+  addSystemInclude(DriverArgs, CC1Args, Base + "/" + TargetArchDir);
+  addSystemInclude(DriverArgs, CC1Args, Base + "/backward");
+  return true;
+}
+
+void Linux::AddClangCXXStdlibIncludeArgs(const ArgList &DriverArgs,
+                                         ArgStringList &CC1Args) const {
+  if (DriverArgs.hasArg(options::OPT_nostdlibinc) ||
+      DriverArgs.hasArg(options::OPT_nostdincxx))
+    return;
+
+  // Check if libc++ has been enabled and provide its include paths if so.
+  if (GetCXXStdlibType(DriverArgs) == ToolChain::CST_Libcxx) {
+    // libc++ is always installed at a fixed path on Linux currently.
+    addSystemInclude(DriverArgs, CC1Args,
+                     getDriver().SysRoot + "/usr/include/c++/v1");
+    return;
+  }
+
+  const llvm::Triple &TargetTriple = getTriple();
+  const llvm::Triple::ArchType TargetArch = TargetTriple.getArch();
+  bool IsTarget64Bit = (TargetArch == llvm::Triple::x86_64 ||
+                        TargetArch == llvm::Triple::ppc64);
+
+  StringRef CxxIncludeRoot(CXX_INCLUDE_ROOT);
+  if (!CxxIncludeRoot.empty()) {
+    StringRef CxxIncludeArch(CXX_INCLUDE_ARCH);
+    if (CxxIncludeArch.empty())
+      CxxIncludeArch = TargetTriple.str();
+
+    addLibStdCXXIncludePaths(
+      CxxIncludeRoot,
+      CxxIncludeArch + (IsTarget64Bit ? CXX_INCLUDE_64BIT_DIR
+                                      : CXX_INCLUDE_32BIT_DIR),
+      DriverArgs, CC1Args);
+    return;
+  }
+
+  // Check if the target architecture specific dirs need a suffix. Note that we
+  // only support the suffix-based bi-arch-like header scheme for host/target
+  // mismatches of just bit width.
+  llvm::Triple::ArchType HostArch =
+    llvm::Triple(getDriver().DefaultHostTriple).getArch();
+  StringRef Suffix;
+  if ((HostArch == llvm::Triple::x86 && TargetArch == llvm::Triple::x86_64) ||
+      (HostArch == llvm::Triple::ppc && TargetArch == llvm::Triple::ppc64))
+    Suffix = "/64";
+  if ((HostArch == llvm::Triple::x86_64 && TargetArch == llvm::Triple::x86) ||
+      (HostArch == llvm::Triple::ppc64 && TargetArch == llvm::Triple::ppc))
+    Suffix = "/32";
+
+  // By default, look for the C++ headers in an include directory adjacent to
+  // the lib directory of the GCC installation. Note that this is expect to be
+  // equivalent to '/usr/include/c++/X.Y' in almost all cases.
+  StringRef LibDir = GCCInstallation.getParentLibPath();
+  StringRef InstallDir = GCCInstallation.getInstallPath();
+  StringRef Version = GCCInstallation.getVersion();
+  if (!addLibStdCXXIncludePaths(LibDir + "/../include/c++/" + Version,
+                                GCCInstallation.getTriple() + Suffix,
+                                DriverArgs, CC1Args)) {
+    // Gentoo is weird and places its headers inside the GCC install, so if the
+    // first attempt to find the headers fails, try this pattern.
+    addLibStdCXXIncludePaths(InstallDir + "/include/g++-v4",
+                             GCCInstallation.getTriple() + Suffix,
+                             DriverArgs, CC1Args);
+  }
+}
+
 /// DragonFly - DragonFly tool chain which can call as(1) and ld(1) directly.
 
 DragonFly::DragonFly(const HostInfo &Host, const llvm::Triple& Triple)
@@ -1990,3 +2179,258 @@
     return "pic";
   return 0;
 }
+
+// FIXME: This probably should goto to some platform utils place.
+#ifdef _MSC_VER
+
+/// \brief Read registry string.
+/// This also supports a means to look for high-versioned keys by use
+/// of a $VERSION placeholder in the key path.
+/// $VERSION in the key path is a placeholder for the version number,
+/// causing the highest value path to be searched for and used.
+/// I.e. "HKEY_LOCAL_MACHINE\\SOFTWARE\\Microsoft\\VisualStudio\\$VERSION".
+/// There can be additional characters in the component.  Only the numberic
+/// characters are compared.
+static bool getSystemRegistryString(const char *keyPath, const char *valueName,
+                                    char *value, size_t maxLength) {
+  HKEY hRootKey = NULL;
+  HKEY hKey = NULL;
+  const char* subKey = NULL;
+  DWORD valueType;
+  DWORD valueSize = maxLength - 1;
+  long lResult;
+  bool returnValue = false;
+
+  if (strncmp(keyPath, "HKEY_CLASSES_ROOT\\", 18) == 0) {
+    hRootKey = HKEY_CLASSES_ROOT;
+    subKey = keyPath + 18;
+  } else if (strncmp(keyPath, "HKEY_USERS\\", 11) == 0) {
+    hRootKey = HKEY_USERS;
+    subKey = keyPath + 11;
+  } else if (strncmp(keyPath, "HKEY_LOCAL_MACHINE\\", 19) == 0) {
+    hRootKey = HKEY_LOCAL_MACHINE;
+    subKey = keyPath + 19;
+  } else if (strncmp(keyPath, "HKEY_CURRENT_USER\\", 18) == 0) {
+    hRootKey = HKEY_CURRENT_USER;
+    subKey = keyPath + 18;
+  } else {
+    return false;
+  }
+
+  const char *placeHolder = strstr(subKey, "$VERSION");
+  char bestName[256];
+  bestName[0] = '\0';
+  // If we have a $VERSION placeholder, do the highest-version search.
+  if (placeHolder) {
+    const char *keyEnd = placeHolder - 1;
+    const char *nextKey = placeHolder;
+    // Find end of previous key.
+    while ((keyEnd > subKey) && (*keyEnd != '\\'))
+      keyEnd--;
+    // Find end of key containing $VERSION.
+    while (*nextKey && (*nextKey != '\\'))
+      nextKey++;
+    size_t partialKeyLength = keyEnd - subKey;
+    char partialKey[256];
+    if (partialKeyLength > sizeof(partialKey))
+      partialKeyLength = sizeof(partialKey);
+    strncpy(partialKey, subKey, partialKeyLength);
+    partialKey[partialKeyLength] = '\0';
+    HKEY hTopKey = NULL;
+    lResult = RegOpenKeyEx(hRootKey, partialKey, 0, KEY_READ, &hTopKey);
+    if (lResult == ERROR_SUCCESS) {
+      char keyName[256];
+      int bestIndex = -1;
+      double bestValue = 0.0;
+      DWORD index, size = sizeof(keyName) - 1;
+      for (index = 0; RegEnumKeyEx(hTopKey, index, keyName, &size, NULL,
+          NULL, NULL, NULL) == ERROR_SUCCESS; index++) {
+        const char *sp = keyName;
+        while (*sp && !isdigit(*sp))
+          sp++;
+        if (!*sp)
+          continue;
+        const char *ep = sp + 1;
+        while (*ep && (isdigit(*ep) || (*ep == '.')))
+          ep++;
+        char numBuf[32];
+        strncpy(numBuf, sp, sizeof(numBuf) - 1);
+        numBuf[sizeof(numBuf) - 1] = '\0';
+        double value = strtod(numBuf, NULL);
+        if (value > bestValue) {
+          bestIndex = (int)index;
+          bestValue = value;
+          strcpy(bestName, keyName);
+        }
+        size = sizeof(keyName) - 1;
+      }
+      // If we found the highest versioned key, open the key and get the value.
+      if (bestIndex != -1) {
+        // Append rest of key.
+        strncat(bestName, nextKey, sizeof(bestName) - 1);
+        bestName[sizeof(bestName) - 1] = '\0';
+        // Open the chosen key path remainder.
+        lResult = RegOpenKeyEx(hTopKey, bestName, 0, KEY_READ, &hKey);
+        if (lResult == ERROR_SUCCESS) {
+          lResult = RegQueryValueEx(hKey, valueName, NULL, &valueType,
+            (LPBYTE)value, &valueSize);
+          if (lResult == ERROR_SUCCESS)
+            returnValue = true;
+          RegCloseKey(hKey);
+        }
+      }
+      RegCloseKey(hTopKey);
+    }
+  } else {
+    lResult = RegOpenKeyEx(hRootKey, subKey, 0, KEY_READ, &hKey);
+    if (lResult == ERROR_SUCCESS) {
+      lResult = RegQueryValueEx(hKey, valueName, NULL, &valueType,
+        (LPBYTE)value, &valueSize);
+      if (lResult == ERROR_SUCCESS)
+        returnValue = true;
+      RegCloseKey(hKey);
+    }
+  }
+  return returnValue;
+}
+
+/// \brief Get Windows SDK installation directory.
+static bool getWindowsSDKDir(std::string &path) {
+  char windowsSDKInstallDir[256];
+  // Try the Windows registry.
+  bool hasSDKDir = getSystemRegistryString(
+   "HKEY_LOCAL_MACHINE\\SOFTWARE\\Microsoft\\Microsoft SDKs\\Windows\\$VERSION",
+                                           "InstallationFolder",
+                                           windowsSDKInstallDir,
+                                           sizeof(windowsSDKInstallDir) - 1);
+    // If we have both vc80 and vc90, pick version we were compiled with.
+  if (hasSDKDir && windowsSDKInstallDir[0]) {
+    path = windowsSDKInstallDir;
+    return true;
+  }
+  return false;
+}
+
+  // Get Visual Studio installation directory.
+static bool getVisualStudioDir(std::string &path) {
+  // First check the environment variables that vsvars32.bat sets.
+  const char* vcinstalldir = getenv("VCINSTALLDIR");
+  if (vcinstalldir) {
+    char *p = const_cast<char *>(strstr(vcinstalldir, "\\VC"));
+    if (p)
+      *p = '\0';
+    path = vcinstalldir;
+    return true;
+  }
+
+  char vsIDEInstallDir[256];
+  char vsExpressIDEInstallDir[256];
+  // Then try the windows registry.
+  bool hasVCDir = getSystemRegistryString(
+    "HKEY_LOCAL_MACHINE\\SOFTWARE\\Microsoft\\VisualStudio\\$VERSION",
+    "InstallDir", vsIDEInstallDir, sizeof(vsIDEInstallDir) - 1);
+  bool hasVCExpressDir = getSystemRegistryString(
+    "HKEY_LOCAL_MACHINE\\SOFTWARE\\Microsoft\\VCExpress\\$VERSION",
+    "InstallDir", vsExpressIDEInstallDir, sizeof(vsExpressIDEInstallDir) - 1);
+    // If we have both vc80 and vc90, pick version we were compiled with.
+  if (hasVCDir && vsIDEInstallDir[0]) {
+    char *p = (char*)strstr(vsIDEInstallDir, "\\Common7\\IDE");
+    if (p)
+      *p = '\0';
+    path = vsIDEInstallDir;
+    return true;
+  }
+
+  if (hasVCExpressDir && vsExpressIDEInstallDir[0]) {
+    char *p = (char*)strstr(vsExpressIDEInstallDir, "\\Common7\\IDE");
+    if (p)
+      *p = '\0';
+    path = vsExpressIDEInstallDir;
+    return true;
+  }
+
+  // Try the environment.
+  const char *vs100comntools = getenv("VS100COMNTOOLS");
+  const char *vs90comntools = getenv("VS90COMNTOOLS");
+  const char *vs80comntools = getenv("VS80COMNTOOLS");
+  const char *vscomntools = NULL;
+
+  // Try to find the version that we were compiled with
+  if(false) {}
+  #if (_MSC_VER >= 1600)  // VC100
+  else if(vs100comntools) {
+    vscomntools = vs100comntools;
+  }
+  #elif (_MSC_VER == 1500) // VC80
+  else if(vs90comntools) {
+    vscomntools = vs90comntools;
+  }
+  #elif (_MSC_VER == 1400) // VC80
+  else if(vs80comntools) {
+    vscomntools = vs80comntools;
+  }
+  #endif
+  // Otherwise find any version we can
+  else if (vs100comntools)
+    vscomntools = vs100comntools;
+  else if (vs90comntools)
+    vscomntools = vs90comntools;
+  else if (vs80comntools)
+    vscomntools = vs80comntools;
+
+  if (vscomntools && *vscomntools) {
+    const char *p = strstr(vscomntools, "\\Common7\\Tools");
+    path = p ? std::string(vscomntools, p) : vscomntools;
+    return true;
+  }
+  return false;
+}
+
+#endif // _MSC_VER
+
+void Windows::AddClangSystemIncludeArgs(const ArgList &DriverArgs,
+                                        ArgStringList &CC1Args) const {
+  if (DriverArgs.hasArg(options::OPT_nostdinc))
+    return;
+
+  if (!DriverArgs.hasArg(options::OPT_nobuiltininc)) {
+    llvm::sys::Path P(getDriver().ResourceDir);
+    P.appendComponent("include");
+    addSystemInclude(DriverArgs, CC1Args, P.str());
+  }
+
+  if (DriverArgs.hasArg(options::OPT_nostdlibinc))
+    return;
+
+  std::string VSDir;
+  std::string WindowsSDKDir;
+
+#ifdef _MSC_VER
+  // When built with access to the proper Windows APIs, try to actually find
+  // the correct include paths first.
+  if (getVisualStudioDir(VSDir)) {
+    addSystemInclude(DriverArgs, CC1Args, VSDir + "\\VC\\include");
+    if (getWindowsSDKDir(WindowsSDKDir))
+      addSystemInclude(DriverArgs, CC1Args, WindowsSDKDir + "\\include");
+    else
+      addSystemInclude(DriverArgs, CC1Args,
+                       VSDir + "\\VC\\PlatformSDK\\Include");
+    return;
+  }
+#endif // _MSC_VER
+
+  // As a fallback, select default install paths.
+  const StringRef Paths[] = {
+    "C:/Program Files/Microsoft Visual Studio 10.0/VC/include",
+    "C:/Program Files/Microsoft Visual Studio 9.0/VC/include",
+    "C:/Program Files/Microsoft Visual Studio 9.0/VC/PlatformSDK/Include",
+    "C:/Program Files/Microsoft Visual Studio 8/VC/include",
+    "C:/Program Files/Microsoft Visual Studio 8/VC/PlatformSDK/Include"
+  };
+  addSystemIncludes(DriverArgs, CC1Args, Paths);
+}
+
+void Windows::AddClangCXXStdlibIncludeArgs(const ArgList &DriverArgs,
+                                           ArgStringList &CC1Args) const {
+  // FIXME: There should probably be logic here to find libc++ on Windows.
+}
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/tools/clang/lib/Driver/ToolChains.h
--- a/head/contrib/llvm/tools/clang/lib/Driver/ToolChains.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/tools/clang/lib/Driver/ToolChains.h	Thu Dec 15 12:59:38 2011 +0200
@@ -372,6 +372,86 @@
 };
 
 class LLVM_LIBRARY_VISIBILITY Linux : public Generic_ELF {
+  /// \brief Struct to store and manipulate GCC versions.
+  ///
+  /// We rely on assumptions about the form and structure of GCC version
+  /// numbers: they consist of at most three '.'-separated components, and each
+  /// component is a non-negative integer except for the last component. For
+  /// the last component we are very flexible in order to tolerate release
+  /// candidates or 'x' wildcards.
+  ///
+  /// Note that the ordering established among GCCVersions is based on the
+  /// preferred version string to use. For example we prefer versions without
+  /// a hard-coded patch number to those with a hard coded patch number.
+  ///
+  /// Currently this doesn't provide any logic for textual suffixes to patches
+  /// in the way that (for example) Debian's version format does. If that ever
+  /// becomes necessary, it can be added.
+  struct GCCVersion {
+    /// \brief The unparsed text of the version.
+    std::string Text;
+
+    /// \brief The parsed major, minor, and patch numbers.
+    int Major, Minor, Patch;
+
+    /// \brief Any textual suffix on the patch number.
+    std::string PatchSuffix;
+
+    static GCCVersion Parse(StringRef VersionText);
+    bool operator<(const GCCVersion &RHS) const;
+    bool operator>(const GCCVersion &RHS) const { return RHS < *this; }
+    bool operator<=(const GCCVersion &RHS) const { return !(*this > RHS); }
+    bool operator>=(const GCCVersion &RHS) const { return !(*this < RHS); }
+  };
+
+
+  /// \brief This is a class to find a viable GCC installation for Clang to
+  /// use.
+  ///
+  /// This class tries to find a GCC installation on the system, and report
+  /// information about it. It starts from the host information provided to the
+  /// Driver, and has logic for fuzzing that where appropriate.
+  class GCCInstallationDetector {
+
+    bool IsValid;
+    std::string GccTriple;
+
+    // FIXME: These might be better as path objects.
+    std::string GccInstallPath;
+    std::string GccParentLibPath;
+
+    GCCVersion Version;
+
+  public:
+    GCCInstallationDetector(const Driver &D);
+
+    /// \brief Check whether we detected a valid GCC install.
+    bool isValid() const { return IsValid; }
+
+    /// \brief Get the GCC triple for the detected install.
+    StringRef getTriple() const { return GccTriple; }
+
+    /// \brief Get the detected GCC installation path.
+    StringRef getInstallPath() const { return GccInstallPath; }
+
+    /// \brief Get the detected GCC parent lib path.
+    StringRef getParentLibPath() const { return GccParentLibPath; }
+
+    /// \brief Get the detected GCC version string.
+    StringRef getVersion() const { return Version.Text; }
+
+  private:
+    static void CollectLibDirsAndTriples(llvm::Triple::ArchType HostArch,
+                                         SmallVectorImpl<StringRef> &LibDirs,
+                                         SmallVectorImpl<StringRef> &Triples);
+
+    void ScanLibDirForGCCTriple(llvm::Triple::ArchType HostArch,
+                                const std::string &LibDir,
+                                StringRef CandidateTriple);
+  };
+
+  GCCInstallationDetector GCCInstallation;
+
 public:
   Linux(const HostInfo &Host, const llvm::Triple& Triple);
 
@@ -380,6 +460,11 @@
   virtual Tool &SelectTool(const Compilation &C, const JobAction &JA,
                            const ActionList &Inputs) const;
 
+  virtual void AddClangSystemIncludeArgs(const ArgList &DriverArgs,
+                                         ArgStringList &CC1Args) const;
+  virtual void AddClangCXXStdlibIncludeArgs(const ArgList &DriverArgs,
+                                            ArgStringList &CC1Args) const;
+
   std::string Linker;
   std::vector<std::string> ExtraOpts;
 };
@@ -417,6 +502,12 @@
   virtual bool IsUnwindTablesDefault() const;
   virtual const char *GetDefaultRelocationModel() const;
   virtual const char *GetForcedPicModel() const;
+
+  virtual void AddClangSystemIncludeArgs(const ArgList &DriverArgs,
+                                         ArgStringList &CC1Args) const;
+  virtual void AddClangCXXStdlibIncludeArgs(const ArgList &DriverArgs,
+                                            ArgStringList &CC1Args) const;
+
 };
 
 } // end namespace toolchains
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/tools/clang/lib/Driver/Tools.cpp
--- a/head/contrib/llvm/tools/clang/lib/Driver/Tools.cpp	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/tools/clang/lib/Driver/Tools.cpp	Thu Dec 15 12:59:38 2011 +0200
@@ -364,16 +364,6 @@
   Args.AddAllArgs(CmdArgs, options::OPT_I_Group, options::OPT_F,
                   options::OPT_index_header_map);
 
-  // Add C++ include arguments, if needed.
-  types::ID InputType = Inputs[0].getType();
-  if (types::isCXX(InputType)) {
-    bool ObjCXXAutoRefCount
-      = types::isObjC(InputType) && isObjCAutoRefCount(Args);
-    getToolChain().AddClangCXXStdlibIncludeArgs(Args, CmdArgs,
-                                                ObjCXXAutoRefCount);
-    Args.AddAllArgs(CmdArgs, options::OPT_stdlib_EQ);
-  }
-
   // Add -Wp, and -Xassembler if using the preprocessor.
 
   // FIXME: There is a very unfortunate problem here, some troubled
@@ -428,6 +418,13 @@
   // OBJCPLUS_INCLUDE_PATH - system includes enabled when compiling ObjC++.
   AddIncludeDirectoryList(Args, CmdArgs, "-objcxx-isystem",
                           ::getenv("OBJCPLUS_INCLUDE_PATH"));
+
+  // Add C++ include arguments, if needed.
+  if (types::isCXX(Inputs[0].getType()))
+    getToolChain().AddClangCXXStdlibIncludeArgs(Args, CmdArgs);
+
+  // Add system include arguments.
+  getToolChain().AddClangSystemIncludeArgs(Args, CmdArgs);
 }
 
 /// getARMTargetCPU - Get the (LLVM) name of the ARM cpu we are targeting.
@@ -1966,6 +1963,16 @@
   if (ARC) {
     CmdArgs.push_back("-fobjc-arc");
 
+    // FIXME: It seems like this entire block, and several around it should be
+    // wrapped in isObjC, but for now we just use it here as this is where it
+    // was being used previously.
+    if (types::isCXX(InputType) && types::isObjC(InputType)) {
+      if (getToolChain().GetCXXStdlibType(Args) == ToolChain::CST_Libcxx)
+        CmdArgs.push_back("-fobjc-arc-cxxlib=libc++");
+      else
+        CmdArgs.push_back("-fobjc-arc-cxxlib=libstdc++");
+    }
+
     // Allow the user to enable full exceptions code emission.
     // We define off for Objective-CC, on for Objective-C++.
     if (Args.hasFlag(options::OPT_fobjc_arc_exceptions,
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/tools/clang/lib/Frontend/CompilerInvocation.cpp
--- a/head/contrib/llvm/tools/clang/lib/Frontend/CompilerInvocation.cpp	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/tools/clang/lib/Frontend/CompilerInvocation.cpp	Thu Dec 15 12:59:38 2011 +0200
@@ -569,10 +569,18 @@
         break;
       }
     } else {
-      if (E.Group != frontend::Angled && E.Group != frontend::System)
-        llvm::report_fatal_error("Invalid option set!");
-      Res.push_back(E.Group == frontend::Angled ? "-iwithprefixbefore" :
-                    "-iwithprefix");
+      if (E.IsInternal) {
+        assert(E.Group == frontend::System && "Unexpected header search group");
+        if (E.ImplicitExternC)
+          Res.push_back("-internal-externc-isystem");
+        else
+          Res.push_back("-internal-isystem");
+      } else {
+        if (E.Group != frontend::Angled && E.Group != frontend::System)
+          llvm::report_fatal_error("Invalid option set!");
+        Res.push_back(E.Group == frontend::Angled ? "-iwithprefixbefore" :
+                      "-iwithprefix");
+      }
     }
     Res.push_back(E.Path);
   }
@@ -1464,6 +1472,15 @@
        ie = Args.filtered_end(); it != ie; ++it)
     Opts.AddPath((*it)->getValue(Args), frontend::ObjCXXSystem, true, false,
                  true);
+
+  // Add the internal paths from a driver that detects standard include paths.
+  for (arg_iterator I = Args.filtered_begin(OPT_internal_isystem,
+                                            OPT_internal_externc_isystem),
+                    E = Args.filtered_end();
+       I != E; ++I)
+    Opts.AddPath((*I)->getValue(Args), frontend::System,
+                 false, false, /*IgnoreSysRoot=*/true, /*IsInternal=*/true,
+                 (*I)->getOption().matches(OPT_internal_externc_isystem));
 }
 
 void CompilerInvocation::setLangDefaults(LangOptions &Opts, InputKind IK,
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/llvm/tools/clang/lib/Frontend/InitHeaderSearch.cpp
--- a/head/contrib/llvm/tools/clang/lib/Frontend/InitHeaderSearch.cpp	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/llvm/tools/clang/lib/Frontend/InitHeaderSearch.cpp	Thu Dec 15 12:59:38 2011 +0200
@@ -28,12 +28,9 @@
 #include "llvm/ADT/Triple.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/Support/raw_ostream.h"
+#include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/Path.h"
 #include "llvm/Config/config.h"
-#ifdef _MSC_VER
-  #define WIN32_LEAN_AND_MEAN 1
-  #include <windows.h>
-#endif
 #ifndef CLANG_PREFIX
 #define CLANG_PREFIX
 #endif
@@ -211,219 +208,6 @@
           CXXSystem, true, false, false);
 }
 
-  // FIXME: This probably should goto to some platform utils place.
-#ifdef _MSC_VER
-
-  // Read registry string.
-  // This also supports a means to look for high-versioned keys by use
-  // of a $VERSION placeholder in the key path.
-  // $VERSION in the key path is a placeholder for the version number,
-  // causing the highest value path to be searched for and used.
-  // I.e. "HKEY_LOCAL_MACHINE\\SOFTWARE\\Microsoft\\VisualStudio\\$VERSION".
-  // There can be additional characters in the component.  Only the numberic
-  // characters are compared.
-static bool getSystemRegistryString(const char *keyPath, const char *valueName,
-                                    char *value, size_t maxLength) {
-  HKEY hRootKey = NULL;
-  HKEY hKey = NULL;
-  const char* subKey = NULL;
-  DWORD valueType;
-  DWORD valueSize = maxLength - 1;
-  long lResult;
-  bool returnValue = false;
-  
-  if (strncmp(keyPath, "HKEY_CLASSES_ROOT\\", 18) == 0) {
-    hRootKey = HKEY_CLASSES_ROOT;
-    subKey = keyPath + 18;
-  } else if (strncmp(keyPath, "HKEY_USERS\\", 11) == 0) {
-    hRootKey = HKEY_USERS;
-    subKey = keyPath + 11;
-  } else if (strncmp(keyPath, "HKEY_LOCAL_MACHINE\\", 19) == 0) {
-    hRootKey = HKEY_LOCAL_MACHINE;
-    subKey = keyPath + 19;
-  } else if (strncmp(keyPath, "HKEY_CURRENT_USER\\", 18) == 0) {
-    hRootKey = HKEY_CURRENT_USER;
-    subKey = keyPath + 18;
-  }
-  else
-    return false;
-  
-  const char *placeHolder = strstr(subKey, "$VERSION");
-  char bestName[256];
-  bestName[0] = '\0';
-  // If we have a $VERSION placeholder, do the highest-version search.
-  if (placeHolder) {
-    const char *keyEnd = placeHolder - 1;
-    const char *nextKey = placeHolder;
-    // Find end of previous key.
-    while ((keyEnd > subKey) && (*keyEnd != '\\'))
-      keyEnd--;
-    // Find end of key containing $VERSION.
-    while (*nextKey && (*nextKey != '\\'))
-      nextKey++;
-    size_t partialKeyLength = keyEnd - subKey;
-    char partialKey[256];
-    if (partialKeyLength > sizeof(partialKey))
-      partialKeyLength = sizeof(partialKey);
-    strncpy(partialKey, subKey, partialKeyLength);
-    partialKey[partialKeyLength] = '\0';
-    HKEY hTopKey = NULL;
-    lResult = RegOpenKeyEx(hRootKey, partialKey, 0, KEY_READ, &hTopKey);
-    if (lResult == ERROR_SUCCESS) {
-      char keyName[256];
-      int bestIndex = -1;
-      double bestValue = 0.0;
-      DWORD index, size = sizeof(keyName) - 1;
-      for (index = 0; RegEnumKeyEx(hTopKey, index, keyName, &size, NULL,
-          NULL, NULL, NULL) == ERROR_SUCCESS; index++) {
-        const char *sp = keyName;
-        while (*sp && !isdigit(*sp))
-          sp++;
-        if (!*sp)
-          continue;
-        const char *ep = sp + 1;
-        while (*ep && (isdigit(*ep) || (*ep == '.')))
-          ep++;
-        char numBuf[32];
-        strncpy(numBuf, sp, sizeof(numBuf) - 1);
-        numBuf[sizeof(numBuf) - 1] = '\0';
-        double value = strtod(numBuf, NULL);
-        if (value > bestValue) {
-          bestIndex = (int)index;
-          bestValue = value;
-          strcpy(bestName, keyName);
-        }
-        size = sizeof(keyName) - 1;
-      }
-      // If we found the highest versioned key, open the key and get the value.
-      if (bestIndex != -1) {
-        // Append rest of key.
-        strncat(bestName, nextKey, sizeof(bestName) - 1);
-        bestName[sizeof(bestName) - 1] = '\0';
-        // Open the chosen key path remainder.
-        lResult = RegOpenKeyEx(hTopKey, bestName, 0, KEY_READ, &hKey);
-        if (lResult == ERROR_SUCCESS) {
-          lResult = RegQueryValueEx(hKey, valueName, NULL, &valueType,
-            (LPBYTE)value, &valueSize);
-          if (lResult == ERROR_SUCCESS)
-            returnValue = true;
-          RegCloseKey(hKey);
-        }
-      }
-      RegCloseKey(hTopKey);
-    }
-  }
-  else {
-    lResult = RegOpenKeyEx(hRootKey, subKey, 0, KEY_READ, &hKey);
-    if (lResult == ERROR_SUCCESS) {
-      lResult = RegQueryValueEx(hKey, valueName, NULL, &valueType,
-        (LPBYTE)value, &valueSize);
-      if (lResult == ERROR_SUCCESS)
-        returnValue = true;
-      RegCloseKey(hKey);
-    }
-  }
-  return returnValue;
-}
-#else // _MSC_VER
-  // Read registry string.
-static bool getSystemRegistryString(const char*, const char*, char*, size_t) {
-  return(false);
-}
-#endif // _MSC_VER
-
-  // Get Visual Studio installation directory.
-static bool getVisualStudioDir(std::string &path) {
-  // First check the environment variables that vsvars32.bat sets.
-  const char* vcinstalldir = getenv("VCINSTALLDIR");
-  if (vcinstalldir) {
-    char *p = const_cast<char *>(strstr(vcinstalldir, "\\VC"));
-    if (p)
-      *p = '\0';
-    path = vcinstalldir;
-    return true;
-  }
-
-  char vsIDEInstallDir[256];
-  char vsExpressIDEInstallDir[256];
-  // Then try the windows registry.
-  bool hasVCDir = getSystemRegistryString(
-    "HKEY_LOCAL_MACHINE\\SOFTWARE\\Microsoft\\VisualStudio\\$VERSION",
-    "InstallDir", vsIDEInstallDir, sizeof(vsIDEInstallDir) - 1);
-  bool hasVCExpressDir = getSystemRegistryString(
-    "HKEY_LOCAL_MACHINE\\SOFTWARE\\Microsoft\\VCExpress\\$VERSION",
-    "InstallDir", vsExpressIDEInstallDir, sizeof(vsExpressIDEInstallDir) - 1);
-    // If we have both vc80 and vc90, pick version we were compiled with.
-  if (hasVCDir && vsIDEInstallDir[0]) {
-    char *p = (char*)strstr(vsIDEInstallDir, "\\Common7\\IDE");
-    if (p)
-      *p = '\0';
-    path = vsIDEInstallDir;
-    return true;
-  }
-  
-  if (hasVCExpressDir && vsExpressIDEInstallDir[0]) {
-    char *p = (char*)strstr(vsExpressIDEInstallDir, "\\Common7\\IDE");
-    if (p)
-      *p = '\0';
-    path = vsExpressIDEInstallDir;
-    return true;
-  }
-
-  // Try the environment.
-  const char *vs100comntools = getenv("VS100COMNTOOLS");
-  const char *vs90comntools = getenv("VS90COMNTOOLS");
-  const char *vs80comntools = getenv("VS80COMNTOOLS");
-  const char *vscomntools = NULL;
-
-  // Try to find the version that we were compiled with
-  if(false) {}
-  #if (_MSC_VER >= 1600)  // VC100
-  else if(vs100comntools) {
-    vscomntools = vs100comntools;
-  }
-  #elif (_MSC_VER == 1500) // VC80
-  else if(vs90comntools) {
-    vscomntools = vs90comntools;
-  }
-  #elif (_MSC_VER == 1400) // VC80
-  else if(vs80comntools) {
-    vscomntools = vs80comntools;
-  }
-  #endif
-  // Otherwise find any version we can
-  else if (vs100comntools)
-    vscomntools = vs100comntools;
-  else if (vs90comntools)
-    vscomntools = vs90comntools;
-  else if (vs80comntools)
-    vscomntools = vs80comntools;
-
-  if (vscomntools && *vscomntools) {
-    const char *p = strstr(vscomntools, "\\Common7\\Tools");
-    path = p ? std::string(vscomntools, p) : vscomntools;
-    return true;
-  }
-  return false;
-}
-
-  // Get Windows SDK installation directory.
-static bool getWindowsSDKDir(std::string &path) {
-  char windowsSDKInstallDir[256];
-  // Try the Windows registry.
-  bool hasSDKDir = getSystemRegistryString(
-   "HKEY_LOCAL_MACHINE\\SOFTWARE\\Microsoft\\Microsoft SDKs\\Windows\\$VERSION",
-                                           "InstallationFolder",
-                                           windowsSDKInstallDir,
-                                           sizeof(windowsSDKInstallDir) - 1);
-    // If we have both vc80 and vc90, pick version we were compiled with.
-  if (hasSDKDir && windowsSDKInstallDir[0]) {
-    path = windowsSDKInstallDir;
-    return(true);
-  }
-  return(false);
-}
-
 void InitHeaderSearch::AddDefaultCIncludePaths(const llvm::Triple &triple,
                                             const HeaderSearchOptions &HSOpts) {
   llvm::Triple::OSType os = triple.getOS();
@@ -468,33 +252,10 @@
   }
 
   switch (os) {
-  case llvm::Triple::Win32: {
-    std::string VSDir;
-    std::string WindowsSDKDir;
-    if (getVisualStudioDir(VSDir)) {
-      AddPath(VSDir + "\\VC\\include", System, false, false, false);
-      if (getWindowsSDKDir(WindowsSDKDir))
-        AddPath(WindowsSDKDir + "\\include", System, false, false, false);
-      else
-        AddPath(VSDir + "\\VC\\PlatformSDK\\Include",
-                System, false, false, false);
-    } else {
-      // Default install paths.
-      AddPath("C:/Program Files/Microsoft Visual Studio 10.0/VC/include",
-              System, false, false, false);
-      AddPath("C:/Program Files/Microsoft Visual Studio 9.0/VC/include",
-              System, false, false, false);
-      AddPath(
-        "C:/Program Files/Microsoft Visual Studio 9.0/VC/PlatformSDK/Include",
-        System, false, false, false);
-      AddPath("C:/Program Files/Microsoft Visual Studio 8/VC/include",
-              System, false, false, false);
-      AddPath(
-        "C:/Program Files/Microsoft Visual Studio 8/VC/PlatformSDK/Include",
-        System, false, false, false);
-    }
-    break;
-  }
+  case llvm::Triple::Linux:
+  case llvm::Triple::Win32:
+    llvm_unreachable("Include management is handled in the driver.");
+
   case llvm::Triple::Haiku:
     AddPath("/boot/common/include", System, true, false, false);
     AddPath("/boot/develop/headers/os", System, true, false, false);
@@ -564,19 +325,6 @@
       System, false, false, false);
     break;
       
-  case llvm::Triple::Linux:
-    // Generic Debian multiarch support:
-    if (triple.getArch() == llvm::Triple::x86_64) {
-      AddPath("/usr/include/x86_64-linux-gnu", System, false, false, false);
-      AddPath("/usr/include/i686-linux-gnu/64", System, false, false, false);
-      AddPath("/usr/include/i486-linux-gnu/64", System, false, false, false);
-    } else if (triple.getArch() == llvm::Triple::x86) {
-      AddPath("/usr/include/x86_64-linux-gnu/32", System, false, false, false);
-      AddPath("/usr/include/i686-linux-gnu", System, false, false, false);
-      AddPath("/usr/include/i486-linux-gnu", System, false, false, false);
-    } else if (triple.getArch() == llvm::Triple::arm) {
-      AddPath("/usr/include/arm-linux-gnueabi", System, false, false, false);
-    }
   default:
     break;
   }
@@ -637,6 +385,10 @@
   }
 
   switch (os) {
+  case llvm::Triple::Linux:
+  case llvm::Triple::Win32:
+    llvm_unreachable("Include management is handled in the driver.");
+
   case llvm::Triple::Cygwin:
     // Cygwin-1.7
     AddMinGWCPlusPlusIncludePaths("/usr/lib/gcc", "i686-pc-cygwin", "4.3.4");
@@ -664,257 +416,6 @@
   case llvm::Triple::DragonFly:
     AddPath("/usr/include/c++/4.1", CXXSystem, true, false, false);
     break;
-  case llvm::Triple::Linux:
-    //===------------------------------------------------------------------===//
-    // Debian based distros.
-    // Note: these distros symlink /usr/include/c++/X.Y.Z -> X.Y
-    //===------------------------------------------------------------------===//
-
-    // Ubuntu 11.11 "Oneiric Ocelot" -- gcc-4.6.0
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.6",
-                                "x86_64-linux-gnu", "32", "", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.6",
-                                "i686-linux-gnu", "", "64", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.6",
-                                "i486-linux-gnu", "", "64", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.6",
-                                "arm-linux-gnueabi", "", "", triple);
-
-    // Ubuntu 11.04 "Natty Narwhal" -- gcc-4.5.2
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.5",
-                                "x86_64-linux-gnu", "32", "", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.5",
-                                "i686-linux-gnu", "", "64", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.5",
-                                "i486-linux-gnu", "", "64", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.5",
-                                "arm-linux-gnueabi", "", "", triple);
-
-    // Ubuntu 10.10 "Maverick Meerkat" -- gcc-4.4.5
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.4",
-                                "i686-linux-gnu", "", "64", triple);
-    // The rest of 10.10 is the same as previous versions.
-
-    // Ubuntu 10.04 LTS "Lucid Lynx" -- gcc-4.4.3
-    // Ubuntu 9.10 "Karmic Koala"    -- gcc-4.4.1
-    // Debian 6.0 "squeeze"          -- gcc-4.4.2
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.4",
-                                "x86_64-linux-gnu", "32", "", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.4",
-                                "i486-linux-gnu", "", "64", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.4",
-                                "arm-linux-gnueabi", "", "", triple);
-    // Ubuntu 9.04 "Jaunty Jackalope" -- gcc-4.3.3
-    // Ubuntu 8.10 "Intrepid Ibex"    -- gcc-4.3.2
-    // Debian 5.0 "lenny"             -- gcc-4.3.2
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.3",
-                                "x86_64-linux-gnu", "32", "", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.3",
-                                "i486-linux-gnu", "", "64", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.3",
-                                "arm-linux-gnueabi", "", "", triple);
-    // Ubuntu 8.04.4 LTS "Hardy Heron"     -- gcc-4.2.4
-    // Ubuntu 8.04.[0-3] LTS "Hardy Heron" -- gcc-4.2.3
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.2",
-                                "x86_64-linux-gnu", "32", "", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.2",
-                                "i486-linux-gnu", "", "64", triple);
-    // Ubuntu 7.10 "Gutsy Gibbon" -- gcc-4.1.3
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.1",
-                                "x86_64-linux-gnu", "32", "", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.1",
-                                "i486-linux-gnu", "", "64", triple);
-
-    //===------------------------------------------------------------------===//
-    // Redhat based distros.
-    //===------------------------------------------------------------------===//
-    // Fedora 15 (GCC 4.6.1)
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.6.1",
-                                "x86_64-redhat-linux", "32", "", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.6.1",
-                                "i686-redhat-linux", "", "", triple);
-    // Fedora 15 (GCC 4.6.0)
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.6.0",
-                                "x86_64-redhat-linux", "32", "", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.6.0",
-                                "i686-redhat-linux", "", "", triple);
-    // Fedora 14
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.5.1",
-                                "x86_64-redhat-linux", "32", "", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.5.1",
-                                "i686-redhat-linux", "", "", triple);
-    // RHEL5(gcc44)
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.4.4",
-                                "x86_64-redhat-linux6E", "32", "", triple);
-    // Fedora 13
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.4.4",
-                                "x86_64-redhat-linux", "32", "", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.4.4",
-                                "i686-redhat-linux","", "", triple);
-    // Fedora 12
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.4.3",
-                                "x86_64-redhat-linux", "32", "", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.4.3",
-                                "i686-redhat-linux","", "", triple);
-    // Fedora 12 (pre-FEB-2010)
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.4.2",
-                                "x86_64-redhat-linux", "32", "", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.4.2",
-                                "i686-redhat-linux","", "", triple);
-    // Fedora 11
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.4.1",
-                                "x86_64-redhat-linux", "32", "", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.4.1",
-                                "i586-redhat-linux","", "", triple);
-    // Fedora 10
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.3.2",
-                                "x86_64-redhat-linux", "32", "", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.3.2",
-                                "i386-redhat-linux","", "", triple);
-    // Fedora 9
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.3.0",
-                                "x86_64-redhat-linux", "32", "", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.3.0",
-                                "i386-redhat-linux", "", "", triple);
-    // Fedora 8
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.1.2",
-                                "x86_64-redhat-linux", "", "", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.1.2",
-                                "i386-redhat-linux", "", "", triple);
-      
-    // RHEL 5
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.1.1",
-                                "x86_64-redhat-linux", "32", "", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.1.1",
-                                "i386-redhat-linux", "", "", triple);
-
-
-    //===------------------------------------------------------------------===//
-
-    // Exherbo (2010-01-25)
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.4.3",
-                                "x86_64-pc-linux-gnu", "32", "", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.4.3",
-                                "i686-pc-linux-gnu", "", "", triple);
-
-    // openSUSE 11.1 32 bit
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.3",
-                                "i586-suse-linux", "", "", triple);
-    // openSUSE 11.1 64 bit
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.3",
-                                "x86_64-suse-linux", "32", "", triple);
-    // openSUSE 11.2
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.4",
-                                "i586-suse-linux", "", "", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.4",
-                                "x86_64-suse-linux", "", "", triple);
-
-    // openSUSE 11.4
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.5",
-                                "i586-suse-linux", "", "", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.5",
-                                "x86_64-suse-linux", "", "", triple);
-
-    // openSUSE 12.1
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.6",
-                                "i586-suse-linux", "", "", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.6",
-                                "x86_64-suse-linux", "", "", triple);
-    // Arch Linux 2008-06-24
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.3.1",
-                                "i686-pc-linux-gnu", "", "", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.3.1",
-                                "x86_64-unknown-linux-gnu", "", "", triple);
-
-    // Arch Linux gcc 4.6
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.6.1",
-                                "i686-pc-linux-gnu", "", "", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.6.1",
-                                "x86_64-unknown-linux-gnu", "", "", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.6.0",
-                                "i686-pc-linux-gnu", "", "", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.6.0",
-                                "x86_64-unknown-linux-gnu", "", "", triple);
-
-    // Slackware gcc 4.5.2 (13.37)
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.5.2",
-                                "i486-slackware-linux", "", "", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.5.2",
-                                "x86_64-slackware-linux", "", "", triple);
-    // Slackware gcc 4.5.3 (-current)
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.5.3",
-                                "i486-slackware-linux", "", "", triple);
-    AddGnuCPlusPlusIncludePaths("/usr/include/c++/4.5.3",
-                                "x86_64-slackware-linux", "", "", triple);
-
-    // Gentoo x86 gcc 4.5.2
-    AddGnuCPlusPlusIncludePaths(
-      "/usr/lib/gcc/i686-pc-linux-gnu/4.5.2/include/g++-v4",
-      "i686-pc-linux-gnu", "", "", triple);
-    // Gentoo x86 gcc 4.4.5
-    AddGnuCPlusPlusIncludePaths(
-      "/usr/lib/gcc/i686-pc-linux-gnu/4.4.5/include/g++-v4",
-      "i686-pc-linux-gnu", "", "", triple);
-    // Gentoo x86 gcc 4.4.4
-    AddGnuCPlusPlusIncludePaths(
-      "/usr/lib/gcc/i686-pc-linux-gnu/4.4.4/include/g++-v4",
-      "i686-pc-linux-gnu", "", "", triple);
-   // Gentoo x86 2010.0 stable
-    AddGnuCPlusPlusIncludePaths(
-      "/usr/lib/gcc/i686-pc-linux-gnu/4.4.3/include/g++-v4",
-      "i686-pc-linux-gnu", "", "", triple);
-    // Gentoo x86 2009.1 stable
-    AddGnuCPlusPlusIncludePaths(
-      "/usr/lib/gcc/i686-pc-linux-gnu/4.3.4/include/g++-v4",
-      "i686-pc-linux-gnu", "", "", triple);
-    // Gentoo x86 2009.0 stable
-    AddGnuCPlusPlusIncludePaths(
-      "/usr/lib/gcc/i686-pc-linux-gnu/4.3.2/include/g++-v4",
-      "i686-pc-linux-gnu", "", "", triple);
-    // Gentoo x86 2008.0 stable
-    AddGnuCPlusPlusIncludePaths(
-      "/usr/lib/gcc/i686-pc-linux-gnu/4.1.2/include/g++-v4",
-      "i686-pc-linux-gnu", "", "", triple);
-    // Gentoo x86 llvm-gcc trunk
-    AddGnuCPlusPlusIncludePaths(
-        "/usr/lib/llvm-gcc-4.2-9999/include/c++/4.2.1",
-        "i686-pc-linux-gnu", "", "", triple);
-
-    // Gentoo amd64 gcc 4.5.2
-    AddGnuCPlusPlusIncludePaths(
-        "/usr/lib/gcc/x86_64-pc-linux-gnu/4.5.2/include/g++-v4",
-        "x86_64-pc-linux-gnu", "32", "", triple);
-    // Gentoo amd64 gcc 4.4.5
-    AddGnuCPlusPlusIncludePaths(
-        "/usr/lib/gcc/x86_64-pc-linux-gnu/4.4.5/include/g++-v4",
-        "x86_64-pc-linux-gnu", "32", "", triple);
-    // Gentoo amd64 gcc 4.4.4
-    AddGnuCPlusPlusIncludePaths(
-        "/usr/lib/gcc/x86_64-pc-linux-gnu/4.4.4/include/g++-v4",
-        "x86_64-pc-linux-gnu", "32", "", triple);
-    // Gentoo amd64 gcc 4.4.3
-    AddGnuCPlusPlusIncludePaths(
-        "/usr/lib/gcc/x86_64-pc-linux-gnu/4.4.3/include/g++-v4",
-        "x86_64-pc-linux-gnu", "32", "", triple);
-    // Gentoo amd64 gcc 4.3.4
-    AddGnuCPlusPlusIncludePaths(
-        "/usr/lib/gcc/x86_64-pc-linux-gnu/4.3.4/include/g++-v4",
-        "x86_64-pc-linux-gnu", "", "", triple);
-    // Gentoo amd64 gcc 4.3.2
-    AddGnuCPlusPlusIncludePaths(
-        "/usr/lib/gcc/x86_64-pc-linux-gnu/4.3.2/include/g++-v4",
-        "x86_64-pc-linux-gnu", "", "", triple);
-    // Gentoo amd64 stable
-    AddGnuCPlusPlusIncludePaths(
-        "/usr/lib/gcc/x86_64-pc-linux-gnu/4.1.2/include/g++-v4",
-        "x86_64-pc-linux-gnu", "", "", triple);
-
-    // Gentoo amd64 llvm-gcc trunk
-    AddGnuCPlusPlusIncludePaths(
-        "/usr/lib/llvm-gcc-4.2-9999/include/c++/4.2.1",
-        "x86_64-pc-linux-gnu", "", "", triple);
-
-    break;
   case llvm::Triple::FreeBSD:
     // FreeBSD 8.0
     // FreeBSD 7.3
@@ -953,6 +454,19 @@
 void InitHeaderSearch::AddDefaultIncludePaths(const LangOptions &Lang,
                                               const llvm::Triple &triple,
                                             const HeaderSearchOptions &HSOpts) {
+  // NB: This code path is going away. All of the logic is moving into the
+  // driver which has the information necessary to do target-specific
+  // selections of default include paths. Each target which moves there will be
+  // exempted from this logic here until we can delete the entire pile of code.
+  switch (triple.getOS()) {
+  default:
+    break; // Everything else continues to use this routine's logic.
+
+  case llvm::Triple::Linux:
+  case llvm::Triple::Win32:
+    return;
+  }
+
   if (Lang.CPlusPlus && HSOpts.UseStandardCXXIncludes &&
       HSOpts.UseStandardSystemIncludes) {
     if (HSOpts.UseLibcxx) {
@@ -1155,8 +669,8 @@
   // Add the user defined entries.
   for (unsigned i = 0, e = HSOpts.UserEntries.size(); i != e; ++i) {
     const HeaderSearchOptions::Entry &E = HSOpts.UserEntries[i];
-    Init.AddPath(E.Path, E.Group, false, E.IsUserSupplied, E.IsFramework,
-                 E.IgnoreSysRoot);
+    Init.AddPath(E.Path, E.Group, !E.ImplicitExternC, E.IsUserSupplied,
+                 E.IsFramework, E.IgnoreSysRoot);
   }
 
   Init.AddDefaultIncludePaths(Lang, Triple, HSOpts);
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/openpam/lib/openpam_configure.c
--- a/head/contrib/openpam/lib/openpam_configure.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/openpam/lib/openpam_configure.c	Thu Dec 15 12:59:38 2011 +0200
@@ -285,6 +285,13 @@
 	size_t len;
 	int r;
 
+	/* don't allow to escape from policy_path */
+	if (strchr(service, '/')) {
+		openpam_log(PAM_LOG_ERROR, "invalid service name: %s",
+		    service);
+		return (-PAM_SYSTEM_ERR);
+	}
+
 	for (path = openpam_policy_path; *path != NULL; ++path) {
 		len = strlen(*path);
 		if ((*path)[len - 1] == '/') {
diff -r 2230520c0499 -r 820af1e39cd6 head/contrib/tzcode/zic/zdump.c
--- a/head/contrib/tzcode/zic/zdump.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/contrib/tzcode/zic/zdump.c	Thu Dec 15 12:59:38 2011 +0200
@@ -5,7 +5,7 @@
 
 #ifndef lint
 static const char rcsid[] =
-  "$FreeBSD$";
+  "$FreeBSD: head/contrib/tzcode/zic/zdump.c 228342 2011-12-08 02:40:46Z eadler $";
 static char	elsieid[] = "@(#)zdump.c	8.10";
 #endif /* not lint */
 
@@ -260,6 +260,7 @@
 	register struct tm *	tmp;
 	register struct tm *	newtmp;
 
+	progname=argv[0];
 	INITIALIZE(cutlotime);
 	INITIALIZE(cuthitime);
 #if HAVE_GETTEXT
diff -r 2230520c0499 -r 820af1e39cd6 head/etc/network.subr
--- a/head/etc/network.subr	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/etc/network.subr	Thu Dec 15 12:59:38 2011 +0200
@@ -22,7 +22,7 @@
 # OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 # SUCH DAMAGE.
 #
-# $FreeBSD: head/etc/network.subr 226652 2011-10-23 07:37:36Z hrs $
+# $FreeBSD: head/etc/network.subr 228472 2011-12-13 14:36:04Z glebius $
 #
 
 #
@@ -716,9 +716,16 @@
 		inet\ *)
 			ifconfig $1 ${ifconfig_args} alias && _ret=0
 			;;
+		inet6\ *)
+			;;
 		"")
 			break
 			;;
+		*)
+			warn "\$ifconfig_$1_alias${alias} needs " \
+			    "\"inet\" keyword for an IPv4 address."
+			ifconfig $1 ${ifconfig_args} alias && _ret=0
+			;;
 		esac
 		alias=$((${alias} + 1))
 	done
diff -r 2230520c0499 -r 820af1e39cd6 head/gnu/usr.bin/groff/tmac/mdoc.local
--- a/head/gnu/usr.bin/groff/tmac/mdoc.local	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/gnu/usr.bin/groff/tmac/mdoc.local	Thu Dec 15 12:59:38 2011 +0200
@@ -22,7 +22,7 @@
 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 .\" SUCH DAMAGE.
 .\"
-.\" $FreeBSD: head/gnu/usr.bin/groff/tmac/mdoc.local 225757 2011-09-26 02:27:04Z kensmith $
+.\" $FreeBSD: head/gnu/usr.bin/groff/tmac/mdoc.local 228351 2011-12-08 13:54:06Z ru $
 .\"
 .\"     %beginstrip%
 .
@@ -34,41 +34,14 @@
 .\" FreeBSD .Lb values
 .ds doc-str-Lb-libarchive  Streaming Archive Library (libarchive, \-larchive)
 .ds doc-str-Lb-libbluetooth Bluetooth User Library (libbluetooth, \-lbluetooth)
-.ds doc-str-Lb-libc_r      Reentrant C\~Library (libc_r, \-lc_r)
-.ds doc-str-Lb-libcalendar Calendar Arithmetic Library (libcalendar, \-lcalendar)
-.ds doc-str-Lb-libcam      Common Access Method User Library (libcam, \-lcam)
-.ds doc-str-Lb-libcipher   FreeSec Crypt Library (libcipher, \-lcipher)
-.ds doc-str-Lb-libdevinfo  Device and Resource Information Utility Library (libdevinfo, \-ldevinfo)
-.ds doc-str-Lb-libdevstat  Device Statistics Library (libdevstat, \-ldevstat)
-.ds doc-str-Lb-libdisk     Interface to Slice and Partition Labels Library (libdisk, \-ldisk)
 .ds doc-str-Lb-libedit     Line Editor and History Library (libedit, \-ledit)
 .ds doc-str-Lb-libefi      EFI Runtime Services Library (libefi, \-lefi)
 .ds doc-str-Lb-libelf      ELF Parsing Library (libelf, \-lelf)
 .ds doc-str-Lb-libfetch    File Transfer Library (libfetch, \-lfetch)
-.ds doc-str-Lb-libgeom     Userland API Library for kernel GEOM subsystem (libgeom, \-lgeom)
-.ds doc-str-Lb-libgpib     General-Purpose Instrument Bus (GPIB) library (libgpib, \-lgpib)
-.ds doc-str-Lb-libipx      IPX Address Conversion Support Library (libipx, \-lipx)
-.ds doc-str-Lb-libjail     Jail Library (libjail, \-ljail)
-.ds doc-str-Lb-libkiconv   Kernel side iconv library (libkiconv, \-lkiconv)
-.ds doc-str-Lb-libkse      N:M Threading Library (libkse, \-lkse)
-.ds doc-str-Lb-libmd       Message Digest (MD4, MD5, etc.) Support Library (libmd, \-lmd)
-.ds doc-str-Lb-libmemstat  Kernel Memory Allocator Statistics Library (libmemstat, \-lmemstat)
-.ds doc-str-Lb-libnetgraph Netgraph User Library (libnetgraph, \-lnetgraph)
 .ds doc-str-Lb-libpmc      Performance Monitoring Counters Interface Library (libpmc, \-lpmc)
 .ds doc-str-Lb-libproc     Processor Monitoring and Analysis Library (libproc, \-lproc)
 .ds doc-str-Lb-libprocstat Process and Files Information Retrieval (libprocstat, \-lprocstat)
-.ds doc-str-Lb-librpcsec_gss RPC GSS-API Authentication Library (librpcsec_gss, \-lrpcsec_gss)
-.ds doc-str-Lb-librpcsvc   RPC Service Library (librpcsvc, \-lrpcsvc)
 .ds doc-str-Lb-librtld_db  Run-time Linker Debugging Library (librtld_db, \-lrtld_db)
-.ds doc-str-Lb-libsdp      Bluetooth Service Discovery Protocol User Library (libsdp, \-lsdp)
-.ds doc-str-Lb-libthr      1:1 Threading Library (libthr, \-lthr)
-.ds doc-str-Lb-libufs      UFS File System Access Library (libufs, \-lufs)
-.ds doc-str-Lb-libugidfw   File System Firewall Interface Library (libugidfw, \-lugidfw)
-.ds doc-str-Lb-libulog     User Login Record Library (libulog, \-lulog)
-.ds doc-str-Lb-libvgl      Video Graphics Library (libvgl, \-lvgl)
-.
-.\" FreeBSD architectures not found in doc-common
-.ds doc-volume-as-arm      arm
 .
 .\" Default .Os value
 .ds doc-default-operating-system FreeBSD\~10.0
@@ -76,7 +49,6 @@
 .\" FreeBSD releases not found in doc-common
 .ds doc-operating-system-FreeBSD-7.4    7.4
 .ds doc-operating-system-FreeBSD-8.3    8.3
-.ds doc-operating-system-FreeBSD-9.0    9.0
 .ds doc-operating-system-FreeBSD-10.0   10.0
 .
 .\" Definitions not (yet) in doc-syms
diff -r 2230520c0499 -r 820af1e39cd6 head/include/netdb.h
--- a/head/include/netdb.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/include/netdb.h	Thu Dec 15 12:59:38 2011 +0200
@@ -51,7 +51,7 @@
 /*
  *      @(#)netdb.h	8.1 (Berkeley) 6/2/93
  *      From: Id: netdb.h,v 8.9 1996/11/19 08:39:29 vixie Exp $
- * $FreeBSD$
+ * $FreeBSD: head/include/netdb.h 228468 2011-12-13 13:32:56Z ed $
  */
 
 #ifndef _NETDB_H_
@@ -276,7 +276,7 @@
 int		getservent_r(struct servent *, char *, size_t,
     struct servent **);
 void		herror(const char *);
-__const char	*hstrerror(int);
+const char	*hstrerror(int);
 int		innetgr(const char *, const char *, const char *, const char *);
 void		setnetgrent(const char *);
 #endif
diff -r 2230520c0499 -r 820af1e39cd6 head/include/regex.h
--- a/head/include/regex.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/include/regex.h	Thu Dec 15 12:59:38 2011 +0200
@@ -31,7 +31,7 @@
  * SUCH DAMAGE.
  *
  *	@(#)regex.h	8.2 (Berkeley) 1/3/94
- * $FreeBSD$
+ * $FreeBSD: head/include/regex.h 228468 2011-12-13 13:32:56Z ed $
  */
 
 #ifndef _REGEX_H_
@@ -51,7 +51,7 @@
 typedef struct {
 	int re_magic;
 	size_t re_nsub;		/* number of parenthesized subexpressions */
-	__const char *re_endp;	/* end pointer for REG_PEND */
+	const char *re_endp;	/* end pointer for REG_PEND */
 	struct re_guts *re_g;	/* none of your business :-) */
 } regex_t;
 
diff -r 2230520c0499 -r 820af1e39cd6 head/include/signal.h
--- a/head/include/signal.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/include/signal.h	Thu Dec 15 12:59:38 2011 +0200
@@ -27,7 +27,7 @@
  * SUCH DAMAGE.
  *
  *	@(#)signal.h	8.3 (Berkeley) 3/30/94
- * $FreeBSD$
+ * $FreeBSD: head/include/signal.h 228468 2011-12-13 13:32:56Z ed $
  */
 
 #ifndef _SIGNAL_H_
@@ -42,9 +42,9 @@
  * XXX should enlarge these, if only to give empty names instead of bounds
  * errors for large signal numbers.
  */
-extern __const char *__const sys_signame[NSIG];
-extern __const char *__const sys_siglist[NSIG];
-extern __const int sys_nsig;
+extern const char * const sys_signame[NSIG];
+extern const char * const sys_siglist[NSIG];
+extern const int sys_nsig;
 #endif
 
 #if __POSIX_VISIBLE >= 200112 || __XSI_VISIBLE
diff -r 2230520c0499 -r 820af1e39cd6 head/include/stdbool.h
--- a/head/include/stdbool.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/include/stdbool.h	Thu Dec 15 12:59:38 2011 +0200
@@ -23,12 +23,13 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- * $FreeBSD$
+ * $FreeBSD: head/include/stdbool.h 228444 2011-12-12 18:44:17Z mdf $
  */
 
 #ifndef _STDBOOL_H_
 #define	_STDBOOL_H_	
 
+#ifndef __bool_true_false_are_defined
 #define	__bool_true_false_are_defined	1
 
 #ifndef __cplusplus
@@ -42,5 +43,6 @@
 #endif
 
 #endif /* !__cplusplus */
+#endif /* __bool_true_false_are_defined */
 
 #endif /* !_STDBOOL_H_ */
diff -r 2230520c0499 -r 820af1e39cd6 head/include/stdio.h
--- a/head/include/stdio.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/include/stdio.h	Thu Dec 15 12:59:38 2011 +0200
@@ -30,7 +30,7 @@
  * SUCH DAMAGE.
  *
  *	@(#)stdio.h	8.5 (Berkeley) 4/29/95
- * $FreeBSD: head/include/stdio.h 227487 2011-11-13 16:18:48Z theraven $
+ * $FreeBSD: head/include/stdio.h 228468 2011-12-13 13:32:56Z ed $
  */
 
 #ifndef	_STDIO_H_
@@ -404,8 +404,8 @@
  * positive errno values.  Use strerror() or strerror_r() from <string.h>
  * instead.
  */
-extern __const int sys_nerr;
-extern __const char *__const sys_errlist[];
+extern const int sys_nerr;
+extern const char * const sys_errlist[];
 
 /*
  * Stdio function-access interface.
diff -r 2230520c0499 -r 820af1e39cd6 head/include/stdlib.h
--- a/head/include/stdlib.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/include/stdlib.h	Thu Dec 15 12:59:38 2011 +0200
@@ -27,7 +27,7 @@
  * SUCH DAMAGE.
  *
  *	@(#)stdlib.h	8.5 (Berkeley) 5/19/95
- * $FreeBSD: head/include/stdlib.h 227753 2011-11-20 14:45:42Z theraven $
+ * $FreeBSD: head/include/stdlib.h 228468 2011-12-13 13:32:56Z ed $
  */
 
 #ifndef _STDLIB_H_
@@ -76,7 +76,7 @@
 extern int ___mb_cur_max(void);
 #define	MB_CUR_MAX	(___mb_cur_max())
 
-void	 abort(void) __dead2;
+_Noreturn void	 abort(void);
 int	 abs(int) __pure2;
 int	 atexit(void (*)(void));
 double	 atof(const char *);
@@ -86,7 +86,7 @@
 	    size_t, int (*)(const void *, const void *));
 void	*calloc(size_t, size_t) __malloc_like;
 div_t	 div(int, int) __pure2;
-void	 exit(int) __dead2;
+_Noreturn void	 exit(int);
 void	 free(void *);
 char	*getenv(const char *);
 long	 labs(long) __pure2;
@@ -145,10 +145,18 @@
 	 strtoull(const char * __restrict, char ** __restrict, int);
 #endif /* __LONG_LONG_SUPPORTED */
 
-void	 _Exit(int) __dead2;
+_Noreturn void	 _Exit(int);
 #endif /* __ISO_C_VISIBLE >= 1999 */
 
 /*
+ * If we're in a mode greater than C99, expose C1x functions.
+ */
+#if __ISO_C_VISIBLE > 1999
+_Noreturn void quick_exit(int)
+int
+at_quick_exit(void (*func)(void));
+#endif /* __ISO_C_VISIBLE > 1999 */
+/*
  * Extensions made by POSIX relative to C.  We don't know yet which edition
  * of POSIX made these extensions, so assume they've always been there until
  * research can be done.
@@ -263,7 +271,7 @@
 char	*fdevname(int);
 char 	*fdevname_r(int, char *, int);
 int	 getloadavg(double [], int);
-__const char *
+const char *
 	 getprogname(void);
 
 int	 heapsort(void *, size_t, size_t, int (*)(const void *, const void *));
diff -r 2230520c0499 -r 820af1e39cd6 head/lib/clang/include/MipsGenCodeEmitter.inc
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/head/lib/clang/include/MipsGenCodeEmitter.inc	Thu Dec 15 12:59:38 2011 +0200
@@ -0,0 +1,2 @@
+/* $FreeBSD: head/lib/clang/include/MipsGenCodeEmitter.inc 228379 2011-12-09 22:23:45Z dim $ */
+#include "MipsGenCodeEmitter.inc.h"
diff -r 2230520c0499 -r 820af1e39cd6 head/lib/clang/include/clang/Basic/Version.inc
--- a/head/lib/clang/include/clang/Basic/Version.inc	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/lib/clang/include/clang/Basic/Version.inc	Thu Dec 15 12:59:38 2011 +0200
@@ -1,10 +1,10 @@
-/* $FreeBSD: head/lib/clang/include/clang/Basic/Version.inc 226633 2011-10-22 14:08:43Z dim $ */
+/* $FreeBSD: head/lib/clang/include/clang/Basic/Version.inc 228383 2011-12-10 01:01:44Z dim $ */
 
 #define	CLANG_VERSION		3.0
 #define	CLANG_VERSION_MAJOR	3
 #define	CLANG_VERSION_MINOR	0
 
 #define	CLANG_VENDOR		"FreeBSD "
-#define	CLANG_VENDOR_SUFFIX	" 20111021"
+#define	CLANG_VENDOR_SUFFIX	" 20111210"
 
-#define	SVN_REVISION		"142614"
+#define	SVN_REVISION		"145349"
diff -r 2230520c0499 -r 820af1e39cd6 head/lib/clang/libllvmmipscodegen/Makefile
--- a/head/lib/clang/libllvmmipscodegen/Makefile	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/lib/clang/libllvmmipscodegen/Makefile	Thu Dec 15 12:59:38 2011 +0200
@@ -1,4 +1,4 @@
-# $FreeBSD: head/lib/clang/libllvmmipscodegen/Makefile 226633 2011-10-22 14:08:43Z dim $
+# $FreeBSD: head/lib/clang/libllvmmipscodegen/Makefile 228379 2011-12-09 22:23:45Z dim $
 
 LIB=	llvmmipscodegen
 
@@ -24,6 +24,7 @@
 TGHDRS=	Intrinsics \
 	MipsGenAsmWriter \
 	MipsGenCallingConv \
+	MipsGenCodeEmitter \
 	MipsGenDAGISel \
 	MipsGenInstrInfo \
 	MipsGenRegisterInfo \
diff -r 2230520c0499 -r 820af1e39cd6 head/lib/libc/gen/getosreldate.c
--- a/head/lib/libc/gen/getosreldate.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/lib/libc/gen/getosreldate.c	Thu Dec 15 12:59:38 2011 +0200
@@ -31,14 +31,13 @@
 static char sccsid[] = "@(#)gethostid.c	8.1 (Berkeley) 6/2/93";
 #endif /* LIBC_SCCS and not lint */
 #include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: head/lib/libc/gen/getosreldate.c 228492 2011-12-14 08:35:08Z ru $");
 
-#include <sys/param.h>
+#include <sys/types.h>
 #include <sys/sysctl.h>
-#include <errno.h>
+
 #include <stdlib.h>
-
-#include <osreldate.h>
+#include <unistd.h>
 
 int
 getosreldate(void)
diff -r 2230520c0499 -r 820af1e39cd6 head/lib/libc/stdlib/Makefile.inc
--- a/head/lib/libc/stdlib/Makefile.inc	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/lib/libc/stdlib/Makefile.inc	Thu Dec 15 12:59:38 2011 +0200
@@ -1,5 +1,5 @@
 #	from @(#)Makefile.inc	8.3 (Berkeley) 2/4/95
-# $FreeBSD: head/lib/libc/stdlib/Makefile.inc 224201 2011-07-18 20:07:29Z dim $
+# $FreeBSD: head/lib/libc/stdlib/Makefile.inc 228322 2011-12-07 15:25:48Z theraven $
 
 # machine-independent stdlib sources
 .PATH: ${.CURDIR}/${LIBC_ARCH}/stdlib ${.CURDIR}/stdlib
@@ -8,8 +8,8 @@
 	bsearch.c div.c exit.c getenv.c getopt.c getopt_long.c \
 	getsubopt.c hcreate.c heapsort.c imaxabs.c imaxdiv.c \
 	insque.c l64a.c labs.c ldiv.c llabs.c lldiv.c lsearch.c malloc.c \
-	merge.c ptsname.c qsort.c qsort_r.c radixsort.c rand.c random.c \
-	reallocf.c realpath.c remque.c strfmon.c strtoimax.c \
+	merge.c ptsname.c qsort.c qsort_r.c quick_exit.c radixsort.c rand.c \
+	random.c reallocf.c realpath.c remque.c strfmon.c strtoimax.c \
 	strtol.c strtoll.c strtoq.c strtoul.c strtonum.c strtoull.c \
         strtoumax.c strtouq.c system.c tdelete.c tfind.c tsearch.c twalk.c
 
@@ -18,10 +18,12 @@
 # machine-dependent stdlib sources
 .sinclude "${.CURDIR}/${LIBC_ARCH}/stdlib/Makefile.inc"
 
-MAN+=	a64l.3 abort.3 abs.3 alloca.3 atexit.3 atof.3 atoi.3 atol.3 bsearch.3 \
+MAN+=	a64l.3 abort.3 abs.3 alloca.3 atexit.3 atof.3 atoi.3 atol.3 \
+	at_quick_exit.3 bsearch.3 \
 	div.3 exit.3 getenv.3 getopt.3 getopt_long.3 getsubopt.3 \
 	hcreate.3 imaxabs.3 imaxdiv.3 insque.3 labs.3 ldiv.3 llabs.3 lldiv.3 \
 	lsearch.3 malloc.3 memory.3 posix_memalign.3 ptsname.3 qsort.3 \
+	quick_exit.3 \
 	radixsort.3 rand.3 random.3 \
 	realpath.3 strfmon.3 strtod.3 strtol.3 strtonum.3 strtoul.3 system.3 \
 	tsearch.3
diff -r 2230520c0499 -r 820af1e39cd6 head/lib/libc/stdlib/Symbol.map
--- a/head/lib/libc/stdlib/Symbol.map	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/lib/libc/stdlib/Symbol.map	Thu Dec 15 12:59:38 2011 +0200
@@ -1,5 +1,5 @@
 /*
- * $FreeBSD: head/lib/libc/stdlib/Symbol.map 227753 2011-11-20 14:45:42Z theraven $
+ * $FreeBSD: head/lib/libc/stdlib/Symbol.map 228322 2011-12-07 15:25:48Z theraven $
  */
 
 FBSD_1.0 {
@@ -97,6 +97,8 @@
 	atoi_l;
 	atol_l;
 	atoll_l;
+	at_quick_exit;
+	quick_exit;
 	strtod_l;
 	strtol_l;
 	strtoll_l;
diff -r 2230520c0499 -r 820af1e39cd6 head/lib/libc/stdlib/at_quick_exit.3
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/head/lib/libc/stdlib/at_quick_exit.3	Thu Dec 15 12:59:38 2011 +0200
@@ -0,0 +1,61 @@
+.\"  Copyright (c) 2011 David Chisnall
+.\"  All rights reserved.
+.\" 
+.\"  Redistribution and use in source and binary forms, with or without
+.\"  modification, are permitted provided that the following conditions
+.\"  are met:
+.\"  1. Redistributions of source code must retain the above copyright
+.\"     notice, this list of conditions and the following disclaimer.
+.\"  2. Redistributions in binary form must reproduce the above copyright
+.\"     notice, this list of conditions and the following disclaimer in the
+.\"     documentation and/or other materials provided with the distribution.
+.\" 
+.\"  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+.\"  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+.\"  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+.\"  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+.\"  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+.\"  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+.\"  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+.\"  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+.\"  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+.\"  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+.\"  SUCH DAMAGE.
+.\" 
+.\"  $FreeBSD: head/lib/libc/stdlib/at_quick_exit.3 228329 2011-12-07 21:02:35Z theraven $
+.\"
+.Dd December 7, 2011
+.Dt AT_QUICK_EXIT 3
+.Os
+.Sh NAME
+.Nm at_quick_exit
+.Nd registers a cleanup function to run on quick exit
+.Sh LIBRARY
+.Lb libc
+.Sh SYNOPSIS
+.In stdlib.h
+.Ft int
+.Fn at_quick_exit "void (*func)(void)"
+.Sh DESCRIPTION
+The
+.Fn at_quick_exit
+function registers a cleanup function to be called when the program exits as a
+result of calling 
+.Xr quick_exit 3 .
+The cleanup functions are called in the reverse order and will not be called if
+the program exits by calling 
+.Xr exit 3 ,
+.Xr _Exit 3 ,
+or
+.Xr abort 3 .
+.Sh RETURN VALUES
+The 
+.Fn at_quick_exit
+function returns the value 0 if successful and a non-zero value on failure.
+.Sh SEE ALSO
+.Xr exit 3 ,
+.Xr quick_exit 3
+.Sh STANDARDS
+The
+.Fn at_quick_exit
+function conforms to the C1x draft specification.
diff -r 2230520c0499 -r 820af1e39cd6 head/lib/libc/stdlib/atexit.3
--- a/head/lib/libc/stdlib/atexit.3	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/lib/libc/stdlib/atexit.3	Thu Dec 15 12:59:38 2011 +0200
@@ -30,7 +30,7 @@
 .\" SUCH DAMAGE.
 .\"
 .\"     @(#)atexit.3	8.1 (Berkeley) 6/4/93
-.\" $FreeBSD$
+.\" $FreeBSD: head/lib/libc/stdlib/atexit.3 228322 2011-12-07 15:25:48Z theraven $
 .\"
 .Dd September 6, 2002
 .Dt ATEXIT 3
@@ -79,6 +79,7 @@
 The existing list of functions is unmodified.
 .El
 .Sh SEE ALSO
+.Xr at_quick_exit 3
 .Xr exit 3
 .Sh STANDARDS
 The
diff -r 2230520c0499 -r 820af1e39cd6 head/lib/libc/stdlib/exit.3
--- a/head/lib/libc/stdlib/exit.3	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/lib/libc/stdlib/exit.3	Thu Dec 15 12:59:38 2011 +0200
@@ -30,7 +30,7 @@
 .\" SUCH DAMAGE.
 .\"
 .\"     @(#)exit.3	8.1 (Berkeley) 6/4/93
-.\" $FreeBSD$
+.\" $FreeBSD: head/lib/libc/stdlib/exit.3 228322 2011-12-07 15:25:48Z theraven $
 .\"
 .Dd September 9, 2002
 .Dt EXIT 3
@@ -118,7 +118,9 @@
 .Xr _exit 2 ,
 .Xr wait 2 ,
 .Xr atexit 3 ,
+.Xr at_quick_exit 3 ,
 .Xr intro 3 ,
+.Xr quick_exit 3 ,
 .Xr sysexits 3 ,
 .Xr tmpfile 3
 .Sh STANDARDS
diff -r 2230520c0499 -r 820af1e39cd6 head/lib/libc/stdlib/quick_exit.3
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/head/lib/libc/stdlib/quick_exit.3	Thu Dec 15 12:59:38 2011 +0200
@@ -0,0 +1,57 @@
+.\"  Copyright (c) 2011 David Chisnall
+.\"  All rights reserved.
+.\" 
+.\"  Redistribution and use in source and binary forms, with or without
+.\"  modification, are permitted provided that the following conditions
+.\"  are met:
+.\"  1. Redistributions of source code must retain the above copyright
+.\"     notice, this list of conditions and the following disclaimer.
+.\"  2. Redistributions in binary form must reproduce the above copyright
+.\"     notice, this list of conditions and the following disclaimer in the
+.\"     documentation and/or other materials provided with the distribution.
+.\" 
+.\"  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+.\"  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+.\"  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+.\"  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+.\"  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+.\"  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+.\"  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+.\"  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+.\"  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+.\"  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+.\"  SUCH DAMAGE.
+.\" 
+.\"  $FreeBSD: head/lib/libc/stdlib/quick_exit.3 228329 2011-12-07 21:02:35Z theraven $
+.\"
+.Dd December 7, 2011
+.Dt QUICK_EXIT 3
+.Os
+.Sh NAME
+.Nm quick_exit
+.Nd exits a program quickly, running minimal cleanup
+.Sh LIBRARY
+.Lb libc
+.Sh SYNOPSIS
+.In stdlib.h
+.Ft _Noreturn void
+.Fn quick_exit "void"
+.Sh DESCRIPTION
+The
+.Fn quick_exit
+function exits the program quickly calling any cleanup functions registered
+with
+.Xr at_quick_exit 3
+but not any C++ destructors or cleanup code registered with
+.Xr atexit 3 .
+.Sh RETURN VALUES
+The
+.Fn quick_exit
+function does not return.
+.Sh SEE ALSO
+.Xr at_quick_exit 3 ,
+.Xr exit 3
+.Sh STANDARDS
+The
+.Fn quick_exit
+function conforms to the C1x draft specification.
diff -r 2230520c0499 -r 820af1e39cd6 head/lib/libc/stdlib/quick_exit.c
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/head/lib/libc/stdlib/quick_exit.c	Thu Dec 15 12:59:38 2011 +0200
@@ -0,0 +1,78 @@
+/*-
+ * Copyright (c) 2011 David Chisnall
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: head/lib/libc/stdlib/quick_exit.c 228323 2011-12-07 16:12:54Z theraven $
+ */
+
+#include <stdlib.h>
+#include <pthread.h>
+
+/**
+ * Linked list of quick exit handlers.  This is simpler than the atexit()
+ * version, because it is not required to support C++ destructors or
+ * DSO-specific cleanups.
+ */
+struct quick_exit_handler {
+	struct quick_exit_handler *next;
+	void (*cleanup)(void);
+};
+
+/**
+ * Lock protecting the handlers list.
+ */
+static pthread_mutex_t atexit_mutex = PTHREAD_MUTEX_INITIALIZER;
+/**
+ * Stack of cleanup handlers.  These will be invoked in reverse order when 
+ */
+static struct quick_exit_handler *handlers;
+
+int
+at_quick_exit(void (*func)(void))
+{
+	struct quick_exit_handler *h = malloc(sizeof(struct quick_exit_handler));
+
+	if (NULL == h)
+		return 1;
+	h->cleanup = func;
+	pthread_mutex_lock(&atexit_mutex);
+	h->next = handlers;
+	handlers = h;
+	pthread_mutex_unlock(&atexit_mutex);
+	return (0);
+}
+
+void
+quick_exit(int status)
+{
+	struct quick_exit_handler *h;
+
+	/*
+	 * XXX: The C++ spec requires us to call std::terminate if there is an
+	 * exception here.
+	 */
+	for (h = handlers; NULL != h; h = h->next)
+		h->cleanup();
+	_Exit(status);
+}
diff -r 2230520c0499 -r 820af1e39cd6 head/lib/libc/sys/kqueue.2
--- a/head/lib/libc/sys/kqueue.2	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/lib/libc/sys/kqueue.2	Thu Dec 15 12:59:38 2011 +0200
@@ -22,9 +22,9 @@
 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 .\" SUCH DAMAGE.
 .\"
-.\" $FreeBSD$
+.\" $FreeBSD: head/lib/libc/sys/kqueue.2 228318 2011-12-07 11:06:18Z ru $
 .\"
-.Dd September 15, 2009
+.Dd December 7, 2011
 .Dt KQUEUE 2
 .Os
 .Sh NAME
@@ -459,7 +459,7 @@
 .It Dv NOTE_FFOR
 Bitwise OR
 .Va fflags .
-.It Dv NOTE_COPY
+.It Dv NOTE_FFCOPY
 Copy
 .Va fflags .
 .It Dv NOTE_FFCTRLMASK
diff -r 2230520c0499 -r 820af1e39cd6 head/lib/libedit/histedit.h
--- a/head/lib/libedit/histedit.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/lib/libedit/histedit.h	Thu Dec 15 12:59:38 2011 +0200
@@ -31,7 +31,7 @@
  *
  *	@(#)histedit.h	8.2 (Berkeley) 1/3/94
  *	$NetBSD: histedit.h,v 1.32 2007/06/10 20:20:28 christos Exp $
- * $FreeBSD: head/lib/libedit/histedit.h 220370 2011-04-05 18:41:01Z obrien $
+ * $FreeBSD: head/lib/libedit/histedit.h 228473 2011-12-13 14:53:26Z ed $
  */
 
 /*
@@ -158,8 +158,8 @@
 /*
  * Set user private data.
  */
-void            el_data_set    __P((EditLine *, void *));
-void *          el_data_get    __P((EditLine *));
+void            el_data_set(EditLine *, void *);
+void *          el_data_get(EditLine *);
 
 /*
  * User-defined function interface.
diff -r 2230520c0499 -r 820af1e39cd6 head/lib/libufs/block.c
--- a/head/lib/libufs/block.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/lib/libufs/block.c	Thu Dec 15 12:59:38 2011 +0200
@@ -26,7 +26,7 @@
  */
 
 #include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: head/lib/libufs/block.c 228349 2011-12-08 12:31:47Z rmh $");
 
 #include <sys/param.h>
 #include <sys/mount.h>
@@ -139,10 +139,56 @@
 	return (cnt);
 }
 
+#ifdef __FreeBSD_kernel__
+
+static int
+berase_helper(struct uufsd *disk, ufs2_daddr_t blockno, ufs2_daddr_t size)
+{
+	off_t ioarg[2];
+
+	ioarg[0] = blockno * disk->d_bsize;
+	ioarg[1] = size;
+	return (ioctl(disk->d_fd, DIOCGDELETE, ioarg));
+}
+
+#else
+
+static int
+berase_helper(struct uufsd *disk, ufs2_daddr_t blockno, ufs2_daddr_t size)
+{
+	char *zero_chunk;
+	off_t offset, zero_chunk_size, pwrite_size;
+	int rv;
+
+	offset = blockno * disk->d_bsize;
+	zero_chunk_size = 65536 * disk->d_bsize;
+	zero_chunk = calloc(1, zero_chunk_size);
+	if (zero_chunk == NULL) {
+		ERROR(disk, "failed to allocate memory");
+		return (-1);
+	}
+	while (size > 0) { 
+		pwrite_size = size;
+		if (pwrite_size > zero_chunk_size)
+			pwrite_size = zero_chunk_size;
+		rv = pwrite(disk->d_fd, zero_chunk, pwrite_size, offset);
+		if (rv == -1) {
+			ERROR(disk, "failed writing to disk");
+			break;
+		}
+		size -= rv;
+		offset += rv;
+		rv = 0;
+	}
+	free(zero_chunk);
+	return (rv);
+}
+
+#endif
+
 int
 berase(struct uufsd *disk, ufs2_daddr_t blockno, ufs2_daddr_t size)
 {
-	off_t ioarg[2];
 	int rv;
 
 	ERROR(disk, NULL);
@@ -151,8 +197,5 @@
 		ERROR(disk, "failed to open disk for writing");
 		return(rv);
 	}
-	ioarg[0] = blockno * disk->d_bsize;
-	ioarg[1] = size;
-	rv = ioctl(disk->d_fd, DIOCGDELETE, ioarg);
-	return (rv);
+	return (berase_helper(disk, blockno, size));
 }
diff -r 2230520c0499 -r 820af1e39cd6 head/libexec/comsat/comsat.c
--- a/head/libexec/comsat/comsat.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/libexec/comsat/comsat.c	Thu Dec 15 12:59:38 2011 +0200
@@ -42,7 +42,7 @@
 static char sccsid[] = "@(#)comsat.c	8.1 (Berkeley) 6/4/93";
 #endif
 static const char rcsid[] =
-  "$FreeBSD: head/libexec/comsat/comsat.c 222825 2011-06-07 16:23:27Z jh $";
+  "$FreeBSD: head/libexec/comsat/comsat.c 228397 2011-12-10 18:35:26Z ed $";
 #endif /* not lint */
 
 #include <sys/param.h>
@@ -68,17 +68,17 @@
 #include <unistd.h>
 #include <utmpx.h>
 
-int	debug = 0;
+static int	debug = 0;
 #define	dsyslog	if (debug) syslog
 
 #define MAXIDLE	120
 
-char	hostname[MAXHOSTNAMELEN];
+static char	hostname[MAXHOSTNAMELEN];
 
-void jkfprintf(FILE *, char[], char[], off_t);
-void mailfor(char *);
-void notify(struct utmpx *, char[], off_t, int);
-void reapchildren(int);
+static void	jkfprintf(FILE *, char[], char[], off_t);
+static void	mailfor(char *);
+static void	notify(struct utmpx *, char[], off_t, int);
+static void	reapchildren(int);
 
 int
 main(int argc __unused, char *argv[] __unused)
@@ -115,13 +115,13 @@
 	}
 }
 
-void
+static void
 reapchildren(int signo __unused)
 {
 	while (wait3(NULL, WNOHANG, NULL) > 0);
 }
 
-void
+static void
 mailfor(char *name)
 {
 	struct utmpx *utp;
@@ -157,7 +157,7 @@
 
 static const char *cr;
 
-void
+static void
 notify(struct utmpx *utp, char file[], off_t offset, int folder)
 {
 	FILE *tp;
@@ -219,7 +219,7 @@
 	_exit(0);
 }
 
-void
+static void
 jkfprintf(FILE *tp, char user[], char file[], off_t offset)
 {
 	unsigned char *cp, ch;
diff -r 2230520c0499 -r 820af1e39cd6 head/libexec/rtld-elf/amd64/reloc.c
--- a/head/libexec/rtld-elf/amd64/reloc.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/libexec/rtld-elf/amd64/reloc.c	Thu Dec 15 12:59:38 2011 +0200
@@ -22,7 +22,7 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * $FreeBSD$
+ * $FreeBSD: head/libexec/rtld-elf/amd64/reloc.c 228503 2011-12-14 16:47:53Z kib $
  */
 
 /*
@@ -344,11 +344,22 @@
     for (rela = obj->pltrela;  rela < relalim;  rela++) {
 	Elf_Addr *where;
 
-	assert(ELF_R_TYPE(rela->r_info) == R_X86_64_JMP_SLOT);
+	switch(ELF_R_TYPE(rela->r_info)) {
+	case R_X86_64_JMP_SLOT:
+	  /* Relocate the GOT slot pointing into the PLT. */
+	  where = (Elf_Addr *)(obj->relocbase + rela->r_offset);
+	  *where += (Elf_Addr)obj->relocbase;
+	  break;
 
-	/* Relocate the GOT slot pointing into the PLT. */
-	where = (Elf_Addr *)(obj->relocbase + rela->r_offset);
-	*where += (Elf_Addr)obj->relocbase;
+	case R_X86_64_IRELATIVE:
+	  obj->irelative = true;
+	  break;
+
+	default:
+	  _rtld_error("Unknown relocation type %x in PLT",
+	    (unsigned int)ELF_R_TYPE(rela->r_info));
+	  return (-1);
+	}
     }
     return 0;
 }
@@ -368,19 +379,98 @@
 	const Elf_Sym *def;
 	const Obj_Entry *defobj;
 
-	assert(ELF_R_TYPE(rela->r_info) == R_X86_64_JMP_SLOT);
-	where = (Elf_Addr *)(obj->relocbase + rela->r_offset);
-	def = find_symdef(ELF_R_SYM(rela->r_info), obj, &defobj, true, NULL,
-	    lockstate);
-	if (def == NULL)
-	    return -1;
-	target = (Elf_Addr)(defobj->relocbase + def->st_value + rela->r_addend);
-	reloc_jmpslot(where, target, defobj, obj, (const Elf_Rel *)rela);
+	switch (ELF_R_TYPE(rela->r_info)) {
+	case R_X86_64_JMP_SLOT:
+	  where = (Elf_Addr *)(obj->relocbase + rela->r_offset);
+	  def = find_symdef(ELF_R_SYM(rela->r_info), obj, &defobj, true, NULL,
+	      lockstate);
+	  if (def == NULL)
+	      return (-1);
+	  if (ELF_ST_TYPE(def->st_info) == STT_GNU_IFUNC) {
+	      obj->gnu_ifunc = true;
+	      continue;
+	  }
+	  target = (Elf_Addr)(defobj->relocbase + def->st_value + rela->r_addend);
+	  reloc_jmpslot(where, target, defobj, obj, (const Elf_Rel *)rela);
+	  break;
+
+	case R_X86_64_IRELATIVE:
+	  break;
+
+	default:
+	  _rtld_error("Unknown relocation type %x in PLT",
+	    (unsigned int)ELF_R_TYPE(rela->r_info));
+	  return (-1);
+	}
     }
     obj->jmpslots_done = true;
     return 0;
 }
 
+int
+reloc_iresolve(Obj_Entry *obj, RtldLockState *lockstate)
+{
+    const Elf_Rela *relalim;
+    const Elf_Rela *rela;
+
+    if (!obj->irelative)
+	return (0);
+    relalim = (const Elf_Rela *)((char *)obj->pltrela + obj->pltrelasize);
+    for (rela = obj->pltrela;  rela < relalim;  rela++) {
+	Elf_Addr *where, target, *ptr;
+
+	switch (ELF_R_TYPE(rela->r_info)) {
+	case R_X86_64_JMP_SLOT:
+	  break;
+
+	case R_X86_64_IRELATIVE:
+	  ptr = (Elf_Addr *)(obj->relocbase + rela->r_addend);
+	  where = (Elf_Addr *)(obj->relocbase + rela->r_offset);
+	  lock_release(rtld_bind_lock, lockstate);
+	  target = ((Elf_Addr (*)(void))ptr)();
+	  wlock_acquire(rtld_bind_lock, lockstate);
+	  *where = target;
+	  break;
+	}
+    }
+    obj->irelative = false;
+    return (0);
+}
+
+int
+reloc_gnu_ifunc(Obj_Entry *obj, RtldLockState *lockstate)
+{
+    const Elf_Rela *relalim;
+    const Elf_Rela *rela;
+
+    if (!obj->gnu_ifunc)
+	return (0);
+    relalim = (const Elf_Rela *)((char *)obj->pltrela + obj->pltrelasize);
+    for (rela = obj->pltrela;  rela < relalim;  rela++) {
+	Elf_Addr *where, target;
+	const Elf_Sym *def;
+	const Obj_Entry *defobj;
+
+	switch (ELF_R_TYPE(rela->r_info)) {
+	case R_X86_64_JMP_SLOT:
+	  where = (Elf_Addr *)(obj->relocbase + rela->r_offset);
+	  def = find_symdef(ELF_R_SYM(rela->r_info), obj, &defobj, true, NULL,
+	      lockstate);
+	  if (def == NULL)
+	      return (-1);
+	  if (ELF_ST_TYPE(def->st_info) != STT_GNU_IFUNC)
+	      continue;
+	  lock_release(rtld_bind_lock, lockstate);
+	  target = (Elf_Addr)rtld_resolve_ifunc(defobj, def);
+	  wlock_acquire(rtld_bind_lock, lockstate);
+	  reloc_jmpslot(where, target, defobj, obj, (const Elf_Rel *)rela);
+	  break;
+	}
+    }
+    obj->gnu_ifunc = false;
+    return (0);
+}
+
 void
 allocate_initial_tls(Obj_Entry *objs)
 {
diff -r 2230520c0499 -r 820af1e39cd6 head/libexec/rtld-elf/arm/reloc.c
--- a/head/libexec/rtld-elf/arm/reloc.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/libexec/rtld-elf/arm/reloc.c	Thu Dec 15 12:59:38 2011 +0200
@@ -1,7 +1,7 @@
 /*	$NetBSD: mdreloc.c,v 1.23 2003/07/26 15:04:38 mrg Exp $	*/
 
 #include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: head/libexec/rtld-elf/arm/reloc.c 228435 2011-12-12 11:03:14Z kib $");
 #include <sys/param.h>
 #include <sys/mman.h>
 
@@ -337,6 +337,22 @@
 	return (0);
 }
 
+int
+reloc_iresolve(Obj_Entry *obj, struct Struct_RtldLockState *lockstate)
+{
+
+	/* XXX not implemented */
+	return (0);
+}
+
+int
+reloc_gnu_ifunc(Obj_Entry *obj, struct Struct_RtldLockState *lockstate)
+{
+
+	/* XXX not implemented */
+	return (0);
+}
+
 Elf_Addr
 reloc_jmpslot(Elf_Addr *where, Elf_Addr target, const Obj_Entry *defobj,
     		const Obj_Entry *obj, const Elf_Rel *rel)
diff -r 2230520c0499 -r 820af1e39cd6 head/libexec/rtld-elf/i386/reloc.c
--- a/head/libexec/rtld-elf/i386/reloc.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/libexec/rtld-elf/i386/reloc.c	Thu Dec 15 12:59:38 2011 +0200
@@ -22,7 +22,7 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * $FreeBSD: head/libexec/rtld-elf/i386/reloc.c 226156 2011-10-08 12:42:19Z kib $
+ * $FreeBSD: head/libexec/rtld-elf/i386/reloc.c 228503 2011-12-14 16:47:53Z kib $
  */
 
 /*
@@ -298,13 +298,24 @@
 
     rellim = (const Elf_Rel *)((char *)obj->pltrel + obj->pltrelsize);
     for (rel = obj->pltrel;  rel < rellim;  rel++) {
-	Elf_Addr *where;
+	Elf_Addr *where/*, val*/;
 
-	assert(ELF_R_TYPE(rel->r_info) == R_386_JMP_SLOT);
+	switch (ELF_R_TYPE(rel->r_info)) {
+	case R_386_JMP_SLOT:
+	  /* Relocate the GOT slot pointing into the PLT. */
+	  where = (Elf_Addr *)(obj->relocbase + rel->r_offset);
+	  *where += (Elf_Addr)obj->relocbase;
+	  break;
 
-	/* Relocate the GOT slot pointing into the PLT. */
-	where = (Elf_Addr *)(obj->relocbase + rel->r_offset);
-	*where += (Elf_Addr)obj->relocbase;
+	case R_386_IRELATIVE:
+	  obj->irelative = true;
+	  break;
+
+	default:
+	  _rtld_error("Unknown relocation type %x in PLT",
+	    ELF_R_TYPE(rel->r_info));
+	  return (-1);
+	}
     }
     return 0;
 }
@@ -324,19 +335,95 @@
 	const Elf_Sym *def;
 	const Obj_Entry *defobj;
 
-	assert(ELF_R_TYPE(rel->r_info) == R_386_JMP_SLOT);
-	where = (Elf_Addr *)(obj->relocbase + rel->r_offset);
-	def = find_symdef(ELF_R_SYM(rel->r_info), obj, &defobj, true, NULL,
-	    lockstate);
-	if (def == NULL)
-	    return -1;
-	target = (Elf_Addr)(defobj->relocbase + def->st_value);
-	reloc_jmpslot(where, target, defobj, obj, rel);
+	switch (ELF_R_TYPE(rel->r_info)) {
+	case R_386_JMP_SLOT:
+	  where = (Elf_Addr *)(obj->relocbase + rel->r_offset);
+	  def = find_symdef(ELF_R_SYM(rel->r_info), obj, &defobj, true, NULL,
+	      lockstate);
+	  if (def == NULL)
+	      return (-1);
+	  if (ELF_ST_TYPE(def->st_info) == STT_GNU_IFUNC) {
+	      obj->gnu_ifunc = true;
+	      continue;
+	  }
+	  target = (Elf_Addr)(defobj->relocbase + def->st_value);
+	  reloc_jmpslot(where, target, defobj, obj, rel);
+	  break;
+
+	case R_386_IRELATIVE:
+	  break;
+
+	default:
+	  _rtld_error("Unknown relocation type %x in PLT",
+	    ELF_R_TYPE(rel->r_info));
+	  return (-1);
+	}
     }
+
     obj->jmpslots_done = true;
     return 0;
 }
 
+int
+reloc_iresolve(Obj_Entry *obj, RtldLockState *lockstate)
+{
+    const Elf_Rel *rellim;
+    const Elf_Rel *rel;
+    Elf_Addr *where, target;
+
+    if (!obj->irelative)
+	return (0);
+    rellim = (const Elf_Rel *)((char *)obj->pltrel + obj->pltrelsize);
+    for (rel = obj->pltrel;  rel < rellim;  rel++) {
+	switch (ELF_R_TYPE(rel->r_info)) {
+	case R_386_IRELATIVE:
+	  where = (Elf_Addr *)(obj->relocbase + rel->r_offset);
+	  lock_release(rtld_bind_lock, lockstate);
+	  target = ((Elf_Addr (*)(void))(obj->relocbase + *where))();
+	  wlock_acquire(rtld_bind_lock, lockstate);
+	  *where = target;
+	  break;
+	}
+    }
+    obj->irelative = false;
+    return (0);
+}
+
+int
+reloc_gnu_ifunc(Obj_Entry *obj, RtldLockState *lockstate)
+{
+    const Elf_Rel *rellim;
+    const Elf_Rel *rel;
+
+    if (!obj->gnu_ifunc)
+	return (0);
+    rellim = (const Elf_Rel *)((char *)obj->pltrel + obj->pltrelsize);
+    for (rel = obj->pltrel;  rel < rellim;  rel++) {
+	Elf_Addr *where, target;
+	const Elf_Sym *def;
+	const Obj_Entry *defobj;
+
+	switch (ELF_R_TYPE(rel->r_info)) {
+	case R_386_JMP_SLOT:
+	  where = (Elf_Addr *)(obj->relocbase + rel->r_offset);
+	  def = find_symdef(ELF_R_SYM(rel->r_info), obj, &defobj, true, NULL,
+	      lockstate);
+	  if (def == NULL)
+	      return (-1);
+	  if (ELF_ST_TYPE(def->st_info) != STT_GNU_IFUNC)
+	      continue;
+	  lock_release(rtld_bind_lock, lockstate);
+	  target = (Elf_Addr)rtld_resolve_ifunc(defobj, def);
+	  wlock_acquire(rtld_bind_lock, lockstate);
+	  reloc_jmpslot(where, target, defobj, obj, rel);
+	  break;
+	}
+    }
+
+    obj->gnu_ifunc = false;
+    return (0);
+}
+
 void
 allocate_initial_tls(Obj_Entry *objs)
 {
diff -r 2230520c0499 -r 820af1e39cd6 head/libexec/rtld-elf/ia64/reloc.c
--- a/head/libexec/rtld-elf/ia64/reloc.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/libexec/rtld-elf/ia64/reloc.c	Thu Dec 15 12:59:38 2011 +0200
@@ -22,7 +22,7 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * $FreeBSD$
+ * $FreeBSD: head/libexec/rtld-elf/ia64/reloc.c 228435 2011-12-12 11:03:14Z kib $
  */
 
 /*
@@ -435,6 +435,22 @@
 	return 0;
 }
 
+int
+reloc_iresolve(Obj_Entry *obj, struct Struct_RtldLockState *lockstate)
+{
+
+	/* XXX not implemented */
+	return (0);
+}
+
+int
+reloc_gnu_ifunc(Obj_Entry *obj, struct Struct_RtldLockState *lockstate)
+{
+
+	/* XXX not implemented */
+	return (0);
+}
+
 /* Relocate the jump slots in an object. */
 int
 reloc_jmpslots(Obj_Entry *obj, RtldLockState *lockstate)
diff -r 2230520c0499 -r 820af1e39cd6 head/libexec/rtld-elf/mips/reloc.c
--- a/head/libexec/rtld-elf/mips/reloc.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/libexec/rtld-elf/mips/reloc.c	Thu Dec 15 12:59:38 2011 +0200
@@ -29,7 +29,7 @@
  */
 
 #include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: head/libexec/rtld-elf/mips/reloc.c 228435 2011-12-12 11:03:14Z kib $");
 
 #include <sys/types.h>
 #include <sys/stat.h>
@@ -498,6 +498,22 @@
 	return (0);
 }
 
+int
+reloc_iresolve(Obj_Entry *obj, struct Struct_RtldLockState *lockstate)
+{
+
+	/* XXX not implemented */
+	return (0);
+}
+
+int
+reloc_gnu_ifunc(Obj_Entry *obj, struct Struct_RtldLockState *lockstate)
+{
+
+	/* XXX not implemented */
+	return (0);
+}
+
 Elf_Addr
 reloc_jmpslot(Elf_Addr *where, Elf_Addr target, const Obj_Entry *defobj,
     		const Obj_Entry *obj, const Elf_Rel *rel)
diff -r 2230520c0499 -r 820af1e39cd6 head/libexec/rtld-elf/powerpc/reloc.c
--- a/head/libexec/rtld-elf/powerpc/reloc.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/libexec/rtld-elf/powerpc/reloc.c	Thu Dec 15 12:59:38 2011 +0200
@@ -26,7 +26,7 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * $FreeBSD$
+ * $FreeBSD: head/libexec/rtld-elf/powerpc/reloc.c 228435 2011-12-12 11:03:14Z kib $
  */
 
 #include <sys/param.h>
@@ -504,6 +504,21 @@
 	return (target);
 }
 
+int
+reloc_iresolve(Obj_Entry *obj, struct Struct_RtldLockState *lockstate)
+{
+
+	/* XXX not implemented */
+	return (0);
+}
+
+int
+reloc_gnu_ifunc(Obj_Entry *obj, struct Struct_RtldLockState *lockstate)
+{
+
+	/* XXX not implemented */
+	return (0);
+}
 
 /*
  * Setup the plt glue routines.
diff -r 2230520c0499 -r 820af1e39cd6 head/libexec/rtld-elf/powerpc64/reloc.c
--- a/head/libexec/rtld-elf/powerpc64/reloc.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/libexec/rtld-elf/powerpc64/reloc.c	Thu Dec 15 12:59:38 2011 +0200
@@ -26,7 +26,7 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * $FreeBSD$
+ * $FreeBSD: head/libexec/rtld-elf/powerpc64/reloc.c 228435 2011-12-12 11:03:14Z kib $
  */
 
 #include <sys/param.h>
@@ -456,6 +456,22 @@
 	return (target);
 }
 
+int
+reloc_iresolve(Obj_Entry *obj, struct Struct_RtldLockState *lockstate)
+{
+
+	/* XXX not implemented */
+	return (0);
+}
+
+int
+reloc_gnu_ifunc(Obj_Entry *obj, struct Struct_RtldLockState *lockstate)
+{
+
+	/* XXX not implemented */
+	return (0);
+}
+
 void
 init_pltgot(Obj_Entry *obj)
 {
diff -r 2230520c0499 -r 820af1e39cd6 head/libexec/rtld-elf/rtld.c
--- a/head/libexec/rtld-elf/rtld.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/libexec/rtld-elf/rtld.c	Thu Dec 15 12:59:38 2011 +0200
@@ -24,7 +24,7 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * $FreeBSD: head/libexec/rtld-elf/rtld.c 227660 2011-11-18 09:55:47Z kib $
+ * $FreeBSD: head/libexec/rtld-elf/rtld.c 228503 2011-12-14 16:47:53Z kib $
  */
 
 /*
@@ -116,6 +116,8 @@
 static void objlist_remove(Objlist *, Obj_Entry *);
 static void *path_enumerate(const char *, path_enum_proc, void *);
 static int relocate_objects(Obj_Entry *, bool, Obj_Entry *, RtldLockState *);
+static int resolve_objects_ifunc(Obj_Entry *first, bool bind_now,
+    RtldLockState *lockstate);
 static int rtld_dirname(const char *, char *);
 static int rtld_dirname_abs(const char *, char *);
 static void rtld_exit(void);
@@ -513,6 +515,10 @@
       ld_bind_now != NULL && *ld_bind_now != '\0', &obj_rtld, NULL) == -1)
 	die();
 
+    if (resolve_objects_ifunc(obj_main,
+      ld_bind_now != NULL && *ld_bind_now != '\0', NULL) == -1)
+	die();
+
     dbg("doing copy relocations");
     if (do_copy_relocations(obj_main) == -1)
 	die();
@@ -561,6 +567,17 @@
     return (func_ptr_type) obj_main->entry;
 }
 
+void *
+rtld_resolve_ifunc(const Obj_Entry *obj, const Elf_Sym *def)
+{
+	void *ptr;
+	Elf_Addr target;
+
+	ptr = (void *)make_function_pointer(def, obj);
+	target = ((Elf_Addr (*)(void))ptr)();
+	return ((void *)target);
+}
+
 Elf_Addr
 _rtld_bind(Obj_Entry *obj, Elf_Size reloff)
 {
@@ -584,8 +601,10 @@
 	&lockstate);
     if (def == NULL)
 	die();
-
-    target = (Elf_Addr)(defobj->relocbase + def->st_value);
+    if (ELF_ST_TYPE(def->st_info) == STT_GNU_IFUNC)
+	target = (Elf_Addr)rtld_resolve_ifunc(defobj, def);
+    else
+	target = (Elf_Addr)(defobj->relocbase + def->st_value);
 
     dbg("\"%s\" in \"%s\" ==> %p in \"%s\"",
       defobj->strtab + def->st_name, basename(obj->path),
@@ -1944,6 +1963,10 @@
 	    }
 	}
 
+
+	/* Set the special PLT or GOT entries. */
+	init_pltgot(obj);
+
 	/* Process the PLT relocations. */
 	if (reloc_plt(obj) == -1)
 	    return -1;
@@ -1952,7 +1975,6 @@
 	    if (reloc_jmpslots(obj, lockstate) == -1)
 		return -1;
 
-
 	/*
 	 * Set up the magic number and version in the Obj_Entry.  These
 	 * were checked in the crt1.o from the original ElfKit, so we
@@ -1960,12 +1982,55 @@
 	 */
 	obj->magic = RTLD_MAGIC;
 	obj->version = RTLD_VERSION;
-
-	/* Set the special PLT or GOT entries. */
-	init_pltgot(obj);
     }
 
-    return 0;
+    return (0);
+}
+
+/*
+ * The handling of R_MACHINE_IRELATIVE relocations and jumpslots
+ * referencing STT_GNU_IFUNC symbols is postponed till the other
+ * relocations are done.  The indirect functions specified as
+ * ifunc are allowed to call other symbols, so we need to have
+ * objects relocated before asking for resolution from indirects.
+ *
+ * The R_MACHINE_IRELATIVE slots are resolved in greedy fashion,
+ * instead of the usual lazy handling of PLT slots.  It is
+ * consistent with how GNU does it.
+ */
+static int
+resolve_object_ifunc(Obj_Entry *obj, bool bind_now, RtldLockState *lockstate)
+{
+	if (obj->irelative && reloc_iresolve(obj, lockstate) == -1)
+		return (-1);
+	if ((obj->bind_now || bind_now) && obj->gnu_ifunc &&
+	    reloc_gnu_ifunc(obj, lockstate) == -1)
+		return (-1);
+	return (0);
+}
+
+static int
+resolve_objects_ifunc(Obj_Entry *first, bool bind_now, RtldLockState *lockstate)
+{
+	Obj_Entry *obj;
+
+	for (obj = first;  obj != NULL;  obj = obj->next) {
+		if (resolve_object_ifunc(obj, bind_now, lockstate) == -1)
+			return (-1);
+	}
+	return (0);
+}
+
+static int
+initlist_objects_ifunc(Objlist *list, bool bind_now, RtldLockState *lockstate)
+{
+	Objlist_Entry *elm;
+
+	STAILQ_FOREACH(elm, list, link) {
+		if (resolve_object_ifunc(elm->obj, bind_now, lockstate) == -1)
+			return (-1);
+	}
+	return (0);
 }
 
 /*
@@ -2170,6 +2235,16 @@
       mode & (RTLD_MODEMASK | RTLD_GLOBAL)));
 }
 
+static void
+dlopen_cleanup(Obj_Entry *obj)
+{
+
+	obj->dl_refcount--;
+	unref_dag(obj);
+	if (obj->refcount == 0)
+		unload_object(obj);
+}
+
 static Obj_Entry *
 dlopen_object(const char *name, Obj_Entry *refobj, int lo_flags, int mode)
 {
@@ -2208,10 +2283,7 @@
 		goto trace;
 	    if (result == -1 || (relocate_objects(obj, (mode & RTLD_MODEMASK)
 	      == RTLD_NOW, &obj_rtld, &lockstate)) == -1) {
-		obj->dl_refcount--;
-		unref_dag(obj);
-		if (obj->refcount == 0)
-		    unload_object(obj);
+		dlopen_cleanup(obj);
 		obj = NULL;
 	    } else {
 		/* Make list of init functions to call. */
@@ -2245,6 +2317,14 @@
 
     map_stacks_exec(&lockstate);
 
+    if (initlist_objects_ifunc(&initlist, (mode & RTLD_MODEMASK) == RTLD_NOW,
+      &lockstate) == -1) {
+	objlist_clear(&initlist);
+	dlopen_cleanup(obj);
+	lock_release(rtld_bind_lock, &lockstate);
+	return (NULL);
+    }
+
     /* Call the init functions. */
     objlist_call_init(&initlist, &lockstate);
     objlist_clear(&initlist);
@@ -2376,9 +2456,11 @@
 	 * the relocated value of the symbol.
 	 */
 	if (ELF_ST_TYPE(def->st_info) == STT_FUNC)
-	    return make_function_pointer(def, defobj);
+	    return (make_function_pointer(def, defobj));
+	else if (ELF_ST_TYPE(def->st_info) == STT_GNU_IFUNC)
+	    return (rtld_resolve_ifunc(defobj, def));
 	else
-	    return defobj->relocbase + def->st_value;
+	    return (defobj->relocbase + def->st_value);
     }
 
     _rtld_error("Undefined symbol \"%s\"", name);
@@ -2822,6 +2904,8 @@
     if (ELF_ST_TYPE(req.sym_out->st_info) == STT_FUNC)
 	return ((const void **)make_function_pointer(req.sym_out,
 	  req.defobj_out));
+    else if (ELF_ST_TYPE(req.sym_out->st_info) == STT_GNU_IFUNC)
+	return ((const void **)rtld_resolve_ifunc(req.defobj_out, req.sym_out));
     else
 	return ((const void **)(req.defobj_out->relocbase +
 	  req.sym_out->st_value));
@@ -3088,6 +3172,7 @@
 	case STT_FUNC:
 	case STT_NOTYPE:
 	case STT_OBJECT:
+	case STT_GNU_IFUNC:
 	    if (symp->st_value == 0)
 		continue;
 		/* fallthrough */
diff -r 2230520c0499 -r 820af1e39cd6 head/libexec/rtld-elf/rtld.h
--- a/head/libexec/rtld-elf/rtld.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/libexec/rtld-elf/rtld.h	Thu Dec 15 12:59:38 2011 +0200
@@ -22,7 +22,7 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * $FreeBSD: head/libexec/rtld-elf/rtld.h 225152 2011-08-24 20:05:13Z kib $
+ * $FreeBSD: head/libexec/rtld-elf/rtld.h 228435 2011-12-12 11:03:14Z kib $
  */
 
 #ifndef RTLD_H /* { */
@@ -230,6 +230,8 @@
     bool on_fini_list: 1;	/* Object is already on fini list. */
     bool dag_inited : 1;	/* Object has its DAG initialized. */
     bool filtees_loaded : 1;	/* Filtees loaded */
+    bool irelative : 1;		/* Object has R_MACHDEP_IRELATIVE relocs */
+    bool gnu_ifunc : 1;		/* Object has references to STT_GNU_IFUNC */
 
     struct link_map linkmap;	/* For GDB and dlinfo() */
     Objlist dldags;		/* Object belongs to these dlopened DAGs (%) */
@@ -246,7 +248,7 @@
 
 /* Flags to be passed into symlook_ family of functions. */
 #define SYMLOOK_IN_PLT	0x01	/* Lookup for PLT symbol */
-#define SYMLOOK_DLSYM	0x02	/* Return newes versioned symbol. Used by
+#define SYMLOOK_DLSYM	0x02	/* Return newest versioned symbol. Used by
 				   dlsym. */
 
 /* Flags for load_object(). */
@@ -317,6 +319,7 @@
 void obj_free(Obj_Entry *);
 Obj_Entry *obj_new(void);
 void _rtld_bind_start(void);
+void *rtld_resolve_ifunc(const Obj_Entry *obj, const Elf_Sym *def);
 void symlook_init(SymLook *, const char *);
 int symlook_obj(SymLook *, const Obj_Entry *);
 void *tls_get_addr_common(Elf_Addr** dtvp, int index, size_t offset);
@@ -334,6 +337,8 @@
 int reloc_non_plt(Obj_Entry *, Obj_Entry *, struct Struct_RtldLockState *);
 int reloc_plt(Obj_Entry *);
 int reloc_jmpslots(Obj_Entry *, struct Struct_RtldLockState *);
+int reloc_iresolve(Obj_Entry *, struct Struct_RtldLockState *);
+int reloc_gnu_ifunc(Obj_Entry *, struct Struct_RtldLockState *);
 void allocate_initial_tls(Obj_Entry *);
 
 #endif /* } */
diff -r 2230520c0499 -r 820af1e39cd6 head/libexec/rtld-elf/sparc64/reloc.c
--- a/head/libexec/rtld-elf/sparc64/reloc.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/libexec/rtld-elf/sparc64/reloc.c	Thu Dec 15 12:59:38 2011 +0200
@@ -31,7 +31,7 @@
  */
 
 #include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: head/libexec/rtld-elf/sparc64/reloc.c 228435 2011-12-12 11:03:14Z kib $");
 
 #include <sys/param.h>
 #include <sys/mman.h>
@@ -550,6 +550,22 @@
 	return (0);
 }
 
+int
+reloc_iresolve(Obj_Entry *obj, struct Struct_RtldLockState *lockstate)
+{
+
+	/* XXX not implemented */
+	return (0);
+}
+
+int
+reloc_gnu_ifunc(Obj_Entry *obj, struct Struct_RtldLockState *lockstate)
+{
+
+	/* XXX not implemented */
+	return (0);
+}
+
 Elf_Addr
 reloc_jmpslot(Elf_Addr *wherep, Elf_Addr target, const Obj_Entry *obj,
     const Obj_Entry *refobj, const Elf_Rel *rel)
diff -r 2230520c0499 -r 820af1e39cd6 head/sbin/bsdlabel/bsdlabel.c
--- a/head/sbin/bsdlabel/bsdlabel.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sbin/bsdlabel/bsdlabel.c	Thu Dec 15 12:59:38 2011 +0200
@@ -53,7 +53,7 @@
 #endif /* not lint */
 #endif
 #include <sys/cdefs.h>
-__FBSDID("$FreeBSD: head/sbin/bsdlabel/bsdlabel.c 227296 2011-11-07 07:51:10Z ae $");
+__FBSDID("$FreeBSD: head/sbin/bsdlabel/bsdlabel.c 228417 2011-12-11 19:28:04Z ed $");
 
 #include <sys/param.h>
 #include <stdint.h>
@@ -130,7 +130,7 @@
 static int labeloffset = LABELOFFSET;
 static int bbsize = BBSIZE;
 
-enum	{
+static enum {
 	UNSPEC, EDIT, READ, RESTORE, WRITE, WRITEBOOT
 } op = UNSPEC;
 
diff -r 2230520c0499 -r 820af1e39cd6 head/sbin/camcontrol/fwdownload.c
--- a/head/sbin/camcontrol/fwdownload.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sbin/camcontrol/fwdownload.c	Thu Dec 15 12:59:38 2011 +0200
@@ -48,7 +48,7 @@
  */
 
 #include <sys/cdefs.h>
-__FBSDID("$FreeBSD: head/sbin/camcontrol/fwdownload.c 228203 2011-12-02 15:47:05Z emaste $");
+__FBSDID("$FreeBSD: head/sbin/camcontrol/fwdownload.c 228407 2011-12-11 11:38:50Z ed $");
 
 #include <sys/types.h>
 #include <sys/stat.h>
@@ -88,7 +88,7 @@
 	int inc_cdb_offset;
 };
 
-struct fw_vendor vendors_list[] = {
+static const struct fw_vendor vendors_list[] = {
 	{VENDOR_HITACHI,	"HITACHI",	0x8000, 0x05, 0x05, 1, 0},
 	{VENDOR_HP,		"HP",		0x8000, 0x07, 0x07, 0, 1},
 	{VENDOR_IBM,		"IBM",		0x8000, 0x05, 0x05, 1, 0},
@@ -98,22 +98,22 @@
 	{VENDOR_UNKNOWN,	NULL,		0x0000, 0x00, 0x00, 0, 0}
 };
 
-static struct fw_vendor *fw_get_vendor(struct cam_device *cam_dev);
-static char	*fw_read_img(char *fw_img_path, struct fw_vendor *vp,
-		    int *num_bytes);
+static const struct fw_vendor *fw_get_vendor(struct cam_device *cam_dev);
+static char	*fw_read_img(const char *fw_img_path,
+		    const struct fw_vendor *vp, int *num_bytes);
 static int	 fw_download_img(struct cam_device *cam_dev,
-		    struct fw_vendor *vp, char *buf, int img_size,
+		    const struct fw_vendor *vp, char *buf, int img_size,
 		    int sim_mode, int verbose, int retry_count, int timeout);
 
 /*
  * Find entry in vendors list that belongs to
  * the vendor of given cam device.
  */
-static struct fw_vendor *
+static const struct fw_vendor *
 fw_get_vendor(struct cam_device *cam_dev)
 {
 	char vendor[SID_VENDOR_SIZE + 1];
-	struct fw_vendor *vp;
+	const struct fw_vendor *vp;
 
 	if (cam_dev == NULL)
 		return (NULL);
@@ -133,7 +133,7 @@
  * in num_bytes.
  */
 static char *
-fw_read_img(char *fw_img_path, struct fw_vendor *vp, int *num_bytes)
+fw_read_img(const char *fw_img_path, const struct fw_vendor *vp, int *num_bytes)
 {
 	int fd;
 	struct stat stbuf;
@@ -205,7 +205,7 @@
  * device but do not sent any actual packets
  */
 static int
-fw_download_img(struct cam_device *cam_dev, struct fw_vendor *vp,
+fw_download_img(struct cam_device *cam_dev, const struct fw_vendor *vp,
     char *buf, int img_size, int sim_mode, int verbose, int retry_count,
     int timeout)
 {
@@ -319,7 +319,7 @@
 fwdownload(struct cam_device *device, int argc, char **argv,
     char *combinedopt, int verbose, int retry_count, int timeout)
 {
-	struct fw_vendor *vp;
+	const struct fw_vendor *vp;
 	char *fw_img_path = NULL;
 	char *buf;
 	int img_size;
diff -r 2230520c0499 -r 820af1e39cd6 head/sbin/camcontrol/modeedit.c
--- a/head/sbin/camcontrol/modeedit.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sbin/camcontrol/modeedit.c	Thu Dec 15 12:59:38 2011 +0200
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: head/sbin/camcontrol/modeedit.c 228407 2011-12-11 11:38:50Z ed $");
 
 #include <sys/queue.h>
 #include <sys/types.h>
@@ -83,15 +83,15 @@
 		char	*svalue;
 	} value;
 };
-STAILQ_HEAD(, editentry) editlist;	/* List of page entries. */
-int editlist_changed = 0;		/* Whether any entries were changed. */
+static STAILQ_HEAD(, editentry) editlist; /* List of page entries. */
+static int editlist_changed = 0;	/* Whether any entries were changed. */
 
 struct pagename {
 	SLIST_ENTRY(pagename) link;
 	int pagenum;
 	char *name;
 };
-SLIST_HEAD(, pagename) namelist;	/* Page number to name mappings. */
+static SLIST_HEAD(, pagename) namelist;	/* Page number to name mappings. */
 
 static char format[MAX_FORMAT_SPEC];	/* Buffer for scsi cdb format def. */
 
diff -r 2230520c0499 -r 820af1e39cd6 head/sbin/dhclient/dhclient-script
--- a/head/sbin/dhclient/dhclient-script	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sbin/dhclient/dhclient-script	Thu Dec 15 12:59:38 2011 +0200
@@ -1,7 +1,7 @@
 #!/bin/sh
 #
 # $OpenBSD: dhclient-script,v 1.6 2004/05/06 18:22:41 claudio Exp $
-# $FreeBSD: head/sbin/dhclient/dhclient-script 228259 2011-12-04 14:44:31Z dumbbell $
+# $FreeBSD: head/sbin/dhclient/dhclient-script 228463 2011-12-13 11:54:51Z glebius $
 #
 # Copyright (c) 2003 Kenneth R Westerback <krw at openbsd.org>
 #
@@ -320,7 +320,7 @@
 
 PREINIT)
 	delete_old_alias
-	$IFCONFIG $interface inet alias 0.0.0.0 netmask 0.0.0.0 broadcast 255.255.255.255 up
+	$IFCONFIG $interface inet alias 0.0.0.0 netmask 255.0.0.0 broadcast 255.255.255.255 up
 	;;
 
 ARPCHECK|ARPSEND)
diff -r 2230520c0499 -r 820af1e39cd6 head/sbin/dumpfs/dumpfs.c
--- a/head/sbin/dumpfs/dumpfs.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sbin/dumpfs/dumpfs.c	Thu Dec 15 12:59:38 2011 +0200
@@ -53,7 +53,7 @@
 static char sccsid[] = "@(#)dumpfs.c	8.5 (Berkeley) 4/29/95";
 #endif
 static const char rcsid[] =
-  "$FreeBSD: head/sbin/dumpfs/dumpfs.c 227081 2011-11-04 13:36:02Z ed $";
+  "$FreeBSD: head/sbin/dumpfs/dumpfs.c 228458 2011-12-13 09:01:44Z ed $";
 #endif /* not lint */
 
 #include <sys/param.h>
@@ -79,16 +79,16 @@
 
 static struct uufsd disk;
 
-int	dumpfs(const char *);
-int	dumpfsid(void);
-int	dumpcg(void);
-int	dumpfreespace(const char *, int);
-void	dumpfreespacecg(int);
-int	marshal(const char *);
-void	pbits(void *, int);
-void	pblklist(void *, int, off_t, int);
-void	ufserr(const char *);
-void	usage(void) __dead2;
+static int	dumpfs(const char *);
+static int	dumpfsid(void);
+static int	dumpcg(void);
+static int	dumpfreespace(const char *, int);
+static void	dumpfreespacecg(int);
+static int	marshal(const char *);
+static void	pbits(void *, int);
+static void	pblklist(void *, int, off_t, int);
+static void	ufserr(const char *);
+static void	usage(void) __dead2;
 
 int
 main(int argc, char *argv[])
@@ -143,7 +143,7 @@
 	exit(eval);
 }
 
-int
+static int
 dumpfsid(void)
 {
 
@@ -151,7 +151,7 @@
 	return 0;
 }
 
-int
+static int
 dumpfs(const char *name)
 {
 	time_t fstime;
@@ -309,7 +309,7 @@
 	return (1);
 }
 
-int
+static int
 dumpcg(void)
 {
 	time_t cgtime;
@@ -370,7 +370,7 @@
 	return (0);
 }
 
-int
+static int
 dumpfreespace(const char *name, int fflag)
 {
 	int i;
@@ -386,7 +386,7 @@
 	return (1);
 }
 
-void
+static void
 dumpfreespacecg(int fflag)
 {
 
@@ -394,7 +394,7 @@
 	    fflag);
 }
 
-int
+static int
 marshal(const char *name)
 {
 	struct fs *fs;
@@ -444,7 +444,7 @@
 	return 0;
 }
 
-void
+static void
 pbits(void *vp, int max)
 {
 	int i;
@@ -466,7 +466,7 @@
 	printf("\n");
 }
 
-void
+static void
 pblklist(void *vp, int max, off_t offset, int fflag)
 {
 	int i, j;
@@ -487,7 +487,7 @@
 	}
 }
 
-void
+static void
 ufserr(const char *name)
 {
 	if (disk.d_error != NULL)
@@ -496,7 +496,7 @@
 		warn("%s", name);
 }
 
-void
+static void
 usage(void)
 {
 	(void)fprintf(stderr, "usage: dumpfs [-fm] filesys | device\n");
diff -r 2230520c0499 -r 820af1e39cd6 head/sbin/rcorder/rcorder.c
--- a/head/sbin/rcorder/rcorder.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sbin/rcorder/rcorder.c	Thu Dec 15 12:59:38 2011 +0200
@@ -36,7 +36,7 @@
  */
 
 #include <sys/types.h>
-__FBSDID("$FreeBSD: head/sbin/rcorder/rcorder.c 227081 2011-11-04 13:36:02Z ed $");
+__FBSDID("$FreeBSD: head/sbin/rcorder/rcorder.c 228422 2011-12-11 20:48:40Z ed $");
 
 #include <sys/stat.h>
 
@@ -52,7 +52,7 @@
 #include "hash.h"
 
 #ifdef DEBUG
-int debug = 0;
+static int debug = 0;
 # define	DPRINTF(args) if (debug) { fflush(stdout); fprintf args; }
 #else
 # define	DPRINTF(args)
@@ -124,33 +124,32 @@
 	strnodelist	*keyword_list;
 };
 
-filenode fn_head_s, *fn_head;
+static filenode fn_head_s, *fn_head;
 
-strnodelist *bl_list;
-strnodelist *keep_list;
-strnodelist *skip_list;
+static strnodelist *bl_list;
+static strnodelist *keep_list;
+static strnodelist *skip_list;
 
-void do_file(filenode *fnode);
-void strnode_add(strnodelist **, char *, filenode *);
-int skip_ok(filenode *fnode);
-int keep_ok(filenode *fnode);
-void satisfy_req(f_reqnode *rnode, char *filename);
-void crunch_file(char *);
-void parse_require(filenode *, char *);
-void parse_provide(filenode *, char *);
-void parse_before(filenode *, char *);
-void parse_keywords(filenode *, char *);
-filenode *filenode_new(char *);
-void add_require(filenode *, char *);
-void add_provide(filenode *, char *);
-void add_before(filenode *, char *);
-void add_keyword(filenode *, char *);
-void insert_before(void);
-Hash_Entry *make_fake_provision(filenode *);
-void crunch_all_files(void);
-void initialize(void);
-void generate_ordering(void);
-int main(int, char *[]);
+static void do_file(filenode *fnode);
+static void strnode_add(strnodelist **, char *, filenode *);
+static int skip_ok(filenode *fnode);
+static int keep_ok(filenode *fnode);
+static void satisfy_req(f_reqnode *rnode, char *filename);
+static void crunch_file(char *);
+static void parse_require(filenode *, char *);
+static void parse_provide(filenode *, char *);
+static void parse_before(filenode *, char *);
+static void parse_keywords(filenode *, char *);
+static filenode *filenode_new(char *);
+static void add_require(filenode *, char *);
+static void add_provide(filenode *, char *);
+static void add_before(filenode *, char *);
+static void add_keyword(filenode *, char *);
+static void insert_before(void);
+static Hash_Entry *make_fake_provision(filenode *);
+static void crunch_all_files(void);
+static void initialize(void);
+static void generate_ordering(void);
 
 int
 main(int argc, char *argv[])
@@ -196,7 +195,7 @@
 /*
  * initialise various variables.
  */
-void
+static void
 initialize(void)
 {
 
@@ -207,7 +206,7 @@
 }
 
 /* generic function to insert a new strnodelist element */
-void
+static void
 strnode_add(strnodelist **listp, char *s, filenode *fnode)
 {
 	strnodelist *ent;
@@ -229,7 +228,7 @@
  * we have a new filename, create a new filenode structure.
  * fill in the bits, and put it in the filenode linked list
  */
-filenode *
+static filenode *
 filenode_new(char *filename)
 {
 	filenode *temp;
@@ -257,7 +256,7 @@
 /*
  * add a requirement to a filenode.
  */
-void
+static void
 add_require(filenode *fnode, char *s)
 {
 	Hash_Entry *entry;
@@ -277,7 +276,7 @@
  * add a provision to a filenode.  if this provision doesn't
  * have a head node, create one here.
  */
-void
+static void
 add_provide(filenode *fnode, char *s)
 {
 	Hash_Entry *entry;
@@ -356,7 +355,7 @@
 /*
  * put the BEFORE: lines to a list and handle them later.
  */
-void
+static void
 add_before(filenode *fnode, char *s)
 {
 	strnodelist *bf_ent;
@@ -371,7 +370,7 @@
 /*
  * add a key to a filenode.
  */
-void
+static void
 add_keyword(filenode *fnode, char *s)
 {
 
@@ -382,7 +381,7 @@
  * loop over the rest of a REQUIRE line, giving each word to
  * add_require() to do the real work.
  */
-void
+static void
 parse_require(filenode *node, char *buffer)
 {
 	char *s;
@@ -396,7 +395,7 @@
  * loop over the rest of a PROVIDE line, giving each word to
  * add_provide() to do the real work.
  */
-void
+static void
 parse_provide(filenode *node, char *buffer)
 {
 	char *s;
@@ -410,7 +409,7 @@
  * loop over the rest of a BEFORE line, giving each word to
  * add_before() to do the real work.
  */
-void
+static void
 parse_before(filenode *node, char *buffer)
 {
 	char *s;
@@ -424,7 +423,7 @@
  * loop over the rest of a KEYWORD line, giving each word to
  * add_keyword() to do the real work.
  */
-void
+static void
 parse_keywords(filenode *node, char *buffer)
 {
 	char *s;
@@ -438,7 +437,7 @@
  * given a file name, create a filenode for it, read in lines looking
  * for provision and requirement lines, building the graphs as needed.
  */
-void
+static void
 crunch_file(char *filename)
 {
 	FILE *fp;
@@ -510,7 +509,7 @@
 	fclose(fp);
 }
 
-Hash_Entry *
+static Hash_Entry *
 make_fake_provision(filenode *node)
 {
 	Hash_Entry *entry;
@@ -556,7 +555,7 @@
  * for each entry in the provision list for S, add a requirement to
  * that provisions filenode for P.
  */
-void
+static void
 insert_before(void)
 {
 	Hash_Entry *entry, *fake_prov_entry;
@@ -594,7 +593,7 @@
  * real work.  after we have built all the nodes, insert the BEFORE:
  * lines into graph(s).
  */
-void
+static void
 crunch_all_files(void)
 {
 	int i;
@@ -619,7 +618,7 @@
  * calling do_file() (enter recursion) for each filenode in this
  * provision.
  */
-void
+static void
 satisfy_req(f_reqnode *rnode, char *filename)
 {
 	Hash_Entry *entry;
@@ -660,7 +659,7 @@
 		do_file(head->next->fnode);
 }
 
-int
+static int
 skip_ok(filenode *fnode)
 {
 	strnodelist *s;
@@ -674,7 +673,7 @@
 	return (1);
 }
 
-int
+static int
 keep_ok(filenode *fnode)
 {
 	strnodelist *s;
@@ -699,7 +698,7 @@
  * safely free() anything related to items that may be recursed on.
  * Circular dependancies will cause problems if we do.
  */
-void
+static void
 do_file(filenode *fnode)
 {
 	f_reqnode *r, *r_tmp;
@@ -782,7 +781,7 @@
 #endif
 }
 
-void
+static void
 generate_ordering(void)
 {
 
diff -r 2230520c0499 -r 820af1e39cd6 head/sbin/reboot/reboot.c
--- a/head/sbin/reboot/reboot.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sbin/reboot/reboot.c	Thu Dec 15 12:59:38 2011 +0200
@@ -39,7 +39,7 @@
 #endif /* not lint */
 #endif
 #include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: head/sbin/reboot/reboot.c 228408 2011-12-11 11:42:44Z ed $");
 
 #include <sys/reboot.h>
 #include <sys/time.h>
@@ -60,7 +60,7 @@
 static void usage(void);
 static u_int get_pageins(void);
 
-int dohalt;
+static int dohalt;
 
 int
 main(int argc, char *argv[])
@@ -69,9 +69,9 @@
 	const struct passwd *pw;
 	int ch, howto, i, fd, lflag, nflag, qflag, sverrno;
 	u_int pageins;
-	const char *p, *user, *kernel = NULL;
+	const char *user, *kernel = NULL;
 
-	if (strstr((p = rindex(*argv, '/')) ? p + 1 : *argv, "halt")) {
+	if (strcmp(getprogname(), "halt") == 0) {
 		dohalt = 1;
 		howto = RB_HALT;
 	} else
diff -r 2230520c0499 -r 820af1e39cd6 head/share/examples/scsi_target/scsi_cmds.c
--- a/head/share/examples/scsi_target/scsi_cmds.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/share/examples/scsi_target/scsi_cmds.c	Thu Dec 15 12:59:38 2011 +0200
@@ -25,7 +25,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- * $FreeBSD: head/share/examples/scsi_target/scsi_cmds.c 225950 2011-10-03 20:32:55Z ken $
+ * $FreeBSD: head/share/examples/scsi_target/scsi_cmds.c 228462 2011-12-13 11:13:28Z mav $
  */
 
 #include <stdio.h>
@@ -103,8 +103,8 @@
 static struct scsi_inquiry_data inq_data;
 static struct initiator_state istates[MAX_INITIATORS];
 extern int		debug;
-extern uint64_t		volume_size;
-extern size_t		sector_size;
+extern off_t		volume_size;
+extern u_int		sector_size;
 extern size_t		buf_size;
 
 cam_status
@@ -609,7 +609,7 @@
 	if (dir == CAM_DIR_IN) {
 		if (notaio) {
 			if (debug)
-				warnx("read sync %lud @ block " OFF_FMT,
+				warnx("read sync %lu @ block " OFF_FMT,
 				    (unsigned long)
 				    (ctio->dxfer_len / sector_size),
 				    c_descr->offset / sector_size);
@@ -625,7 +625,7 @@
 			}
 		} else {
 			if (debug)
-				warnx("read async %lud @ block " OFF_FMT,
+				warnx("read async %lu @ block " OFF_FMT,
 				    (unsigned long)
 				    (ctio->dxfer_len / sector_size),
 				    c_descr->offset / sector_size);
@@ -725,7 +725,7 @@
 			a_descr->targ_req += ctio->dxfer_len;
 			if (notaio) {
 				if (debug)
-					warnx("write sync %lud @ block "
+					warnx("write sync %lu @ block "
 					    OFF_FMT, (unsigned long)
 					    (ctio->dxfer_len / sector_size),
 					    c_descr->offset / sector_size);
@@ -742,7 +742,7 @@
 				tcmd_rdwr_done(atio, ctio, AIO_DONE);
 			} else {
 				if (debug)
-					warnx("write async %lud @ block "
+					warnx("write async %lu @ block "
 					    OFF_FMT, (unsigned long)
 					    (ctio->dxfer_len / sector_size),
 					    c_descr->offset / sector_size);
diff -r 2230520c0499 -r 820af1e39cd6 head/share/examples/scsi_target/scsi_target.c
--- a/head/share/examples/scsi_target/scsi_target.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/share/examples/scsi_target/scsi_target.c	Thu Dec 15 12:59:38 2011 +0200
@@ -25,7 +25,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- * $FreeBSD: head/share/examples/scsi_target/scsi_target.c 225950 2011-10-03 20:32:55Z ken $
+ * $FreeBSD: head/share/examples/scsi_target/scsi_target.c 228481 2011-12-13 21:26:33Z ed $
  */
 
 #include <sys/types.h>
@@ -100,8 +100,8 @@
 int
 main(int argc, char *argv[])
 {
-	int ch, unit;
-	char *file_name, targname[16];
+	int ch;
+	char *file_name;
 	u_int16_t req_flags, sim_flags;
 	off_t user_size;
 
@@ -283,17 +283,11 @@
 			warnx("aio support tested ok");
 	}
 
-	/* Go through all the control devices and find one that isn't busy. */
-	unit = 0;
-	do {
-		snprintf(targname, sizeof(targname), "/dev/targ%d", unit++);
-    		targ_fd = open(targname, O_RDWR);
-	} while (targ_fd < 0 && errno == EBUSY);
-
+	targ_fd = open("/dev/targ", O_RDWR);
 	if (targ_fd < 0)
-    	    errx(1, "Tried to open %d devices, none available", unit);
+    	    err(1, "/dev/targ");
 	else
-	    warnx("opened %s", targname);
+	    warnx("opened /dev/targ");
 
 	/* The first three are handled by kevent() later */
 	signal(SIGHUP, SIG_IGN);
diff -r 2230520c0499 -r 820af1e39cd6 head/share/man/man4/Makefile
--- a/head/share/man/man4/Makefile	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/share/man/man4/Makefile	Thu Dec 15 12:59:38 2011 +0200
@@ -1,5 +1,5 @@
 #	@(#)Makefile	8.1 (Berkeley) 6/18/93
-# $FreeBSD: head/share/man/man4/Makefile 228174 2011-12-01 07:41:30Z lstewart $
+# $FreeBSD: head/share/man/man4/Makefile 228501 2011-12-14 15:19:40Z mav $
 
 MAN=	aac.4 \
 	acpi.4 \
@@ -116,6 +116,7 @@
 	epair.4 \
 	esp.4 \
 	et.4 \
+	eventtimers.4 \
 	exca.4 \
 	faith.4 \
 	fatm.4 \
@@ -499,6 +500,7 @@
 	vga.4 \
 	vge.4 \
 	viapm.4 \
+	${_viawd.4} \
 	vinum.4 \
 	vkbd.4 \
 	vlan.4 \
@@ -711,6 +713,7 @@
 _spkr.4=	spkr.4
 _tpm.4=		tpm.4
 _urtw.4=	urtw.4
+_viawd.4=	viawd.4
 _wpi.4=		wpi.4
 _xen.4=		xen.4
 
diff -r 2230520c0499 -r 820af1e39cd6 head/share/man/man4/altq.4
--- a/head/share/man/man4/altq.4	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/share/man/man4/altq.4	Thu Dec 15 12:59:38 2011 +0200
@@ -23,9 +23,9 @@
 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 .\" SUCH DAMAGE.
 .\"
-.\" $FreeBSD: head/share/man/man4/altq.4 227348 2011-11-08 18:35:11Z yongari $
+.\" $FreeBSD: head/share/man/man4/altq.4 228370 2011-12-09 19:17:51Z yongari $
 .\"
-.Dd November 8, 2011
+.Dd December 9, 2011
 .Dt ALTQ 4
 .Os
 .Sh NAME
@@ -134,6 +134,7 @@
 .Xr em 4 ,
 .Xr ep 4 ,
 .Xr epair 4 ,
+.Xr et 4 ,
 .Xr fxp 4 ,
 .Xr gem 4 ,
 .Xr hme 4 ,
diff -r 2230520c0499 -r 820af1e39cd6 head/share/man/man4/atrtc.4
--- a/head/share/man/man4/atrtc.4	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/share/man/man4/atrtc.4	Thu Dec 15 12:59:38 2011 +0200
@@ -22,7 +22,7 @@
 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 .\" SUCH DAMAGE.
 .\"
-.\" $FreeBSD: head/share/man/man4/atrtc.4 222286 2011-05-25 14:13:53Z ru $
+.\" $FreeBSD: head/share/man/man4/atrtc.4 228501 2011-12-14 15:19:40Z mav $
 .\"
 .Dd September 17, 2010
 .Dt ATRTC 4
@@ -53,4 +53,4 @@
 .Sh SEE ALSO
 .Xr attimer 4 ,
 .Xr hpet 4 ,
-.Xr eventtimers 7
+.Xr eventtimers 4
diff -r 2230520c0499 -r 820af1e39cd6 head/share/man/man4/attimer.4
--- a/head/share/man/man4/attimer.4	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/share/man/man4/attimer.4	Thu Dec 15 12:59:38 2011 +0200
@@ -22,7 +22,7 @@
 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 .\" SUCH DAMAGE.
 .\"
-.\" $FreeBSD: head/share/man/man4/attimer.4 222286 2011-05-25 14:13:53Z ru $
+.\" $FreeBSD: head/share/man/man4/attimer.4 228501 2011-12-14 15:19:40Z mav $
 .\"
 .Dd September 14, 2010
 .Dt ATTIMER 4
@@ -72,4 +72,4 @@
 .Sh SEE ALSO
 .Xr atrtc 4 ,
 .Xr hpet 4 ,
-.Xr eventtimers 7
+.Xr eventtimers 4
diff -r 2230520c0499 -r 820af1e39cd6 head/share/man/man4/et.4
--- a/head/share/man/man4/et.4	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/share/man/man4/et.4	Thu Dec 15 12:59:38 2011 +0200
@@ -28,9 +28,9 @@
 .\" OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 .\" SUCH DAMAGE.
 .\"
-.\" $FreeBSD$
+.\" $FreeBSD: head/share/man/man4/et.4 228370 2011-12-09 19:17:51Z yongari $
 .\"
-.Dd November 25, 2010
+.Dd December 9, 2011
 .Dt ET 4
 .Os
 .Sh NAME
@@ -156,6 +156,7 @@
 The default value is 1000000000 (nanoseconds).
 .El
 .Sh SEE ALSO
+.Xr altq 4 ,
 .Xr arp 4 ,
 .Xr miibus 4 ,
 .Xr netintro 4 ,
diff -r 2230520c0499 -r 820af1e39cd6 head/share/man/man4/eventtimers.4
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/head/share/man/man4/eventtimers.4	Thu Dec 15 12:59:38 2011 +0200
@@ -0,0 +1,133 @@
+.\" Copyright (c) 2010 Alexander Motin <mav at FreeBSD.org>
+.\" All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\"    notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\"    notice, this list of conditions and the following disclaimer in the
+.\"    documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+.\" ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+.\" SUCH DAMAGE.
+.\"
+.\" $FreeBSD: head/share/man/man4/eventtimers.4 228501 2011-12-14 15:19:40Z mav $
+.\"
+.Dd September 15, 2010
+.Dt EVENTTIMERS 4
+.Os
+.Sh NAME
+.Nm eventtimers
+.Nd kernel event timers subsystem
+.Sh SYNOPSIS
+Kernel uses several types of time-related devices, such as: real time clocks,
+time counters and event timers.
+Real time clocks responsible for tracking real world time, mostly when system
+is down.
+Time counters are responsible for generation of monotonically increasing
+timestamps for precise uptime tracking purposes, when system is running.
+Event timers are responsible for generating interrupts at specified time or
+periodically, to run different time-based events.
+This page is about the last.
+.Sh DESCRIPTION
+Kernel uses time-based events for many different purposes: scheduling,
+statistics, time keeping, profiling and many other things, based on
+.Xr callout 9
+mechanism.
+These purposes now grouped into three main callbacks:
+.Bl -tag
+.It hardclock()
+.Xr callout 9
+and timekeeping events entry. Called with frequency defined by hz variable,
+usually 1000Hz.
+.It statclock()
+statistics and scheduler events entry. Called with frequency about 128Hz.
+.It profclock()
+profiler events entry. When enabled, called with frequency about 8KHz.
+.El
+Different platforms provide different kinds of timer hardware.
+The goal of the event timers subsystem is to provide unified way to control
+that hardware, and to use it, supplying kernel with all required time-based
+events.
+.Pp
+Each driver implementing event timers, registers them at the subsystem.
+It is possible to see the list of present event timers, like this, via
+.Va kern.eventtimer
+sysctl:
+.Bd -literal
+kern.eventtimer.choice: HPET(550) LAPIC(400) i8254(100) RTC(0)
+kern.eventtimer.et.LAPIC.flags: 15
+kern.eventtimer.et.LAPIC.frequency: 0
+kern.eventtimer.et.LAPIC.quality: 400
+kern.eventtimer.et.i8254.flags: 1
+kern.eventtimer.et.i8254.frequency: 1193182
+kern.eventtimer.et.i8254.quality: 100
+kern.eventtimer.et.RTC.flags: 17
+kern.eventtimer.et.RTC.frequency: 32768
+kern.eventtimer.et.RTC.quality: 0
+kern.eventtimer.et.HPET.flags: 7
+kern.eventtimer.et.HPET.frequency: 14318180
+kern.eventtimer.et.HPET.quality: 550
+.Ed
+, where:
+.Bl -tag
+.It Va kern.eventtimer.et. Ns Ar X Ns Va .flags
+bitmask, defining event timer capabilities:
+.Bl -tag -compact
+.It 1
+periodic mode supported,
+.It 2
+one-shot mode supported,
+.It 4
+timer is per-CPU,
+.It 8
+timer may stop when CPU goes to sleep state,
+.It 16
+timer supports only power-of-2 divisors.
+.El
+.It Va kern.eventtimer.et. Ns Ar X Ns Va .frequency
+timer base frequency,
+.It Va kern.eventtimer.et. Ns Ar X Ns Va .quality
+integral value, defining how good is this timer, comparing to others.
+.El
+.Pp
+Timers management code of the kernel chooses one timer from that list.
+Current choice can be read and affected via
+.Va kern.eventtimer.timer
+tunable/sysctl.
+Several other tunables/sysctls are affecting how exactly this timer is used:
+.Bl -tag
+.It Va kern.eventtimer.periodic
+allows to choose periodic and one-shot operation mode.
+In periodic mode, periodic interrupts from timer hardware are taken as the
+only source of time for time events.
+One-shot mode instead uses currently selected time counter to precisely
+schedule all needed events and programs event timer to generate interrupt
+exactly in specified time.
+Default value depends of chosen timer capabilities, but one-shot mode is
+preferred, until other is forced by user or hardware.
+.It Va kern.eventtimer.singlemul
+in periodic mode specifies how much times higher timer frequency should be,
+to not strictly alias hardclock() and statclock() events. Default values are
+1, 2 or 4, depending on configured HZ value.
+.It Va kern.eventtimer.idletick
+makes each CPU to receive every timer interrupt independently of whether they
+busy or not. By default this options is disabled. If chosen timer is per-CPU
+and runs in periodic mode, this option has no effect - all interrupts are
+always generating.
+.El
+.Sh SEE ALSO
+.Xr attimer 4 ,
+.Xr atrtc 4 ,
+.Xr hpet 4
diff -r 2230520c0499 -r 820af1e39cd6 head/share/man/man4/hpet.4
--- a/head/share/man/man4/hpet.4	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/share/man/man4/hpet.4	Thu Dec 15 12:59:38 2011 +0200
@@ -22,7 +22,7 @@
 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 .\" SUCH DAMAGE.
 .\"
-.\" $FreeBSD: head/share/man/man4/hpet.4 221938 2011-05-15 01:01:53Z mav $
+.\" $FreeBSD: head/share/man/man4/hpet.4 228501 2011-12-14 15:19:40Z mav $
 .\"
 .Dd September 14, 2010
 .Dt HPET 4
@@ -96,7 +96,7 @@
 .Xr acpi 4 ,
 .Xr atrtc 4 ,
 .Xr attimer 4 ,
-.Xr eventtimers 7
+.Xr eventtimers 4
 .Sh HISTORY
 The
 .Nm
diff -r 2230520c0499 -r 820af1e39cd6 head/share/man/man4/splash.4
--- a/head/share/man/man4/splash.4	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/share/man/man4/splash.4	Thu Dec 15 12:59:38 2011 +0200
@@ -24,7 +24,7 @@
 .\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 .\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 .\"
-.\" $FreeBSD$
+.\" $FreeBSD: head/share/man/man4/splash.4 228445 2011-12-12 21:12:07Z eadler $
 .\"
 .Dd November 29, 2010
 .Dt SPLASH 4
@@ -74,6 +74,14 @@
 ZSoft PCX decoder.
 This decoder currently only supports version 5 8-bpp single-plane
 images.
+.It Pa splash_txt.ko
+TheDraw binary ASCII drawing file decoder.
+Displays a text-mode 80x25 ASCII drawing, such as that produced by
+the Binary save format in TheDraw.
+This format consists of a sequence
+of two byte pairs representing the 80x25 display, where the first byte
+is the ASCII character to draw and the second byte indicates the
+colors/attributes to use when drawing the character.
 .El
 .Pp
 The
@@ -223,6 +231,16 @@
 necessary to load the VESA module.
 Just load the bitmap file and the splash decoder module as in the
 first example above.
+.Pp
+To load a binary ASCII drawing and display this while booting, include the
+following into your
+.Pa /boot/loader.conf
+:
+.Bd -literal -offset indent
+splash_txt_load="YES"
+bitmap_load="YES"
+bitmap_name="/boot/splash.bin"
+.Ed
 .\".Sh DIAGNOSTICS
 .Sh SEE ALSO
 .Xr vidcontrol 1 ,
@@ -256,6 +274,15 @@
 based on the
 .Pa splash_bmp
 code.
+The
+.Pa splash_txt
+module was written by
+.An Antony Mawer Aq antony at mawer.org
+based on the
+.Pa splash_bmp
+code, with some additional inspiration from the
+.Pa daemon_saver
+code.
 .Sh CAVEATS
 Both the splash screen and the screen saver work with
 .Xr syscons 4
diff -r 2230520c0499 -r 820af1e39cd6 head/share/man/man4/targ.4
--- a/head/share/man/man4/targ.4	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/share/man/man4/targ.4	Thu Dec 15 12:59:38 2011 +0200
@@ -22,9 +22,9 @@
 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 .\" SUCH DAMAGE.
 .\"
-.\" $FreeBSD$
+.\" $FreeBSD: head/share/man/man4/targ.4 228481 2011-12-13 21:26:33Z ed $
 .\"
-.Dd November 15, 2002
+.Dd December 13, 2011
 .Dt TARG 4
 .Os
 .Sh NAME
@@ -49,16 +49,8 @@
 .Pp
 The
 .Nm
-driver supplies control devices,
-.Pa /dev/targ0 ,
-.Pa /dev/targ1 ,
-etc.
-If a device is already in use,
-.Xr open 2
-will fail and
-.Va errno
-will be set to
-.Er EBUSY .
+driver supplies the control device
+.Pa /dev/targ .
 After opening the device, the file descriptor must be bound to a
 specific bus/target/LUN and enabled to process CCBs using the
 .Dv TARGIOCENABLE
@@ -123,8 +115,8 @@
 describes the usermode interface.
 .It Pa /sys/cam/scsi/scsi_target.c
 is the driver source file.
-.It Pa /dev/targ*
-are the control devices.
+.It Pa /dev/targ
+is the control device.
 .El
 .Sh SEE ALSO
 .Pa /usr/share/examples/scsi_target ,
diff -r 2230520c0499 -r 820af1e39cd6 head/share/man/man4/viawd.4
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/head/share/man/man4/viawd.4	Thu Dec 15 12:59:38 2011 +0200
@@ -0,0 +1,79 @@
+.\"-
+.\" Copyright (c) 2011 Fabien Thomas <fabient at FreeBSD.org>
+.\" All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\"    notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\"    notice, this list of conditions and the following disclaimer in the
+.\"    documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS `AS IS'' AND
+.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+.\" ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+.\" SUCH DAMAGE.
+.\"
+.\" $FreeBSD: head/share/man/man4/viawd.4 228431 2011-12-12 09:50:33Z fabient $
+.\"
+.Dd December 7, 2011
+.Dt VIAWD 4
+.Os
+.Sh NAME
+.Nm viawd
+.Nd device driver for VIA south bridge watchdog timer
+.Sh SYNOPSIS
+To compile this driver into the kernel,
+place the following line in your
+kernel configuration file:
+.Bd -ragged -offset indent
+.Cd "device viawd"
+.Ed
+.Pp
+Alternatively, to load the driver as a
+module at boot time, place the following line in
+.Xr loader.conf 5 :
+.Bd -literal -offset indent
+viawd_load="YES"
+.Ed
+.Sh DESCRIPTION
+The
+.Nm
+driver provides
+.Xr watchdog 4
+support for the watchdog interrupt timer present on
+VIA south bridge chipset (VT8251, CX700, VX800, VX855, VX900).
+.Pp
+The VIA south bridge have a built-in watchdog timer,
+which can be enabled and disabled by user's program and set between
+1 to 1023 seconds.
+.Pp
+The
+.Nm
+driver when unloaded with running watchdog will reschedule the watchdog
+to 5 minutes.
+.Sh SEE ALSO
+.Xr watchdog 4 ,
+.Xr watchdog 8 ,
+.Xr watchdogd 8 ,
+.Xr watchdog 9
+.Sh HISTORY
+The
+.Nm
+driver first appeared in
+.Fx 10.0 .
+.Sh AUTHORS
+.An -nosplit
+The
+.Nm
+driver and this manual page were written by
+.An Fabien Thomas Aq fabient at FreeBSD.org .
diff -r 2230520c0499 -r 820af1e39cd6 head/share/man/man5/make.conf.5
--- a/head/share/man/man5/make.conf.5	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/share/man/man5/make.conf.5	Thu Dec 15 12:59:38 2011 +0200
@@ -22,9 +22,9 @@
 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 .\" SUCH DAMAGE.
 .\"
-.\" $FreeBSD: head/share/man/man5/make.conf.5 223148 2011-06-16 12:28:37Z ru $
+.\" $FreeBSD: head/share/man/man5/make.conf.5 228419 2011-12-11 20:01:37Z gjb $
 .\"
-.Dd June 16, 2011
+.Dd December 11, 2011
 .Dt MAKE.CONF 5
 .Os
 .Sh NAME
@@ -333,6 +333,12 @@
 .Pa src
 tree with
 .Dq Li "make update" .
+Note that since a subversion client is not included in the base system,
+you will need to set
+.Va SVN
+to the full path of a
+.Xr svn 1
+binary.
 .It Va WWWSUPFILE
 .Pq Vt str
 The www
@@ -494,7 +500,7 @@
 .Pq Vt bool
 Defining this and recompiling
 .Pa /usr/src/sys/boot/i386
-will add 
+will add
 .Xr dcons 4
 console driver to
 .Xr loader 8
@@ -634,7 +640,7 @@
 .Pq Vt str
 Additional maps to rebuild when using
 .Pa /etc/mail/Makefile .
-The 
+The
 .Pa access ,
 .Pa bitdomain ,
 .Pa domaintable ,
diff -r 2230520c0499 -r 820af1e39cd6 head/share/man/man5/periodic.conf.5
--- a/head/share/man/man5/periodic.conf.5	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/share/man/man5/periodic.conf.5	Thu Dec 15 12:59:38 2011 +0200
@@ -23,9 +23,9 @@
 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 .\" SUCH DAMAGE.
 .\"
-.\" $FreeBSD$
+.\" $FreeBSD: head/share/man/man5/periodic.conf.5 228355 2011-12-08 23:58:26Z gjb $
 .\"
-.Dd June 15, 2010
+.Dd December 8, 2011
 .Dt PERIODIC.CONF 5
 .Os
 .Sh NAME
@@ -631,7 +631,7 @@
 .It Va daily_scrub_zfs_default_threshold
 .Pq Vt int
 Number of days between a scrub if no pool-specific threshold is set.
-The default value if no value is set is 30.
+If not set, the default value is 35, corresponding to 5 weeks.
 .It Va daily_scrub_zfs_ Ns Ao Ar poolname Ac Ns Va _threshold
 .Pq Vt int
 The same as
diff -r 2230520c0499 -r 820af1e39cd6 head/share/man/man5/rc.conf.5
--- a/head/share/man/man5/rc.conf.5	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/share/man/man5/rc.conf.5	Thu Dec 15 12:59:38 2011 +0200
@@ -22,9 +22,9 @@
 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 .\" SUCH DAMAGE.
 .\"
-.\" $FreeBSD: head/share/man/man5/rc.conf.5 226658 2011-10-23 10:20:31Z mm $
+.\" $FreeBSD: head/share/man/man5/rc.conf.5 228457 2011-12-13 08:23:03Z ru $
 .\"
-.Dd October 23, 2011
+.Dd December 13, 2011
 .Dt RC.CONF 5
 .Os
 .Sh NAME
@@ -1101,7 +1101,9 @@
 .Pp
 It is also possible to add IP alias entries using
 .Xr ifconfig 8
-syntax.
+syntax with the
+.Dq Li inet
+keyword.
 Assuming that the interface in question was
 .Li ed0 ,
 it might look
@@ -1114,7 +1116,9 @@
 And so on.
 For each
 .Va ifconfig_ Ns Ao Ar interface Ac Ns Va _alias Ns Aq Ar n
-entry that is found,
+entry with the
+.Dq Li inet
+keyword that is found,
 its contents are passed to
 .Xr ifconfig 8 .
 Execution stops at the first unsuccessful access, so if
diff -r 2230520c0499 -r 820af1e39cd6 head/share/man/man7/Makefile
--- a/head/share/man/man7/Makefile	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/share/man/man7/Makefile	Thu Dec 15 12:59:38 2011 +0200
@@ -1,5 +1,5 @@
 #	@(#)Makefile	8.1 (Berkeley) 6/5/93
-# $FreeBSD$
+# $FreeBSD: head/share/man/man7/Makefile 228501 2011-12-14 15:19:40Z mav $
 
 #MISSING: eqnchar.7 ms.7 term.7
 MAN=	adding_user.7 \
@@ -10,7 +10,6 @@
 	c99.7 \
 	development.7 \
 	environ.7 \
-	eventtimers.7 \
 	ffs.7 \
 	firewall.7 \
 	hier.7 \
diff -r 2230520c0499 -r 820af1e39cd6 head/share/man/man7/eventtimers.7
--- a/head/share/man/man7/eventtimers.7	Sun Dec 11 15:53:23 2011 +0200
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,133 +0,0 @@
-.\" Copyright (c) 2010 Alexander Motin <mav at FreeBSD.org>
-.\" All rights reserved.
-.\"
-.\" Redistribution and use in source and binary forms, with or without
-.\" modification, are permitted provided that the following conditions
-.\" are met:
-.\" 1. Redistributions of source code must retain the above copyright
-.\"    notice, this list of conditions and the following disclaimer.
-.\" 2. Redistributions in binary form must reproduce the above copyright
-.\"    notice, this list of conditions and the following disclaimer in the
-.\"    documentation and/or other materials provided with the distribution.
-.\"
-.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
-.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-.\" ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
-.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-.\" SUCH DAMAGE.
-.\"
-.\" $FreeBSD: head/share/man/man7/eventtimers.7 222286 2011-05-25 14:13:53Z ru $
-.\"
-.Dd September 15, 2010
-.Dt EVENTTIMERS 4
-.Os
-.Sh NAME
-.Nm eventtimers
-.Nd kernel event timers subsystem
-.Sh SYNOPSIS
-Kernel uses several types of time-related devices, such as: real time clocks,
-time counters and event timers.
-Real time clocks responsible for tracking real world time, mostly when system
-is down.
-Time counters are responsible for generation of monotonically increasing
-timestamps for precise uptime tracking purposes, when system is running.
-Event timers are responsible for generating interrupts at specified time or
-periodically, to run different time-based events.
-This page is about the last.
-.Sh DESCRIPTION
-Kernel uses time-based events for many different purposes: scheduling,
-statistics, time keeping, profiling and many other things, based on
-.Xr callout 9
-mechanism.
-These purposes now grouped into three main callbacks:
-.Bl -tag
-.It hardclock()
-.Xr callout 9
-and timekeeping events entry. Called with frequency defined by hz variable,
-usually 1000Hz.
-.It statclock()
-statistics and scheduler events entry. Called with frequency about 128Hz.
-.It profclock()
-profiler events entry. When enabled, called with frequency about 8KHz.
-.El
-Different platforms provide different kinds of timer hardware.
-The goal of the event timers subsystem is to provide unified way to control
-that hardware, and to use it, supplying kernel with all required time-based
-events.
-.Pp
-Each driver implementing event timers, registers them at the subsystem.
-It is possible to see the list of present event timers, like this, via
-.Va kern.eventtimer
-sysctl:
-.Bd -literal
-kern.eventtimer.choice: HPET(550) LAPIC(400) i8254(100) RTC(0)
-kern.eventtimer.et.LAPIC.flags: 15
-kern.eventtimer.et.LAPIC.frequency: 0
-kern.eventtimer.et.LAPIC.quality: 400
-kern.eventtimer.et.i8254.flags: 1
-kern.eventtimer.et.i8254.frequency: 1193182
-kern.eventtimer.et.i8254.quality: 100
-kern.eventtimer.et.RTC.flags: 17
-kern.eventtimer.et.RTC.frequency: 32768
-kern.eventtimer.et.RTC.quality: 0
-kern.eventtimer.et.HPET.flags: 7
-kern.eventtimer.et.HPET.frequency: 14318180
-kern.eventtimer.et.HPET.quality: 550
-.Ed
-, where:
-.Bl -tag
-.It Va kern.eventtimer.et. Ns Ar X Ns Va .flags
-bitmask, defining event timer capabilities:
-.Bl -tag -compact
-.It 1
-periodic mode supported,
-.It 2
-one-shot mode supported,
-.It 4
-timer is per-CPU,
-.It 8
-timer may stop when CPU goes to sleep state,
-.It 16
-timer supports only power-of-2 divisors.
-.El
-.It Va kern.eventtimer.et. Ns Ar X Ns Va .frequency
-timer base frequency,
-.It Va kern.eventtimer.et. Ns Ar X Ns Va .quality
-integral value, defining how good is this timer, comparing to others.
-.El
-.Pp
-Timers management code of the kernel chooses one timer from that list.
-Current choice can be read and affected via
-.Va kern.eventtimer.timer
-tunable/sysctl.
-Several other tunables/sysctls are affecting how exactly this timer is used:
-.Bl -tag
-.It Va kern.eventtimer.periodic
-allows to choose periodic and one-shot operation mode.
-In periodic mode, periodic interrupts from timer hardware are taken as the
-only source of time for time events.
-One-shot mode instead uses currently selected time counter to precisely
-schedule all needed events and programs event timer to generate interrupt
-exactly in specified time.
-Default value depends of chosen timer capabilities, but one-shot mode is
-preferred, until other is forced by user or hardware.
-.It Va kern.eventtimer.singlemul
-in periodic mode specifies how much times higher timer frequency should be,
-to not strictly alias hardclock() and statclock() events. Default values are
-1, 2 or 4, depending on configured HZ value.
-.It Va kern.eventtimer.idletick
-makes each CPU to receive every timer interrupt independently of whether they
-busy or not. By default this options is disabled. If chosen timer is per-CPU
-and runs in periodic mode, this option has no effect - all interrupts are
-always generating.
-.El
-.Sh SEE ALSO
-.Xr attimer 4 ,
-.Xr atrtc 4 ,
-.Xr hpet 4
diff -r 2230520c0499 -r 820af1e39cd6 head/share/man/man8/yp.8
--- a/head/share/man/man8/yp.8	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/share/man/man8/yp.8	Thu Dec 15 12:59:38 2011 +0200
@@ -26,9 +26,9 @@
 .\" SUCH DAMAGE.
 .\"
 .\"     from: @(#)yp.8	1.0 (deraadt) 4/26/93
-.\" $FreeBSD$
+.\" $FreeBSD: head/share/man/man8/yp.8 228505 2011-12-14 19:48:21Z joel $
 .\"
-.Dd June 25, 2009
+.Dd December 14, 2011
 .Dt YP 8
 .Os
 .Sh NAME
@@ -519,6 +519,20 @@
 .Xr ypserv 8
 manual page for a detailed description of these special features
 and flags.)
+.Sh SEE ALSO
+.Xr domainname 1 ,
+.Xr ypcat 1 ,
+.Xr ypmatch 1 ,
+.Xr ypwhich 1 ,
+.Xr nsswitch.conf 5 ,
+.Xr yp_mkdb 8 ,
+.Xr ypbind 8 ,
+.Xr ypinit 8 ,
+.Xr yppoll 8 ,
+.Xr yppush 8 ,
+.Xr ypserv 8 ,
+.Xr ypset 8 ,
+.Xr ypxfr 8
 .Sh HISTORY
 The
 .Nm YP
diff -r 2230520c0499 -r 820af1e39cd6 head/share/man/man9/Makefile
--- a/head/share/man/man9/Makefile	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/share/man/man9/Makefile	Thu Dec 15 12:59:38 2011 +0200
@@ -1,4 +1,4 @@
-# $FreeBSD: head/share/man/man9/Makefile 227537 2011-11-15 20:11:03Z marius $
+# $FreeBSD: head/share/man/man9/Makefile 228509 2011-12-14 22:22:19Z jhb $
 
 MAN=	accept_filter.9 \
 	accf_data.9 \
@@ -234,6 +234,7 @@
 	sema.9 \
 	sf_buf.9 \
 	sglist.9 \
+	shm_map.9 \
 	signal.9 \
 	sleep.9 \
 	sleepqueue.9 \
@@ -1023,8 +1024,12 @@
 	rmlock.9 rm_wunlock.9
 MLINKS+=rtalloc.9 rtalloc1.9 \
 	rtalloc.9 rtalloc_ign.9 \
+	rtalloc.9 RTFREE_LOCKED.9 \
 	rtalloc.9 RTFREE.9 \
-	rtalloc.9 rtfree.9
+	rtalloc.9 rtfree.9 \
+	rtalloc.9 rtalloc1_fib.9 \
+	rtalloc.9 rtalloc_ign_fib.9 \
+	rtalloc.9 rtalloc_fib.9
 MLINKS+=runqueue.9 choosethread.9 \
 	runqueue.9 procrunnable.9 \
 	runqueue.9 remrunqueue.9 \
@@ -1107,6 +1112,7 @@
 	sglist.9 sglist_reset.9 \
 	sglist.9 sglist_slice.9 \
 	sglist.9 sglist_split.9
+MLINKS+=shm_map.9 shm_unmap.9
 MLINKS+=signal.9 cursig.9 \
 	signal.9 execsigs.9 \
 	signal.9 issignal.9 \
diff -r 2230520c0499 -r 820af1e39cd6 head/share/man/man9/rtalloc.9
--- a/head/share/man/man9/rtalloc.9	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/share/man/man9/rtalloc.9	Thu Dec 15 12:59:38 2011 +0200
@@ -26,162 +26,165 @@
 .\" OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 .\" SUCH DAMAGE.
 .\"
-.\" $FreeBSD$
+.\" $FreeBSD: head/share/man/man9/rtalloc.9 228499 2011-12-14 14:52:50Z glebius $
 .\"
-.Dd December 11, 2008
+.Dd December 14, 2011
 .Dt RTALLOC 9
 .Os
 .Sh NAME
-.Nm rtalloc ,
-.Nm rtalloc_ign ,
-.Nm rtalloc1 ,
-.Nm rtfree
+.Nm rtalloc1_fib ,
+.Nm rtalloc_ign_fib ,
+.Nm rtalloc_fib
 .Nd look up a route in the kernel routing table
 .Sh SYNOPSIS
 .In sys/types.h
 .In sys/socket.h
 .In net/route.h
+.Ft "struct rtentry *"
+.Fn rtalloc1_fib "struct sockaddr *dst" "int report" "u_long flags" "u_int fibnum"
 .Ft void
-.Fn rtalloc "struct route *ro"
+.Fn rtalloc_fib "struct route *ro" "u_int fibnum"
 .Ft void
-.Fn rtalloc_ign "struct route *ro" "u_long flags"
-.Ft "struct rtentry *"
-.Fn rtalloc1 "struct sockaddr *sa" "int report" "u_long flags"
-.Ft void
-.Fn rtfree "struct rt_entry *rt"
+.Fn rtalloc_ign_fib "struct route *ro" "u_long flags" "u_int fibnum"
+.Fn RTFREE_LOCKED "struct rt_entry *rt"
 .Fn RTFREE "struct rt_entry *rt"
 .Fn RT_LOCK "struct rt_entry *rt"
 .Fn RT_UNLOCK "struct rt_entry *rt"
 .Fn RT_ADDREF "struct rt_entry *rt"
 .Fn RT_REMREF "struct rt_entry *rt"
+.Ft void
+.Fn rtfree "struct rt_entry *rt"
+.Ft "struct rtentry *"
+.Fn rtalloc1 "struct sockaddr *dst" "int report" "u_long flags"
+.Ft void
+.Fn rtalloc "struct route *ro"
+.Ft void
+.Fn rtalloc_ign "struct route *ro" "u_long flags"
+.Pp
+.Cd options RADIX_MPATH
 .Sh DESCRIPTION
 The kernel uses a radix tree structure to manage routes for the
 networking subsystem.
+If compiled with
+.Cd options RADIX_MPATH
+kernel may maintain several independent forwarding information databases (FIBs).
 The
 .Fn rtalloc
-family of routines is used by protocols to query this structure for a
+family of routines is used by protocols to query these structures for a
 route corresponding to a particular end-node address, and to cause
 certain protocol\- and interface-specific actions to take place.
-.\" XXX - -mdoc should contain a standard request for getting em and
-.\" en dashes.
 .Pp
-.Dv RTF_PRCLONING
-flag is obsolete and thus ignored by facility.
-If the
-.Dv RTF_XRESOLVE
-flag is set, then the
-.Dv RTM_RESOLVE
-message is sent instead on the
-.Xr route 4
-socket interface, requesting that an external program resolve the
-address in question and modify the route appropriately.
+The
+.Fn rtalloc1_fib
+function is the most general form of
+.Fn rtalloc ,
+and all of the other forms are implemented as calls to it.
+It takes a
+.Fa "struct sockaddr *"
+directly as the
+.Fa dst
+argument.
+The second argument,
+.Fa report ,
+controls whether the routing sockets are notified when a lookup fails.
+The third argument,
+.Fa flags ,
+is a combination of
+the following values:
+.Bl -item -offset indent
+.It
+.Dv RTF_RNH_LOCKED
+indicates that the radix tree lock is already held
+.El
 .Pp
-The default interface is
-.Fn rtalloc .
-Its only argument is
+The last argument
+.Fa fibnum
+specifies number of forwarding information database (FIB) on which
+the lookup should be performed.
+In case of success the
+.Fn rtalloc1_fib
+function returns a pointer to a locked
+.Vt "struct rtentry"
+with an additional reference.
+.Pp
+The
+.Fn rtalloc_fib
+is the most simple variant.
+Its main argument is
 .Fa ro ,
 a pointer to a
-.Dq Li "struct route" ,
+.Fa "struct route" ,
 which is defined as follows:
 .Bd -literal -offset indent
 struct route {
+	struct rtentry *ro_rt;
+	struct llentry *ro_lle;
 	struct sockaddr ro_dst;
-	struct rtentry *ro_rt;
 };
 .Ed
 .Pp
 Thus, this function can only be used for address families which are
 smaller than the default
-.Dq Li "struct sockaddr" .
+.Ft "struct sockaddr" .
 Before calling
-.Fn rtalloc
+.Fn rtalloc_fib
 for the first time, callers should ensure that unused bits of the
 structure are set to zero.
+The second argument
+.Fa fibnum
+is FIB number.
+In case of success of the
+.Fn rtalloc_fib
+the
+.Fa ro_rt
+points to a valid and unlocked
+.Xr rtentry 9 ,
+which has an additional reference put on it, freeing which is
+responsibility of the caller.
 On subsequent calls,
-.Fn rtalloc
+.Fn rtalloc_fib
 returns without performing a lookup if
 .Fa ro->ro_rt
 is non-null and the
 .Dv RTF_UP
-flag is set in the route's
-.Li rt_flags
+flag is set in the rtentry's
+.Fa rt_flags
 field.
 .Pp
 The
-.Fn rtalloc_ign
-interface can be used when the caller does not want to receive
-the returned
-.Fa rtentry
-locked.
-The
-.Fa ro
-argument is the same as
-.Fn rtalloc ,
-but there is additionally a
+.Fn rtalloc_ign_fib
+function is the same as the
+.Fn rtalloc_fib ,
+but there is additional
 .Fa flags
-argument, which is now only used to pass
-.Dv RTF_RNH_LOCKED
-indicating that the radix tree lock is already held.
-Both
-.Fn rtalloc
-and
-.Fn rtalloc_ign
-functions return a pointer to an unlocked
-.Vt "struct rtentry" .
+argument, which is same as in
+.Fn rtalloc1_fib .
 .Pp
 The
-.Fn rtalloc1
-function is the most general form of
-.Fn rtalloc
-(and both of the other forms are implemented as calls to rtalloc1).
-It does not use the
-.Dq Li "struct route" ,
-and is therefore suitable for address families which require more
-space than is in a traditional
-.Dq Li "struct sockaddr" .
-Instead, it takes a
-.Dq Li "struct sockaddr *"
-directly as the
-.Fa sa
-argument.
-The second argument,
-.Fa report ,
-controls whether the lower layers are notified when a lookup fails.
-The third argument,
-.Fa flags ,
-is a set of flags to ignore, as in
-.Fn rtalloc_ign .
-The
-.Fn rtalloc1
-function returns a pointer to a locked
-.Vt "struct rtentry" .
-.Pp
-The
-.Fn rtfree
-function frees a locked route entry, e.g., a previously allocated by
-.Fn rtalloc1 .
+.Fn RTFREE_LOCKED
+macro is used to unref and possibly free a locked routing entry
+with one our reference, for example previously allocated by
+.Fn rtalloc1_fib .
 .Pp
 The
 .Fn RTFREE
-macro is used to free unlocked route entries, previously allocated by
-.Fn rtalloc
+macro is used to unref and possibly free an unlocked route entries with
+one our reference, for example previously allocated by
+.Fn rtalloc_fib
 or
-.Fn rtalloc_ign .
-The
+.Fn rtalloc_ign_fib .
+.Pp
+Both
+.Fn RTFREE_LOCKED
+and
 .Fn RTFREE
-macro decrements the reference count on the routing table entry (see below),
-and frees it if the reference count has reached zero.
-.Pp
-The preferred usage is allocating a route using
-.Fn rtalloc
-or
-.Fn rtalloc_ign
-and freeing using
-.Fn RTFREE .
+macros decrement the reference count on the routing table entry,
+and proceed with actual freeing if the reference count has reached zero.
 .Pp
 The
 .Fn RT_LOCK
 macro is used to lock a routing table entry.
+.Pp
 The
 .Fn RT_UNLOCK
 macro is used to unlock a routing table entry.
@@ -189,20 +192,53 @@
 The
 .Fn RT_ADDREF
 macro increments the reference count on a previously locked route entry.
+It should be used whenever a reference to an
+.Xr rtentry 9
+is going to be stored outside the routing table.
+.Pp
 The
 .Fn RT_REMREF
 macro decrements the reference count on a previously locked route entry.
+Its usage is contrary to
+.Fn RT_ADDREF .
+.Pp
+The
+.Fn rtfree
+function does the actual free of the routing table entry, and shouldn't
+be called directly by facilities, that just perform routing table lookups.
+.Sh LEGACY INTERFACE
+Prior to introduction of multiple routing tables functions did not
+require the
+.Fa "u_int fibnum"
+argument.
+Legacy
+.Fn rtalloc1 ,
+.Fn rtalloc
+and
+.Fn rtalloc_ign
+functions are kept for compatibility, and are equivalent to
+calling new interface with
+.Fa fibnum
+argument equal to
+.Va 0 ,
+which implies default forwarding table.
 .Sh RETURN VALUES
 The
-.Fn rtalloc ,
-.Fn rtalloc_ign
+.Fn rtalloc1_fib
+function returns a pointer to a locked routing-table entry if it succeeds,
+otherwise a null pointer.
+The
+.Fn rtalloc_fib
 and
-.Fn rtfree
-functions do not return a value.
-The
-.Fn rtalloc1
-function returns a pointer to a routing-table entry if it succeeds,
-otherwise a null pointer.
+.Fn rtalloc_ign_fib
+functions do not return a value, but they fill in the
+.Fa *ro_rt
+member of the
+.Fa *ro
+argument with a pointer to an unlocked routing-table entry if they
+succeed, otherwise a null pointer.
+In a case of success all functions put a reference on the
+routing-table entry, freeing of which is responsibility of the caller.
 Lack of a route should in most cases be
 translated to the
 .Xr errno 2
@@ -213,7 +249,7 @@
 .Xr rtentry 9
 .Sh HISTORY
 The
-.Nm
+.Nm rtalloc
 facility first appeared in
 .Bx 4.2 ,
 although with much different internals.
@@ -227,14 +263,11 @@
 .Fx 2.0 .
 Routing table locking was introduced in
 .Fx 5.2 .
+Multiple routing tables were introduced in
+.Fx 8.0 .
 .Sh AUTHORS
-This manual page was written by
-.An Garrett Wollman ,
-as were the changes to implement
-.Dv RTF_PRCLONING
-and the
-.Fn rtalloc_ign
-function and the
-.Fa flags
-argument to
-.Fn rtalloc1 .
+The original version of this manual page was written by
+.An -nosplit
+.An "Garrett Wollman" .
+It was significantly updated by
+.An "Gleb Smirnoff" .
diff -r 2230520c0499 -r 820af1e39cd6 head/share/man/man9/sbuf.9
--- a/head/share/man/man9/sbuf.9	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/share/man/man9/sbuf.9	Thu Dec 15 12:59:38 2011 +0200
@@ -23,9 +23,9 @@
 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 .\" SUCH DAMAGE.
 .\"
-.\" $FreeBSD: head/share/man/man9/sbuf.9 222176 2011-05-22 14:03:30Z uqs $
+.\" $FreeBSD: head/share/man/man9/sbuf.9 228359 2011-12-09 13:28:41Z jh $
 .\"
-.Dd January 25, 2011
+.Dd December 9, 2011
 .Dt SBUF 9
 .Os
 .Sh NAME
@@ -117,7 +117,7 @@
 .Pp
 Any errors encountered during the allocation or composition of the
 string will be latched in the data structure,
-making a single error test at the end of the composition 
+making a single error test at the end of the composition
 sufficient to determine success or failure of the entire process.
 .Pp
 The
@@ -391,7 +391,8 @@
 only works on a finished
 .Fa sbuf .
 The
-.Fn sbuf_len function returns the length of the string.
+.Fn sbuf_len
+function returns the length of the string.
 For an
 .Fa sbuf
 with an attached drain,
@@ -462,12 +463,8 @@
 drain error, and zero otherwise.
 .Pp
 The
-.Fn sbuf_data
-and
 .Fn sbuf_len
-functions return
-.Dv NULL
-and \-1, respectively, if the buffer overflowed.
+function returns \-1 if the buffer overflowed.
 .Pp
 The
 .Fn sbuf_copyin
@@ -482,7 +479,7 @@
 or returns the error code from the drain if one is attached.
 .Pp
 The
-.Fn sbuf_finish 3 
+.Fn sbuf_finish 3
 function (the userland version)
 will return zero for success and \-1 and set errno on error.
 .Sh EXAMPLES
diff -r 2230520c0499 -r 820af1e39cd6 head/share/man/man9/shm_map.9
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/head/share/man/man9/shm_map.9	Thu Dec 15 12:59:38 2011 +0200
@@ -0,0 +1,187 @@
+.\"
+.\" Copyright (c) 2011 Advanced Computing Technologies LLC
+.\" Written by: John H. Baldwin <jhb at FreeBSD.org>
+.\" All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\"    notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\"    notice, this list of conditions and the following disclaimer in the
+.\"    documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+.\" ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+.\" SUCH DAMAGE.
+.\"
+.\" $FreeBSD: head/share/man/man9/shm_map.9 228509 2011-12-14 22:22:19Z jhb $
+.\"
+.Dd December 14, 2011
+.Dt SHM_MAP 9
+.Os
+.Sh NAME
+.Nm shm_map ,
+.Nm shm_unmap
+.Nd map shared memory objects into the kernel's address space
+.Sh SYNOPSIS
+.In sys/types.h
+.In sys/mman.h
+.Ft int
+.Fn shm_map "struct file *fp" "size_t size" "off_t offset" "void **memp"
+.Ft int
+.Fn shm_unmap "struct file *fp" "void *mem" "size_t size"
+.Sh DESCRIPTION
+The
+.Nm shm_map
+and
+.Nm shm_unmap
+functions provide an API for mapping shared memory objects into the kernel.
+Shared memory objects are created by
+.Xr shm_open 2 .
+These objects can then be passed into the kernel via file descriptors.
+.Pp
+A shared memory object cannot be shrunk while it is mapped into the kernel.
+This is to avoid invalidating any pages that may be wired into the kernel's
+address space.
+Shared memory objects can still be grown while mapped into the kernel.
+.Pp
+To simplify the accounting needed to enforce the above requirement,
+callers of this API are required to unmap the entire region mapped by
+.Nm shm_map
+when calling
+.Nm shm_unmap .
+Unmapping only a portion of the region is not permitted.
+.Pp
+The
+.Nm shm_map
+function locates the shared memory object associated with the open file
+.Fa fp .
+It maps the region of that object described by
+.Fa offset
+and
+.Fa size
+into the kernel's address space.
+If it succeeds,
+.Fa *memp
+will be set to the start of the mapping.
+All pages for the range will be wired into memory upon successful return.
+.Pp
+The
+.Nm shm_unmap
+function unmaps a region previously mapped by
+.Nm shm_map .
+The
+.Fa mem
+argument should match the value previously returned in
+.Fa *memp ,
+and the
+.Fa size
+argument should match the value passed to
+.Nm shm_map .
+.Pp
+Note that
+.Nm shm_map
+will not hold an extra reference on the open file
+.Fa fp
+for the lifetime of the mapping.
+Instead,
+the calling code is required to do this if it wishes to use
+.Nm shm_unmap
+on the region in the future.
+.Sh RETURN VALUES
+The
+.Nm shm_map
+and
+.Nm shm_unmap
+functions return zero on success or an error on failure.
+.Sh EXAMPLES
+The following function accepts a file descriptor for a shared memory
+object.
+It maps the first sixteen kilobytes of the object into the kernel,
+performs some work on that address,
+and then unmaps the address before returning.
+.Bd -literal
+int
+shm_example(int fd)
+{
+	struct file *fp;
+	void *mem;
+	int error;
+
+	error = fget(curthread, fd, CAP_MMAP, &fp)
+	if (error)
+		return (error);
+	error = shm_map(fp, 16384, 0, &mem);
+	if (error) {
+		fdrop(fp, curthread);
+		return (error);
+	}
+	
+	/* Do something with 'mem'. */
+
+	error = shm_unmap(fp, mem, 16384);
+	fdrop(fp, curthread);
+	return (error);
+}
+.Ed
+.Sh ERRORS
+The
+.Nm shm_map
+function returns the following errors on failure:
+.Bl -tag -width Er
+.It Bq Er EINVAL
+The open file
+.Fa fp
+is not a shared memory object.
+.It Bq Er EINVAL
+The requested region described by
+.Fa offset
+and
+.Fa size
+extends beyond the end of the shared memory object.
+.It Bq Er ENOMEM
+Insufficient address space was available.
+.It Bq Er EACCES
+The shared memory object could not be mapped due to a protection error.
+.It Bq Er EINVAL
+The shared memory object could not be mapped due to some other VM error.
+.El
+.Pp
+The
+.Nm shm_unmap
+function returns the following errors on failure:
+.Bl -tag -width Er
+.It Bq Er EINVAL
+The open file
+.Fa fp
+is not a shared memory object.
+.It Bq Er EINVAL
+The address range described by
+.Fa mem
+and
+.Fa size
+is not a valid address range.
+.It Bq Er EINVAL
+The address range described by
+.Fa mem
+and
+.Fa size
+is not backed by the shared memory object associated with the open file
+.Fa fp ,
+or the address range does not cover the entire mapping of the object.
+.El
+.Sh SEE ALSO
+.Xr shm_open 2
+.Sh HISTORY
+This API was first introduced in
+.Fx 10.0 .
diff -r 2230520c0499 -r 820af1e39cd6 head/share/misc/committers-src.dot
--- a/head/share/misc/committers-src.dot	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/share/misc/committers-src.dot	Thu Dec 15 12:59:38 2011 +0200
@@ -1,4 +1,4 @@
-# $FreeBSD: head/share/misc/committers-src.dot 228225 2011-12-03 14:03:53Z jhibbits $
+# $FreeBSD: head/share/misc/committers-src.dot 228373 2011-12-09 20:23:58Z jimharris $
 
 # This file is meant to list all FreeBSD src committers and describe the
 # mentor-mentee relationships between them.
@@ -161,6 +161,7 @@
 jhb [label="John Baldwin\njhb at FreeBSD.org\n1999/08/23"]
 jhibbits [label="Justin Hibbits\njhibbits at FreeBSD.org\n2011/11/30"]
 jilles [label="Jilles Tjoelker\njilles at FreeBSD.org\n2009/05/22"]
+jimharris [label="Jim Harris\njimharris at FreeBSD.org\n2011/12/09"]
 jinmei [label="JINMEI Tatuya\njinmei at FreeBSD.org\n2007/03/17"]
 jkim [label="Jung-uk Kim\njkim at FreeBSD.org\n2005/07/06"]
 jkoshy [label="A. Joseph Koshy\njkoshy at FreeBSD.org\n1998/05/13"]
@@ -203,6 +204,7 @@
 olli [label="Oliver Fromme\nolli at FreeBSD.org\n2008/02/14"]
 peadar [label="Peter Edwards\npeadar at FreeBSD.org\n2004/03/08"]
 peter [label="Peter Wemm\npeter at FreeBSD.org\n????/??/??"]
+pfg [label="Pedro Giffuni\npfg at FreeBSD.org\n2011/12/01"]
 philip [label="Philip Paeps\nphilip at FreBSD.org\n2004/01/21"]
 phk [label="Poul-Henning Kamp\nphk at FreeBSD.org\n1994/02/21"]
 pho [label="Peter Holm\npho at FreeBSD.org\n2008/11/16"]
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/amd64/conf/NOTES
--- a/head/sys/amd64/conf/NOTES	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/amd64/conf/NOTES	Thu Dec 15 12:59:38 2011 +0200
@@ -4,7 +4,7 @@
 # This file contains machine dependent kernel configuration notes.  For
 # machine independent notes, look in /sys/conf/NOTES.
 #
-# $FreeBSD: head/sys/amd64/conf/NOTES 228085 2011-11-28 18:51:40Z philip $
+# $FreeBSD: head/sys/amd64/conf/NOTES 228431 2011-12-12 09:50:33Z fabient $
 #
 
 #
@@ -458,6 +458,7 @@
 #
 device		ichwd
 device		amdsbwd
+device		viawd
 
 #
 # Temperature sensors:
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/amd64/include/_types.h
--- a/head/sys/amd64/include/_types.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/amd64/include/_types.h	Thu Dec 15 12:59:38 2011 +0200
@@ -33,7 +33,7 @@
  *
  *	From: @(#)ansi.h	8.2 (Berkeley) 1/4/94
  *	From: @(#)types.h	8.3 (Berkeley) 1/5/94
- * $FreeBSD: head/sys/amd64/include/_types.h 222813 2011-06-07 08:46:13Z attilio $
+ * $FreeBSD: head/sys/amd64/include/_types.h 228469 2011-12-13 13:38:03Z ed $
  */
 
 #ifndef _MACHINE__TYPES_H_
@@ -48,7 +48,7 @@
 /*
  * Basic types upon which most other types are built.
  */
-typedef	__signed char		__int8_t;
+typedef	signed char		__int8_t;
 typedef	unsigned char		__uint8_t;
 typedef	short			__int16_t;
 typedef	unsigned short		__uint16_t;
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/arm/arm/irq_dispatch.S
--- a/head/sys/arm/arm/irq_dispatch.S	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/arm/arm/irq_dispatch.S	Thu Dec 15 12:59:38 2011 +0200
@@ -72,7 +72,7 @@
 #include <machine/asm.h>
 #include <machine/asmacros.h>
 #include <machine/armreg.h>
-__FBSDID("$FreeBSD: head/sys/arm/arm/irq_dispatch.S 224612 2011-08-02 17:49:27Z attilio $");
+__FBSDID("$FreeBSD: head/sys/arm/arm/irq_dispatch.S 228504 2011-12-14 17:12:59Z raj $");
 
 /*
  * irq_entry:
@@ -98,10 +98,9 @@
 	PULLFRAMEFROMSVCANDEXIT
 	movs	pc, lr			/* Exit */
 
-	.bss
+	.data
 	.align	0
 
-
 	.global _C_LABEL(intrnames), _C_LABEL(sintrnames)
 	.global _C_LABEL(intrcnt), _C_LABEL(sintrcnt)
 _C_LABEL(intrnames): 
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/arm/arm/vm_machdep.c
--- a/head/sys/arm/arm/vm_machdep.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/arm/arm/vm_machdep.c	Thu Dec 15 12:59:38 2011 +0200
@@ -41,7 +41,7 @@
  */
 
 #include <sys/cdefs.h>
-__FBSDID("$FreeBSD: head/sys/arm/arm/vm_machdep.c 227293 2011-11-07 06:44:47Z ed $");
+__FBSDID("$FreeBSD: head/sys/arm/arm/vm_machdep.c 228522 2011-12-15 05:07:16Z alc $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -617,7 +617,6 @@
 	void *ret;
 	struct arm_small_page *sp;
 	TAILQ_HEAD(,arm_small_page) *head;
-	static vm_pindex_t color;
 	vm_page_t m;
 
 	*flags = UMA_SLAB_PRIV;
@@ -650,8 +649,7 @@
 		if (wait & M_ZERO)
 			pflags |= VM_ALLOC_ZERO;
 		for (;;) {
-			m = vm_page_alloc(NULL, color++, 
-			    pflags | VM_ALLOC_NOOBJ);
+			m = vm_page_alloc(NULL, 0, pflags | VM_ALLOC_NOOBJ);
 			if (m == NULL) {
 				if (wait & M_NOWAIT)
 					return (NULL);
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/arm/econa/ehci_ebus.c
--- a/head/sys/arm/econa/ehci_ebus.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/arm/econa/ehci_ebus.c	Thu Dec 15 12:59:38 2011 +0200
@@ -32,7 +32,7 @@
 
 
 #include <sys/cdefs.h>
-__FBSDID("$FreeBSD: head/sys/arm/econa/ehci_ebus.c 227849 2011-11-22 21:56:55Z hselasky $");
+__FBSDID("$FreeBSD: head/sys/arm/econa/ehci_ebus.c 228483 2011-12-14 00:28:54Z hselasky $");
 
 #include "opt_bus.h"
 
@@ -75,10 +75,6 @@
 
 static device_attach_t ehci_ebus_attach;
 static device_detach_t ehci_ebus_detach;
-static device_shutdown_t ehci_ebus_shutdown;
-static device_suspend_t ehci_ebus_suspend;
-static device_resume_t ehci_ebus_resume;
-
 
 static void *ih_err;
 
@@ -86,45 +82,6 @@
 #define	USB_BRIDGE_INTR_MASK   0x214
 
 static int
-ehci_ebus_suspend(device_t self)
-{
-	ehci_softc_t *sc = device_get_softc(self);
-	int err;
-
-	err = bus_generic_suspend(self);
-	if (err)
-		return (err);
-	ehci_suspend(sc);
-	return (0);
-}
-
-static int
-ehci_ebus_resume(device_t self)
-{
-	ehci_softc_t *sc = device_get_softc(self);
-
-	ehci_resume(sc);
-
-	bus_generic_resume(self);
-
-	return (0);
-}
-
-static int
-ehci_ebus_shutdown(device_t self)
-{
-	ehci_softc_t *sc = device_get_softc(self);
-	int err;
-
-	err = bus_generic_shutdown(self);
-	if (err)
-		return (err);
-	ehci_shutdown(sc);
-
-	return (0);
-}
-
-static int
 ehci_ebus_probe(device_t self)
 {
 
@@ -277,17 +234,17 @@
 	DEVMETHOD(device_probe, ehci_ebus_probe),
 	DEVMETHOD(device_attach, ehci_ebus_attach),
 	DEVMETHOD(device_detach, ehci_ebus_detach),
-	DEVMETHOD(device_suspend, ehci_ebus_suspend),
-	DEVMETHOD(device_resume, ehci_ebus_resume),
-	DEVMETHOD(device_shutdown, ehci_ebus_shutdown),
+	DEVMETHOD(device_suspend, bus_generic_suspend),
+	DEVMETHOD(device_resume, bus_generic_resume),
+	DEVMETHOD(device_shutdown, bus_generic_shutdown),
 
 	DEVMETHOD_END
 };
 
 static driver_t ehci_driver = {
-	"ehci",
-	ehci_methods,
-	sizeof(ehci_softc_t),
+	.name = "ehci",
+	.methods = ehci_methods,
+	.size = sizeof(ehci_softc_t),
 };
 
 static devclass_t ehci_devclass;
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/arm/econa/ohci_ec.c
--- a/head/sys/arm/econa/ohci_ec.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/arm/econa/ohci_ec.c	Thu Dec 15 12:59:38 2011 +0200
@@ -24,7 +24,7 @@
  */
 
 #include <sys/cdefs.h>
-__FBSDID("$FreeBSD: head/sys/arm/econa/ohci_ec.c 227849 2011-11-22 21:56:55Z hselasky $");
+__FBSDID("$FreeBSD: head/sys/arm/econa/ohci_ec.c 228483 2011-12-14 00:28:54Z hselasky $");
 
 #include <sys/stdint.h>
 #include <sys/stddef.h>
@@ -220,15 +220,17 @@
 	DEVMETHOD(device_probe, ohci_ec_probe),
 	DEVMETHOD(device_attach, ohci_ec_attach),
 	DEVMETHOD(device_detach, ohci_ec_detach),
+	DEVMETHOD(device_resume, bus_generic_resume),
+	DEVMETHOD(device_suspend, bus_generic_suspend),
 	DEVMETHOD(device_shutdown, bus_generic_shutdown),
 
 	DEVMETHOD_END
 };
 
 static driver_t ohci_driver = {
-	"ohci",
-	ohci_methods,
-	sizeof(struct ec_ohci_softc),
+	.name = "ohci",
+	.methods = ohci_methods,
+	.size = sizeof(struct ec_ohci_softc),
 };
 
 static devclass_t ohci_devclass;
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/arm/include/_types.h
--- a/head/sys/arm/include/_types.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/arm/include/_types.h	Thu Dec 15 12:59:38 2011 +0200
@@ -33,7 +33,7 @@
  *
  *	From: @(#)ansi.h	8.2 (Berkeley) 1/4/94
  *	From: @(#)types.h	8.3 (Berkeley) 1/5/94
- * $FreeBSD: head/sys/arm/include/_types.h 222813 2011-06-07 08:46:13Z attilio $
+ * $FreeBSD: head/sys/arm/include/_types.h 228469 2011-12-13 13:38:03Z ed $
  */
 
 #ifndef _MACHINE__TYPES_H_
@@ -46,7 +46,7 @@
 /*
  * Basic types upon which most other types are built.
  */
-typedef	__signed char		__int8_t;
+typedef	signed char		__int8_t;
 typedef	unsigned char		__uint8_t;
 typedef	short			__int16_t;
 typedef	unsigned short		__uint16_t;
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/boot/arm/at91/libat91/sd-card.c
--- a/head/sys/boot/arm/at91/libat91/sd-card.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/boot/arm/at91/libat91/sd-card.c	Thu Dec 15 12:59:38 2011 +0200
@@ -24,7 +24,7 @@
  * This software is derived from software provide by Kwikbyte who specifically
  * disclaimed copyright on the code.
  *
- * $FreeBSD$
+ * $FreeBSD: head/sys/boot/arm/at91/libat91/sd-card.c 228471 2011-12-13 14:06:01Z ed $
  */
 
 //*----------------------------------------------------------------------------
@@ -94,14 +94,14 @@
 	}	// End of if AT91C_MCI_RXBUFF
 }
 
-inline static unsigned int
+static inline unsigned int
 swap(unsigned int a)
 {
     return (((a & 0xff) << 24) | ((a & 0xff00) << 8) | ((a & 0xff0000) >> 8)
       | ((a & 0xff000000) >> 24));
 }
 
-inline static void
+static inline void
 wait_ready()
 {
 	int status;
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/cam/scsi/scsi_sa.c
--- a/head/sys/cam/scsi/scsi_sa.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/cam/scsi/scsi_sa.c	Thu Dec 15 12:59:38 2011 +0200
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__FBSDID("$FreeBSD: head/sys/cam/scsi/scsi_sa.c 227293 2011-11-07 06:44:47Z ed $");
+__FBSDID("$FreeBSD: head/sys/cam/scsi/scsi_sa.c 228344 2011-12-08 03:20:48Z eadler $");
 
 #include <sys/param.h>
 #include <sys/queue.h>
@@ -334,6 +334,10 @@
 		"STT20000*", "*"}, SA_QUIRK_1FM, 0
 	},
 	{
+		{ T_SEQUENTIAL, SIP_MEDIA_REMOVABLE, "SEAGATE",
+		"DAT    06241-XXX", "*"}, SA_QUIRK_VARIABLE|SA_QUIRK_2FM, 0
+	},
+	{
 		{ T_SEQUENTIAL, SIP_MEDIA_REMOVABLE, "TANDBERG",
 		  " TDC 3600", "U07:"}, SA_QUIRK_NOCOMP|SA_QUIRK_1FM, 512
 	},
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/cam/scsi/scsi_target.c
--- a/head/sys/cam/scsi/scsi_target.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/cam/scsi/scsi_target.c	Thu Dec 15 12:59:38 2011 +0200
@@ -28,7 +28,7 @@
  */
 
 #include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: head/sys/cam/scsi/scsi_target.c 228481 2011-12-13 21:26:33Z ed $");
 
 
 #include <sys/param.h>
@@ -96,12 +96,9 @@
 	targ_state		 state;
 	struct selinfo		 read_select;
 	struct devstat		 device_stats;
-	struct callout		destroy_dev_callout;
-	struct mtx		destroy_mtx;
 };
 
 static d_open_t		targopen;
-static d_close_t	targclose;
 static d_read_t		targread;
 static d_write_t	targwrite;
 static d_ioctl_t	targioctl;
@@ -119,7 +116,6 @@
 	.d_version =	D_VERSION,
 	.d_flags =	D_NEEDGIANT,
 	.d_open =	targopen,
-	.d_close =	targclose,
 	.d_read =	targread,
 	.d_write =	targwrite,
 	.d_ioctl =	targioctl,
@@ -152,15 +148,12 @@
 static struct targ_cmd_descr *
 			targgetdescr(struct targ_softc *softc);
 static periph_init_t	targinit;
-static void		targclone(void *arg, struct ucred *cred, char *name,
-				  int namelen, struct cdev **dev);
 static void		targasync(void *callback_arg, u_int32_t code,
 				  struct cam_path *path, void *arg);
 static void		abort_all_pending(struct targ_softc *softc);
 static void		notify_user(struct targ_softc *softc);
 static int		targcamstatus(cam_status status);
 static size_t		targccblen(xpt_opcode func_code);
-static void		targdestroy(void *);
 
 static struct periph_driver targdriver =
 {
@@ -171,31 +164,50 @@
 
 static MALLOC_DEFINE(M_TARG, "TARG", "TARG data");
 
+/* Disable LUN if enabled and teardown softc */
+static void
+targcdevdtor(void *data)
+{
+	struct targ_softc *softc;
+	struct cam_periph *periph;
+
+	softc = data;
+	if (softc->periph == NULL) {
+		printf("%s: destroying non-enabled target\n", __func__);
+		free(softc, M_TARG);
+		return;
+	}
+
+	/*
+	 * Acquire a hold on the periph so that it doesn't go away before
+	 * we are ready at the end of the function.
+	 */
+	periph = softc->periph;
+	cam_periph_acquire(periph);
+	cam_periph_lock(periph);
+	(void)targdisable(softc);
+	if (softc->periph != NULL) {
+		cam_periph_invalidate(softc->periph);
+		softc->periph = NULL;
+	}
+	cam_periph_unlock(periph);
+	cam_periph_release(periph);
+	free(softc, M_TARG);
+}
+
 /*
- * Create softc and initialize it. Only one proc can open each targ device.
- * There is no locking here because a periph doesn't get created until an
- * ioctl is issued to do so, and that can't happen until this method returns.
+ * Create softc and initialize it.  There is no locking here because a
+ * periph doesn't get created until an ioctl is issued to do so, and
+ * that can't happen until this method returns.
  */
 static int
 targopen(struct cdev *dev, int flags, int fmt, struct thread *td)
 {
 	struct targ_softc *softc;
 
-	if (dev->si_drv1 != 0) {
-		return (EBUSY);
-	}
-	
-	/* Mark device busy before any potentially blocking operations */
-	dev->si_drv1 = (void *)~0;
-
-	/* Create the targ device, allocate its softc, initialize it */
-	if ((dev->si_flags & SI_NAMED) == 0) {
-		make_dev(&targ_cdevsw, dev2unit(dev), UID_ROOT, GID_WHEEL, 0600,
-			 "targ%d", dev2unit(dev));
-	}
+	/* Allocate its softc, initialize it */
 	softc = malloc(sizeof(*softc), M_TARG,
 	       M_WAITOK | M_ZERO);
-	dev->si_drv1 = softc;
 	softc->state = TARG_STATE_OPENED;
 	softc->periph = NULL;
 	softc->path = NULL;
@@ -206,61 +218,10 @@
 	TAILQ_INIT(&softc->user_ccb_queue);
 	knlist_init_mtx(&softc->read_select.si_note, NULL);
 
+	devfs_set_cdevpriv(softc, targcdevdtor);
 	return (0);
 }
 
-/* Disable LUN if enabled and teardown softc */
-static int
-targclose(struct cdev *dev, int flag, int fmt, struct thread *td)
-{
-	struct targ_softc     *softc;
-	struct cam_periph     *periph;
-	int    error;
-
-	softc = (struct targ_softc *)dev->si_drv1;
-	mtx_init(&softc->destroy_mtx, "targ_destroy", "SCSI Target dev destroy", MTX_DEF);
- 	callout_init_mtx(&softc->destroy_dev_callout, &softc->destroy_mtx, CALLOUT_RETURNUNLOCKED);
-	if (softc->periph == NULL) {
-#if 0
-		destroy_dev(dev);
-		free(softc, M_TARG);
-#endif
-		printf("%s: destroying non-enabled target\n", __func__);
-		mtx_lock(&softc->destroy_mtx);
-       		callout_reset(&softc->destroy_dev_callout, hz / 2,
-                        (void *)targdestroy, (void *)dev);
-		mtx_unlock(&softc->destroy_mtx);
-		return (0);
-	}
-
-	/*
-	 * Acquire a hold on the periph so that it doesn't go away before
-	 * we are ready at the end of the function.
-	 */
-	periph = softc->periph;
-	cam_periph_acquire(periph);
-	cam_periph_lock(periph);
-	error = targdisable(softc);
-	if (softc->periph != NULL) {
-		cam_periph_invalidate(softc->periph);
-		softc->periph = NULL;
-	}
-	cam_periph_unlock(periph);
-	cam_periph_release(periph);
-
-#if 0
-	destroy_dev(dev);
-	free(softc, M_TARG);
-#endif
-
-	printf("%s: close finished error(%d)\n", __func__, error);
-	mtx_lock(&softc->destroy_mtx);
-      	callout_reset(&softc->destroy_dev_callout, hz / 2,
-		(void *)targdestroy, (void *)dev);
-	mtx_unlock(&softc->destroy_mtx);
-	return (error);
-}
-
 /* Enable/disable LUNs, set debugging level */
 static int
 targioctl(struct cdev *dev, u_long cmd, caddr_t addr, int flag, struct thread *td)
@@ -268,7 +229,7 @@
 	struct targ_softc *softc;
 	cam_status	   status;
 
-	softc = (struct targ_softc *)dev->si_drv1;
+	devfs_get_cdevpriv((void **)&softc);
 
 	switch (cmd) {
 	case TARGIOCENABLE:
@@ -346,7 +307,7 @@
 	struct targ_softc *softc;
 	int	revents;
 
-	softc = (struct targ_softc *)dev->si_drv1;
+	devfs_get_cdevpriv((void **)&softc);
 
 	/* Poll for write() is always ok. */
 	revents = poll_events & (POLLOUT | POLLWRNORM);
@@ -371,7 +332,7 @@
 {
 	struct  targ_softc *softc;
 
-	softc = (struct targ_softc *)dev->si_drv1;
+	devfs_get_cdevpriv((void **)&softc);
 	kn->kn_hook = (caddr_t)softc;
 	kn->kn_fop = &targread_filtops;
 	knlist_add(&softc->read_select.si_note, kn, 0);
@@ -572,7 +533,7 @@
 	int write_len, error;
 	int func_code, priority;
 
-	softc = (struct targ_softc *)dev->si_drv1;
+	devfs_get_cdevpriv((void **)&softc);
 	write_len = error = 0;
 	CAM_DEBUG(softc->path, CAM_DEBUG_PERIPH,
 		  ("write - uio_resid %zd\n", uio->uio_resid));
@@ -866,7 +827,7 @@
 
 	error = 0;
 	read_len = 0;
-	softc = (struct targ_softc *)dev->si_drv1;
+	devfs_get_cdevpriv((void **)&softc);
 	user_queue = &softc->user_ccb_queue;
 	abort_queue = &softc->abort_queue;
 	CAM_DEBUG(softc->path, CAM_DEBUG_PERIPH, ("targread\n"));
@@ -1051,23 +1012,11 @@
 static void
 targinit(void)
 {
-	EVENTHANDLER_REGISTER(dev_clone, targclone, 0, 1000);
-}
+	struct cdev *dev;
 
-static void
-targclone(void *arg, struct ucred *cred, char *name, int namelen,
-    struct cdev **dev)
-{
-	int u;
-
-	if (*dev != NULL)
-		return;
-	if (dev_stdclone(name, NULL, "targ", &u) != 1)
-		return;
-	*dev = make_dev(&targ_cdevsw, u, UID_ROOT, GID_WHEEL,
-			0600, "targ%d", u);
-	dev_ref(*dev);
-	(*dev)->si_flags |= SI_CHEAPCLONE;
+	/* Add symbolic link to targ0 for compatibility. */
+	dev = make_dev(&targ_cdevsw, 0, UID_ROOT, GID_WHEEL, 0600, "targ");
+	make_dev_alias(dev, "targ0");
 }
 
 static void
@@ -1221,25 +1170,3 @@
 
 	return (len);
 }
-
-/*
- * work around to destroy targ device
- * outside of targclose
- */
-static void
-targdestroy(void *dev)
-{
-	struct cdev *device = (struct cdev *)dev;
-	struct targ_softc *softc = (struct targ_softc *)device->si_drv1;
-
-#if 0
-	callout_stop(&softc->destroy_dev_callout);
-#endif
-
-	mtx_unlock(&softc->destroy_mtx);
-	mtx_destroy(&softc->destroy_mtx);
-	free(softc, M_TARG);
-	device->si_drv1 = 0;
-	destroy_dev(device);
-	printf("%s: destroyed dev\n", __func__);
-}
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/cam/scsi/scsi_xpt.c
--- a/head/sys/cam/scsi/scsi_xpt.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/cam/scsi/scsi_xpt.c	Thu Dec 15 12:59:38 2011 +0200
@@ -28,7 +28,7 @@
  */
 
 #include <sys/cdefs.h>
-__FBSDID("$FreeBSD: head/sys/cam/scsi/scsi_xpt.c 223448 2011-06-22 22:55:51Z will $");
+__FBSDID("$FreeBSD: head/sys/cam/scsi/scsi_xpt.c 228442 2011-12-12 18:43:18Z mdf $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -1811,14 +1811,14 @@
 static int
 sysctl_cam_search_luns(SYSCTL_HANDLER_ARGS)
 {
-	int error, bool;
+	int error, val;
 
-	bool = cam_srch_hi;
-	error = sysctl_handle_int(oidp, &bool, 0, req);
+	val = cam_srch_hi;
+	error = sysctl_handle_int(oidp, &val, 0, req);
 	if (error != 0 || req->newptr == NULL)
 		return (error);
-	if (bool == 0 || bool == 1) {
-		cam_srch_hi = bool;
+	if (val == 0 || val == 1) {
+		cam_srch_hi = val;
 		return (0);
 	} else {
 		return (EINVAL);
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/cddl/contrib/opensolaris/uts/common/dtrace/dtrace.c
--- a/head/sys/cddl/contrib/opensolaris/uts/common/dtrace/dtrace.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/cddl/contrib/opensolaris/uts/common/dtrace/dtrace.c	Thu Dec 15 12:59:38 2011 +0200
@@ -18,7 +18,7 @@
  *
  * CDDL HEADER END
  *
- * $FreeBSD: head/sys/cddl/contrib/opensolaris/uts/common/dtrace/dtrace.c 225617 2011-09-16 13:58:51Z kmacy $
+ * $FreeBSD: head/sys/cddl/contrib/opensolaris/uts/common/dtrace/dtrace.c 228448 2011-12-12 23:29:32Z attilio $
  */
 
 /*
@@ -5877,6 +5877,9 @@
 	volatile uint16_t *flags;
 	hrtime_t now;
 
+	if (panicstr != NULL)
+		return;
+
 #if defined(sun)
 	/*
 	 * Kick out immediately if this CPU is still being born (in which case
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/arc.c
--- a/head/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/arc.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/arc.c	Thu Dec 15 12:59:38 2011 +0200
@@ -3105,6 +3105,9 @@
 		ARCSTAT_CONDSTAT(!(hdr->b_flags & ARC_PREFETCH),
 		    demand, prefetch, hdr->b_type != ARC_BUFC_METADATA,
 		    data, metadata, misses);
+#ifdef _KERNEL
+		curthread->td_ru.ru_inblock++;
+#endif
 
 		if (vd != NULL && l2arc_ndev != 0 && !(l2arc_norw && devw)) {
 			/*
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dbuf.c
--- a/head/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dbuf.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dbuf.c	Thu Dec 15 12:59:38 2011 +0200
@@ -627,10 +627,6 @@
 	} else if (db->db_state == DB_UNCACHED) {
 		spa_t *spa = dn->dn_objset->os_spa;
 
-#ifdef _KERNEL
-		curthread->td_ru.ru_inblock++;
-#endif
-
 		if (zio == NULL)
 			zio = zio_root(spa, NULL, NULL, ZIO_FLAG_CANFAIL);
 		dbuf_read_impl(db, zio, &flags);
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/txg.c
--- a/head/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/txg.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/txg.c	Thu Dec 15 12:59:38 2011 +0200
@@ -43,7 +43,7 @@
 SYSCTL_DECL(_vfs_zfs);
 SYSCTL_NODE(_vfs_zfs, OID_AUTO, txg, CTLFLAG_RW, 0, "ZFS TXG");
 TUNABLE_INT("vfs.zfs.txg.timeout", &zfs_txg_timeout);
-SYSCTL_INT(_vfs_zfs_txg, OID_AUTO, timeout, CTLFLAG_RDTUN, &zfs_txg_timeout, 0,
+SYSCTL_INT(_vfs_zfs_txg, OID_AUTO, timeout, CTLFLAG_RW, &zfs_txg_timeout, 0,
     "Maximum seconds worth of delta per txg");
 
 /*
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/conf/files
--- a/head/sys/conf/files	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/conf/files	Thu Dec 15 12:59:38 2011 +0200
@@ -1811,7 +1811,8 @@
 dev/switch/switch_if.m		optional switch
 dev/switch/switchb_if.m		optional switch
 dev/switch/switch.c		optional switch
-dev/switch/switch_mii.c		optional switch mii | miibus
+dev/switch/switch_mii.c		optional switch mii
+dev/switch/switch_mii.c		optional switch miibus # XXX
 dev/switch/switch_obio.c	optional switch obio
 dev/switch/switch_obio.c	optional switch_obio
 dev/switch/ar8x16_switch.c	optional switch switch_ar8x16
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/conf/files.amd64
--- a/head/sys/conf/files.amd64	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/conf/files.amd64	Thu Dec 15 12:59:38 2011 +0200
@@ -1,7 +1,7 @@
 # This file tells config what files go into building a kernel,
 # files marked standard are always included.
 #
-# $FreeBSD: head/sys/conf/files.amd64 228085 2011-11-28 18:51:40Z philip $
+# $FreeBSD: head/sys/conf/files.amd64 228431 2011-12-12 09:50:33Z fabient $
 #
 # The long compile-with and dependency lines are required because of
 # limitations in config: backslash-newline doesn't work in strings, and
@@ -260,6 +260,7 @@
 dev/tpm/tpm_acpi.c		optional	tpm acpi
 dev/tpm/tpm_isa.c		optional	tpm isa
 dev/uart/uart_cpu_amd64.c	optional	uart
+dev/viawd/viawd.c		optional	viawd
 dev/wpi/if_wpi.c		optional	wpi
 isa/syscons_isa.c		optional	sc
 isa/vga_isa.c			optional	vga
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/conf/files.i386
--- a/head/sys/conf/files.i386	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/conf/files.i386	Thu Dec 15 12:59:38 2011 +0200
@@ -1,7 +1,7 @@
 # This file tells config what files go into building a kernel,
 # files marked standard are always included.
 #
-# $FreeBSD: head/sys/conf/files.i386 224120 2011-07-17 01:23:50Z jhb $
+# $FreeBSD: head/sys/conf/files.i386 228431 2011-12-12 09:50:33Z fabient $
 #
 # The long compile-with and dependency lines are required because of
 # limitations in config: backslash-newline doesn't work in strings, and
@@ -236,6 +236,7 @@
 dev/tpm/tpm_acpi.c		optional tpm acpi
 dev/tpm/tpm_isa.c		optional tpm isa
 dev/uart/uart_cpu_i386.c	optional uart
+dev/viawd/viawd.c		optional viawd
 dev/acpica/acpi_if.m		standard
 dev/acpi_support/acpi_wmi_if.m	standard
 dev/wpi/if_wpi.c		optional wpi
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/conf/kmod.mk
--- a/head/sys/conf/kmod.mk	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/conf/kmod.mk	Thu Dec 15 12:59:38 2011 +0200
@@ -1,5 +1,5 @@
 #	From: @(#)bsd.prog.mk	5.26 (Berkeley) 6/25/91
-# $FreeBSD: head/sys/conf/kmod.mk 228158 2011-11-30 18:11:49Z fjoe $
+# $FreeBSD: head/sys/conf/kmod.mk 228311 2011-12-06 18:01:09Z fjoe $
 #
 # The include file <bsd.kmod.mk> handles building and installing loadable
 # kernel modules.
@@ -201,7 +201,7 @@
 ${FULLPROG}: ${OBJS}
 .endif
 	${LD} ${LDFLAGS} -r -d -o ${.TARGET} ${OBJS}
-.if ${MK_CTF} != "no"
+.if defined(MK_CTF) && ${MK_CTF} != "no"
 	${CTFMERGE} ${CTFFLAGS} -o ${.TARGET} ${OBJS}
 .endif
 .if defined(EXPORT_SYMS)
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/ddb/db_thread.c
--- a/head/sys/ddb/db_thread.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/ddb/db_thread.c	Thu Dec 15 12:59:38 2011 +0200
@@ -25,7 +25,7 @@
  */
 
 #include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: head/sys/ddb/db_thread.c 228376 2011-12-09 20:41:54Z kib $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -109,7 +109,7 @@
  * Lookup a thread based on a db expression address.  We assume that the
  * address was parsed in hexadecimal.  We reparse the address in decimal
  * first and try to treat it as a thread ID to find an associated thread.
- * If that fails and check_pid is true, we terat the decimal value as a
+ * If that fails and check_pid is true, we treat the decimal value as a
  * PID.  If that matches a process, we return the first thread in that
  * process.  Otherwise, we treat the addr as a pointer to a thread.
  */
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/ata/ata-pci.h
--- a/head/sys/dev/ata/ata-pci.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/ata/ata-pci.h	Thu Dec 15 12:59:38 2011 +0200
@@ -23,7 +23,7 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * $FreeBSD: head/sys/dev/ata/ata-pci.h 226680 2011-10-24 08:47:23Z mav $
+ * $FreeBSD: head/sys/dev/ata/ata-pci.h 228497 2011-12-14 13:12:55Z mav $
  */
 
 /* structure holding chipset config info */
@@ -194,6 +194,10 @@
 #define ATA_I82801IB_AH4        0x29238086
 #define ATA_I82801IB_R1         0x29258086
 #define ATA_I82801IB_S2         0x29268086
+#define ATA_I82801IBM_S1        0x29288086
+#define ATA_I82801IBM_AH        0x29298086
+#define ATA_I82801IBM_R1        0x292a8086
+#define ATA_I82801IBM_S2        0x292d8086
 #define ATA_I82801JIB_S1        0x3a208086
 #define ATA_I82801JIB_AH        0x3a228086
 #define ATA_I82801JIB_R1        0x3a258086
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/ata/chipsets/ata-intel.c
--- a/head/sys/dev/ata/chipsets/ata-intel.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/ata/chipsets/ata-intel.c	Thu Dec 15 12:59:38 2011 +0200
@@ -25,7 +25,7 @@
  */
 
 #include <sys/cdefs.h>
-__FBSDID("$FreeBSD: head/sys/dev/ata/chipsets/ata-intel.c 224270 2011-07-22 16:37:04Z mav $");
+__FBSDID("$FreeBSD: head/sys/dev/ata/chipsets/ata-intel.c 228497 2011-12-14 13:12:55Z mav $");
 
 #include "opt_ata.h"
 #include <sys/param.h>
@@ -157,6 +157,10 @@
      { ATA_I82801IB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
      { ATA_I82801IB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
      { ATA_I82801IB_R1,  0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
+     { ATA_I82801IBM_S1, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" },
+     { ATA_I82801IBM_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9M" },
+     { ATA_I82801IBM_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9M" },
+     { ATA_I82801IBM_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" },
      { ATA_I82801JIB_S1, 0, INTEL_6CH,  0, ATA_SA300, "ICH10" },
      { ATA_I82801JIB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
      { ATA_I82801JIB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/ath/ath_hal/ar5416/ar2133.c
--- a/head/sys/dev/ath/ath_hal/ar5416/ar2133.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/ath/ath_hal/ar5416/ar2133.c	Thu Dec 15 12:59:38 2011 +0200
@@ -14,7 +14,7 @@
  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  *
- * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar2133.c 223459 2011-06-23 02:38:36Z adrian $
+ * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar2133.c 228517 2011-12-15 00:59:11Z adrian $
  */
 #include "opt_ah.h"
 
@@ -549,3 +549,11 @@
 
 	return AH_TRUE;
 }
+
+static HAL_BOOL
+ar2133Probe(struct ath_hal *ah)
+{
+	return (AR_SREV_OWL(ah) || AR_SREV_HOWL(ah) || AR_SREV_SOWL(ah));
+}
+
+AH_RF(RF2133, ar2133Probe, ar2133RfAttach);
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c
--- a/head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c	Thu Dec 15 12:59:38 2011 +0200
@@ -14,7 +14,7 @@
  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  *
- * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c 227410 2011-11-09 22:39:44Z adrian $
+ * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c 228515 2011-12-15 00:54:11Z adrian $
  */
 #include "opt_ah.h"
 
@@ -339,7 +339,7 @@
 	OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
 
 	/* Read Radio Chip Rev Extract */
-	AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah);
+	AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
 	switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
         case AR_RAD5122_SREV_MAJOR:	/* Fowl: 5G/2x2 */
         case AR_RAD2122_SREV_MAJOR:	/* Fowl: 2+5G/2x2 */
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/ath/ath_hal/ar9002/ar9280.c
--- a/head/sys/dev/ath/ath_hal/ar9002/ar9280.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/ath/ath_hal/ar9002/ar9280.c	Thu Dec 15 12:59:38 2011 +0200
@@ -14,7 +14,7 @@
  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  *
- * $FreeBSD: head/sys/dev/ath/ath_hal/ar9002/ar9280.c 224519 2011-07-30 13:45:12Z adrian $
+ * $FreeBSD: head/sys/dev/ath/ath_hal/ar9002/ar9280.c 228517 2011-12-15 00:59:11Z adrian $
  */
 #include "opt_ah.h"
 
@@ -384,3 +384,11 @@
 
 	return AH_TRUE;
 }
+
+static HAL_BOOL
+ar9280RfProbe(struct ath_hal *ah)
+{
+	return (AR_SREV_MERLIN(ah));
+}
+
+AH_RF(RF9280, ar9280RfProbe, ar9280RfAttach);
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/ath/ath_hal/ar9002/ar9285.c
--- a/head/sys/dev/ath/ath_hal/ar9002/ar9285.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/ath/ath_hal/ar9002/ar9285.c	Thu Dec 15 12:59:38 2011 +0200
@@ -14,7 +14,7 @@
  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  *
- * $FreeBSD: head/sys/dev/ath/ath_hal/ar9002/ar9285.c 219605 2011-03-13 13:00:45Z adrian $
+ * $FreeBSD: head/sys/dev/ath/ath_hal/ar9002/ar9285.c 228517 2011-12-15 00:59:11Z adrian $
  */
 #include "opt_ah.h"
 
@@ -77,3 +77,11 @@
 
 	return AH_TRUE;
 }
+
+static HAL_BOOL
+ar9285RfProbe(struct ath_hal *ah)
+{
+	return (AR_SREV_KITE(ah));
+}
+
+AH_RF(RF9285, ar9285RfProbe, ar9285RfAttach);
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/ath/ath_hal/ar9002/ar9287.c
--- a/head/sys/dev/ath/ath_hal/ar9002/ar9287.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/ath/ath_hal/ar9002/ar9287.c	Thu Dec 15 12:59:38 2011 +0200
@@ -14,7 +14,7 @@
  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  *
- * $FreeBSD: head/sys/dev/ath/ath_hal/ar9002/ar9287.c 222324 2011-05-26 20:22:10Z adrian $
+ * $FreeBSD: head/sys/dev/ath/ath_hal/ar9002/ar9287.c 228517 2011-12-15 00:59:11Z adrian $
  */
 #include "opt_ah.h"
 
@@ -390,3 +390,11 @@
 
 	return AH_TRUE;
 }
+
+static HAL_BOOL
+ar9287RfProbe(struct ath_hal *ah)
+{
+	return (AR_SREV_KIWI(ah));
+}
+
+AH_RF(RF9287, ar9287RfProbe, ar9287RfAttach);
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/ath/if_ath.c
--- a/head/sys/dev/ath/if_ath.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/ath/if_ath.c	Thu Dec 15 12:59:38 2011 +0200
@@ -28,7 +28,7 @@
  */
 
 #include <sys/cdefs.h>
-__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath.c 227872 2011-11-23 07:12:26Z adrian $");
+__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath.c 228516 2011-12-15 00:55:27Z adrian $");
 
 /*
  * Driver for the Atheros Wireless LAN controller.
@@ -6218,6 +6218,8 @@
 	if_printf(ifp, "AR%s mac %d.%d RF%s phy %d.%d\n",
 		ath_hal_mac_name(ah), ah->ah_macVersion, ah->ah_macRev,
 		ath_hal_rf_name(ah), ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf);
+	if_printf(ifp, "2GHz radio: 0x%.4x; 5GHz radio: 0x%.4x\n",
+		ah->ah_analog2GhzRev, ah->ah_analog5GhzRev);
 	if (bootverbose) {
 		int i;
 		for (i = 0; i <= WME_AC_VO; i++) {
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/bce/if_bce.c
--- a/head/sys/dev/bce/if_bce.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/bce/if_bce.c	Thu Dec 15 12:59:38 2011 +0200
@@ -29,7 +29,7 @@
  */
 
 #include <sys/cdefs.h>
-__FBSDID("$FreeBSD: head/sys/dev/bce/if_bce.c 227843 2011-11-22 21:28:20Z marius $");
+__FBSDID("$FreeBSD: head/sys/dev/bce/if_bce.c 228476 2011-12-13 18:11:25Z yongari $");
 
 /*
  * The following controllers are supported by this driver:
@@ -1982,6 +1982,7 @@
 bce_miibus_statchg(device_t dev)
 {
 	struct bce_softc *sc;
+	struct ifnet *ifp;
 	struct mii_data *mii;
 	int val;
 
@@ -1989,41 +1990,56 @@
 
 	DBENTER(BCE_VERBOSE_PHY);
 
+	ifp = sc->bce_ifp;
 	mii = device_get_softc(sc->bce_miibus);
-
+	if (mii == NULL || ifp == NULL ||
+	    (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
+		return;
+
+	sc->bce_link_up = FALSE;
 	val = REG_RD(sc, BCE_EMAC_MODE);
 	val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX |
 	    BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK |
 	    BCE_EMAC_MODE_25G);
 
 	/* Set MII or GMII interface based on the PHY speed. */
-	switch (IFM_SUBTYPE(mii->mii_media_active)) {
-	case IFM_10_T:
-		if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
-			DBPRINT(sc, BCE_INFO_PHY,
-			    "Enabling 10Mb interface.\n");
-			val |= BCE_EMAC_MODE_PORT_MII_10;
+	if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
+	    (IFM_ACTIVE | IFM_AVALID)) {
+		switch (IFM_SUBTYPE(mii->mii_media_active)) {
+		case IFM_10_T:
+			if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
+				DBPRINT(sc, BCE_INFO_PHY,
+				    "Enabling 10Mb interface.\n");
+				val |= BCE_EMAC_MODE_PORT_MII_10;
+				sc->bce_link_up = TRUE;
+				break;
+			}
+			/* FALLTHROUGH */
+		case IFM_100_TX:
+			DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n");
+			val |= BCE_EMAC_MODE_PORT_MII;
+			sc->bce_link_up = TRUE;
 			break;
-		}
-		/* fall-through */
-	case IFM_100_TX:
-		DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n");
-		val |= BCE_EMAC_MODE_PORT_MII;
-		break;
-	case IFM_2500_SX:
-		DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n");
-		val |= BCE_EMAC_MODE_25G;
-		/* fall-through */
-	case IFM_1000_T:
-	case IFM_1000_SX:
-		DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n");
-		val |= BCE_EMAC_MODE_PORT_GMII;
-		break;
-	default:
-		DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling "
-		    "default GMII interface.\n");
-		val |= BCE_EMAC_MODE_PORT_GMII;
-	}
+		case IFM_2500_SX:
+			DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n");
+			val |= BCE_EMAC_MODE_25G;
+			/* FALLTHROUGH */
+		case IFM_1000_T:
+		case IFM_1000_SX:
+			DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n");
+			val |= BCE_EMAC_MODE_PORT_GMII;
+			sc->bce_link_up = TRUE;
+			if (bce_verbose || bootverbose)
+				BCE_PRINTF("Gigabit link up!\n");
+			break;
+		default:
+			DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed.\n");
+			break;
+		}
+	}
+
+	if (sc->bce_link_up == FALSE)
+		return;
 
 	/* Set half or full duplex based on PHY settings. */
 	if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) {
@@ -2036,7 +2052,7 @@
 
 	REG_WR(sc, BCE_EMAC_MODE, val);
 
- 	if ((mii->mii_media_active & IFM_ETH_RXPAUSE) != 0) {
+	if ((mii->mii_media_active & IFM_ETH_RXPAUSE) != 0) {
 		DBPRINT(sc, BCE_INFO_PHY,
 		    "%s(): Enabling RX flow control.\n", __FUNCTION__);
 		BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
@@ -2046,7 +2062,7 @@
 		BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
 	}
 
- 	if ((mii->mii_media_active & IFM_ETH_TXPAUSE) != 0) {
+	if ((mii->mii_media_active & IFM_ETH_TXPAUSE) != 0) {
 		DBPRINT(sc, BCE_INFO_PHY,
 		    "%s(): Enabling TX flow control.\n", __FUNCTION__);
 		BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
@@ -6206,15 +6222,11 @@
 			DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n",
 			    __FUNCTION__);
 		}
-
 		/*
-		 * Assume link is down and allow
-		 * tick routine to update the state
-		 * based on the actual media state.
+		 * Link state changed, allow tick routine to update
+		 * the state baased on actual media state.
 		 */
-		sc->bce_link_up = FALSE;
-		callout_stop(&sc->bce_tick_callout);
-		bce_tick(sc);
+		sc->bce_link_tick = TRUE;
 	}
 
 	/* Acknowledge the link change interrupt. */
@@ -6898,12 +6910,13 @@
 	/* Enable host interrupts. */
 	bce_enable_intr(sc, 1);
 
-	bce_ifmedia_upd_locked(ifp);
-
 	/* Let the OS know the driver is up and running. */
 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 
+	sc->bce_link_tick = TRUE;
+	bce_ifmedia_upd_locked(ifp);
+
 	callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
 
 bce_init_locked_exit:
@@ -8199,31 +8212,19 @@
 	bce_watchdog(sc);
 
 	/* If link is up already up then we're done. */
-	if (sc->bce_link_up == TRUE)
+	if (sc->bce_link_tick == FALSE && sc->bce_link_up == TRUE)
 		goto bce_tick_exit;
 
 	/* Link is down.  Check what the PHY's doing. */
 	mii = device_get_softc(sc->bce_miibus);
 	mii_tick(mii);
 
-	/* Check if the link has come up. */
-	if ((mii->mii_media_status & IFM_ACTIVE) &&
-	    (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) {
+	sc->bce_link_tick = FALSE;
+	/* Now that link is up, handle any outstanding TX traffic. */
+	if (sc->bce_link_up == TRUE && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
 		DBPRINT(sc, BCE_VERBOSE_MISC,
-		    "%s(): Link up!\n", __FUNCTION__);
-		sc->bce_link_up = TRUE;
-		if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
-		    IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX ||
-		    IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) &&
-		    (bce_verbose || bootverbose))
-			BCE_PRINTF("Gigabit link up!\n");
-
-		/* Now that link is up, handle any outstanding TX traffic. */
-		if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
-			DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found "
-			    "pending TX traffic.\n", __FUNCTION__);
-			bce_start_locked(ifp);
-		}
+		    "%s(): Found pending TX traffic.\n", __FUNCTION__);
+		bce_start_locked(ifp);
 	}
 
 bce_tick_exit:
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/bce/if_bcereg.h
--- a/head/sys/dev/bce/if_bcereg.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/bce/if_bcereg.h	Thu Dec 15 12:59:38 2011 +0200
@@ -26,7 +26,7 @@
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  * THE POSSIBILITY OF SUCH DAMAGE.
  *
- * $FreeBSD: head/sys/dev/bce/if_bcereg.h 226123 2011-10-08 00:00:54Z yongari $
+ * $FreeBSD: head/sys/dev/bce/if_bcereg.h 228476 2011-12-13 18:11:25Z yongari $
  */
 
 #ifndef	_BCEREG_H_DEFINED
@@ -6560,6 +6560,7 @@
 	u16			pg_prod;
 	u16			pg_cons;
 
+	int			bce_link_tick;
 	int			bce_link_up;
 	struct		callout bce_tick_callout;
 	struct		callout bce_pulse_callout;
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/bge/if_bge.c
--- a/head/sys/dev/bge/if_bge.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/bge/if_bge.c	Thu Dec 15 12:59:38 2011 +0200
@@ -32,7 +32,7 @@
  */
 
 #include <sys/cdefs.h>
-__FBSDID("$FreeBSD: head/sys/dev/bge/if_bge.c 227843 2011-11-22 21:28:20Z marius $");
+__FBSDID("$FreeBSD: head/sys/dev/bge/if_bge.c 228480 2011-12-13 20:31:57Z yongari $");
 
 /*
  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
@@ -2080,9 +2080,15 @@
 			val |= BGE_RDMAMODE_TSO6_ENABLE;
 	}
 
-	if (sc->bge_asicrev == BGE_ASICREV_BCM5720)
+	if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
 		val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
 			BGE_RDMAMODE_H2BNC_VLAN_DET;
+		/*
+		 * Allow multiple outstanding read requests from
+		 * non-LSO read DMA engine.
+		 */
+		val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
+	}
 
 	if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
 	    sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
@@ -2112,12 +2118,20 @@
 		    BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
 	}
 
-	if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
-	    sc->bge_asicrev == BGE_ASICREV_BCM5720) {
+	if (sc->bge_asicrev == BGE_ASICREV_BCM5719) {
 		CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
 		    CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
 		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
 		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
+	} else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
+		/*
+		 * Allow 4KB burst length reads for non-LSO frames.
+		 * Enable 512B burst length reads for buffer descriptors.
+		 */
+		CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
+		    CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
+		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
+		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
 	}
 
 	CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
@@ -2344,6 +2358,8 @@
 
 	if (sc->bge_cdata.bge_rx_mtag)
 		bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
+	if (sc->bge_cdata.bge_mtag_jumbo)
+		bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo);
 	if (sc->bge_cdata.bge_tx_mtag)
 		bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
 
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/bge/if_bgereg.h
--- a/head/sys/dev/bge/if_bgereg.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/bge/if_bgereg.h	Thu Dec 15 12:59:38 2011 +0200
@@ -30,7 +30,7 @@
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  * THE POSSIBILITY OF SUCH DAMAGE.
  *
- * $FreeBSD: head/sys/dev/bge/if_bgereg.h 226871 2011-10-28 01:04:40Z yongari $
+ * $FreeBSD: head/sys/dev/bge/if_bgereg.h 228479 2011-12-13 20:26:46Z yongari $
  */
 
 /*
@@ -1573,6 +1573,7 @@
 #define	BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK	0x000FF000
 #define	BGE_RDMA_RSRVCTRL_TXMRGN_MASK	0xFFE00000
 
+#define	BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512	0x00020000
 #define	BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K	0x00030000
 #define	BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K	0x000C0000
 
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/bwn/if_bwnvar.h
--- a/head/sys/dev/bwn/if_bwnvar.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/bwn/if_bwnvar.h	Thu Dec 15 12:59:38 2011 +0200
@@ -26,7 +26,7 @@
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  * THE POSSIBILITY OF SUCH DAMAGES.
  *
- * $FreeBSD$
+ * $FreeBSD: head/sys/dev/bwn/if_bwnvar.h 228399 2011-12-10 21:05:06Z eadler $
  */
 
 #ifndef _IF_BWNVAR_H
@@ -714,7 +714,7 @@
 			uint16_t	tx_status;
 			struct bwn_plcp6	rts_plcp;
 			uint8_t		rts_frame[16];
-			uint8_t		pad1[2];;
+			uint8_t		pad1[2];
 			struct bwn_plcp6	plcp;
 		} __packed old;
 		/* format > r410 */
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/bxe/bxe_reg.h
--- a/head/sys/dev/bxe/bxe_reg.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/bxe/bxe_reg.h	Thu Dec 15 12:59:38 2011 +0200
@@ -30,7 +30,7 @@
  * THE POSSIBILITY OF SUCH DAMAGE.
  */
 
- /*$FreeBSD$*/
+ /*$FreeBSD: head/sys/dev/bxe/bxe_reg.h 228526 2011-12-15 06:29:13Z kevlo $*/
 
 /* bxe_reg.h: Broadcom Everest network driver.
  * The registers description starts with the register Access type followed
@@ -1594,7 +1594,7 @@
 /*
  * [RW 1] Setting this bit enables a timer in the GRC block to timeout an
  * access that does not finish within
- * ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is
+ * ~misc_registers_grc_timeout_val.grc_timeout_val cycles. When this bit is
  * cleared; this timeout is disabled. If this timeout occurs; the GRC shall
  * assert it attention output.
  */
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/cm/smc90cx6.c
--- a/head/sys/dev/cm/smc90cx6.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/cm/smc90cx6.c	Thu Dec 15 12:59:38 2011 +0200
@@ -1,7 +1,7 @@
 /*	$NetBSD: smc90cx6.c,v 1.38 2001/07/07 15:57:53 thorpej Exp $ */
 
 #include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: head/sys/dev/cm/smc90cx6.c 228471 2011-12-13 14:06:01Z ed $");
 
 /*-
  * Copyright (c) 1994, 1995, 1998 The NetBSD Foundation, Inc.
@@ -596,7 +596,7 @@
 	}
 }
 
-__inline static void
+static inline void
 cm_tint_locked(sc, isr)
 	struct cm_softc *sc;
 	int isr;
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/cpuctl/cpuctl.c
--- a/head/sys/dev/cpuctl/cpuctl.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/cpuctl/cpuctl.c	Thu Dec 15 12:59:38 2011 +0200
@@ -26,7 +26,7 @@
  */
 
 #include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: head/sys/dev/cpuctl/cpuctl.c 228436 2011-12-12 12:30:44Z fabient $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -74,6 +74,8 @@
 static int update_intel(int cpu, cpuctl_update_args_t *args,
     struct thread *td);
 static int update_amd(int cpu, cpuctl_update_args_t *args, struct thread *td);
+static int update_via(int cpu, cpuctl_update_args_t *args,
+    struct thread *td);
 
 static struct cdev **cpuctl_devs;
 static MALLOC_DEFINE(M_CPUCTL, "cpuctl", "CPUCTL buffer");
@@ -281,8 +283,10 @@
 	vendor[12] = '\0';
 	if (strncmp(vendor, INTEL_VENDOR_ID, sizeof(INTEL_VENDOR_ID)) == 0)
 		ret = update_intel(cpu, data, td);
-	else if(strncmp(vendor, INTEL_VENDOR_ID, sizeof(AMD_VENDOR_ID)) == 0)
+	else if(strncmp(vendor, AMD_VENDOR_ID, sizeof(AMD_VENDOR_ID)) == 0)
 		ret = update_amd(cpu, data, td);
+	else if(strncmp(vendor, CENTAUR_VENDOR_ID, sizeof(CENTAUR_VENDOR_ID)) == 0)
+		ret = update_via(cpu, data, td);
 	else
 		ret = ENXIO;
 	return (ret);
@@ -402,6 +406,81 @@
 	return (ret);
 }
 
+static int
+update_via(int cpu, cpuctl_update_args_t *args, struct thread *td)
+{
+	void *ptr = NULL;
+	uint64_t rev0, rev1, res;
+	uint32_t tmp[4];
+	int is_bound = 0;
+	int oldcpu;
+	int ret;
+
+	if (args->size == 0 || args->data == NULL) {
+		DPRINTF("[cpuctl,%d]: zero-sized firmware image", __LINE__);
+		return (EINVAL);
+	}
+	if (args->size > UCODE_SIZE_MAX) {
+		DPRINTF("[cpuctl,%d]: firmware image too large", __LINE__);
+		return (EINVAL);
+	}
+
+	/*
+	 * 4 byte alignment required.
+	 */
+	ptr = malloc(args->size + 16, M_CPUCTL, M_WAITOK);
+	ptr = (void *)(16 + ((intptr_t)ptr & ~0xf));
+	if (copyin(args->data, ptr, args->size) != 0) {
+		DPRINTF("[cpuctl,%d]: copyin %p->%p of %zd bytes failed",
+		    __LINE__, args->data, ptr, args->size);
+		ret = EFAULT;
+		goto fail;
+	}
+	oldcpu = td->td_oncpu;
+	is_bound = cpu_sched_is_bound(td);
+	set_cpu(cpu, td);
+	critical_enter();
+	rdmsr_safe(MSR_BIOS_SIGN, &rev0); /* Get current micorcode revision. */
+
+	/*
+	 * Perform update.
+	 */
+	wrmsr_safe(MSR_BIOS_UPDT_TRIG, (uintptr_t)(ptr));
+	do_cpuid(1, tmp);
+
+	/*
+	 * Result are in low byte of MSR FCR5:
+	 * 0x00: No update has been attempted since RESET.
+	 * 0x01: The last attempted update was successful.
+	 * 0x02: The last attempted update was unsuccessful due to a bad
+	 *       environment. No update was loaded and any preexisting
+	 *       patches are still active.
+	 * 0x03: The last attempted update was not applicable to this processor.
+	 *       No update was loaded and any preexisting patches are still
+	 *       active.
+	 * 0x04: The last attempted update was not successful due to an invalid
+	 *       update data block. No update was loaded and any preexisting
+	 *       patches are still active
+	 */
+	rdmsr_safe(0x1205, &res);
+	res &= 0xff;
+	critical_exit();
+	rdmsr_safe(MSR_BIOS_SIGN, &rev1); /* Get new microcode revision. */
+	restore_cpu(oldcpu, is_bound, td);
+
+	DPRINTF("[cpu,%d]: rev0=%x rev1=%x res=%x\n", __LINE__,
+	    (unsigned)(rev0 >> 32), (unsigned)(rev1 >> 32), (unsigned)res);
+
+	if (res != 0x01)
+		ret = EINVAL;
+	else
+		ret = 0;
+fail:
+	if (ptr != NULL)
+		contigfree(ptr, args->size, M_CPUCTL);
+	return (ret);
+}
+
 int
 cpuctl_open(struct cdev *dev, int flags, int fmt __unused, struct thread *td)
 {
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/cxgbe/osdep.h
--- a/head/sys/dev/cxgbe/osdep.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/cxgbe/osdep.h	Thu Dec 15 12:59:38 2011 +0200
@@ -24,7 +24,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- * $FreeBSD: head/sys/dev/cxgbe/osdep.h 222509 2011-05-30 21:07:26Z np $
+ * $FreeBSD: head/sys/dev/cxgbe/osdep.h 228443 2011-12-12 18:43:24Z mdf $
  *
  */
 
@@ -70,9 +70,11 @@
 #error "Must set BYTE_ORDER"
 #endif
 
+#ifndef __bool_true_false_are_defined
 typedef boolean_t bool;
 #define false FALSE
 #define true TRUE
+#endif
 
 #define mdelay(x) DELAY((x) * 1000)
 #define udelay(x) DELAY(x)
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/cxgbe/t4_sge.c
--- a/head/sys/dev/cxgbe/t4_sge.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/cxgbe/t4_sge.c	Thu Dec 15 12:59:38 2011 +0200
@@ -26,7 +26,7 @@
  */
 
 #include <sys/cdefs.h>
-__FBSDID("$FreeBSD: head/sys/dev/cxgbe/t4_sge.c 222973 2011-06-11 04:50:54Z np $");
+__FBSDID("$FreeBSD: head/sys/dev/cxgbe/t4_sge.c 228491 2011-12-14 05:34:23Z np $");
 
 #include "opt_inet.h"
 
@@ -1187,7 +1187,7 @@
 		}
 		fl->needed = fl->cap;
 
-		c.iqns_to_fl0congen =
+		c.iqns_to_fl0congen |=
 		    htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
 			F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
 			F_FW_IQ_CMD_FL0PADEN);
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/de/if_de.c
--- a/head/sys/dev/de/if_de.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/de/if_de.c	Thu Dec 15 12:59:38 2011 +0200
@@ -36,7 +36,7 @@
  */
 
 #include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: head/sys/dev/de/if_de.c 228471 2011-12-13 14:06:01Z ed $");
 
 #define	TULIP_HDR_DATA
 
@@ -1567,7 +1567,7 @@
 #endif
 }
 
-__inline static void
+static inline void
 tulip_21140_mediainit(tulip_softc_t * const sc, tulip_media_info_t * const mip,
     tulip_media_t const media, unsigned gpdata, unsigned cmdmode)
 {
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/drm/i915_drv.h
--- a/head/sys/dev/drm/i915_drv.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/drm/i915_drv.h	Thu Dec 15 12:59:38 2011 +0200
@@ -28,7 +28,7 @@
  */
 
 #include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
+__FBSDID("$FreeBSD: head/sys/dev/drm/i915_drv.h 228443 2011-12-12 18:43:24Z mdf $");
 
 #ifndef _I915_DRV_H_
 #define _I915_DRV_H_
@@ -560,7 +560,7 @@
 		LOCK_TEST_WITH_RETURN(dev, file_priv);			\
 } while (0)
 
-#if defined(__FreeBSD__)
+#if defined(__FreeBSD__) && !defined(__bool_true_false_are_defined)
 typedef boolean_t bool;
 #endif
 
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/e1000/e1000_80003es2lan.c
--- a/head/sys/dev/e1000/e1000_80003es2lan.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/e1000/e1000_80003es2lan.c	Thu Dec 15 12:59:38 2011 +0200
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD: head/sys/dev/e1000/e1000_80003es2lan.c 228386 2011-12-10 06:55:02Z jfv $*/
 
 /*
  * 80003ES2LAN Gigabit Ethernet Controller (Copper)
@@ -47,18 +47,18 @@
 static s32  e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw);
 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw);
 static s32  e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
-                                                   u32 offset,
-                                                   u16 *data);
+						   u32 offset,
+						   u16 *data);
 static s32  e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
-                                                    u32 offset,
-                                                    u16 data);
+						    u32 offset,
+						    u16 data);
 static s32  e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
-                                        u16 words, u16 *data);
+					u16 words, u16 *data);
 static s32  e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw);
 static s32  e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw);
 static s32  e1000_get_cable_length_80003es2lan(struct e1000_hw *hw);
 static s32  e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
-                                               u16 *duplex);
+					       u16 *duplex);
 static s32  e1000_reset_hw_80003es2lan(struct e1000_hw *hw);
 static s32  e1000_init_hw_80003es2lan(struct e1000_hw *hw);
 static s32  e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
@@ -68,9 +68,9 @@
 static s32  e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
 static s32  e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
 static s32  e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
-                                            u16 *data);
+					    u16 *data);
 static s32  e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
-                                             u16 data);
+					     u16 data);
 static s32  e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw);
 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
@@ -85,8 +85,8 @@
 static const u16 e1000_gg82563_cable_length_table[] = {
 	0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
-                (sizeof(e1000_gg82563_cable_length_table) / \
-                 sizeof(e1000_gg82563_cable_length_table[0]))
+		(sizeof(e1000_gg82563_cable_length_table) / \
+		 sizeof(e1000_gg82563_cable_length_table[0]))
 
 /**
  *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
@@ -100,34 +100,34 @@
 	DEBUGFUNC("e1000_init_phy_params_80003es2lan");
 
 	if (hw->phy.media_type != e1000_media_type_copper) {
-		phy->type        = e1000_phy_none;
+		phy->type = e1000_phy_none;
 		goto out;
 	} else {
 		phy->ops.power_up = e1000_power_up_phy_copper;
 		phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
 	}
 
-	phy->addr                = 1;
-	phy->autoneg_mask        = AUTONEG_ADVERTISE_SPEED_DEFAULT;
-	phy->reset_delay_us      = 100;
-	phy->type                = e1000_phy_gg82563;
+	phy->addr		= 1;
+	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;
+	phy->reset_delay_us	= 100;
+	phy->type		= e1000_phy_gg82563;
 
-	phy->ops.acquire            = e1000_acquire_phy_80003es2lan;
-	phy->ops.check_polarity     = e1000_check_polarity_m88;
-	phy->ops.check_reset_block  = e1000_check_reset_block_generic;
-	phy->ops.commit             = e1000_phy_sw_reset_generic;
-	phy->ops.get_cfg_done       = e1000_get_cfg_done_80003es2lan;
-	phy->ops.get_info           = e1000_get_phy_info_m88;
-	phy->ops.release            = e1000_release_phy_80003es2lan;
-	phy->ops.reset              = e1000_phy_hw_reset_generic;
-	phy->ops.set_d3_lplu_state  = e1000_set_d3_lplu_state_generic;
+	phy->ops.acquire	= e1000_acquire_phy_80003es2lan;
+	phy->ops.check_polarity	= e1000_check_polarity_m88;
+	phy->ops.check_reset_block = e1000_check_reset_block_generic;
+	phy->ops.commit		= e1000_phy_sw_reset_generic;
+	phy->ops.get_cfg_done	= e1000_get_cfg_done_80003es2lan;
+	phy->ops.get_info	= e1000_get_phy_info_m88;
+	phy->ops.release	= e1000_release_phy_80003es2lan;
+	phy->ops.reset		= e1000_phy_hw_reset_generic;
+	phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
 
 	phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan;
-	phy->ops.get_cable_length   = e1000_get_cable_length_80003es2lan;
-	phy->ops.read_reg           = e1000_read_phy_reg_gg82563_80003es2lan;
-	phy->ops.write_reg          = e1000_write_phy_reg_gg82563_80003es2lan;
+	phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan;
+	phy->ops.read_reg	= e1000_read_phy_reg_gg82563_80003es2lan;
+	phy->ops.write_reg	= e1000_write_phy_reg_gg82563_80003es2lan;
 
-	phy->ops.cfg_on_link_up    = e1000_cfg_on_link_up_80003es2lan;
+	phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan;
 
 	/* This can only be done after all function pointers are setup. */
 	ret_val = e1000_get_phy_id(hw);
@@ -154,19 +154,19 @@
 
 	DEBUGFUNC("e1000_init_nvm_params_80003es2lan");
 
-	nvm->opcode_bits        = 8;
-	nvm->delay_usec         = 1;
+	nvm->opcode_bits = 8;
+	nvm->delay_usec = 1;
 	switch (nvm->override) {
 	case e1000_nvm_override_spi_large:
-		nvm->page_size    = 32;
+		nvm->page_size = 32;
 		nvm->address_bits = 16;
 		break;
 	case e1000_nvm_override_spi_small:
-		nvm->page_size    = 8;
+		nvm->page_size = 8;
 		nvm->address_bits = 8;
 		break;
 	default:
-		nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
+		nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 		break;
 	}
@@ -174,7 +174,7 @@
 	nvm->type = e1000_nvm_eeprom_spi;
 
 	size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
-	                  E1000_EECD_SIZE_EX_SHIFT);
+		     E1000_EECD_SIZE_EX_SHIFT);
 
 	/*
 	 * Added to a constant, "size" becomes the left-shift value
@@ -185,16 +185,16 @@
 	/* EEPROM access above 16k is unsupported */
 	if (size > 14)
 		size = 14;
-	nvm->word_size	= 1 << size;
+	nvm->word_size = 1 << size;
 
 	/* Function Pointers */
-	nvm->ops.acquire           = e1000_acquire_nvm_80003es2lan;
-	nvm->ops.read              = e1000_read_nvm_eerd;
-	nvm->ops.release           = e1000_release_nvm_80003es2lan;
-	nvm->ops.update            = e1000_update_nvm_checksum_generic;
+	nvm->ops.acquire	= e1000_acquire_nvm_80003es2lan;
+	nvm->ops.read		= e1000_read_nvm_eerd;
+	nvm->ops.release	= e1000_release_nvm_80003es2lan;
+	nvm->ops.update		= e1000_update_nvm_checksum_generic;
 	nvm->ops.valid_led_default = e1000_valid_led_default_generic;
-	nvm->ops.validate          = e1000_validate_nvm_checksum_generic;
-	nvm->ops.write             = e1000_write_nvm_80003es2lan;
+	nvm->ops.validate	= e1000_validate_nvm_checksum_generic;
+	nvm->ops.write		= e1000_write_nvm_80003es2lan;
 
 	return E1000_SUCCESS;
 }
@@ -215,13 +215,13 @@
 		hw->phy.media_type = e1000_media_type_internal_serdes;
 		mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
 		mac->ops.setup_physical_interface =
-			e1000_setup_fiber_serdes_link_generic;
+					e1000_setup_fiber_serdes_link_generic;
 		break;
 	default:
 		hw->phy.media_type = e1000_media_type_copper;
 		mac->ops.check_for_link = e1000_check_for_copper_link_generic;
 		mac->ops.setup_physical_interface =
-			e1000_setup_copper_link_80003es2lan;
+					e1000_setup_copper_link_80003es2lan;
 		break;
 	}
 
@@ -234,9 +234,8 @@
 	/* FWSM register */
 	mac->has_fwsm = TRUE;
 	/* ARC supported; valid only if manageability features are enabled. */
-	mac->arc_subsystem_valid =
-	        (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
-	                ? TRUE : FALSE;
+	mac->arc_subsystem_valid = (E1000_READ_REG(hw, E1000_FWSM) &
+				    E1000_FWSM_MODE_MASK) ? TRUE : FALSE;
 	/* Adaptive IFS not supported */
 	mac->adaptive_ifs = FALSE;
 
@@ -330,7 +329,7 @@
 }
 
 /**
- *  e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register
+ *  e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register
  *  @hw: pointer to the HW structure
  *
  *  Acquire the semaphore to access the Kumeran interface.
@@ -348,7 +347,7 @@
 }
 
 /**
- *  e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register
+ *  e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register
  *  @hw: pointer to the HW structure
  *
  *  Release the semaphore used to access the Kumeran interface
@@ -488,7 +487,7 @@
  *  Read the GG82563 PHY register.
  **/
 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
-                                                  u32 offset, u16 *data)
+						  u32 offset, u16 *data)
 {
 	s32 ret_val;
 	u32 page_select;
@@ -538,14 +537,14 @@
 		usec_delay(200);
 
 		ret_val = e1000_read_phy_reg_mdic(hw,
-		                                  MAX_PHY_REG_ADDRESS & offset,
-		                                  data);
+						  MAX_PHY_REG_ADDRESS & offset,
+						  data);
 
 		usec_delay(200);
 	} else {
 		ret_val = e1000_read_phy_reg_mdic(hw,
-		                                  MAX_PHY_REG_ADDRESS & offset,
-		                                  data);
+						  MAX_PHY_REG_ADDRESS & offset,
+						  data);
 	}
 
 	e1000_release_phy_80003es2lan(hw);
@@ -563,7 +562,7 @@
  *  Write to the GG82563 PHY register.
  **/
 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
-                                                   u32 offset, u16 data)
+						   u32 offset, u16 data)
 {
 	s32 ret_val;
 	u32 page_select;
@@ -613,14 +612,14 @@
 		usec_delay(200);
 
 		ret_val = e1000_write_phy_reg_mdic(hw,
-		                                  MAX_PHY_REG_ADDRESS & offset,
-		                                  data);
+						  MAX_PHY_REG_ADDRESS & offset,
+						  data);
 
 		usec_delay(200);
 	} else {
 		ret_val = e1000_write_phy_reg_mdic(hw,
-		                                  MAX_PHY_REG_ADDRESS & offset,
-		                                  data);
+						  MAX_PHY_REG_ADDRESS & offset,
+						  data);
 	}
 
 	e1000_release_phy_80003es2lan(hw);
@@ -639,7 +638,7 @@
  *  Write "words" of data to the ESB2 NVM.
  **/
 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
-                            u16 words, u16 *data)
+				       u16 words, u16 *data)
 {
 	DEBUGFUNC("e1000_write_nvm_80003es2lan");
 
@@ -729,11 +728,10 @@
 	usec_delay(1);
 
 	if (hw->phy.autoneg_wait_to_complete) {
-		DEBUGOUT("Waiting for forced speed/duplex link "
-		         "on GG82563 phy.\n");
+		DEBUGOUT("Waiting for forced speed/duplex link on GG82563 phy.\n");
 
 		ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
-		                                     100000, &link);
+						     100000, &link);
 		if (ret_val)
 			goto out;
 
@@ -749,12 +747,13 @@
 
 		/* Try once more */
 		ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
-		                                     100000, &link);
+						     100000, &link);
 		if (ret_val)
 			goto out;
 	}
 
-	ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
+	ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
+				       &phy_data);
 	if (ret_val)
 		goto out;
 
@@ -773,7 +772,8 @@
 	 * duplex.
 	 */
 	phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
-	ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
+	ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
+					phy_data);
 
 out:
 	return ret_val;
@@ -826,21 +826,20 @@
  *  Retrieve the current speed and duplex configuration.
  **/
 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
-                                              u16 *duplex)
+					      u16 *duplex)
 {
 	s32 ret_val;
 
 	DEBUGFUNC("e1000_get_link_up_info_80003es2lan");
 
 	if (hw->phy.media_type == e1000_media_type_copper) {
-		ret_val = e1000_get_speed_and_duplex_copper_generic(hw,
-		                                                    speed,
-		                                                    duplex);
+		ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
+								    duplex);
 		hw->phy.ops.cfg_on_link_up(hw);
 	} else {
 		ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw,
-		                                                  speed,
-		                                                  duplex);
+								  speed,
+								  duplex);
 	}
 
 	return ret_val;
@@ -939,21 +938,21 @@
 
 	/* Disable IBIST slave mode (far-end loopback) */
 	e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
-	                                &kum_reg_data);
+					&kum_reg_data);
 	kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
 	e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
-	                                 kum_reg_data);
+					 kum_reg_data);
 
 	/* Set the transmit descriptor write-back policy */
 	reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
 	reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
-	           E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
+		   E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
 	E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
 
 	/* ...for both queues. */
 	reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
 	reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
-	           E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
+		   E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
 	E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
 
 	/* Enable retransmit on late collisions */
@@ -981,9 +980,9 @@
 	hw->dev_spec._80003es2lan.mdic_wa_enable = TRUE;
 
 	ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
-	                              E1000_KMRNCTRLSTA_OFFSET >>
-	                              E1000_KMRNCTRLSTA_OFFSET_SHIFT,
-	                              &i);
+						 E1000_KMRNCTRLSTA_OFFSET >>
+						 E1000_KMRNCTRLSTA_OFFSET_SHIFT,
+						 &i);
 	if (!ret_val) {
 		if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
 		     E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
@@ -1056,11 +1055,7 @@
 
 	DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan");
 
-	if (phy->reset_disable)
-		goto skip_reset;
-
-	ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
-				     &data);
+	ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
 	if (ret_val)
 		goto out;
 
@@ -1068,8 +1063,7 @@
 	/* Use 25MHz for both link down and 1000Base-T for Tx clock. */
 	data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
 
-	ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
-				      data);
+	ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
 	if (ret_val)
 		goto out;
 
@@ -1122,7 +1116,6 @@
 		goto out;
 	}
 
-skip_reset:
 	/* Bypass Rx and Tx FIFO's */
 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
 					E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
@@ -1132,14 +1125,12 @@
 		goto out;
 
 	ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
-	                              E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
-	                              &data);
+				E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, &data);
 	if (ret_val)
 		goto out;
 	data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
-	                               E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
-	                               data);
+				E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, data);
 	if (ret_val)
 		goto out;
 
@@ -1169,18 +1160,18 @@
 		/* Enable Electrical Idle on the PHY */
 		data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
 		ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
-		                                data);
+						data);
 		if (ret_val)
 			goto out;
 
 		ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
-		                               &data);
+					       &data);
 		if (ret_val)
 			goto out;
 
 		data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
 		ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
-		                                data);
+						data);
 		if (ret_val)
 			goto out;
 	}
@@ -1228,27 +1219,25 @@
 	 * polling the phy; this fixes erroneous timeouts at 10Mbps.
 	 */
 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
-	                                           0xFFFF);
+						   0xFFFF);
 	if (ret_val)
 		goto out;
 	ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
-	                                          &reg_data);
+						  &reg_data);
 	if (ret_val)
 		goto out;
 	reg_data |= 0x3F;
 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
-	                                           reg_data);
+						   reg_data);
 	if (ret_val)
 		goto out;
 	ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
-	                              E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
-	                              &reg_data);
+				E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, &reg_data);
 	if (ret_val)
 		goto out;
 	reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
-	                               E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
-	                               reg_data);
+				E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, reg_data);
 	if (ret_val)
 		goto out;
 
@@ -1279,9 +1268,8 @@
 	DEBUGFUNC("e1000_configure_on_link_up");
 
 	if (hw->phy.media_type == e1000_media_type_copper) {
-		ret_val = e1000_get_speed_and_duplex_copper_generic(hw,
-		                                                    &speed,
-		                                                    &duplex);
+		ret_val = e1000_get_speed_and_duplex_copper_generic(hw, &speed,
+								    &duplex);
 		if (ret_val)
 			goto out;
 
@@ -1314,8 +1302,8 @@
 
 	reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
-	                               E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
-	                               reg_data);
+				       E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
+				       reg_data);
 	if (ret_val)
 		goto out;
 
@@ -1327,12 +1315,12 @@
 
 	do {
 		ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
-		                               &reg_data);
+					       &reg_data);
 		if (ret_val)
 			goto out;
 
 		ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
-		                               &reg_data2);
+					       &reg_data2);
 		if (ret_val)
 			goto out;
 		i++;
@@ -1343,7 +1331,8 @@
 	else
 		reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
 
-	ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
+	ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
+					reg_data);
 
 out:
 	return ret_val;
@@ -1367,8 +1356,7 @@
 
 	reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
 	ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
-	                               E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
-	                               reg_data);
+				E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, reg_data);
 	if (ret_val)
 		goto out;
 
@@ -1380,19 +1368,20 @@
 
 	do {
 		ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
-		                               &reg_data);
+					       &reg_data);
 		if (ret_val)
 			goto out;
 
 		ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
-		                               &reg_data2);
+					       &reg_data2);
 		if (ret_val)
 			goto out;
 		i++;
 	} while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
 
 	reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
-	ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
+	ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
+					reg_data);
 
 out:
 	return ret_val;
@@ -1409,7 +1398,7 @@
  *  Release the semaphore before exiting.
  **/
 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
-                                           u16 *data)
+					   u16 *data)
 {
 	u32 kmrnctrlsta;
 	s32 ret_val = E1000_SUCCESS;
@@ -1421,8 +1410,9 @@
 		goto out;
 
 	kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
-	               E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
+		       E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
 	E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
+	E1000_WRITE_FLUSH(hw);
 
 	usec_delay(2);
 
@@ -1446,7 +1436,7 @@
  *  before exiting.
  **/
 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
-                                            u16 data)
+					    u16 data)
 {
 	u32 kmrnctrlsta;
 	s32 ret_val = E1000_SUCCESS;
@@ -1458,8 +1448,9 @@
 		goto out;
 
 	kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
-	               E1000_KMRNCTRLSTA_OFFSET) | data;
+		       E1000_KMRNCTRLSTA_OFFSET) | data;
 	E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
+	E1000_WRITE_FLUSH(hw);
 
 	usec_delay(2);
 
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/e1000/e1000_80003es2lan.h
--- a/head/sys/dev/e1000/e1000_80003es2lan.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/e1000/e1000_80003es2lan.h	Thu Dec 15 12:59:38 2011 +0200
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,53 +30,52 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD: head/sys/dev/e1000/e1000_80003es2lan.h 228386 2011-12-10 06:55:02Z jfv $*/
 
 #ifndef _E1000_80003ES2LAN_H_
 #define _E1000_80003ES2LAN_H_
 
-#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL       0x00
-#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL        0x02
-#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL         0x10
-#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE  0x1F
+#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL	0x00
+#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL	0x02
+#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL	0x10
+#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE	0x1F
 
-#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS    0x0008
-#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS    0x0800
-#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING   0x0010
+#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS	0x0008
+#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS	0x0800
+#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING	0x0010
 
 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
-#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT   0x0000
-#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE          0x2000
+#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT	0x0000
+#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE		0x2000
 
-#define E1000_KMRNCTRLSTA_OPMODE_MASK            0x000C
-#define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO     0x0004
+#define E1000_KMRNCTRLSTA_OPMODE_MASK		0x000C
+#define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO	0x0004
 
 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
-#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN        0x00010000
+#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN	0x00010000
 
-#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN       0x8
-#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN     0x9
+#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN	0x8
+#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN	0x9
 
 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
-#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE  0x0002 /* 1=Reversal Disabled */
-#define GG82563_PSCR_CROSSOVER_MODE_MASK        0x0060
-#define GG82563_PSCR_CROSSOVER_MODE_MDI         0x0000 /* 00=Manual MDI */
-#define GG82563_PSCR_CROSSOVER_MODE_MDIX        0x0020 /* 01=Manual MDIX */
-#define GG82563_PSCR_CROSSOVER_MODE_AUTO        0x0060 /* 11=Auto crossover */
+#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE	0x0002 /* 1=Reversal Disabled */
+#define GG82563_PSCR_CROSSOVER_MODE_MASK	0x0060
+#define GG82563_PSCR_CROSSOVER_MODE_MDI		0x0000 /* 00=Manual MDI */
+#define GG82563_PSCR_CROSSOVER_MODE_MDIX	0x0020 /* 01=Manual MDIX */
+#define GG82563_PSCR_CROSSOVER_MODE_AUTO	0x0060 /* 11=Auto crossover */
 
 /* PHY Specific Control Register 2 (Page 0, Register 26) */
-#define GG82563_PSCR2_REVERSE_AUTO_NEG          0x2000
-                                               /* 1=Reverse Auto-Negotiation */
+#define GG82563_PSCR2_REVERSE_AUTO_NEG		0x2000 /* 1=Reverse Auto-Nego */
 
 /* MAC Specific Control Register (Page 2, Register 21) */
 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
-#define GG82563_MSCR_TX_CLK_MASK                0x0007
-#define GG82563_MSCR_TX_CLK_10MBPS_2_5          0x0004
-#define GG82563_MSCR_TX_CLK_100MBPS_25          0x0005
-#define GG82563_MSCR_TX_CLK_1000MBPS_2_5        0x0006
-#define GG82563_MSCR_TX_CLK_1000MBPS_25         0x0007
+#define GG82563_MSCR_TX_CLK_MASK		0x0007
+#define GG82563_MSCR_TX_CLK_10MBPS_2_5		0x0004
+#define GG82563_MSCR_TX_CLK_100MBPS_25		0x0005
+#define GG82563_MSCR_TX_CLK_1000MBPS_2_5	0x0006
+#define GG82563_MSCR_TX_CLK_1000MBPS_25		0x0007
 
-#define GG82563_MSCR_ASSERT_CRS_ON_TX           0x0010 /* 1=Assert */
+#define GG82563_MSCR_ASSERT_CRS_ON_TX		0x0010 /* 1=Assert */
 
 /* DSP Distance Register (Page 5, Register 26) */
 /*
@@ -86,19 +85,19 @@
  * 3 = 110-140M
  * 4 = >140M
  */
-#define GG82563_DSPD_CABLE_LENGTH               0x0007
+#define GG82563_DSPD_CABLE_LENGTH		0x0007
 
 /* Kumeran Mode Control Register (Page 193, Register 16) */
-#define GG82563_KMCR_PASS_FALSE_CARRIER         0x0800
+#define GG82563_KMCR_PASS_FALSE_CARRIER		0x0800
 
 /* Max number of times Kumeran read/write should be validated */
-#define GG82563_MAX_KMRN_RETRY                  0x5
+#define GG82563_MAX_KMRN_RETRY			0x5
 
 /* Power Management Control Register (Page 193, Register 20) */
-#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE     0x0001
-                                          /* 1=Enable SERDES Electrical Idle */
+/* 1=Enable SERDES Electrical Idle */
+#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE	0x0001
 
 /* In-Band Control Register (Page 194, Register 18) */
-#define GG82563_ICR_DIS_PADDING                 0x0010 /* Disable Padding */
+#define GG82563_ICR_DIS_PADDING			0x0010 /* Disable Padding */
 
 #endif
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/e1000/e1000_82540.c
--- a/head/sys/dev/e1000/e1000_82540.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/e1000/e1000_82540.c	Thu Dec 15 12:59:38 2011 +0200
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD: head/sys/dev/e1000/e1000_82540.c 228386 2011-12-10 06:55:02Z jfv $*/
 
 /*
  * 82540EM Gigabit Ethernet Controller
@@ -68,23 +68,23 @@
 	struct e1000_phy_info *phy = &hw->phy;
 	s32 ret_val = E1000_SUCCESS;
 
-	phy->addr                      = 1;
-	phy->autoneg_mask              = AUTONEG_ADVERTISE_SPEED_DEFAULT;
-	phy->reset_delay_us            = 10000;
-	phy->type                      = e1000_phy_m88;
+	phy->addr		= 1;
+	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;
+	phy->reset_delay_us	= 10000;
+	phy->type		= e1000_phy_m88;
 
 	/* Function Pointers */
-	phy->ops.check_polarity        = e1000_check_polarity_m88;
-	phy->ops.commit                = e1000_phy_sw_reset_generic;
-	phy->ops.force_speed_duplex    = e1000_phy_force_speed_duplex_m88;
-	phy->ops.get_cable_length      = e1000_get_cable_length_m88;
-	phy->ops.get_cfg_done          = e1000_get_cfg_done_generic;
-	phy->ops.read_reg              = e1000_read_phy_reg_m88;
-	phy->ops.reset                 = e1000_phy_hw_reset_generic;
-	phy->ops.write_reg             = e1000_write_phy_reg_m88;
-	phy->ops.get_info              = e1000_get_phy_info_m88;
-	phy->ops.power_up              = e1000_power_up_phy_copper;
-	phy->ops.power_down            = e1000_power_down_phy_copper_82540;
+	phy->ops.check_polarity	= e1000_check_polarity_m88;
+	phy->ops.commit		= e1000_phy_sw_reset_generic;
+	phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
+	phy->ops.get_cable_length = e1000_get_cable_length_m88;
+	phy->ops.get_cfg_done	= e1000_get_cfg_done_generic;
+	phy->ops.read_reg	= e1000_read_phy_reg_m88;
+	phy->ops.reset		= e1000_phy_hw_reset_generic;
+	phy->ops.write_reg	= e1000_write_phy_reg_m88;
+	phy->ops.get_info	= e1000_get_phy_info_m88;
+	phy->ops.power_up	= e1000_power_up_phy_copper;
+	phy->ops.power_down	= e1000_power_down_phy_copper_82540;
 
 	ret_val = e1000_get_phy_id(hw);
 	if (ret_val)
@@ -121,32 +121,32 @@
 
 	DEBUGFUNC("e1000_init_nvm_params_82540");
 
-	nvm->type               = e1000_nvm_eeprom_microwire;
-	nvm->delay_usec         = 50;
-	nvm->opcode_bits        = 3;
+	nvm->type = e1000_nvm_eeprom_microwire;
+	nvm->delay_usec = 50;
+	nvm->opcode_bits = 3;
 	switch (nvm->override) {
 	case e1000_nvm_override_microwire_large:
-		nvm->address_bits       = 8;
-		nvm->word_size          = 256;
+		nvm->address_bits = 8;
+		nvm->word_size = 256;
 		break;
 	case e1000_nvm_override_microwire_small:
-		nvm->address_bits       = 6;
-		nvm->word_size          = 64;
+		nvm->address_bits = 6;
+		nvm->word_size = 64;
 		break;
 	default:
-		nvm->address_bits       = eecd & E1000_EECD_SIZE ? 8 : 6;
-		nvm->word_size          = eecd & E1000_EECD_SIZE ? 256 : 64;
+		nvm->address_bits = eecd & E1000_EECD_SIZE ? 8 : 6;
+		nvm->word_size = eecd & E1000_EECD_SIZE ? 256 : 64;
 		break;
 	}
 
 	/* Function Pointers */
-	nvm->ops.acquire            = e1000_acquire_nvm_generic;
-	nvm->ops.read               = e1000_read_nvm_microwire;
-	nvm->ops.release            = e1000_release_nvm_generic;
-	nvm->ops.update             = e1000_update_nvm_checksum_generic;
-	nvm->ops.valid_led_default  = e1000_valid_led_default_generic;
-	nvm->ops.validate           = e1000_validate_nvm_checksum_generic;
-	nvm->ops.write              = e1000_write_nvm_microwire;
+	nvm->ops.acquire	= e1000_acquire_nvm_generic;
+	nvm->ops.read		= e1000_read_nvm_microwire;
+	nvm->ops.release	= e1000_release_nvm_generic;
+	nvm->ops.update		= e1000_update_nvm_checksum_generic;
+	nvm->ops.valid_led_default = e1000_valid_led_default_generic;
+	nvm->ops.validate	= e1000_validate_nvm_checksum_generic;
+	nvm->ops.write		= e1000_write_nvm_microwire;
 
 	return E1000_SUCCESS;
 }
@@ -198,9 +198,9 @@
 	mac->ops.setup_link = e1000_setup_link_generic;
 	/* physical interface setup */
 	mac->ops.setup_physical_interface =
-	        (hw->phy.media_type == e1000_media_type_copper)
-	                ? e1000_setup_copper_link_82540
-	                : e1000_setup_fiber_serdes_link_82540;
+		(hw->phy.media_type == e1000_media_type_copper)
+			? e1000_setup_copper_link_82540
+			: e1000_setup_fiber_serdes_link_82540;
 	/* check for link */
 	switch (hw->phy.media_type) {
 	case e1000_media_type_copper:
@@ -219,9 +219,9 @@
 	}
 	/* link info */
 	mac->ops.get_link_up_info =
-	        (hw->phy.media_type == e1000_media_type_copper)
-	                ? e1000_get_speed_and_duplex_copper_generic
-	                : e1000_get_speed_and_duplex_fiber_serdes_generic;
+		(hw->phy.media_type == e1000_media_type_copper)
+			? e1000_get_speed_and_duplex_copper_generic
+			: e1000_get_speed_and_duplex_fiber_serdes_generic;
 	/* multicast address update */
 	mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 	/* writing VFTA */
@@ -374,7 +374,7 @@
 
 	txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
 	txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
-	         E1000_TXDCTL_FULL_TX_DESC_WB;
+		  E1000_TXDCTL_FULL_TX_DESC_WB;
 	E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
 
 	/*
@@ -427,11 +427,13 @@
 
 	if (hw->mac.type == e1000_82545_rev_3 ||
 	    hw->mac.type == e1000_82546_rev_3) {
-		ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &data);
+		ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
+					       &data);
 		if (ret_val)
 			goto out;
 		data |= 0x00000008;
-		ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, data);
+		ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
+						data);
 		if (ret_val)
 			goto out;
 	}
@@ -508,9 +510,8 @@
 	if (nvm_data != NVM_RESERVED_WORD) {
 		/* Adjust serdes output amplitude only. */
 		nvm_data &= NVM_SERDES_AMPLITUDE_MASK;
-		ret_val = hw->phy.ops.write_reg(hw,
-		                             M88E1000_PHY_EXT_CTRL,
-		                             nvm_data);
+		ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_EXT_CTRL,
+						nvm_data);
 		if (ret_val)
 			goto out;
 	}
@@ -535,9 +536,8 @@
 
 	/* Set PHY register 30, page 5, bit 8 to 0 */
 
-	ret_val = hw->phy.ops.read_reg(hw,
-	                            M88E1000_PHY_PAGE_SELECT,
-	                            &default_page);
+	ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_PAGE_SELECT,
+				       &default_page);
 	if (ret_val)
 		goto out;
 
@@ -570,7 +570,7 @@
 		goto out;
 
 	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
-	                              default_page);
+					default_page);
 
 out:
 	return ret_val;
@@ -587,7 +587,6 @@
  **/
 static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw)
 {
-	struct e1000_phy_info *phy = &hw->phy;
 	s32 ret_val = E1000_SUCCESS;
 	u16 nvm_data;
 
@@ -604,20 +603,18 @@
 
 	if ((nvm_data != NVM_RESERVED_WORD) && (nvm_data & NVM_PHY_CLASS_A)) {
 		ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
-		                              0x000B);
+						0x000B);
 		if (ret_val) {
 			ret_val = -E1000_ERR_PHY;
 			goto out;
 		}
-		ret_val = hw->phy.ops.write_reg(hw,
-		                              M88E1000_PHY_GEN_CONTROL,
-		                              0x8104);
+		ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL,
+						0x8104);
 		if (ret_val) {
 			ret_val = -E1000_ERR_PHY;
 			goto out;
 		}
 
-		phy->reset_disable = FALSE;
 	}
 
 out:
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/e1000/e1000_82541.c
--- a/head/sys/dev/e1000/e1000_82541.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/e1000/e1000_82541.c	Thu Dec 15 12:59:38 2011 +0200
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD: head/sys/dev/e1000/e1000_82541.c 228386 2011-12-10 06:55:02Z jfv $*/
 
 /*
  * 82541EI Gigabit Ethernet Controller
@@ -300,7 +300,7 @@
  **/
 static s32 e1000_reset_hw_82541(struct e1000_hw *hw)
 {
-	u32 ledctl, ctrl, manc;
+	u32 ledctl, ctrl, icr, manc;
 
 	DEBUGFUNC("e1000_reset_hw_82541");
 
@@ -364,7 +364,7 @@
 	E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
 
 	/* Clear any pending interrupt events. */
-	E1000_READ_REG(hw, E1000_ICR);
+	icr = E1000_READ_REG(hw, E1000_ICR);
 
 	return E1000_SUCCESS;
 }
@@ -390,7 +390,7 @@
 		DEBUGOUT("Error initializing identification LED\n");
 		/* This is not fatal and we should not stop init due to this */
 	}
-
+        
 	/* Storing the Speed Power Down  value for later use */
 	ret_val = hw->phy.ops.read_reg(hw,
 	                               IGP01E1000_GMII_FIFO,
@@ -549,8 +549,6 @@
 	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
 
-	hw->phy.reset_disable = FALSE;
-
 	/* Earlier revs of the IGP phy require us to force MDI. */
 	if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) {
 		dev_spec->dsp_config = e1000_dsp_config_disabled;
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/e1000/e1000_82543.c
--- a/head/sys/dev/e1000/e1000_82543.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/e1000/e1000_82543.c	Thu Dec 15 12:59:38 2011 +0200
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD: head/sys/dev/e1000/e1000_82543.c 228386 2011-12-10 06:55:02Z jfv $*/
 
 /*
  * 82543GC Gigabit Ethernet Controller (Fiber)
@@ -901,7 +901,7 @@
  **/
 static s32 e1000_reset_hw_82543(struct e1000_hw *hw)
 {
-	u32 ctrl;
+	u32 ctrl, icr;
 	s32 ret_val = E1000_SUCCESS;
 
 	DEBUGFUNC("e1000_reset_hw_82543");
@@ -943,7 +943,7 @@
 
 	/* Masking off and clearing any pending interrupts */
 	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
-	E1000_READ_REG(hw, E1000_ICR);
+	icr = E1000_READ_REG(hw, E1000_ICR);
 
 	return ret_val;
 }
@@ -1079,7 +1079,6 @@
 		ret_val = hw->phy.ops.reset(hw);
 		if (ret_val)
 			goto out;
-		hw->phy.reset_disable = FALSE;
 	} else {
 		ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
 		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/e1000/e1000_82571.c
--- a/head/sys/dev/e1000/e1000_82571.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/e1000/e1000_82571.c	Thu Dec 15 12:59:38 2011 +0200
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD: head/sys/dev/e1000/e1000_82571.c 228386 2011-12-10 06:55:02Z jfv $*/
 
 /*
  * 82571EB Gigabit Ethernet Controller
@@ -57,12 +57,12 @@
 static s32  e1000_acquire_nvm_82571(struct e1000_hw *hw);
 static void e1000_release_nvm_82571(struct e1000_hw *hw);
 static s32  e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
-                                  u16 words, u16 *data);
+				  u16 words, u16 *data);
 static s32  e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
 static s32  e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
 static s32  e1000_get_cfg_done_82571(struct e1000_hw *hw);
 static s32  e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
-                                          bool active);
+					  bool active);
 static s32  e1000_reset_hw_82571(struct e1000_hw *hw);
 static s32  e1000_init_hw_82571(struct e1000_hw *hw);
 static void e1000_clear_vfta_82571(struct e1000_hw *hw);
@@ -83,12 +83,12 @@
 static s32  e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
 static s32  e1000_set_d0_lplu_state_82574(struct e1000_hw *hw,
-                                          bool active);
+					  bool active);
 static s32  e1000_set_d3_lplu_state_82574(struct e1000_hw *hw,
-                                          bool active);
+					  bool active);
 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
 static s32  e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
-                                       u16 words, u16 *data);
+				       u16 words, u16 *data);
 static s32  e1000_read_mac_addr_82571(struct e1000_hw *hw);
 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
 
@@ -108,61 +108,61 @@
 		goto out;
 	}
 
-	phy->addr                        = 1;
-	phy->autoneg_mask                = AUTONEG_ADVERTISE_SPEED_DEFAULT;
-	phy->reset_delay_us              = 100;
+	phy->addr			= 1;
+	phy->autoneg_mask		= AUTONEG_ADVERTISE_SPEED_DEFAULT;
+	phy->reset_delay_us		= 100;
 
-	phy->ops.check_reset_block       = e1000_check_reset_block_generic;
-	phy->ops.reset                   = e1000_phy_hw_reset_generic;
-	phy->ops.set_d0_lplu_state       = e1000_set_d0_lplu_state_82571;
-	phy->ops.set_d3_lplu_state       = e1000_set_d3_lplu_state_generic;
-	phy->ops.power_up                = e1000_power_up_phy_copper;
-	phy->ops.power_down              = e1000_power_down_phy_copper_82571;
+	phy->ops.check_reset_block	= e1000_check_reset_block_generic;
+	phy->ops.reset			= e1000_phy_hw_reset_generic;
+	phy->ops.set_d0_lplu_state	= e1000_set_d0_lplu_state_82571;
+	phy->ops.set_d3_lplu_state	= e1000_set_d3_lplu_state_generic;
+	phy->ops.power_up		= e1000_power_up_phy_copper;
+	phy->ops.power_down		= e1000_power_down_phy_copper_82571;
 
 	switch (hw->mac.type) {
 	case e1000_82571:
 	case e1000_82572:
-		phy->type                   = e1000_phy_igp_2;
-		phy->ops.get_cfg_done       = e1000_get_cfg_done_82571;
-		phy->ops.get_info           = e1000_get_phy_info_igp;
-		phy->ops.check_polarity     = e1000_check_polarity_igp;
+		phy->type		= e1000_phy_igp_2;
+		phy->ops.get_cfg_done	= e1000_get_cfg_done_82571;
+		phy->ops.get_info	= e1000_get_phy_info_igp;
+		phy->ops.check_polarity	= e1000_check_polarity_igp;
 		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
-		phy->ops.get_cable_length   = e1000_get_cable_length_igp_2;
-		phy->ops.read_reg           = e1000_read_phy_reg_igp;
-		phy->ops.write_reg          = e1000_write_phy_reg_igp;
-		phy->ops.acquire            = e1000_get_hw_semaphore_82571;
-		phy->ops.release            = e1000_put_hw_semaphore_82571;
+		phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
+		phy->ops.read_reg	= e1000_read_phy_reg_igp;
+		phy->ops.write_reg	= e1000_write_phy_reg_igp;
+		phy->ops.acquire	= e1000_get_hw_semaphore_82571;
+		phy->ops.release	= e1000_put_hw_semaphore_82571;
 		break;
 	case e1000_82573:
-		phy->type                   = e1000_phy_m88;
-		phy->ops.get_cfg_done       = e1000_get_cfg_done_generic;
-		phy->ops.get_info           = e1000_get_phy_info_m88;
-		phy->ops.check_polarity     = e1000_check_polarity_m88;
-		phy->ops.commit             = e1000_phy_sw_reset_generic;
+		phy->type		= e1000_phy_m88;
+		phy->ops.get_cfg_done	= e1000_get_cfg_done_generic;
+		phy->ops.get_info	= e1000_get_phy_info_m88;
+		phy->ops.check_polarity	= e1000_check_polarity_m88;
+		phy->ops.commit		= e1000_phy_sw_reset_generic;
 		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
-		phy->ops.get_cable_length   = e1000_get_cable_length_m88;
-		phy->ops.read_reg           = e1000_read_phy_reg_m88;
-		phy->ops.write_reg          = e1000_write_phy_reg_m88;
-		phy->ops.acquire            = e1000_get_hw_semaphore_82571;
-		phy->ops.release            = e1000_put_hw_semaphore_82571;
+		phy->ops.get_cable_length = e1000_get_cable_length_m88;
+		phy->ops.read_reg	= e1000_read_phy_reg_m88;
+		phy->ops.write_reg	= e1000_write_phy_reg_m88;
+		phy->ops.acquire	= e1000_get_hw_semaphore_82571;
+		phy->ops.release	= e1000_put_hw_semaphore_82571;
 		break;
 	case e1000_82574:
 	case e1000_82583:
 		E1000_MUTEX_INIT(&hw->dev_spec._82571.swflag_mutex);
 
-		phy->type                   = e1000_phy_bm;
-		phy->ops.get_cfg_done       = e1000_get_cfg_done_generic;
-		phy->ops.get_info           = e1000_get_phy_info_m88;
-		phy->ops.check_polarity     = e1000_check_polarity_m88;
-		phy->ops.commit             = e1000_phy_sw_reset_generic;
+		phy->type		= e1000_phy_bm;
+		phy->ops.get_cfg_done	= e1000_get_cfg_done_generic;
+		phy->ops.get_info	= e1000_get_phy_info_m88;
+		phy->ops.check_polarity	= e1000_check_polarity_m88;
+		phy->ops.commit		= e1000_phy_sw_reset_generic;
 		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
-		phy->ops.get_cable_length   = e1000_get_cable_length_m88;
-		phy->ops.read_reg           = e1000_read_phy_reg_bm2;
-		phy->ops.write_reg          = e1000_write_phy_reg_bm2;
-		phy->ops.acquire            = e1000_get_hw_semaphore_82574;
-		phy->ops.release            = e1000_put_hw_semaphore_82574;
-		phy->ops.set_d0_lplu_state  = e1000_set_d0_lplu_state_82574;
-		phy->ops.set_d3_lplu_state  = e1000_set_d3_lplu_state_82574;
+		phy->ops.get_cable_length = e1000_get_cable_length_m88;
+		phy->ops.read_reg	= e1000_read_phy_reg_bm2;
+		phy->ops.write_reg	= e1000_write_phy_reg_bm2;
+		phy->ops.acquire	= e1000_get_hw_semaphore_82574;
+		phy->ops.release	= e1000_put_hw_semaphore_82574;
+		phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
+		phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
 		break;
 	default:
 		ret_val = -E1000_ERR_PHY;
@@ -253,7 +253,7 @@
 	default:
 		nvm->type = e1000_nvm_eeprom_spi;
 		size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
-		                  E1000_EECD_SIZE_EX_SHIFT);
+			     E1000_EECD_SIZE_EX_SHIFT);
 		/*
 		 * Added to a constant, "size" becomes the left-shift value
 		 * for setting word_size.
@@ -263,7 +263,7 @@
 		/* EEPROM access above 16k is unsupported */
 		if (size > 14)
 			size = 14;
-		nvm->word_size	= 1 << size;
+		nvm->word_size = 1 << size;
 		break;
 	}
 
@@ -279,11 +279,11 @@
 		nvm->ops.release = e1000_release_nvm_82571;
 		break;
 	}
-	nvm->ops.read          = e1000_read_nvm_eerd;
-	nvm->ops.update        = e1000_update_nvm_checksum_82571;
-	nvm->ops.validate      = e1000_validate_nvm_checksum_82571;
+	nvm->ops.read = e1000_read_nvm_eerd;
+	nvm->ops.update = e1000_update_nvm_checksum_82571;
+	nvm->ops.validate = e1000_validate_nvm_checksum_82571;
 	nvm->ops.valid_led_default = e1000_valid_led_default_82571;
-	nvm->ops.write         = e1000_write_nvm_82571;
+	nvm->ops.write = e1000_write_nvm_82571;
 
 	return E1000_SUCCESS;
 }
@@ -363,8 +363,6 @@
 	mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
 	/* ID LED init */
 	mac->ops.id_led_init = e1000_id_led_init_generic;
-	/* blink LED */
-	mac->ops.blink_led = e1000_blink_led_generic;
 	/* setup LED */
 	mac->ops.setup_led = e1000_setup_led_generic;
 	/* cleanup LED */
@@ -380,6 +378,7 @@
 		mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 		mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 		mac->ops.led_on = e1000_led_on_generic;
+		mac->ops.blink_led = e1000_blink_led_generic;
 
 		/* FWSM register */
 		mac->has_fwsm = TRUE;
@@ -387,9 +386,8 @@
 		 * ARC supported; valid only if manageability features are
 		 * enabled.
 		 */
-		mac->arc_subsystem_valid =
-			(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
-			? TRUE : FALSE;
+		mac->arc_subsystem_valid = (E1000_READ_REG(hw, E1000_FWSM) &
+					   E1000_FWSM_MODE_MASK) ? TRUE : FALSE;
 		break;
 	case e1000_82574:
 	case e1000_82583:
@@ -400,6 +398,7 @@
 	default:
 		mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 		mac->ops.led_on = e1000_led_on_generic;
+		mac->ops.blink_led = e1000_blink_led_generic;
 
 		/* FWSM register */
 		mac->has_fwsm = TRUE;
@@ -420,8 +419,8 @@
 
 		if (!(swsm2 & E1000_SWSM2_LOCK)) {
 			/* Only do this for the first interface on this card */
-			E1000_WRITE_REG(hw, E1000_SWSM2,
-			    swsm2 | E1000_SWSM2_LOCK);
+			E1000_WRITE_REG(hw, E1000_SWSM2, swsm2 |
+					E1000_SWSM2_LOCK);
 			force_clear_smbi = TRUE;
 		} else
 			force_clear_smbi = FALSE;
@@ -746,8 +745,8 @@
 	if (!active) {
 		data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
 	} else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
-	           (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
-	           (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
+		   (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
+		   (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
 		data |= E1000_PHY_CTRL_NOND0A_LPLU;
 	}
 
@@ -816,7 +815,7 @@
  *  EEPROM will most likely contain an invalid checksum.
  **/
 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
-                                 u16 *data)
+				 u16 *data)
 {
 	s32 ret_val = E1000_SUCCESS;
 
@@ -941,7 +940,7 @@
  *  EEPROM will most likely contain an invalid checksum.
  **/
 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
-                                      u16 words, u16 *data)
+				      u16 words, u16 *data)
 {
 	struct e1000_nvm_info *nvm = &hw->nvm;
 	u32 i, eewr = 0;
@@ -1039,22 +1038,22 @@
 	if (active) {
 		data |= IGP02E1000_PM_D0_LPLU;
 		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
-		                             data);
+					     data);
 		if (ret_val)
 			goto out;
 
 		/* When LPLU is enabled, we should disable SmartSpeed */
 		ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-		                            &data);
+					    &data);
 		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 		ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-		                             data);
+					     data);
 		if (ret_val)
 			goto out;
 	} else {
 		data &= ~IGP02E1000_PM_D0_LPLU;
 		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
-		                             data);
+					     data);
 		/*
 		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 		 * during Dx states where the power conservation is most
@@ -1063,28 +1062,28 @@
 		 */
 		if (phy->smart_speed == e1000_smart_speed_on) {
 			ret_val = phy->ops.read_reg(hw,
-			                            IGP01E1000_PHY_PORT_CONFIG,
-			                            &data);
+						    IGP01E1000_PHY_PORT_CONFIG,
+						    &data);
 			if (ret_val)
 				goto out;
 
 			data |= IGP01E1000_PSCFR_SMART_SPEED;
 			ret_val = phy->ops.write_reg(hw,
-			                             IGP01E1000_PHY_PORT_CONFIG,
-			                             data);
+						     IGP01E1000_PHY_PORT_CONFIG,
+						     data);
 			if (ret_val)
 				goto out;
 		} else if (phy->smart_speed == e1000_smart_speed_off) {
 			ret_val = phy->ops.read_reg(hw,
-			                            IGP01E1000_PHY_PORT_CONFIG,
-			                            &data);
+						    IGP01E1000_PHY_PORT_CONFIG,
+						    &data);
 			if (ret_val)
 				goto out;
 
 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 			ret_val = phy->ops.write_reg(hw,
-			                             IGP01E1000_PHY_PORT_CONFIG,
-			                             data);
+						     IGP01E1000_PHY_PORT_CONFIG,
+						     data);
 			if (ret_val)
 				goto out;
 		}
@@ -1255,8 +1254,7 @@
 	/* Set the transmit descriptor write-back policy */
 	reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
 	reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
-	           E1000_TXDCTL_FULL_TX_DESC_WB |
-	           E1000_TXDCTL_COUNT_DESC;
+		   E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
 	E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
 
 	/* ...for both queues. */
@@ -1273,8 +1271,8 @@
 	default:
 		reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
 		reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
-		           E1000_TXDCTL_FULL_TX_DESC_WB |
-		           E1000_TXDCTL_COUNT_DESC;
+			   E1000_TXDCTL_FULL_TX_DESC_WB |
+			   E1000_TXDCTL_COUNT_DESC;
 		E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
 		break;
 	}
@@ -1320,6 +1318,10 @@
 	case e1000_82572:
 		reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
 		break;
+	case e1000_82574:
+	case e1000_82583:
+		reg |= (1 << 26);
+		break;
 	default:
 		break;
 	}
@@ -1527,12 +1529,12 @@
 	 * read the Base1000T status register If both are max then PHY is hung.
 	 */
 	ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,
-	                               &receive_errors);
+				       &receive_errors);
 	if (ret_val)
 		goto out;
 	if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
 		ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,
-		                               &status_1kbt);
+					       &status_1kbt);
 		if (ret_val)
 			goto out;
 		if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
@@ -1640,7 +1642,8 @@
 		 * mode.  This prevents drivers from twiddling their thumbs
 		 * if another tool failed to take it out of loopback mode.
 		 */
-		E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
+		E1000_WRITE_REG(hw, E1000_SCTL,
+				E1000_SCTL_DISABLE_SERDES_LOOPBACK);
 		break;
 	default:
 		break;
@@ -1664,7 +1667,7 @@
  *
  *  1) down
  *  2) autoneg_progress
- *  3) autoneg_complete (the link sucessfully autonegotiated)
+ *  3) autoneg_complete (the link successfully autonegotiated)
  *  4) forced_up (the link has been forced up, it did not autonegotiate)
  *
  **/
@@ -1763,7 +1766,7 @@
 					break;
 				}
 				mac->serdes_link_state =
-				e1000_serdes_link_forced_up;
+						e1000_serdes_link_forced_up;
 				mac->serdes_has_link = TRUE;
 				DEBUGOUT("AN_PROG   -> FORCED_UP\n");
 			}
@@ -1777,10 +1780,10 @@
 			 * up.
 			 */
 			E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
-			E1000_WRITE_REG(hw, E1000_CTRL,
-			    (ctrl & ~E1000_CTRL_SLU));
+			E1000_WRITE_REG(hw, E1000_CTRL, (ctrl &
+					~E1000_CTRL_SLU));
 			mac->serdes_link_state =
-			    e1000_serdes_link_autoneg_progress;
+					e1000_serdes_link_autoneg_progress;
 			mac->serdes_has_link = FALSE;
 			DEBUGOUT("DOWN      -> AN_PROG\n");
 			break;
@@ -1804,7 +1807,7 @@
 				      (rxcw & E1000_RXCW_C))) {
 					mac->serdes_has_link = FALSE;
 					mac->serdes_link_state =
-					    e1000_serdes_link_down;
+							e1000_serdes_link_down;
 					DEBUGOUT("ANYSTATE  -> DOWN\n");
 					break;
 				}
@@ -1815,7 +1818,7 @@
 				txcw |= E1000_TXCW_ANE;
 				E1000_WRITE_REG(hw, E1000_TXCW, txcw);
 				mac->serdes_link_state =
-				    e1000_serdes_link_autoneg_progress;
+					e1000_serdes_link_autoneg_progress;
 				mac->serdes_has_link = FALSE;
 				DEBUGOUT("ANYSTATE  -> AN_PROG\n");
 			}
@@ -1905,7 +1908,7 @@
 		 * Eventually the LAA will be in RAR[0] and RAR[14].
 		 */
 		e1000_rar_set_generic(hw, hw->mac.addr,
-		                      hw->mac.rar_entry_count - 1);
+				      hw->mac.rar_entry_count - 1);
 	return;
 }
 
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/e1000/e1000_82575.c
--- a/head/sys/dev/e1000/e1000_82575.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/e1000/e1000_82575.c	Thu Dec 15 12:59:38 2011 +0200
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD: head/sys/dev/e1000/e1000_82575.c 226436 2011-10-16 14:30:28Z eadler $*/
+/*$FreeBSD: head/sys/dev/e1000/e1000_82575.c 228386 2011-12-10 06:55:02Z jfv $*/
 
 /*
  * 82575EB Gigabit Network Connection
@@ -51,32 +51,34 @@
 static s32  e1000_check_for_link_82575(struct e1000_hw *hw);
 static s32  e1000_get_cfg_done_82575(struct e1000_hw *hw);
 static s32  e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
-                                         u16 *duplex);
+					 u16 *duplex);
 static s32  e1000_init_hw_82575(struct e1000_hw *hw);
 static s32  e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
 static s32  e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
-                                           u16 *data);
+					   u16 *data);
 static s32  e1000_reset_hw_82575(struct e1000_hw *hw);
 static s32  e1000_reset_hw_82580(struct e1000_hw *hw);
 static s32  e1000_read_phy_reg_82580(struct e1000_hw *hw,
-                                    u32 offset, u16 *data);
+				     u32 offset, u16 *data);
 static s32  e1000_write_phy_reg_82580(struct e1000_hw *hw,
-                                     u32 offset, u16 data);
+				      u32 offset, u16 data);
 static s32  e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
-                                          bool active);
+					  bool active);
 static s32  e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
-                                          bool active);
+					  bool active);
 static s32  e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
-                                          bool active);
+					  bool active);
 static s32  e1000_setup_copper_link_82575(struct e1000_hw *hw);
 static s32  e1000_setup_serdes_link_82575(struct e1000_hw *hw);
+static s32  e1000_get_media_type_82575(struct e1000_hw *hw);
+static s32  e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
 static s32  e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
 static s32  e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
-                                            u32 offset, u16 data);
+					    u32 offset, u16 data);
 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
 static s32  e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
 static s32  e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
-                                                 u16 *speed, u16 *duplex);
+						 u16 *speed, u16 *duplex);
 static s32  e1000_get_phy_id_82575(struct e1000_hw *hw);
 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
 static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
@@ -91,15 +93,28 @@
 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
 static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
-						u16 offset);
+						 u16 offset);
 static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
-						u16 offset);
+						   u16 offset);
 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
-
-static const u16 e1000_82580_rxpbs_table[] =
-	{ 36, 72, 144, 1, 2, 4, 8, 16,
-	  35, 70, 140 };
+static void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);
+static void e1000_clear_vfta_i350(struct e1000_hw *hw);
+
+static void e1000_i2c_start(struct e1000_hw *hw);
+static void e1000_i2c_stop(struct e1000_hw *hw);
+static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
+static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
+static s32 e1000_get_i2c_ack(struct e1000_hw *hw);
+static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
+static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
+static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
+static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
+static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
+static bool e1000_get_i2c_data(u32 *i2cctl);
+
+static const u16 e1000_82580_rxpbs_table[] = {
+	36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
 #define E1000_82580_RXPBS_TABLE_SIZE \
 	(sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
 
@@ -155,22 +170,22 @@
 	phy->ops.power_up   = e1000_power_up_phy_copper;
 	phy->ops.power_down = e1000_power_down_phy_copper_82575;
 
-	phy->autoneg_mask           = AUTONEG_ADVERTISE_SPEED_DEFAULT;
-	phy->reset_delay_us         = 100;
-
-	phy->ops.acquire            = e1000_acquire_phy_82575;
-	phy->ops.check_reset_block  = e1000_check_reset_block_generic;
-	phy->ops.commit             = e1000_phy_sw_reset_generic;
-	phy->ops.get_cfg_done       = e1000_get_cfg_done_82575;
-	phy->ops.release            = e1000_release_phy_82575;
+	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;
+	phy->reset_delay_us	= 100;
+
+	phy->ops.acquire	= e1000_acquire_phy_82575;
+	phy->ops.check_reset_block = e1000_check_reset_block_generic;
+	phy->ops.commit		= e1000_phy_sw_reset_generic;
+	phy->ops.get_cfg_done	= e1000_get_cfg_done_82575;
+	phy->ops.release	= e1000_release_phy_82575;
 
 	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 
 	if (e1000_sgmii_active_82575(hw)) {
-		phy->ops.reset      = e1000_phy_hw_reset_sgmii_82575;
+		phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
 		ctrl_ext |= E1000_CTRL_I2C_ENA;
 	} else {
-		phy->ops.reset      = e1000_phy_hw_reset_generic;
+		phy->ops.reset = e1000_phy_hw_reset_generic;
 		ctrl_ext &= ~E1000_CTRL_I2C_ENA;
 	}
 
@@ -178,14 +193,14 @@
 	e1000_reset_mdicnfg_82580(hw);
 
 	if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
-		phy->ops.read_reg   = e1000_read_phy_reg_sgmii_82575;
-		phy->ops.write_reg  = e1000_write_phy_reg_sgmii_82575;
+		phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
+		phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
 	} else if (hw->mac.type >= e1000_82580) {
-		phy->ops.read_reg   = e1000_read_phy_reg_82580;
-		phy->ops.write_reg  = e1000_write_phy_reg_82580;
+		phy->ops.read_reg = e1000_read_phy_reg_82580;
+		phy->ops.write_reg = e1000_write_phy_reg_82580;
 	} else {
-		phy->ops.read_reg   = e1000_read_phy_reg_igp;
-		phy->ops.write_reg  = e1000_write_phy_reg_igp;
+		phy->ops.read_reg = e1000_read_phy_reg_igp;
+		phy->ops.write_reg = e1000_write_phy_reg_igp;
 	}
 
 	/* Set phy->phy_addr and phy->id. */
@@ -197,36 +212,38 @@
 	case M88E1112_E_PHY_ID:
 	case M88E1340M_E_PHY_ID:
 	case M88E1111_I_PHY_ID:
-		phy->type                   = e1000_phy_m88;
-		phy->ops.check_polarity     = e1000_check_polarity_m88;
-		phy->ops.get_info           = e1000_get_phy_info_m88;
+		phy->type		= e1000_phy_m88;
+		phy->ops.check_polarity	= e1000_check_polarity_m88;
+		phy->ops.get_info	= e1000_get_phy_info_m88;
 		if (phy->id == I347AT4_E_PHY_ID ||
 		    phy->id == M88E1112_E_PHY_ID ||
 		    phy->id == M88E1340M_E_PHY_ID)
-			phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
+			phy->ops.get_cable_length =
+					 e1000_get_cable_length_m88_gen2;
 		else
 			phy->ops.get_cable_length = e1000_get_cable_length_m88;
 		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 		break;
 	case IGP03E1000_E_PHY_ID:
 	case IGP04E1000_E_PHY_ID:
-		phy->type                   = e1000_phy_igp_3;
-		phy->ops.check_polarity     = e1000_check_polarity_igp;
-		phy->ops.get_info           = e1000_get_phy_info_igp;
-		phy->ops.get_cable_length   = e1000_get_cable_length_igp_2;
+		phy->type = e1000_phy_igp_3;
+		phy->ops.check_polarity = e1000_check_polarity_igp;
+		phy->ops.get_info = e1000_get_phy_info_igp;
+		phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
 		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
-		phy->ops.set_d0_lplu_state  = e1000_set_d0_lplu_state_82575;
-		phy->ops.set_d3_lplu_state  = e1000_set_d3_lplu_state_generic;
+		phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
+		phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
 		break;
 	case I82580_I_PHY_ID:
 	case I350_I_PHY_ID:
-		phy->type                   = e1000_phy_82580;
-		phy->ops.check_polarity     = e1000_check_polarity_82577;
-		phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82577;
-		phy->ops.get_cable_length   = e1000_get_cable_length_82577;
-		phy->ops.get_info           = e1000_get_phy_info_82577;
-		phy->ops.set_d0_lplu_state  = e1000_set_d0_lplu_state_82580;
-		phy->ops.set_d3_lplu_state  = e1000_set_d3_lplu_state_82580;
+		phy->type = e1000_phy_82580;
+		phy->ops.check_polarity = e1000_check_polarity_82577;
+		phy->ops.force_speed_duplex =
+					 e1000_phy_force_speed_duplex_82577;
+		phy->ops.get_cable_length = e1000_get_cable_length_82577;
+		phy->ops.get_info = e1000_get_phy_info_82577;
+		phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
+		phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
 		break;
 	default:
 		ret_val = -E1000_ERR_PHY;
@@ -250,27 +267,33 @@
 	DEBUGFUNC("e1000_init_nvm_params_82575");
 
 	size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
-	             E1000_EECD_SIZE_EX_SHIFT);
+		     E1000_EECD_SIZE_EX_SHIFT);
 	/*
 	 * Added to a constant, "size" becomes the left-shift value
 	 * for setting word_size.
 	 */
 	size += NVM_WORD_SIZE_BASE_SHIFT;
 
+	/* Just in case size is out of range, cap it to the largest
+	 * EEPROM size supported
+	 */
+	if (size > 15)
+		size = 15;
+
 	nvm->word_size = 1 << size;
-	nvm->opcode_bits        = 8;
-	nvm->delay_usec         = 1;
+	nvm->opcode_bits = 8;
+	nvm->delay_usec = 1;
 	switch (nvm->override) {
 	case e1000_nvm_override_spi_large:
-		nvm->page_size    = 32;
+		nvm->page_size = 32;
 		nvm->address_bits = 16;
 		break;
 	case e1000_nvm_override_spi_small:
-		nvm->page_size    = 8;
+		nvm->page_size = 8;
 		nvm->address_bits = 8;
 		break;
 	default:
-		nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
+		nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 		break;
 	}
@@ -281,17 +304,17 @@
 		nvm->page_size = 128;
 
 	/* Function Pointers */
-	nvm->ops.acquire    = e1000_acquire_nvm_82575;
-	nvm->ops.release    = e1000_release_nvm_82575;
+	nvm->ops.acquire = e1000_acquire_nvm_82575;
+	nvm->ops.release = e1000_release_nvm_82575;
 	if (nvm->word_size < (1 << 15))
-		nvm->ops.read    = e1000_read_nvm_eerd;
+		nvm->ops.read = e1000_read_nvm_eerd;
 	else
-		nvm->ops.read    = e1000_read_nvm_spi;
-
-	nvm->ops.write              = e1000_write_nvm_spi;
-	nvm->ops.validate           = e1000_validate_nvm_checksum_generic;
-	nvm->ops.update             = e1000_update_nvm_checksum_generic;
-	nvm->ops.valid_led_default  = e1000_valid_led_default_82575;
+		nvm->ops.read = e1000_read_nvm_spi;
+
+	nvm->ops.write = e1000_write_nvm_spi;
+	nvm->ops.validate = e1000_validate_nvm_checksum_generic;
+	nvm->ops.update = e1000_update_nvm_checksum_generic;
+	nvm->ops.valid_led_default = e1000_valid_led_default_82575;
 
 	/* override genric family function pointers for specific descendants */
 	switch (hw->mac.type) {
@@ -318,34 +341,11 @@
 {
 	struct e1000_mac_info *mac = &hw->mac;
 	struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
-	u32 ctrl_ext = 0;
 
 	DEBUGFUNC("e1000_init_mac_params_82575");
 
-	/* Set media type */
-        /*
-	 * The 82575 uses bits 22:23 for link mode. The mode can be changed
-         * based on the EEPROM. We cannot rely upon device ID. There
-         * is no distinguishable difference between fiber and internal
-         * SerDes mode on the 82575. There can be an external PHY attached
-         * on the SGMII interface. For this, we'll set sgmii_active to TRUE.
-         */
-	hw->phy.media_type = e1000_media_type_copper;
-	dev_spec->sgmii_active = FALSE;
-
-	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
-	switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
-	case E1000_CTRL_EXT_LINK_MODE_SGMII:
-		dev_spec->sgmii_active = TRUE;
-		break;
-	case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
-	case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
-		hw->phy.media_type = e1000_media_type_internal_serdes;
-		break;
-	default:
-		break;
-	}
-
+	/* Derives media type */
+	e1000_get_media_type_82575(hw);
 	/* Set mta register count */
 	mac->mta_reg_count = 128;
 	/* Set uta register count */
@@ -368,8 +368,8 @@
 	mac->has_fwsm = TRUE;
 	/* ARC supported; valid only if manageability features are enabled. */
 	mac->arc_subsystem_valid =
-	        (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
-	                ? TRUE : FALSE;
+		(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
+			? TRUE : FALSE;
 
 	/* Function pointers */
 
@@ -386,9 +386,8 @@
 	mac->ops.setup_link = e1000_setup_link_generic;
 	/* physical interface link setup */
 	mac->ops.setup_physical_interface =
-	        (hw->phy.media_type == e1000_media_type_copper)
-	                ? e1000_setup_copper_link_82575
-	                : e1000_setup_serdes_link_82575;
+		(hw->phy.media_type == e1000_media_type_copper)
+		? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
 	/* physical interface shutdown */
 	mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
 	/* physical interface power up */
@@ -403,10 +402,17 @@
 	mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
 	/* multicast address update */
 	mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
-	/* writing VFTA */
-	mac->ops.write_vfta = e1000_write_vfta_generic;
-	/* clearing VFTA */
-	mac->ops.clear_vfta = e1000_clear_vfta_generic;
+	if (hw->mac.type == e1000_i350) {
+		/* writing VFTA */
+		mac->ops.write_vfta = e1000_write_vfta_i350;
+		/* clearing VFTA */
+		mac->ops.clear_vfta = e1000_clear_vfta_i350;
+	} else {
+		/* writing VFTA */
+		mac->ops.write_vfta = e1000_write_vfta_generic;
+		/* clearing VFTA */
+		mac->ops.clear_vfta = e1000_clear_vfta_generic;
+	}
 	/* ID LED init */
 	mac->ops.id_led_init = e1000_id_led_init_generic;
 	/* blink LED */
@@ -499,7 +505,7 @@
  *  interface and stores the retrieved information in data.
  **/
 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
-                                          u16 *data)
+					  u16 *data)
 {
 	s32 ret_val = -E1000_ERR_PARAM;
 
@@ -532,7 +538,7 @@
  *  media independent interface.
  **/
 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
-                                           u16 data)
+					   u16 data)
 {
 	s32 ret_val = -E1000_ERR_PARAM;
 
@@ -611,7 +617,7 @@
 	/* Power on sgmii phy if it is disabled */
 	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 	E1000_WRITE_REG(hw, E1000_CTRL_EXT,
-	                ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
+			ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
 	E1000_WRITE_FLUSH(hw);
 	msec_delay(300);
 
@@ -623,8 +629,7 @@
 		ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
 		if (ret_val == E1000_SUCCESS) {
 			DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
-			          phy_id,
-			          phy->addr);
+				  phy_id, phy->addr);
 			/*
 			 * At the time of this writing, The M88 part is
 			 * the only supported SGMII PHY product.
@@ -633,7 +638,7 @@
 				break;
 		} else {
 			DEBUGOUT1("PHY address %u was unreadable\n",
-			          phy->addr);
+				  phy->addr);
 		}
 	}
 
@@ -719,22 +724,22 @@
 	if (active) {
 		data |= IGP02E1000_PM_D0_LPLU;
 		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
-		                             data);
+					     data);
 		if (ret_val)
 			goto out;
 
 		/* When LPLU is enabled, we should disable SmartSpeed */
 		ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-		                            &data);
+					    &data);
 		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 		ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-		                             data);
+					     data);
 		if (ret_val)
 			goto out;
 	} else {
 		data &= ~IGP02E1000_PM_D0_LPLU;
 		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
-		                             data);
+					     data);
 		/*
 		 * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 		 * during Dx states where the power conservation is most
@@ -743,28 +748,28 @@
 		 */
 		if (phy->smart_speed == e1000_smart_speed_on) {
 			ret_val = phy->ops.read_reg(hw,
-			                            IGP01E1000_PHY_PORT_CONFIG,
-			                            &data);
+						    IGP01E1000_PHY_PORT_CONFIG,
+						    &data);
 			if (ret_val)
 				goto out;
 
 			data |= IGP01E1000_PSCFR_SMART_SPEED;
 			ret_val = phy->ops.write_reg(hw,
-			                             IGP01E1000_PHY_PORT_CONFIG,
-			                             data);
+						     IGP01E1000_PHY_PORT_CONFIG,
+						     data);
 			if (ret_val)
 				goto out;
 		} else if (phy->smart_speed == e1000_smart_speed_off) {
 			ret_val = phy->ops.read_reg(hw,
-			                            IGP01E1000_PHY_PORT_CONFIG,
-			                            &data);
+						    IGP01E1000_PHY_PORT_CONFIG,
+						    &data);
 			if (ret_val)
 				goto out;
 
 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 			ret_val = phy->ops.write_reg(hw,
-			                             IGP01E1000_PHY_PORT_CONFIG,
-			                             data);
+						     IGP01E1000_PHY_PORT_CONFIG,
+						     data);
 			if (ret_val)
 				goto out;
 		}
@@ -811,11 +816,10 @@
 		 * important.  During driver activity we should enable
 		 * SmartSpeed, so performance is maintained.
 		 */
-		if (phy->smart_speed == e1000_smart_speed_on) {
+		if (phy->smart_speed == e1000_smart_speed_on)
 			data |= E1000_82580_PM_SPD;
-		} else if (phy->smart_speed == e1000_smart_speed_off) {
+		else if (phy->smart_speed == e1000_smart_speed_off)
 			data &= ~E1000_82580_PM_SPD;
-		}
 	}
 
 	E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
@@ -854,14 +858,13 @@
 		 * important.  During driver activity we should enable
 		 * SmartSpeed, so performance is maintained.
 		 */
-		if (phy->smart_speed == e1000_smart_speed_on) {
+		if (phy->smart_speed == e1000_smart_speed_on)
 			data |= E1000_82580_PM_SPD;
-		} else if (phy->smart_speed == e1000_smart_speed_off) {
+		else if (phy->smart_speed == e1000_smart_speed_off)
 			data &= ~E1000_82580_PM_SPD;
-		}
 	} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
-	           (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
-	           (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
+		   (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
+		   (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 		data |= E1000_82580_PM_D3_LPLU;
 		/* When LPLU is enabled, we should disable SmartSpeed */
 		data &= ~E1000_82580_PM_SPD;
@@ -889,7 +892,37 @@
 	ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 	if (ret_val)
 		goto out;
-	ret_val = e1000_acquire_nvm_generic(hw);
+
+	/*
+	 * Check if there is some access
+	 * error this access may hook on
+	 */
+	if (hw->mac.type == e1000_i350) {
+		u32 eecd = E1000_READ_REG(hw, E1000_EECD);
+		if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
+		    E1000_EECD_TIMEOUT)) {
+			/* Clear all access error flags */
+			E1000_WRITE_REG(hw, E1000_EECD, eecd |
+					E1000_EECD_ERROR_CLR);
+			DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
+		}
+	}
+	if (hw->mac.type == e1000_82580) {
+		u32 eecd = E1000_READ_REG(hw, E1000_EECD);
+		if (eecd & E1000_EECD_BLOCKED) {
+			/* Clear access error flag */
+			E1000_WRITE_REG(hw, E1000_EECD, eecd |
+					E1000_EECD_BLOCKED);
+			DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
+		}
+	}
+
+
+	switch (hw->mac.type) {
+	default:
+		ret_val = e1000_acquire_nvm_generic(hw);
+	}
+
 	if (ret_val)
 		e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 
@@ -908,6 +941,10 @@
 {
 	DEBUGFUNC("e1000_release_nvm_82575");
 
+	switch (hw->mac.type) {
+	default:
+		e1000_release_nvm_generic(hw);
+	}
 	e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
 }
 
@@ -977,8 +1014,8 @@
 
 	DEBUGFUNC("e1000_release_swfw_sync_82575");
 
-	while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS);
-	/* Empty */
+	while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
+		; /* Empty */
 
 	swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
 	swfw_sync &= ~mask;
@@ -1039,7 +1076,7 @@
  *  Otherwise, use the generic function to get the link speed and duplex info.
  **/
 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
-                                        u16 *duplex)
+					u16 *duplex)
 {
 	s32 ret_val;
 
@@ -1047,10 +1084,10 @@
 
 	if (hw->phy.media_type != e1000_media_type_copper)
 		ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
-		                                               duplex);
+							       duplex);
 	else
 		ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
-		                                                    duplex);
+								    duplex);
 
 	return ret_val;
 }
@@ -1071,7 +1108,7 @@
 
 	if (hw->phy.media_type != e1000_media_type_copper) {
 		ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
-		                                               &duplex);
+							       &duplex);
 		/*
 		 * Use this flag to determine if link needs to be checked or
 		 * not.  If we have link clear the flag so that we do not
@@ -1124,7 +1161,7 @@
  *  duplex, then store the values in the pointers provided.
  **/
 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
-                                                u16 *speed, u16 *duplex)
+						u16 *speed, u16 *duplex)
 {
 	struct e1000_mac_info *mac = &hw->mac;
 	u32 pcs;
@@ -1152,20 +1189,18 @@
 		mac->serdes_has_link = TRUE;
 
 		/* Detect and store PCS speed */
-		if (pcs & E1000_PCS_LSTS_SPEED_1000) {
+		if (pcs & E1000_PCS_LSTS_SPEED_1000)
 			*speed = SPEED_1000;
-		} else if (pcs & E1000_PCS_LSTS_SPEED_100) {
+		else if (pcs & E1000_PCS_LSTS_SPEED_100)
 			*speed = SPEED_100;
-		} else {
+		else
 			*speed = SPEED_10;
-		}
 
 		/* Detect and store PCS duplex */
-		if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
+		if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
 			*duplex = FULL_DUPLEX;
-		} else {
+		else
 			*duplex = HALF_DUPLEX;
-		}
 	}
 
 	return E1000_SUCCESS;
@@ -1225,15 +1260,13 @@
 	 * on the last TLP read/write transaction when MAC is reset.
 	 */
 	ret_val = e1000_disable_pcie_master_generic(hw);
-	if (ret_val) {
+	if (ret_val)
 		DEBUGOUT("PCI-E Master disable polling has failed.\n");
-	}
 
 	/* set the completion timeout for interface */
 	ret_val = e1000_set_pcie_completion_timeout(hw);
-	if (ret_val) {
+	if (ret_val)
 		DEBUGOUT("PCI-E Set completion timeout has failed.\n");
-	}
 
 	DEBUGOUT("Masking off all interrupts\n");
 	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
@@ -1314,6 +1347,9 @@
 	/* Setup link and flow control */
 	ret_val = mac->ops.setup_link(hw);
 
+	/* Set the default MTU size */
+	hw->dev_spec._82575.mtu = 1500;
+
 	/*
 	 * Clear all of the statistics registers (clear on read).  It is
 	 * important that we do this after we have tried to establish link
@@ -1349,7 +1385,7 @@
 	if (ret_val)
 		goto out;
 
-	if (e1000_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
+	if (e1000_sgmii_active_82575(hw)) {
 		/* allow time for SFP cage time to power up phy */
 		msec_delay(300);
 
@@ -1400,12 +1436,14 @@
 {
 	u32 ctrl_ext, ctrl_reg, reg;
 	bool pcs_autoneg;
+	s32 ret_val = E1000_SUCCESS;
+	u16 data;
 
 	DEBUGFUNC("e1000_setup_serdes_link_82575");
 
 	if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
 	    !e1000_sgmii_active_82575(hw))
-		return E1000_SUCCESS;
+		return ret_val;
 
 	/*
 	 * On the 82575, SerDes loopback mode persists until it is
@@ -1444,13 +1482,25 @@
 		pcs_autoneg = FALSE;
 		/* fall through to default case */
 	default:
+		if (hw->mac.type == e1000_82575 ||
+		    hw->mac.type == e1000_82576) {
+			ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
+			if (ret_val) {
+				DEBUGOUT("NVM Read Error\n");
+				return ret_val;
+			}
+
+			if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
+				pcs_autoneg = FALSE;
+		}
+
 		/*
 		 * non-SGMII modes only supports a speed of 1000/Full for the
 		 * link so it is best to just force the MAC and let the pcs
 		 * link either autoneg or be forced to 1000/Full
 		 */
 		ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
-		            E1000_CTRL_FD | E1000_CTRL_FRCDPX;
+			    E1000_CTRL_FD | E1000_CTRL_FRCDPX;
 
 		/* set speed of 1000/Full if speed/duplex is forced */
 		reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
@@ -1466,7 +1516,7 @@
 	 * However, both are supported by the hardware and some drivers/tools.
 	 */
 	reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
-	         E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
+		 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
 
 	/*
 	 * We force flow control to prevent the CTRL register values from being
@@ -1481,7 +1531,7 @@
 		DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
 	} else {
 		/* Set PCS register for forced link */
-		reg |= E1000_PCS_LCTL_FSD;        /* Force Speed */
+		reg |= E1000_PCS_LCTL_FSD;	/* Force Speed */
 		DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
 	}
 
@@ -1490,7 +1540,216 @@
 	if (!e1000_sgmii_active_82575(hw))
 		e1000_force_mac_fc_generic(hw);
 
-	return E1000_SUCCESS;
+	return ret_val;
+}
+
+/**
+ *  e1000_get_media_type_82575 - derives current media type.
+ *  @hw: pointer to the HW structure
+ *
+ *  The media type is chosen reflecting few settings.
+ *  The following are taken into account:
+ *  - link mode set in the current port Init Control Word #3
+ *  - current link mode settings in CSR register
+ *  - MDIO vs. I2C PHY control interface chosen
+ *  - SFP module media type
+ **/
+static s32 e1000_get_media_type_82575(struct e1000_hw *hw)
+{
+	u32 lan_id = 0;
+	s32 ret_val = E1000_ERR_CONFIG;
+	struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
+	u32 ctrl_ext = 0;
+	u32 current_link_mode = 0;
+	u16 init_ctrl_wd_3 = 0;
+	u8 init_ctrl_wd_3_offset = 0;
+	u8 init_ctrl_wd_3_bit_offset = 0;
+
+	/* Set internal phy as default */
+	dev_spec->sgmii_active = FALSE;
+	dev_spec->module_plugged = FALSE;
+
+	/*
+	 * Check if NVM access method is attached already.
+	 * If it is then Init Control Word #3 is considered
+	 * otherwise runtime CSR register content is taken.
+	 */
+
+	/* Get CSR setting */
+	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
+
+	/* Get link mode setting */
+	if ((hw->nvm.ops.read) && (hw->nvm.ops.read != e1000_null_read_nvm)) {
+		/* Take link mode from EEPROM */
+
+		/*
+		 * Get LAN port ID to derive its
+		 * adequate Init Control Word #3
+		 */
+		lan_id = ((E1000_READ_REG(hw, E1000_STATUS) &
+		      E1000_STATUS_LAN_ID_MASK) >> E1000_STATUS_LAN_ID_OFFSET);
+		/*
+		 * Derive Init Control Word #3 offset
+		 * and mask to pick up link mode setting.
+		 */
+		if (hw->mac.type < e1000_82580) {
+			init_ctrl_wd_3_offset = lan_id ?
+			   NVM_INIT_CONTROL3_PORT_A : NVM_INIT_CONTROL3_PORT_B;
+			init_ctrl_wd_3_bit_offset = NVM_WORD24_LNK_MODE_OFFSET;
+		} else {
+			init_ctrl_wd_3_offset =
+					    NVM_82580_LAN_FUNC_OFFSET(lan_id) +
+					    NVM_INIT_CONTROL3_PORT_A;
+			init_ctrl_wd_3_bit_offset =
+					      NVM_WORD24_82580_LNK_MODE_OFFSET;
+		}
+		/* Read Init Control Word #3*/
+		hw->nvm.ops.read(hw, init_ctrl_wd_3_offset, 1, &init_ctrl_wd_3);
+		current_link_mode = init_ctrl_wd_3;
+		/*
+		 * Switch to CSR for all but internal PHY.
+		 */
+		if ((init_ctrl_wd_3 << (E1000_CTRL_EXT_LINK_MODE_OFFSET -
+		    init_ctrl_wd_3_bit_offset)) !=
+		    E1000_CTRL_EXT_LINK_MODE_GMII) {
+			current_link_mode = ctrl_ext;
+			init_ctrl_wd_3_bit_offset =
+					      E1000_CTRL_EXT_LINK_MODE_OFFSET;
+		}
+	} else {
+		/* Take link mode from CSR */
+		current_link_mode = ctrl_ext;
+		init_ctrl_wd_3_bit_offset = E1000_CTRL_EXT_LINK_MODE_OFFSET;
+	}
+
+	/*
+	 * Align link mode bits to
+	 * their CTRL_EXT location.
+	 */
+	current_link_mode <<= (E1000_CTRL_EXT_LINK_MODE_OFFSET -
+			       init_ctrl_wd_3_bit_offset);
+	current_link_mode &= E1000_CTRL_EXT_LINK_MODE_MASK;
+
+	switch (current_link_mode) {
+
+	case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
+		hw->phy.media_type = e1000_media_type_internal_serdes;
+		current_link_mode = E1000_CTRL_EXT_LINK_MODE_1000BASE_KX;
+		break;
+	case E1000_CTRL_EXT_LINK_MODE_GMII:
+		hw->phy.media_type = e1000_media_type_copper;
+		current_link_mode = E1000_CTRL_EXT_LINK_MODE_GMII;
+		break;
+	case E1000_CTRL_EXT_LINK_MODE_SGMII:
+	case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
+		/* Get phy control interface type set (MDIO vs. I2C)*/
+		if (e1000_sgmii_uses_mdio_82575(hw)) {
+			hw->phy.media_type = e1000_media_type_copper;
+			dev_spec->sgmii_active = TRUE;
+			current_link_mode = E1000_CTRL_EXT_LINK_MODE_SGMII;
+		} else {
+			ret_val = e1000_set_sfp_media_type_82575(hw);
+			if (ret_val != E1000_SUCCESS)
+				goto out;
+			if (hw->phy.media_type ==
+				e1000_media_type_internal_serdes) {
+				current_link_mode =
+					 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
+			} else if (hw->phy.media_type ==
+				e1000_media_type_copper) {
+				current_link_mode =
+					       E1000_CTRL_EXT_LINK_MODE_SGMII;
+			}
+		}
+		break;
+	default:
+		DEBUGOUT("Link mode mask doesn't fit bit field size\n");
+		goto out;
+	}
+	/*
+	 * Do not change current link mode setting
+	 * if media type is fibre or has not been
+	 * recognized.
+	 */
+	if ((hw->phy.media_type != e1000_media_type_unknown) &&
+	    (hw->phy.media_type != e1000_media_type_fiber)) {
+		/* Update link mode */
+		ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
+		E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext |
+				current_link_mode);
+	}
+
+	ret_val = E1000_SUCCESS;
+out:
+	/*
+	 * If media type was not identified then return media type
+	 * defined by the CTRL_EXT settings.
+	 */
+	if (hw->phy.media_type == e1000_media_type_unknown) {
+		if (current_link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII)
+			hw->phy.media_type = e1000_media_type_copper;
+		else
+			hw->phy.media_type = e1000_media_type_internal_serdes;
+	}
+
+	return ret_val;
+}
+
+/**
+ *  e1000_set_sfp_media_type_82575 - derives SFP module media type.
+ *  @hw: pointer to the HW structure
+ *
+ *  The media type is chosen based on SFP module.
+ *  compatibility flags retrieved from SFP ID EEPROM.
+ **/
+static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
+{
+	s32 ret_val = E1000_ERR_CONFIG;
+	u32 ctrl_ext = 0;
+	struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
+	struct sfp_e1000_flags eth_flags = {0};
+	u8 tranceiver_type = 0;
+
+	/* Turn I2C interface ON */
+	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
+	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
+
+	/* Read SFP module data */
+	ret_val = e1000_read_sfp_data_byte(hw,
+			E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
+			&tranceiver_type);
+	if (ret_val != E1000_SUCCESS)
+		goto out;
+	ret_val = e1000_read_sfp_data_byte(hw,
+			E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
+			(u8 *)&eth_flags);
+	if (ret_val != E1000_SUCCESS)
+		goto out;
+	/*
+	 * Check if there is some SFP
+	 * module plugged and powered
+	 */
+	if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
+	    (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
+		dev_spec->module_plugged = TRUE;
+		if (eth_flags.e1000_base_lx || eth_flags.e1000_base_sx) {
+			hw->phy.media_type = e1000_media_type_internal_serdes;
+		} else if (eth_flags.e1000_base_t) {
+			dev_spec->sgmii_active = TRUE;
+			hw->phy.media_type = e1000_media_type_copper;
+		} else {
+				hw->phy.media_type = e1000_media_type_unknown;
+				DEBUGOUT("PHY module has not been recognized\n");
+				goto out;
+		}
+	} else {
+		hw->phy.media_type = e1000_media_type_unknown;
+	}
+	ret_val = E1000_SUCCESS;
+out:
+	/* Restore I2C interface setting */
+	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
+	return ret_val;
 }
 
 /**
@@ -1514,7 +1773,7 @@
 	}
 
 	if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
-		switch(hw->phy.media_type) {
+		switch (hw->phy.media_type) {
 		case e1000_media_type_internal_serdes:
 			*data = ID_LED_DEFAULT_82575_SERDES;
 			break;
@@ -1549,7 +1808,7 @@
  *  Inits recommended HW defaults after a reset when there is no EEPROM
  *  detected. This is only for the 82575.
  **/
-static s32 e1000_reset_init_script_82575(struct e1000_hw* hw)
+static s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
 {
 	DEBUGFUNC("e1000_reset_init_script_82575");
 
@@ -1736,7 +1995,7 @@
 	for (i = 0; i < 4; i++) {
 		rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
 		E1000_WRITE_REG(hw, E1000_RXDCTL(i),
-		                rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
+				rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
 	}
 	/* Poll all queues to verify they have shut down */
 	for (ms_wait = 0; ms_wait < 10; ms_wait++) {
@@ -1822,14 +2081,14 @@
 	 * 16ms to 55ms
 	 */
 	ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
-	                                  &pcie_devctl2);
+					  &pcie_devctl2);
 	if (ret_val)
 		goto out;
 
 	pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
 
 	ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
-	                                   &pcie_devctl2);
+					   &pcie_devctl2);
 out:
 	/* disable completion timeout resend */
 	gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
@@ -1852,20 +2111,35 @@
 
 	switch (hw->mac.type) {
 	case e1000_82576:
-	case e1000_i350:
 		dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
 		if (enable) {
 			dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
 				   E1000_DTXSWC_VLAN_SPOOF_MASK);
 			/* The PF can spoof - it has to in order to
 			 * support emulation mode NICs */
-			dtxswc ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
+			dtxswc ^= (1 << pf | 1 << (pf +
+				   E1000_DTXSWC_VLAN_SPOOF_SHIFT));
 		} else {
 			dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
 				    E1000_DTXSWC_VLAN_SPOOF_MASK);
 		}
 		E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
 		break;
+	case e1000_i350:
+		dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
+		if (enable) {
+			dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
+				   E1000_DTXSWC_VLAN_SPOOF_MASK);
+			/* The PF can spoof - it has to in order to
+			 * support emulation mode NICs
+			 */
+			dtxswc ^= (1 << pf | 1 << (pf +
+				   E1000_DTXSWC_VLAN_SPOOF_SHIFT));
+		} else {
+			dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
+				    E1000_DTXSWC_VLAN_SPOOF_MASK);
+		}
+		E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
 	default:
 		break;
 	}
@@ -1983,7 +2257,7 @@
  *  e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
  *  @hw: pointer to the HW structure
  *
- *  This resets the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
+ *  This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
  *  the values found in the EEPROM.  This addresses an issue in which these
  *  bits are not restored from EEPROM after reset.
  **/
@@ -2001,8 +2275,8 @@
 		goto out;
 
 	ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
-	                           NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
-	                           &nvm_data);
+				   NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
+				   &nvm_data);
 	if (ret_val) {
 		DEBUGOUT("NVM Read Error\n");
 		goto out;
@@ -2057,17 +2331,18 @@
 	msec_delay(10);
 
 	/* Determine whether or not a global dev reset is requested */
-	if (global_device_reset &&
-		e1000_acquire_swfw_sync_82575(hw, swmbsw_mask))
+	if (global_device_reset && e1000_acquire_swfw_sync_82575(hw,
+	    swmbsw_mask))
 			global_device_reset = FALSE;
 
-	if (global_device_reset &&
-		!(E1000_READ_REG(hw, E1000_STATUS) & E1000_STAT_DEV_RST_SET))
+	if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
+	    E1000_STAT_DEV_RST_SET))
 		ctrl |= E1000_CTRL_DEV_RST;
 	else
 		ctrl |= E1000_CTRL_RST;
 
 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
+	E1000_WRITE_FLUSH(hw);
 
 	/* Add delay to insure DEV_RST has time to complete */
 	if (global_device_reset)
@@ -2192,7 +2467,7 @@
 	}
 	checksum = (u16) NVM_SUM - checksum;
 	ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
-				&checksum);
+				    &checksum);
 	if (ret_val)
 		DEBUGOUT("NVM Write Error while updating checksum.\n");
 
@@ -2232,7 +2507,7 @@
 	for (j = 0; j < eeprom_regions_count; j++) {
 		nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
 		ret_val = e1000_validate_nvm_checksum_with_offset(hw,
-								nvm_offset);
+								  nvm_offset);
 		if (ret_val != E1000_SUCCESS)
 			goto out;
 	}
@@ -2259,8 +2534,7 @@
 
 	ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
 	if (ret_val) {
-		DEBUGOUT("NVM Read Error while updating checksum"
-			" compatibility bit.\n");
+		DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
 		goto out;
 	}
 
@@ -2268,10 +2542,9 @@
 		/* set compatibility bit to validate checksums appropriately */
 		nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
 		ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
-					&nvm_data);
+					    &nvm_data);
 		if (ret_val) {
-			DEBUGOUT("NVM Write Error while updating checksum"
-				" compatibility bit.\n");
+			DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
 			goto out;
 		}
 	}
@@ -2279,9 +2552,8 @@
 	for (j = 0; j < 4; j++) {
 		nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
 		ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
-		if (ret_val) {
+		if (ret_val)
 			goto out;
-		}
 	}
 
 out:
@@ -2307,7 +2579,7 @@
 	for (j = 0; j < 4; j++) {
 		nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
 		ret_val = e1000_validate_nvm_checksum_with_offset(hw,
-								nvm_offset);
+								  nvm_offset);
 		if (ret_val != E1000_SUCCESS)
 			goto out;
 	}
@@ -2353,37 +2625,628 @@
 s32 e1000_set_eee_i350(struct e1000_hw *hw)
 {
 	s32 ret_val = E1000_SUCCESS;
-	u32 ipcnfg, eeer, ctrl_ext;
+	u32 ipcnfg, eeer;
 
 	DEBUGFUNC("e1000_set_eee_i350");
 
-	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
-	if ((hw->mac.type != e1000_i350) ||
-	    (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK))
+	if ((hw->mac.type < e1000_i350) ||
+	    (hw->phy.media_type != e1000_media_type_copper))
 		goto out;
 	ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
 	eeer = E1000_READ_REG(hw, E1000_EEER);
 
 	/* enable or disable per user setting */
 	if (!(hw->dev_spec._82575.eee_disable)) {
-		ipcnfg |= (E1000_IPCNFG_EEE_1G_AN |
-		           E1000_IPCNFG_EEE_100M_AN);
-		eeer |= (E1000_EEER_TX_LPI_EN |
-		         E1000_EEER_RX_LPI_EN |
-		         E1000_EEER_LPI_FC);
+		ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
+		eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
+			 E1000_EEER_LPI_FC);
 
 	} else {
-		ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
-		            E1000_IPCNFG_EEE_100M_AN);
-		eeer &= ~(E1000_EEER_TX_LPI_EN |
-		          E1000_EEER_RX_LPI_EN |
-		          E1000_EEER_LPI_FC);
+		ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
+		eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
+			  E1000_EEER_LPI_FC);
 	}
 	E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
 	E1000_WRITE_REG(hw, E1000_EEER, eeer);
-			E1000_READ_REG(hw, E1000_IPCNFG);
-			E1000_READ_REG(hw, E1000_EEER);
+	E1000_READ_REG(hw, E1000_IPCNFG);
+	E1000_READ_REG(hw, E1000_EEER);
 out:
 
 	return ret_val;
 }
+
+/* Due to a hw errata, if the host tries to  configure the VFTA register
+ * while performing queries from the BMC or DMA, then the VFTA in some
+ * cases won't be written.
+ */
+
+/**
+ *  e1000_clear_vfta_i350 - Clear VLAN filter table
+ *  @hw: pointer to the HW structure
+ *
+ *  Clears the register array which contains the VLAN filter table by
+ *  setting all the values to 0.
+ **/
+void e1000_clear_vfta_i350(struct e1000_hw *hw)
+{
+	u32 offset;
+	int i;
+
+	DEBUGFUNC("e1000_clear_vfta_350");
+
+	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
+		for (i = 0; i < 10; i++)
+			E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
+
+		E1000_WRITE_FLUSH(hw);
+	}
+}
+
+/**
+ *  e1000_write_vfta_i350 - Write value to VLAN filter table
+ *  @hw: pointer to the HW structure
+ *  @offset: register offset in VLAN filter table
+ *  @value: register value written to VLAN filter table
+ *
+ *  Writes value at the given offset in the register array which stores
+ *  the VLAN filter table.
+ **/
+void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
+{
+	int i;
+
+	DEBUGFUNC("e1000_write_vfta_350");
+
+	for (i = 0; i < 10; i++)
+		E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
+
+	E1000_WRITE_FLUSH(hw);
+}
+
+
+/**
+ *  e1000_set_i2c_bb - Enable I2C bit-bang
+ *  @hw: pointer to the HW structure
+ *
+ *  Enable I2C bit-bang interface
+ *
+ **/
+s32 e1000_set_i2c_bb(struct e1000_hw *hw)
+{
+	s32 ret_val = E1000_SUCCESS;
+	u32 ctrl_ext, i2cparams;
+
+	DEBUGFUNC("e1000_set_i2c_bb");
+
+	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
+	ctrl_ext |= E1000_CTRL_I2C_ENA;
+	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
+	E1000_WRITE_FLUSH(hw);
+
+	i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
+	i2cparams |= E1000_I2CBB_EN;
+	i2cparams |= E1000_I2C_DATA_OE_N;
+	i2cparams |= E1000_I2C_CLK_OE_N;
+	E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
+	E1000_WRITE_FLUSH(hw);
+
+	return ret_val;
+}
+
+/**
+ *  e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
+ *  @hw: pointer to hardware structure
+ *  @byte_offset: byte offset to read
+ *  @data: value read
+ *
+ *  Performs byte read operation over I2C interface at
+ *  a specified device address.
+ **/
+s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
+				u8 dev_addr, u8 *data)
+{
+	s32 status = E1000_SUCCESS;
+	u32 max_retry = 10;
+	u32 retry = 1;
+	u16 swfw_mask = 0;
+
+	bool nack = 1;
+
+	DEBUGFUNC("e1000_read_i2c_byte_generic");
+
+	swfw_mask = E1000_SWFW_PHY0_SM;
+
+	do {
+		if (e1000_acquire_swfw_sync_82575(hw, swfw_mask)
+		    != E1000_SUCCESS) {
+			status = E1000_ERR_SWFW_SYNC;
+			goto read_byte_out;
+		}
+
+		e1000_i2c_start(hw);
+
+		/* Device Address and write indication */
+		status = e1000_clock_out_i2c_byte(hw, dev_addr);
+		if (status != E1000_SUCCESS)
+			goto fail;
+
+		status = e1000_get_i2c_ack(hw);
+		if (status != E1000_SUCCESS)
+			goto fail;
+
+		status = e1000_clock_out_i2c_byte(hw, byte_offset);
+		if (status != E1000_SUCCESS)
+			goto fail;
+
+		status = e1000_get_i2c_ack(hw);
+		if (status != E1000_SUCCESS)
+			goto fail;
+
+		e1000_i2c_start(hw);
+
+		/* Device Address and read indication */
+		status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
+		if (status != E1000_SUCCESS)
+			goto fail;
+
+		status = e1000_get_i2c_ack(hw);
+		if (status != E1000_SUCCESS)
+			goto fail;
+
+		status = e1000_clock_in_i2c_byte(hw, data);
+		if (status != E1000_SUCCESS)
+			goto fail;
+
+		status = e1000_clock_out_i2c_bit(hw, nack);
+		if (status != E1000_SUCCESS)
+			goto fail;
+
+		e1000_i2c_stop(hw);
+		break;
+
+fail:
+		e1000_release_swfw_sync_82575(hw, swfw_mask);
+		msec_delay(100);
+		e1000_i2c_bus_clear(hw);
+		retry++;
+		if (retry < max_retry)
+			DEBUGOUT("I2C byte read error - Retrying.\n");
+		else
+			DEBUGOUT("I2C byte read error.\n");
+
+	} while (retry < max_retry);
+
+	e1000_release_swfw_sync_82575(hw, swfw_mask);
+
+read_byte_out:
+
+	return status;
+}
+
+/**
+ *  e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
+ *  @hw: pointer to hardware structure
+ *  @byte_offset: byte offset to write
+ *  @data: value to write
+ *
+ *  Performs byte write operation over I2C interface at
+ *  a specified device address.
+ **/
+s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
+				 u8 dev_addr, u8 data)
+{
+	s32 status = E1000_SUCCESS;
+	u32 max_retry = 1;
+	u32 retry = 0;
+	u16 swfw_mask = 0;
+
+	DEBUGFUNC("e1000_write_i2c_byte_generic");
+
+	swfw_mask = E1000_SWFW_PHY0_SM;
+
+	if (e1000_acquire_swfw_sync_82575(hw, swfw_mask) != E1000_SUCCESS) {
+		status = E1000_ERR_SWFW_SYNC;
+		goto write_byte_out;
+	}
+
+	do {
+		e1000_i2c_start(hw);
+
+		status = e1000_clock_out_i2c_byte(hw, dev_addr);
+		if (status != E1000_SUCCESS)
+			goto fail;
+
+		status = e1000_get_i2c_ack(hw);
+		if (status != E1000_SUCCESS)
+			goto fail;
+
+		status = e1000_clock_out_i2c_byte(hw, byte_offset);
+		if (status != E1000_SUCCESS)
+			goto fail;
+
+		status = e1000_get_i2c_ack(hw);
+		if (status != E1000_SUCCESS)
+			goto fail;
+
+		status = e1000_clock_out_i2c_byte(hw, data);
+		if (status != E1000_SUCCESS)
+			goto fail;
+
+		status = e1000_get_i2c_ack(hw);
+		if (status != E1000_SUCCESS)
+			goto fail;
+
+		e1000_i2c_stop(hw);
+		break;
+
+fail:
+		e1000_i2c_bus_clear(hw);
+		retry++;
+		if (retry < max_retry)
+			DEBUGOUT("I2C byte write error - Retrying.\n");
+		else
+			DEBUGOUT("I2C byte write error.\n");
+	} while (retry < max_retry);
+
+	e1000_release_swfw_sync_82575(hw, swfw_mask);
+
+write_byte_out:
+
+	return status;
+}
+
+/**
+ *  e1000_i2c_start - Sets I2C start condition
+ *  @hw: pointer to hardware structure
+ *
+ *  Sets I2C start condition (High -> Low on SDA while SCL is High)
+ **/
+static void e1000_i2c_start(struct e1000_hw *hw)
+{
+	u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
+
+	DEBUGFUNC("e1000_i2c_start");
+
+	/* Start condition must begin with data and clock high */
+	e1000_set_i2c_data(hw, &i2cctl, 1);
+	e1000_raise_i2c_clk(hw, &i2cctl);
+
+	/* Setup time for start condition (4.7us) */
+	usec_delay(E1000_I2C_T_SU_STA);
+
+	e1000_set_i2c_data(hw, &i2cctl, 0);
+
+	/* Hold time for start condition (4us) */
+	usec_delay(E1000_I2C_T_HD_STA);
+
+	e1000_lower_i2c_clk(hw, &i2cctl);
+
+	/* Minimum low period of clock is 4.7 us */
+	usec_delay(E1000_I2C_T_LOW);
+
+}
+
+/**
+ *  e1000_i2c_stop - Sets I2C stop condition
+ *  @hw: pointer to hardware structure
+ *
+ *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
+ **/
+static void e1000_i2c_stop(struct e1000_hw *hw)
+{
+	u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
+
+	DEBUGFUNC("e1000_i2c_stop");
+
+	/* Stop condition must begin with data low and clock high */
+	e1000_set_i2c_data(hw, &i2cctl, 0);
+	e1000_raise_i2c_clk(hw, &i2cctl);
+
+	/* Setup time for stop condition (4us) */
+	usec_delay(E1000_I2C_T_SU_STO);
+
+	e1000_set_i2c_data(hw, &i2cctl, 1);
+
+	/* bus free time between stop and start (4.7us)*/
+	usec_delay(E1000_I2C_T_BUF);
+}
+
+/**
+ *  e1000_clock_in_i2c_byte - Clocks in one byte via I2C
+ *  @hw: pointer to hardware structure
+ *  @data: data byte to clock in
+ *
+ *  Clocks in one byte data via I2C data/clock
+ **/
+static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
+{
+	s32 i;
+	bool bit = 0;
+
+	DEBUGFUNC("e1000_clock_in_i2c_byte");
+
+	*data = 0;
+	for (i = 7; i >= 0; i--) {
+		e1000_clock_in_i2c_bit(hw, &bit);
+		*data |= bit << i;
+	}
+
+	return E1000_SUCCESS;
+}
+
+/**
+ *  e1000_clock_out_i2c_byte - Clocks out one byte via I2C
+ *  @hw: pointer to hardware structure
+ *  @data: data byte clocked out
+ *
+ *  Clocks out one byte data via I2C data/clock
+ **/
+static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
+{
+	s32 status = E1000_SUCCESS;
+	s32 i;
+	u32 i2cctl;
+	bool bit = 0;
+
+	DEBUGFUNC("e1000_clock_out_i2c_byte");
+
+	for (i = 7; i >= 0; i--) {
+		bit = (data >> i) & 0x1;
+		status = e1000_clock_out_i2c_bit(hw, bit);
+
+		if (status != E1000_SUCCESS)
+			break;
+	}
+
+	/* Release SDA line (set high) */
+	i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
+
+	i2cctl |= E1000_I2C_DATA_OE_N;
+	E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
+	E1000_WRITE_FLUSH(hw);
+
+	return status;
+}
+
+/**
+ *  e1000_get_i2c_ack - Polls for I2C ACK
+ *  @hw: pointer to hardware structure
+ *
+ *  Clocks in/out one bit via I2C data/clock
+ **/
+static s32 e1000_get_i2c_ack(struct e1000_hw *hw)
+{
+	s32 status = E1000_SUCCESS;
+	u32 i = 0;
+	u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
+	u32 timeout = 10;
+	bool ack = 1;
+
+	DEBUGFUNC("e1000_get_i2c_ack");
+
+	e1000_raise_i2c_clk(hw, &i2cctl);
+
+	/* Minimum high period of clock is 4us */
+	usec_delay(E1000_I2C_T_HIGH);
+
+	/* Wait until SCL returns high */
+	for (i = 0; i < timeout; i++) {
+		usec_delay(1);
+		i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
+		if (i2cctl & E1000_I2C_CLK_IN)
+			break;
+	}
+	if (!(i2cctl & E1000_I2C_CLK_IN))
+		return E1000_ERR_I2C;
+
+	ack = e1000_get_i2c_data(&i2cctl);
+	if (ack == 1) {
+		DEBUGOUT("I2C ack was not received.\n");
+		status = E1000_ERR_I2C;
+	}
+
+	e1000_lower_i2c_clk(hw, &i2cctl);
+
+	/* Minimum low period of clock is 4.7 us */
+	usec_delay(E1000_I2C_T_LOW);
+
+	return status;
+}
+
+/**
+ *  e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
+ *  @hw: pointer to hardware structure
+ *  @data: read data value
+ *
+ *  Clocks in one bit via I2C data/clock
+ **/
+static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
+{
+	u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
+
+	DEBUGFUNC("e1000_clock_in_i2c_bit");
+
+	e1000_raise_i2c_clk(hw, &i2cctl);
+
+	/* Minimum high period of clock is 4us */
+	usec_delay(E1000_I2C_T_HIGH);
+
+	i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
+	*data = e1000_get_i2c_data(&i2cctl);
+
+	e1000_lower_i2c_clk(hw, &i2cctl);
+
+	/* Minimum low period of clock is 4.7 us */
+	usec_delay(E1000_I2C_T_LOW);
+
+	return E1000_SUCCESS;
+}
+
+/**
+ *  e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
+ *  @hw: pointer to hardware structure
+ *  @data: data value to write
+ *
+ *  Clocks out one bit via I2C data/clock
+ **/
+static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
+{
+	s32 status;
+	u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
+
+	DEBUGFUNC("e1000_clock_out_i2c_bit");
+
+	status = e1000_set_i2c_data(hw, &i2cctl, data);
+	if (status == E1000_SUCCESS) {
+		e1000_raise_i2c_clk(hw, &i2cctl);
+
+		/* Minimum high period of clock is 4us */
+		usec_delay(E1000_I2C_T_HIGH);
+
+		e1000_lower_i2c_clk(hw, &i2cctl);
+
+		/* Minimum low period of clock is 4.7 us.
+		 * This also takes care of the data hold time.
+		 */
+		usec_delay(E1000_I2C_T_LOW);
+	} else {
+		status = E1000_ERR_I2C;
+		DEBUGOUT1("I2C data was not set to %X\n", data);
+	}
+
+	return status;
+}
+/**
+ *  e1000_raise_i2c_clk - Raises the I2C SCL clock
+ *  @hw: pointer to hardware structure
+ *  @i2cctl: Current value of I2CCTL register
+ *
+ *  Raises the I2C clock line '0'->'1'
+ **/
+static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
+{
+	DEBUGFUNC("e1000_raise_i2c_clk");
+
+	*i2cctl |= E1000_I2C_CLK_OUT;
+	*i2cctl &= ~E1000_I2C_CLK_OE_N;
+	E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
+	E1000_WRITE_FLUSH(hw);
+
+	/* SCL rise time (1000ns) */
+	usec_delay(E1000_I2C_T_RISE);
+}
+
+/**
+ *  e1000_lower_i2c_clk - Lowers the I2C SCL clock
+ *  @hw: pointer to hardware structure
+ *  @i2cctl: Current value of I2CCTL register
+ *
+ *  Lowers the I2C clock line '1'->'0'
+ **/
+static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
+{
+
+	DEBUGFUNC("e1000_lower_i2c_clk");
+
+	*i2cctl &= ~E1000_I2C_CLK_OUT;
+	*i2cctl &= ~E1000_I2C_CLK_OE_N;
+	E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
+	E1000_WRITE_FLUSH(hw);
+
+	/* SCL fall time (300ns) */
+	usec_delay(E1000_I2C_T_FALL);
+}
+
+/**
+ *  e1000_set_i2c_data - Sets the I2C data bit
+ *  @hw: pointer to hardware structure
+ *  @i2cctl: Current value of I2CCTL register
+ *  @data: I2C data value (0 or 1) to set
+ *
+ *  Sets the I2C data bit
+ **/
+static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
+{
+	s32 status = E1000_SUCCESS;
+
+	DEBUGFUNC("e1000_set_i2c_data");
+
+	if (data)
+		*i2cctl |= E1000_I2C_DATA_OUT;
+	else
+		*i2cctl &= ~E1000_I2C_DATA_OUT;
+
+	*i2cctl &= ~E1000_I2C_DATA_OE_N;
+	*i2cctl |= E1000_I2C_CLK_OE_N;
+	E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
+	E1000_WRITE_FLUSH(hw);
+
+	/* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
+	usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
+
+	*i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
+	if (data != e1000_get_i2c_data(i2cctl)) {
+		status = E1000_ERR_I2C;
+		DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
+	}
+
+	return status;
+}
+
+/**
+ *  e1000_get_i2c_data - Reads the I2C SDA data bit
+ *  @hw: pointer to hardware structure
+ *  @i2cctl: Current value of I2CCTL register
+ *
+ *  Returns the I2C data bit value
+ **/
+static bool e1000_get_i2c_data(u32 *i2cctl)
+{
+	bool data;
+
+	DEBUGFUNC("e1000_get_i2c_data");
+
+	if (*i2cctl & E1000_I2C_DATA_IN)
+		data = 1;
+	else
+		data = 0;
+
+	return data;
+}
+
+/**
+ *  e1000_i2c_bus_clear - Clears the I2C bus
+ *  @hw: pointer to hardware structure
+ *
+ *  Clears the I2C bus by sending nine clock pulses.
+ *  Used when data line is stuck low.
+ **/
+void e1000_i2c_bus_clear(struct e1000_hw *hw)
+{
+	u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
+	u32 i;
+
+	DEBUGFUNC("e1000_i2c_bus_clear");
+
+	e1000_i2c_start(hw);
+
+	e1000_set_i2c_data(hw, &i2cctl, 1);
+
+	for (i = 0; i < 9; i++) {
+		e1000_raise_i2c_clk(hw, &i2cctl);
+
+		/* Min high period of clock is 4us */
+		usec_delay(E1000_I2C_T_HIGH);
+
+		e1000_lower_i2c_clk(hw, &i2cctl);
+
+		/* Min low period of clock is 4.7us*/
+		usec_delay(E1000_I2C_T_LOW);
+	}
+
+	e1000_i2c_start(hw);
+
+	/* Put the i2c bus back to default state */
+	e1000_i2c_stop(hw);
+}
+
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/e1000/e1000_82575.h
--- a/head/sys/dev/e1000/e1000_82575.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/e1000/e1000_82575.h	Thu Dec 15 12:59:38 2011 +0200
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,15 +30,15 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD: head/sys/dev/e1000/e1000_82575.h 228386 2011-12-10 06:55:02Z jfv $*/
 
 #ifndef _E1000_82575_H_
 #define _E1000_82575_H_
 
-#define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \
-                                     (ID_LED_DEF1_DEF2 <<  8) | \
-                                     (ID_LED_DEF1_DEF2 <<  4) | \
-                                     (ID_LED_OFF1_ON2))
+#define ID_LED_DEFAULT_82575_SERDES	((ID_LED_DEF1_DEF2 << 12) | \
+					 (ID_LED_DEF1_DEF2 <<  8) | \
+					 (ID_LED_DEF1_DEF2 <<  4) | \
+					 (ID_LED_OFF1_ON2))
 /*
  * Receive Address Register Count
  * Number of high/low register pairs in the RAR.  The RAR (Receive Address
@@ -49,13 +49,13 @@
  * For 82576, there are an additional set of RARs that begin at an offset
  * separate from the first set of RARs.
  */
-#define E1000_RAR_ENTRIES_82575        16
-#define E1000_RAR_ENTRIES_82576        24
-#define E1000_RAR_ENTRIES_82580        24
-#define E1000_RAR_ENTRIES_I350         32
-#define E1000_SW_SYNCH_MB              0x00000100
-#define E1000_STAT_DEV_RST_SET         0x00100000
-#define E1000_CTRL_DEV_RST             0x20000000
+#define E1000_RAR_ENTRIES_82575	16
+#define E1000_RAR_ENTRIES_82576	24
+#define E1000_RAR_ENTRIES_82580	24
+#define E1000_RAR_ENTRIES_I350	32
+#define E1000_SW_SYNCH_MB	0x00000100
+#define E1000_STAT_DEV_RST_SET	0x00100000
+#define E1000_CTRL_DEV_RST	0x20000000
 
 #ifdef E1000_BIT_FIELDS
 struct e1000_adv_data_desc {
@@ -63,137 +63,138 @@
 	union {
 		u32 data;
 		struct {
-			u32 datalen :16; /* Data buffer length */
-			u32 rsvd    :4;
-			u32 dtyp    :4;  /* Descriptor type */
-			u32 dcmd    :8;  /* Descriptor command */
+			u32 datalen:16; /* Data buffer length */
+			u32 rsvd:4;
+			u32 dtyp:4;  /* Descriptor type */
+			u32 dcmd:8;  /* Descriptor command */
 		} config;
 	} lower;
 	union {
 		u32 data;
 		struct {
-			u32 status  :4;  /* Descriptor status */
-			u32 idx     :4;
-			u32 popts   :6;  /* Packet Options */
-			u32 paylen  :18; /* Payload length */
+			u32 status:4;  /* Descriptor status */
+			u32 idx:4;
+			u32 popts:6;  /* Packet Options */
+			u32 paylen:18; /* Payload length */
 		} options;
 	} upper;
 };
 
-#define E1000_TXD_DTYP_ADV_C    0x2  /* Advanced Context Descriptor */
-#define E1000_TXD_DTYP_ADV_D    0x3  /* Advanced Data Descriptor */
-#define E1000_ADV_TXD_CMD_DEXT  0x20 /* Descriptor extension (0 = legacy) */
-#define E1000_ADV_TUCMD_IPV4    0x2  /* IP Packet Type: 1=IPv4 */
-#define E1000_ADV_TUCMD_IPV6    0x0  /* IP Packet Type: 0=IPv6 */
-#define E1000_ADV_TUCMD_L4T_UDP 0x0  /* L4 Packet TYPE of UDP */
-#define E1000_ADV_TUCMD_L4T_TCP 0x4  /* L4 Packet TYPE of TCP */
-#define E1000_ADV_TUCMD_MKRREQ  0x10 /* Indicates markers are required */
-#define E1000_ADV_DCMD_EOP      0x1  /* End of Packet */
-#define E1000_ADV_DCMD_IFCS     0x2  /* Insert FCS (Ethernet CRC) */
-#define E1000_ADV_DCMD_RS       0x8  /* Report Status */
-#define E1000_ADV_DCMD_VLE      0x40 /* Add VLAN tag */
-#define E1000_ADV_DCMD_TSE      0x80 /* TCP Seg enable */
+#define E1000_TXD_DTYP_ADV_C	0x2  /* Advanced Context Descriptor */
+#define E1000_TXD_DTYP_ADV_D	0x3  /* Advanced Data Descriptor */
+#define E1000_ADV_TXD_CMD_DEXT	0x20 /* Descriptor extension (0 = legacy) */
+#define E1000_ADV_TUCMD_IPV4	0x2  /* IP Packet Type: 1=IPv4 */
+#define E1000_ADV_TUCMD_IPV6	0x0  /* IP Packet Type: 0=IPv6 */
+#define E1000_ADV_TUCMD_L4T_UDP	0x0  /* L4 Packet TYPE of UDP */
+#define E1000_ADV_TUCMD_L4T_TCP	0x4  /* L4 Packet TYPE of TCP */
+#define E1000_ADV_TUCMD_MKRREQ	0x10 /* Indicates markers are required */
+#define E1000_ADV_DCMD_EOP	0x1  /* End of Packet */
+#define E1000_ADV_DCMD_IFCS	0x2  /* Insert FCS (Ethernet CRC) */
+#define E1000_ADV_DCMD_RS	0x8  /* Report Status */
+#define E1000_ADV_DCMD_VLE	0x40 /* Add VLAN tag */
+#define E1000_ADV_DCMD_TSE	0x80 /* TCP Seg enable */
 /* Extended Device Control */
-#define E1000_CTRL_EXT_NSICR    0x00000001 /* Disable Intr Clear all on read */
+#define E1000_CTRL_EXT_NSICR	0x00000001 /* Disable Intr Clear all on read */
 
 struct e1000_adv_context_desc {
 	union {
 		u32 ip_config;
 		struct {
-			u32 iplen    :9;
-			u32 maclen   :7;
-			u32 vlan_tag :16;
+			u32 iplen:9;
+			u32 maclen:7;
+			u32 vlan_tag:16;
 		} fields;
 	} ip_setup;
 	u32 seq_num;
 	union {
 		u64 l4_config;
 		struct {
-			u32 mkrloc :9;
-			u32 tucmd  :11;
-			u32 dtyp   :4;
-			u32 adv    :8;
-			u32 rsvd   :4;
-			u32 idx    :4;
-			u32 l4len  :8;
-			u32 mss    :16;
+			u32 mkrloc:9;
+			u32 tucmd:11;
+			u32 dtyp:4;
+			u32 adv:8;
+			u32 rsvd:4;
+			u32 idx:4;
+			u32 l4len:8;
+			u32 mss:16;
 		} fields;
 	} l4_setup;
 };
 #endif
 
 /* SRRCTL bit definitions */
-#define E1000_SRRCTL_BSIZEPKT_SHIFT                     10 /* Shift _right_ */
-#define E1000_SRRCTL_BSIZEHDRSIZE_MASK                  0x00000F00
-#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT                 2  /* Shift _left_ */
-#define E1000_SRRCTL_DESCTYPE_LEGACY                    0x00000000
-#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF                0x02000000
-#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT                 0x04000000
-#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS          0x0A000000
-#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION           0x06000000
+#define E1000_SRRCTL_BSIZEPKT_SHIFT		10 /* Shift _right_ */
+#define E1000_SRRCTL_BSIZEHDRSIZE_MASK		0x00000F00
+#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT		2  /* Shift _left_ */
+#define E1000_SRRCTL_DESCTYPE_LEGACY		0x00000000
+#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF	0x02000000
+#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT		0x04000000
+#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS	0x0A000000
+#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION	0x06000000
 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
-#define E1000_SRRCTL_DESCTYPE_MASK                      0x0E000000
-#define E1000_SRRCTL_TIMESTAMP                          0x40000000
-#define E1000_SRRCTL_DROP_EN                            0x80000000
+#define E1000_SRRCTL_DESCTYPE_MASK		0x0E000000
+#define E1000_SRRCTL_TIMESTAMP			0x40000000
+#define E1000_SRRCTL_DROP_EN			0x80000000
 
-#define E1000_SRRCTL_BSIZEPKT_MASK      0x0000007F
-#define E1000_SRRCTL_BSIZEHDR_MASK      0x00003F00
+#define E1000_SRRCTL_BSIZEPKT_MASK		0x0000007F
+#define E1000_SRRCTL_BSIZEHDR_MASK		0x00003F00
 
-#define E1000_TX_HEAD_WB_ENABLE   0x1
-#define E1000_TX_SEQNUM_WB_ENABLE 0x2
+#define E1000_TX_HEAD_WB_ENABLE		0x1
+#define E1000_TX_SEQNUM_WB_ENABLE	0x2
 
-#define E1000_MRQC_ENABLE_RSS_4Q            0x00000002
-#define E1000_MRQC_ENABLE_VMDQ              0x00000003
-#define E1000_MRQC_ENABLE_VMDQ_RSS_2Q       0x00000005
-#define E1000_MRQC_RSS_FIELD_IPV4_UDP       0x00400000
-#define E1000_MRQC_RSS_FIELD_IPV6_UDP       0x00800000
-#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX    0x01000000
-#define E1000_MRQC_ENABLE_RSS_8Q            0x00000002
+#define E1000_MRQC_ENABLE_RSS_4Q		0x00000002
+#define E1000_MRQC_ENABLE_VMDQ			0x00000003
+#define E1000_MRQC_ENABLE_VMDQ_RSS_2Q		0x00000005
+#define E1000_MRQC_RSS_FIELD_IPV4_UDP		0x00400000
+#define E1000_MRQC_RSS_FIELD_IPV6_UDP		0x00800000
+#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX	0x01000000
+#define E1000_MRQC_ENABLE_RSS_8Q		0x00000002
 
-#define E1000_VMRCTL_MIRROR_PORT_SHIFT      8
-#define E1000_VMRCTL_MIRROR_DSTPORT_MASK    (7 << E1000_VMRCTL_MIRROR_PORT_SHIFT)
-#define E1000_VMRCTL_POOL_MIRROR_ENABLE     (1 << 0)
-#define E1000_VMRCTL_UPLINK_MIRROR_ENABLE   (1 << 1)
-#define E1000_VMRCTL_DOWNLINK_MIRROR_ENABLE (1 << 2)
+#define E1000_VMRCTL_MIRROR_PORT_SHIFT		8
+#define E1000_VMRCTL_MIRROR_DSTPORT_MASK	(7 << \
+						 E1000_VMRCTL_MIRROR_PORT_SHIFT)
+#define E1000_VMRCTL_POOL_MIRROR_ENABLE		(1 << 0)
+#define E1000_VMRCTL_UPLINK_MIRROR_ENABLE	(1 << 1)
+#define E1000_VMRCTL_DOWNLINK_MIRROR_ENABLE	(1 << 2)
 
 #define E1000_EICR_TX_QUEUE ( \
-    E1000_EICR_TX_QUEUE0 |    \
-    E1000_EICR_TX_QUEUE1 |    \
-    E1000_EICR_TX_QUEUE2 |    \
-    E1000_EICR_TX_QUEUE3)
+	E1000_EICR_TX_QUEUE0 |    \
+	E1000_EICR_TX_QUEUE1 |    \
+	E1000_EICR_TX_QUEUE2 |    \
+	E1000_EICR_TX_QUEUE3)
 
 #define E1000_EICR_RX_QUEUE ( \
-    E1000_EICR_RX_QUEUE0 |    \
-    E1000_EICR_RX_QUEUE1 |    \
-    E1000_EICR_RX_QUEUE2 |    \
-    E1000_EICR_RX_QUEUE3)
+	E1000_EICR_RX_QUEUE0 |    \
+	E1000_EICR_RX_QUEUE1 |    \
+	E1000_EICR_RX_QUEUE2 |    \
+	E1000_EICR_RX_QUEUE3)
 
-#define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE
-#define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE
+#define E1000_EIMS_RX_QUEUE	E1000_EICR_RX_QUEUE
+#define E1000_EIMS_TX_QUEUE	E1000_EICR_TX_QUEUE
 
 #define EIMS_ENABLE_MASK ( \
-    E1000_EIMS_RX_QUEUE  | \
-    E1000_EIMS_TX_QUEUE  | \
-    E1000_EIMS_TCP_TIMER | \
-    E1000_EIMS_OTHER)
+	E1000_EIMS_RX_QUEUE  | \
+	E1000_EIMS_TX_QUEUE  | \
+	E1000_EIMS_TCP_TIMER | \
+	E1000_EIMS_OTHER)
 
 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
-#define E1000_IMIR_PORT_IM_EN     0x00010000  /* TCP port enable */
-#define E1000_IMIR_PORT_BP        0x00020000  /* TCP port check bypass */
-#define E1000_IMIREXT_SIZE_BP     0x00001000  /* Packet size bypass */
-#define E1000_IMIREXT_CTRL_URG    0x00002000  /* Check URG bit in header */
-#define E1000_IMIREXT_CTRL_ACK    0x00004000  /* Check ACK bit in header */
-#define E1000_IMIREXT_CTRL_PSH    0x00008000  /* Check PSH bit in header */
-#define E1000_IMIREXT_CTRL_RST    0x00010000  /* Check RST bit in header */
-#define E1000_IMIREXT_CTRL_SYN    0x00020000  /* Check SYN bit in header */
-#define E1000_IMIREXT_CTRL_FIN    0x00040000  /* Check FIN bit in header */
-#define E1000_IMIREXT_CTRL_BP     0x00080000  /* Bypass check of ctrl bits */
+#define E1000_IMIR_PORT_IM_EN	0x00010000  /* TCP port enable */
+#define E1000_IMIR_PORT_BP	0x00020000  /* TCP port check bypass */
+#define E1000_IMIREXT_SIZE_BP	0x00001000  /* Packet size bypass */
+#define E1000_IMIREXT_CTRL_URG	0x00002000  /* Check URG bit in header */
+#define E1000_IMIREXT_CTRL_ACK	0x00004000  /* Check ACK bit in header */
+#define E1000_IMIREXT_CTRL_PSH	0x00008000  /* Check PSH bit in header */
+#define E1000_IMIREXT_CTRL_RST	0x00010000  /* Check RST bit in header */
+#define E1000_IMIREXT_CTRL_SYN	0x00020000  /* Check SYN bit in header */
+#define E1000_IMIREXT_CTRL_FIN	0x00040000  /* Check FIN bit in header */
+#define E1000_IMIREXT_CTRL_BP	0x00080000  /* Bypass check of ctrl bits */
 
 /* Receive Descriptor - Advanced */
 union e1000_adv_rx_desc {
 	struct {
-		__le64 pkt_addr;             /* Packet buffer address */
-		__le64 hdr_addr;             /* Header buffer address */
+		__le64 pkt_addr; /* Packet buffer address */
+		__le64 hdr_addr; /* Header buffer address */
 	} read;
 	struct {
 		struct {
@@ -206,74 +207,74 @@
 				} hs_rss;
 			} lo_dword;
 			union {
-				__le32 rss;          /* RSS Hash */
+				__le32 rss; /* RSS Hash */
 				struct {
-					__le16 ip_id;    /* IP id */
-					__le16 csum;     /* Packet Checksum */
+					__le16 ip_id; /* IP id */
+					__le16 csum; /* Packet Checksum */
 				} csum_ip;
 			} hi_dword;
 		} lower;
 		struct {
-			__le32 status_error;     /* ext status/error */
-			__le16 length;           /* Packet length */
-			__le16 vlan;             /* VLAN tag */
+			__le32 status_error; /* ext status/error */
+			__le16 length; /* Packet length */
+			__le16 vlan; /* VLAN tag */
 		} upper;
 	} wb;  /* writeback */
 };
 
-#define E1000_RXDADV_RSSTYPE_MASK        0x0000000F
-#define E1000_RXDADV_RSSTYPE_SHIFT       12
-#define E1000_RXDADV_HDRBUFLEN_MASK      0x7FE0
-#define E1000_RXDADV_HDRBUFLEN_SHIFT     5
-#define E1000_RXDADV_SPLITHEADER_EN      0x00001000
-#define E1000_RXDADV_SPH                 0x8000
-#define E1000_RXDADV_STAT_TS             0x10000 /* Pkt was time stamped */
-#define E1000_RXDADV_STAT_TSIP           0x08000 /* timestamp in packet */
-#define E1000_RXDADV_ERR_HBO             0x00800000
+#define E1000_RXDADV_RSSTYPE_MASK	0x0000000F
+#define E1000_RXDADV_RSSTYPE_SHIFT	12
+#define E1000_RXDADV_HDRBUFLEN_MASK	0x7FE0
+#define E1000_RXDADV_HDRBUFLEN_SHIFT	5
+#define E1000_RXDADV_SPLITHEADER_EN	0x00001000
+#define E1000_RXDADV_SPH		0x8000
+#define E1000_RXDADV_STAT_TS		0x10000 /* Pkt was time stamped */
+#define E1000_RXDADV_STAT_TSIP		0x08000 /* timestamp in packet */
+#define E1000_RXDADV_ERR_HBO		0x00800000
 
 /* RSS Hash results */
-#define E1000_RXDADV_RSSTYPE_NONE        0x00000000
-#define E1000_RXDADV_RSSTYPE_IPV4_TCP    0x00000001
-#define E1000_RXDADV_RSSTYPE_IPV4        0x00000002
-#define E1000_RXDADV_RSSTYPE_IPV6_TCP    0x00000003
-#define E1000_RXDADV_RSSTYPE_IPV6_EX     0x00000004
-#define E1000_RXDADV_RSSTYPE_IPV6        0x00000005
+#define E1000_RXDADV_RSSTYPE_NONE	0x00000000
+#define E1000_RXDADV_RSSTYPE_IPV4_TCP	0x00000001
+#define E1000_RXDADV_RSSTYPE_IPV4	0x00000002
+#define E1000_RXDADV_RSSTYPE_IPV6_TCP	0x00000003
+#define E1000_RXDADV_RSSTYPE_IPV6_EX	0x00000004
+#define E1000_RXDADV_RSSTYPE_IPV6	0x00000005
 #define E1000_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
-#define E1000_RXDADV_RSSTYPE_IPV4_UDP    0x00000007
-#define E1000_RXDADV_RSSTYPE_IPV6_UDP    0x00000008
+#define E1000_RXDADV_RSSTYPE_IPV4_UDP	0x00000007
+#define E1000_RXDADV_RSSTYPE_IPV6_UDP	0x00000008
 #define E1000_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
 
 /* RSS Packet Types as indicated in the receive descriptor */
-#define E1000_RXDADV_PKTTYPE_NONE        0x00000000
-#define E1000_RXDADV_PKTTYPE_IPV4        0x00000010 /* IPV4 hdr present */
-#define E1000_RXDADV_PKTTYPE_IPV4_EX     0x00000020 /* IPV4 hdr + extensions */
-#define E1000_RXDADV_PKTTYPE_IPV6        0x00000040 /* IPV6 hdr present */
-#define E1000_RXDADV_PKTTYPE_IPV6_EX     0x00000080 /* IPV6 hdr + extensions */
-#define E1000_RXDADV_PKTTYPE_TCP         0x00000100 /* TCP hdr present */
-#define E1000_RXDADV_PKTTYPE_UDP         0x00000200 /* UDP hdr present */
-#define E1000_RXDADV_PKTTYPE_SCTP        0x00000400 /* SCTP hdr present */
-#define E1000_RXDADV_PKTTYPE_NFS         0x00000800 /* NFS hdr present */
+#define E1000_RXDADV_PKTTYPE_NONE	0x00000000
+#define E1000_RXDADV_PKTTYPE_IPV4	0x00000010 /* IPV4 hdr present */
+#define E1000_RXDADV_PKTTYPE_IPV4_EX	0x00000020 /* IPV4 hdr + extensions */
+#define E1000_RXDADV_PKTTYPE_IPV6	0x00000040 /* IPV6 hdr present */
+#define E1000_RXDADV_PKTTYPE_IPV6_EX	0x00000080 /* IPV6 hdr + extensions */
+#define E1000_RXDADV_PKTTYPE_TCP	0x00000100 /* TCP hdr present */
+#define E1000_RXDADV_PKTTYPE_UDP	0x00000200 /* UDP hdr present */
+#define E1000_RXDADV_PKTTYPE_SCTP	0x00000400 /* SCTP hdr present */
+#define E1000_RXDADV_PKTTYPE_NFS	0x00000800 /* NFS hdr present */
 
-#define E1000_RXDADV_PKTTYPE_IPSEC_ESP   0x00001000 /* IPSec ESP */
-#define E1000_RXDADV_PKTTYPE_IPSEC_AH    0x00002000 /* IPSec AH */
-#define E1000_RXDADV_PKTTYPE_LINKSEC     0x00004000 /* LinkSec Encap */
-#define E1000_RXDADV_PKTTYPE_ETQF        0x00008000 /* PKTTYPE is ETQF index */
-#define E1000_RXDADV_PKTTYPE_ETQF_MASK   0x00000070 /* ETQF has 8 indices */
-#define E1000_RXDADV_PKTTYPE_ETQF_SHIFT  4          /* Right-shift 4 bits */
+#define E1000_RXDADV_PKTTYPE_IPSEC_ESP	0x00001000 /* IPSec ESP */
+#define E1000_RXDADV_PKTTYPE_IPSEC_AH	0x00002000 /* IPSec AH */
+#define E1000_RXDADV_PKTTYPE_LINKSEC	0x00004000 /* LinkSec Encap */
+#define E1000_RXDADV_PKTTYPE_ETQF	0x00008000 /* PKTTYPE is ETQF index */
+#define E1000_RXDADV_PKTTYPE_ETQF_MASK	0x00000070 /* ETQF has 8 indices */
+#define E1000_RXDADV_PKTTYPE_ETQF_SHIFT	4 /* Right-shift 4 bits */
 
 /* LinkSec results */
 /* Security Processing bit Indication */
-#define E1000_RXDADV_LNKSEC_STATUS_SECP         0x00020000
-#define E1000_RXDADV_LNKSEC_ERROR_BIT_MASK      0x18000000
-#define E1000_RXDADV_LNKSEC_ERROR_NO_SA_MATCH   0x08000000
-#define E1000_RXDADV_LNKSEC_ERROR_REPLAY_ERROR  0x10000000
-#define E1000_RXDADV_LNKSEC_ERROR_BAD_SIG       0x18000000
+#define E1000_RXDADV_LNKSEC_STATUS_SECP		0x00020000
+#define E1000_RXDADV_LNKSEC_ERROR_BIT_MASK	0x18000000
+#define E1000_RXDADV_LNKSEC_ERROR_NO_SA_MATCH	0x08000000
+#define E1000_RXDADV_LNKSEC_ERROR_REPLAY_ERROR	0x10000000
+#define E1000_RXDADV_LNKSEC_ERROR_BAD_SIG	0x18000000
 
-#define E1000_RXDADV_IPSEC_STATUS_SECP          0x00020000
-#define E1000_RXDADV_IPSEC_ERROR_BIT_MASK       0x18000000
-#define E1000_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL       0x08000000
-#define E1000_RXDADV_IPSEC_ERROR_INVALID_LENGTH         0x10000000
-#define E1000_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED  0x18000000
+#define E1000_RXDADV_IPSEC_STATUS_SECP			0x00020000
+#define E1000_RXDADV_IPSEC_ERROR_BIT_MASK		0x18000000
+#define E1000_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL	0x08000000
+#define E1000_RXDADV_IPSEC_ERROR_INVALID_LENGTH		0x10000000
+#define E1000_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED	0x18000000
 
 /* Transmit Descriptor - Advanced */
 union e1000_adv_tx_desc {
@@ -290,25 +291,26 @@
 };
 
 /* Adv Transmit Descriptor Config Masks */
-#define E1000_ADVTXD_DTYP_CTXT    0x00200000 /* Advanced Context Descriptor */
-#define E1000_ADVTXD_DTYP_DATA    0x00300000 /* Advanced Data Descriptor */
-#define E1000_ADVTXD_DCMD_EOP     0x01000000 /* End of Packet */
-#define E1000_ADVTXD_DCMD_IFCS    0x02000000 /* Insert FCS (Ethernet CRC) */
-#define E1000_ADVTXD_DCMD_RS      0x08000000 /* Report Status */
-#define E1000_ADVTXD_DCMD_DDTYP_ISCSI  0x10000000 /* DDP hdr type or iSCSI */
-#define E1000_ADVTXD_DCMD_DEXT    0x20000000 /* Descriptor extension (1=Adv) */
-#define E1000_ADVTXD_DCMD_VLE     0x40000000 /* VLAN pkt enable */
-#define E1000_ADVTXD_DCMD_TSE     0x80000000 /* TCP Seg enable */
-#define E1000_ADVTXD_MAC_LINKSEC  0x00040000 /* Apply LinkSec on packet */
-#define E1000_ADVTXD_MAC_TSTAMP   0x00080000 /* IEEE1588 Timestamp packet */
-#define E1000_ADVTXD_STAT_SN_CRC  0x00000002 /* NXTSEQ/SEED present in WB */
-#define E1000_ADVTXD_IDX_SHIFT    4  /* Adv desc Index shift */
-#define E1000_ADVTXD_POPTS_ISCO_1ST  0x00000000 /* 1st TSO of iSCSI PDU */
-#define E1000_ADVTXD_POPTS_ISCO_MDL  0x00000800 /* Middle TSO of iSCSI PDU */
-#define E1000_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
-#define E1000_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU*/
-#define E1000_ADVTXD_POPTS_IPSEC     0x00000400 /* IPSec offload request */
-#define E1000_ADVTXD_PAYLEN_SHIFT    14 /* Adv desc PAYLEN shift */
+#define E1000_ADVTXD_DTYP_CTXT	0x00200000 /* Advanced Context Descriptor */
+#define E1000_ADVTXD_DTYP_DATA	0x00300000 /* Advanced Data Descriptor */
+#define E1000_ADVTXD_DCMD_EOP	0x01000000 /* End of Packet */
+#define E1000_ADVTXD_DCMD_IFCS	0x02000000 /* Insert FCS (Ethernet CRC) */
+#define E1000_ADVTXD_DCMD_RS	0x08000000 /* Report Status */
+#define E1000_ADVTXD_DCMD_DDTYP_ISCSI	0x10000000 /* DDP hdr type or iSCSI */
+#define E1000_ADVTXD_DCMD_DEXT	0x20000000 /* Descriptor extension (1=Adv) */
+#define E1000_ADVTXD_DCMD_VLE	0x40000000 /* VLAN pkt enable */
+#define E1000_ADVTXD_DCMD_TSE	0x80000000 /* TCP Seg enable */
+#define E1000_ADVTXD_MAC_LINKSEC	0x00040000 /* Apply LinkSec on pkt */
+#define E1000_ADVTXD_MAC_TSTAMP		0x00080000 /* IEEE1588 Timestamp pkt */
+#define E1000_ADVTXD_STAT_SN_CRC	0x00000002 /* NXTSEQ/SEED prsnt in WB */
+#define E1000_ADVTXD_IDX_SHIFT		4  /* Adv desc Index shift */
+#define E1000_ADVTXD_POPTS_ISCO_1ST	0x00000000 /* 1st TSO of iSCSI PDU */
+#define E1000_ADVTXD_POPTS_ISCO_MDL	0x00000800 /* Middle TSO of iSCSI PDU */
+#define E1000_ADVTXD_POPTS_ISCO_LAST	0x00001000 /* Last TSO of iSCSI PDU */
+/* 1st & Last TSO-full iSCSI PDU*/
+#define E1000_ADVTXD_POPTS_ISCO_FULL	0x00001800
+#define E1000_ADVTXD_POPTS_IPSEC	0x00000400 /* IPSec offload request */
+#define E1000_ADVTXD_PAYLEN_SHIFT	14 /* Adv desc PAYLEN shift */
 
 /* Context descriptors */
 struct e1000_adv_tx_context_desc {
@@ -318,65 +320,66 @@
 	__le32 mss_l4len_idx;
 };
 
-#define E1000_ADVTXD_MACLEN_SHIFT    9  /* Adv ctxt desc mac len shift */
-#define E1000_ADVTXD_VLAN_SHIFT     16  /* Adv ctxt vlan tag shift */
-#define E1000_ADVTXD_TUCMD_IPV4    0x00000400  /* IP Packet Type: 1=IPv4 */
-#define E1000_ADVTXD_TUCMD_IPV6    0x00000000  /* IP Packet Type: 0=IPv6 */
-#define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000  /* L4 Packet TYPE of UDP */
-#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800  /* L4 Packet TYPE of TCP */
-#define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000  /* L4 Packet TYPE of SCTP */
-#define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP    0x00002000 /* IPSec Type ESP */
+#define E1000_ADVTXD_MACLEN_SHIFT	9  /* Adv ctxt desc mac len shift */
+#define E1000_ADVTXD_VLAN_SHIFT		16  /* Adv ctxt vlan tag shift */
+#define E1000_ADVTXD_TUCMD_IPV4		0x00000400  /* IP Packet Type: 1=IPv4 */
+#define E1000_ADVTXD_TUCMD_IPV6		0x00000000  /* IP Packet Type: 0=IPv6 */
+#define E1000_ADVTXD_TUCMD_L4T_UDP	0x00000000  /* L4 Packet TYPE of UDP */
+#define E1000_ADVTXD_TUCMD_L4T_TCP	0x00000800  /* L4 Packet TYPE of TCP */
+#define E1000_ADVTXD_TUCMD_L4T_SCTP	0x00001000  /* L4 Packet TYPE of SCTP */
+#define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP	0x00002000 /* IPSec Type ESP */
 /* IPSec Encrypt Enable for ESP */
-#define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN  0x00004000
-#define E1000_ADVTXD_TUCMD_MKRREQ  0x00002000 /* Req requires Markers and CRC */
-#define E1000_ADVTXD_L4LEN_SHIFT     8  /* Adv ctxt L4LEN shift */
-#define E1000_ADVTXD_MSS_SHIFT      16  /* Adv ctxt MSS shift */
+#define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN	0x00004000
+/* Req requires Markers and CRC */
+#define E1000_ADVTXD_TUCMD_MKRREQ	0x00002000
+#define E1000_ADVTXD_L4LEN_SHIFT	8  /* Adv ctxt L4LEN shift */
+#define E1000_ADVTXD_MSS_SHIFT		16  /* Adv ctxt MSS shift */
 /* Adv ctxt IPSec SA IDX mask */
-#define E1000_ADVTXD_IPSEC_SA_INDEX_MASK     0x000000FF
+#define E1000_ADVTXD_IPSEC_SA_INDEX_MASK	0x000000FF
 /* Adv ctxt IPSec ESP len mask */
-#define E1000_ADVTXD_IPSEC_ESP_LEN_MASK      0x000000FF
+#define E1000_ADVTXD_IPSEC_ESP_LEN_MASK		0x000000FF
 
 /* Additional Transmit Descriptor Control definitions */
-#define E1000_TXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Tx Queue */
-#define E1000_TXDCTL_SWFLSH        0x04000000 /* Tx Desc. write-back flushing */
+#define E1000_TXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Tx Queue */
+#define E1000_TXDCTL_SWFLSH		0x04000000 /* Tx Desc. wbk flushing */
 /* Tx Queue Arbitration Priority 0=low, 1=high */
-#define E1000_TXDCTL_PRIORITY      0x08000000
+#define E1000_TXDCTL_PRIORITY		0x08000000
 
 /* Additional Receive Descriptor Control definitions */
-#define E1000_RXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Rx Queue */
-#define E1000_RXDCTL_SWFLSH        0x04000000 /* Rx Desc. write-back flushing */
+#define E1000_RXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Rx Queue */
+#define E1000_RXDCTL_SWFLSH		0x04000000 /* Rx Desc. wbk flushing */
 
 /* Direct Cache Access (DCA) definitions */
-#define E1000_DCA_CTRL_DCA_ENABLE  0x00000000 /* DCA Enable */
-#define E1000_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
+#define E1000_DCA_CTRL_DCA_ENABLE	0x00000000 /* DCA Enable */
+#define E1000_DCA_CTRL_DCA_DISABLE	0x00000001 /* DCA Disable */
 
-#define E1000_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
-#define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
+#define E1000_DCA_CTRL_DCA_MODE_CB1	0x00 /* DCA Mode CB1 */
+#define E1000_DCA_CTRL_DCA_MODE_CB2	0x02 /* DCA Mode CB2 */
 
-#define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
-#define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
-#define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
-#define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
+#define E1000_DCA_RXCTRL_CPUID_MASK	0x0000001F /* Rx CPUID Mask */
+#define E1000_DCA_RXCTRL_DESC_DCA_EN	(1 << 5) /* DCA Rx Desc enable */
+#define E1000_DCA_RXCTRL_HEAD_DCA_EN	(1 << 6) /* DCA Rx Desc header ena */
+#define E1000_DCA_RXCTRL_DATA_DCA_EN	(1 << 7) /* DCA Rx Desc payload ena */
 
-#define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
-#define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
-#define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
+#define E1000_DCA_TXCTRL_CPUID_MASK	0x0000001F /* Tx CPUID Mask */
+#define E1000_DCA_TXCTRL_DESC_DCA_EN	(1 << 5) /* DCA Tx Desc enable */
+#define E1000_DCA_TXCTRL_TX_WB_RO_EN	(1 << 11) /* Tx Desc writeback RO bit */
 
-#define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
-#define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
-#define E1000_DCA_TXCTRL_CPUID_SHIFT_82576 24 /* Tx CPUID */
-#define E1000_DCA_RXCTRL_CPUID_SHIFT_82576 24 /* Rx CPUID */
+#define E1000_DCA_TXCTRL_CPUID_MASK_82576	0xFF000000 /* Tx CPUID Mask */
+#define E1000_DCA_RXCTRL_CPUID_MASK_82576	0xFF000000 /* Rx CPUID Mask */
+#define E1000_DCA_TXCTRL_CPUID_SHIFT_82576	24 /* Tx CPUID */
+#define E1000_DCA_RXCTRL_CPUID_SHIFT_82576	24 /* Rx CPUID */
 
 /* Additional interrupt register bit definitions */
-#define E1000_ICR_LSECPNS       0x00000020          /* PN threshold - server */
-#define E1000_IMS_LSECPNS       E1000_ICR_LSECPNS   /* PN threshold - server */
-#define E1000_ICS_LSECPNS       E1000_ICR_LSECPNS   /* PN threshold - server */
+#define E1000_ICR_LSECPNS	0x00000020 /* PN threshold - server */
+#define E1000_IMS_LSECPNS	E1000_ICR_LSECPNS /* PN threshold - server */
+#define E1000_ICS_LSECPNS	E1000_ICR_LSECPNS /* PN threshold - server */
 
 /* ETQF register bit definitions */
-#define E1000_ETQF_FILTER_ENABLE   (1 << 26)
-#define E1000_ETQF_IMM_INT         (1 << 29)
-#define E1000_ETQF_1588            (1 << 30)
-#define E1000_ETQF_QUEUE_ENABLE    (1 << 31)
+#define E1000_ETQF_FILTER_ENABLE	(1 << 26)
+#define E1000_ETQF_IMM_INT		(1 << 29)
+#define E1000_ETQF_1588			(1 << 30)
+#define E1000_ETQF_QUEUE_ENABLE		(1 << 31)
 /*
  * ETQF filter list: one static filter per filter consumer. This is
  *                   to avoid filter collisions later. Add new filters
@@ -385,87 +388,89 @@
  * Current filters:
  *    EAPOL 802.1x (0x888e): Filter 0
  */
-#define E1000_ETQF_FILTER_EAPOL          0
+#define E1000_ETQF_FILTER_EAPOL		0
 
-#define E1000_FTQF_VF_BP               0x00008000
-#define E1000_FTQF_1588_TIME_STAMP     0x08000000
-#define E1000_FTQF_MASK                0xF0000000
-#define E1000_FTQF_MASK_PROTO_BP       0x10000000
-#define E1000_FTQF_MASK_SOURCE_ADDR_BP 0x20000000
-#define E1000_FTQF_MASK_DEST_ADDR_BP   0x40000000
-#define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000
+#define E1000_FTQF_VF_BP		0x00008000
+#define E1000_FTQF_1588_TIME_STAMP	0x08000000
+#define E1000_FTQF_MASK			0xF0000000
+#define E1000_FTQF_MASK_PROTO_BP	0x10000000
+#define E1000_FTQF_MASK_SOURCE_ADDR_BP	0x20000000
+#define E1000_FTQF_MASK_DEST_ADDR_BP	0x40000000
+#define E1000_FTQF_MASK_SOURCE_PORT_BP	0x80000000
 
-#define E1000_NVM_APME_82575          0x0400
-#define MAX_NUM_VFS                   8
+#define E1000_NVM_APME_82575		0x0400
+#define MAX_NUM_VFS			7
 
-#define E1000_DTXSWC_MAC_SPOOF_MASK   0x000000FF /* Per VF MAC spoof control */
-#define E1000_DTXSWC_VLAN_SPOOF_MASK  0x0000FF00 /* Per VF VLAN spoof control */
-#define E1000_DTXSWC_LLE_MASK         0x00FF0000 /* Per VF Local LB enables */
-#define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8
-#define E1000_DTXSWC_LLE_SHIFT        16
-#define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31)  /* global VF LB enable */
+#define E1000_DTXSWC_MAC_SPOOF_MASK	0x000000FF /* Per VF MAC spoof cntrl */
+#define E1000_DTXSWC_VLAN_SPOOF_MASK	0x0000FF00 /* Per VF VLAN spoof cntrl */
+#define E1000_DTXSWC_LLE_MASK		0x00FF0000 /* Per VF Local LB enables */
+#define E1000_DTXSWC_VLAN_SPOOF_SHIFT	8
+#define E1000_DTXSWC_LLE_SHIFT		16
+#define E1000_DTXSWC_VMDQ_LOOPBACK_EN	(1 << 31)  /* global VF LB enable */
 
 /* Easy defines for setting default pool, would normally be left a zero */
-#define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7
-#define E1000_VT_CTL_DEFAULT_POOL_MASK  (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)
+#define E1000_VT_CTL_DEFAULT_POOL_SHIFT	7
+#define E1000_VT_CTL_DEFAULT_POOL_MASK	(0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)
 
 /* Other useful VMD_CTL register defines */
-#define E1000_VT_CTL_IGNORE_MAC         (1 << 28)
-#define E1000_VT_CTL_DISABLE_DEF_POOL   (1 << 29)
-#define E1000_VT_CTL_VM_REPL_EN         (1 << 30)
+#define E1000_VT_CTL_IGNORE_MAC		(1 << 28)
+#define E1000_VT_CTL_DISABLE_DEF_POOL	(1 << 29)
+#define E1000_VT_CTL_VM_REPL_EN		(1 << 30)
 
 /* Per VM Offload register setup */
-#define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */
-#define E1000_VMOLR_LPE        0x00010000 /* Accept Long packet */
-#define E1000_VMOLR_RSSE       0x00020000 /* Enable RSS */
-#define E1000_VMOLR_AUPE       0x01000000 /* Accept untagged packets */
-#define E1000_VMOLR_ROMPE      0x02000000 /* Accept overflow multicast */
-#define E1000_VMOLR_ROPE       0x04000000 /* Accept overflow unicast */
-#define E1000_VMOLR_BAM        0x08000000 /* Accept Broadcast packets */
-#define E1000_VMOLR_MPME       0x10000000 /* Multicast promiscuous mode */
-#define E1000_VMOLR_STRVLAN    0x40000000 /* Vlan stripping enable */
-#define E1000_VMOLR_STRCRC     0x80000000 /* CRC stripping enable */
+#define E1000_VMOLR_RLPML_MASK	0x00003FFF /* Long Packet Maximum Length mask */
+#define E1000_VMOLR_LPE		0x00010000 /* Accept Long packet */
+#define E1000_VMOLR_RSSE	0x00020000 /* Enable RSS */
+#define E1000_VMOLR_AUPE	0x01000000 /* Accept untagged packets */
+#define E1000_VMOLR_ROMPE	0x02000000 /* Accept overflow multicast */
+#define E1000_VMOLR_ROPE	0x04000000 /* Accept overflow unicast */
+#define E1000_VMOLR_BAM		0x08000000 /* Accept Broadcast packets */
+#define E1000_VMOLR_MPME	0x10000000 /* Multicast promiscuous mode */
+#define E1000_VMOLR_STRVLAN	0x40000000 /* Vlan stripping enable */
+#define E1000_VMOLR_STRCRC	0x80000000 /* CRC stripping enable */
 
-#define E1000_VMOLR_VPE        0x00800000 /* VLAN promiscuous enable */
-#define E1000_VMOLR_UPE        0x20000000 /* Unicast promisuous enable */
-#define E1000_DVMOLR_HIDVLAN   0x20000000 /* Vlan hiding enable */
-#define E1000_DVMOLR_STRVLAN   0x40000000 /* Vlan stripping enable */
-#define E1000_DVMOLR_STRCRC    0x80000000 /* CRC stripping enable */
+#define E1000_VMOLR_VPE		0x00800000 /* VLAN promiscuous enable */
+#define E1000_VMOLR_UPE		0x20000000 /* Unicast promisuous enable */
+#define E1000_DVMOLR_HIDVLAN	0x20000000 /* Vlan hiding enable */
+#define E1000_DVMOLR_STRVLAN	0x40000000 /* Vlan stripping enable */
+#define E1000_DVMOLR_STRCRC	0x80000000 /* CRC stripping enable */
 
-#define E1000_PBRWAC_WALPB     0x00000007 /* Wrap around event on LAN Rx PB */
-#define E1000_PBRWAC_PBE       0x00000008 /* Rx packet buffer empty */
+#define E1000_PBRWAC_WALPB	0x00000007 /* Wrap around event on LAN Rx PB */
+#define E1000_PBRWAC_PBE	0x00000008 /* Rx packet buffer empty */
 
-#define E1000_VLVF_ARRAY_SIZE     32
-#define E1000_VLVF_VLANID_MASK    0x00000FFF
-#define E1000_VLVF_POOLSEL_SHIFT  12
-#define E1000_VLVF_POOLSEL_MASK   (0xFF << E1000_VLVF_POOLSEL_SHIFT)
-#define E1000_VLVF_LVLAN          0x00100000
-#define E1000_VLVF_VLANID_ENABLE  0x80000000
+#define E1000_VLVF_ARRAY_SIZE		32
+#define E1000_VLVF_VLANID_MASK		0x00000FFF
+#define E1000_VLVF_POOLSEL_SHIFT	12
+#define E1000_VLVF_POOLSEL_MASK		(0xFF << E1000_VLVF_POOLSEL_SHIFT)
+#define E1000_VLVF_LVLAN		0x00100000
+#define E1000_VLVF_VLANID_ENABLE	0x80000000
 
-#define E1000_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
-#define E1000_VMVIR_VLANA_NEVER   0x80000000 /* Never insert VLAN tag */
+#define E1000_VMVIR_VLANA_DEFAULT	0x40000000 /* Always use default VLAN */
+#define E1000_VMVIR_VLANA_NEVER		0x80000000 /* Never insert VLAN tag */
 
-#define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
+#define E1000_VF_INIT_TIMEOUT	200 /* Number of retries to clear RSTI */
 
-#define E1000_IOVCTL 0x05BBC
-#define E1000_IOVCTL_REUSE_VFQ 0x00000001
+#define E1000_IOVCTL		0x05BBC
+#define E1000_IOVCTL_REUSE_VFQ	0x00000001
 
-#define E1000_RPLOLR_STRVLAN   0x40000000
-#define E1000_RPLOLR_STRCRC    0x80000000
+#define E1000_RPLOLR_STRVLAN	0x40000000
+#define E1000_RPLOLR_STRCRC	0x80000000
 
-#define E1000_TCTL_EXT_COLD       0x000FFC00
-#define E1000_TCTL_EXT_COLD_SHIFT 10
+#define E1000_TCTL_EXT_COLD	0x000FFC00
+#define E1000_TCTL_EXT_COLD_SHIFT	10
 
-#define E1000_DTXCTL_8023LL     0x0004
-#define E1000_DTXCTL_VLAN_ADDED 0x0008
-#define E1000_DTXCTL_OOS_ENABLE 0x0010
-#define E1000_DTXCTL_MDP_EN     0x0020
-#define E1000_DTXCTL_SPOOF_INT  0x0040
+#define E1000_DTXCTL_8023LL	0x0004
+#define E1000_DTXCTL_VLAN_ADDED	0x0008
+#define E1000_DTXCTL_OOS_ENABLE	0x0010
+#define E1000_DTXCTL_MDP_EN	0x0020
+#define E1000_DTXCTL_SPOOF_INT	0x0040
 
-#define ALL_QUEUES   0xFFFF
+#define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT	(1 << 14)
+
+#define ALL_QUEUES		0xFFFF
 
 /* Rx packet buffer size defines */
-#define E1000_RXPBS_SIZE_MASK_82576  0x0000007F
+#define E1000_RXPBS_SIZE_MASK_82576	0x0000007F
 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable);
 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf);
 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable);
@@ -484,4 +489,23 @@
 s32 e1000_promisc_set_vf(struct e1000_hw *, enum e1000_promisc_type type);
 u16 e1000_rxpbs_adjust_82580(u32 data);
 s32 e1000_set_eee_i350(struct e1000_hw *);
+
+/* I2C SDA and SCL timing parameters for standard mode */
+#define E1000_I2C_T_HD_STA	4
+#define E1000_I2C_T_LOW		5
+#define E1000_I2C_T_HIGH	4
+#define E1000_I2C_T_SU_STA	5
+#define E1000_I2C_T_HD_DATA	5
+#define E1000_I2C_T_SU_DATA	1
+#define E1000_I2C_T_RISE	1
+#define E1000_I2C_T_FALL	1
+#define E1000_I2C_T_SU_STO	4
+#define E1000_I2C_T_BUF		5
+
+s32 e1000_set_i2c_bb(struct e1000_hw *hw);
+s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
+				u8 dev_addr, u8 *data);
+s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
+				 u8 dev_addr, u8 data);
+void e1000_i2c_bus_clear(struct e1000_hw *hw);
 #endif /* _E1000_82575_H_ */
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/e1000/e1000_api.c
--- a/head/sys/dev/e1000/e1000_api.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/e1000/e1000_api.c	Thu Dec 15 12:59:38 2011 +0200
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD: head/sys/dev/e1000/e1000_api.c 228386 2011-12-10 06:55:02Z jfv $*/
 
 #include "e1000_api.h"
 
@@ -277,7 +277,6 @@
 	case E1000_DEV_ID_ICH10_D_BM_LM:
 	case E1000_DEV_ID_ICH10_D_BM_LF:
 	case E1000_DEV_ID_ICH10_D_BM_V:
-	case E1000_DEV_ID_ICH10_HANKSVILLE:
 		mac->type = e1000_ich10lan;
 		break;
 	case E1000_DEV_ID_PCH_D_HV_DM:
@@ -293,7 +292,6 @@
 	case E1000_DEV_ID_82575EB_COPPER:
 	case E1000_DEV_ID_82575EB_FIBER_SERDES:
 	case E1000_DEV_ID_82575GB_QUAD_COPPER:
-	case E1000_DEV_ID_82575GB_QUAD_COPPER_PM:
 		mac->type = e1000_82575;
 		break;
 	case E1000_DEV_ID_82576:
@@ -322,6 +320,7 @@
 	case E1000_DEV_ID_I350_FIBER:
 	case E1000_DEV_ID_I350_SERDES:
 	case E1000_DEV_ID_I350_SGMII:
+	case E1000_DEV_ID_I350_DA4:
 		mac->type = e1000_i350;
 		break;
 	case E1000_DEV_ID_82576_VF:
@@ -343,10 +342,10 @@
  *  e1000_setup_init_funcs - Initializes function pointers
  *  @hw: pointer to the HW structure
  *  @init_device: TRUE will initialize the rest of the function pointers
- *                 getting the device ready for use.  FALSE will only set
- *                 MAC type and the function pointers for the other init
- *                 functions.  Passing FALSE will not generate any hardware
- *                 reads or writes.
+ *		  getting the device ready for use.  FALSE will only set
+ *		  MAC type and the function pointers for the other init
+ *		  functions.  Passing FALSE will not generate any hardware
+ *		  reads or writes.
  *
  *  This function must be called by a driver in order to use the rest
  *  of the 'shared' code files. Called by drivers only.
@@ -518,11 +517,11 @@
  *  The caller must have a packed mc_addr_list of multicast addresses.
  **/
 void e1000_update_mc_addr_list(struct e1000_hw *hw, u8 *mc_addr_list,
-                               u32 mc_addr_count)
+			       u32 mc_addr_count)
 {
 	if (hw->mac.ops.update_mc_addr_list)
 		hw->mac.ops.update_mc_addr_list(hw, mc_addr_list,
-		                                mc_addr_count);
+						mc_addr_count);
 }
 
 /**
@@ -856,12 +855,12 @@
  *  It also does alignment considerations to do the writes in most efficient
  *  way.  Also fills up the sum of the buffer in *buffer parameter.
  **/
-s32 e1000_mng_host_if_write(struct e1000_hw * hw, u8 *buffer, u16 length,
-                            u16 offset, u8 *sum)
+s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length,
+			    u16 offset, u8 *sum)
 {
 	if (hw->mac.ops.mng_host_if_write)
 		return hw->mac.ops.mng_host_if_write(hw, buffer, length,
-		                                     offset, sum);
+						     offset, sum);
 
 	return E1000_NOT_IMPLEMENTED;
 }
@@ -874,7 +873,7 @@
  *  Writes the command header after does the checksum calculation.
  **/
 s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
-                               struct e1000_host_mng_command_header *hdr)
+			       struct e1000_host_mng_command_header *hdr)
 {
 	if (hw->mac.ops.mng_write_cmd_header)
 		return hw->mac.ops.mng_write_cmd_header(hw, hdr);
@@ -892,7 +891,7 @@
  *  and also checks whether the previous command is completed.  It busy waits
  *  in case of previous command is not completed.
  **/
-s32 e1000_mng_enable_host_if(struct e1000_hw * hw)
+s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
 {
 	if (hw->mac.ops.mng_enable_host_if)
 		return hw->mac.ops.mng_enable_host_if(hw);
@@ -1277,7 +1276,7 @@
  *  This is a function pointer entry point called by drivers.
  **/
 s32 e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, u32 offset,
-                              u8 data)
+			      u8 data)
 {
 	return e1000_write_8bit_ctrl_reg_generic(hw, reg, offset, data);
 }
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/e1000/e1000_api.h
--- a/head/sys/dev/e1000/e1000_api.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/e1000/e1000_api.h	Thu Dec 15 12:59:38 2011 +0200
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,97 +30,94 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD: head/sys/dev/e1000/e1000_api.h 228386 2011-12-10 06:55:02Z jfv $*/
 
 #ifndef _E1000_API_H_
 #define _E1000_API_H_
 
 #include "e1000_hw.h"
 
-extern void    e1000_init_function_pointers_82542(struct e1000_hw *hw);
-extern void    e1000_init_function_pointers_82543(struct e1000_hw *hw);
-extern void    e1000_init_function_pointers_82540(struct e1000_hw *hw);
-extern void    e1000_init_function_pointers_82571(struct e1000_hw *hw);
-extern void    e1000_init_function_pointers_82541(struct e1000_hw *hw);
-extern void    e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw);
-extern void    e1000_init_function_pointers_ich8lan(struct e1000_hw *hw);
-extern void    e1000_init_function_pointers_82575(struct e1000_hw *hw);
-extern void    e1000_rx_fifo_flush_82575(struct e1000_hw *hw);
-extern void    e1000_init_function_pointers_vf(struct e1000_hw *hw);
-extern void    e1000_power_up_fiber_serdes_link(struct e1000_hw *hw);
-extern void    e1000_shutdown_fiber_serdes_link(struct e1000_hw *hw);
+extern void e1000_init_function_pointers_82542(struct e1000_hw *hw);
+extern void e1000_init_function_pointers_82543(struct e1000_hw *hw);
+extern void e1000_init_function_pointers_82540(struct e1000_hw *hw);
+extern void e1000_init_function_pointers_82571(struct e1000_hw *hw);
+extern void e1000_init_function_pointers_82541(struct e1000_hw *hw);
+extern void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw);
+extern void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw);
+extern void e1000_init_function_pointers_82575(struct e1000_hw *hw);
+extern void e1000_rx_fifo_flush_82575(struct e1000_hw *hw);
+extern void e1000_init_function_pointers_vf(struct e1000_hw *hw);
+extern void e1000_power_up_fiber_serdes_link(struct e1000_hw *hw);
+extern void e1000_shutdown_fiber_serdes_link(struct e1000_hw *hw);
 
-s32  e1000_set_mac_type(struct e1000_hw *hw);
-s32  e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device);
-s32  e1000_init_mac_params(struct e1000_hw *hw);
-s32  e1000_init_nvm_params(struct e1000_hw *hw);
-s32  e1000_init_phy_params(struct e1000_hw *hw);
-s32  e1000_init_mbx_params(struct e1000_hw *hw);
-s32  e1000_get_bus_info(struct e1000_hw *hw);
+s32 e1000_set_mac_type(struct e1000_hw *hw);
+s32 e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device);
+s32 e1000_init_mac_params(struct e1000_hw *hw);
+s32 e1000_init_nvm_params(struct e1000_hw *hw);
+s32 e1000_init_phy_params(struct e1000_hw *hw);
+s32 e1000_init_mbx_params(struct e1000_hw *hw);
+s32 e1000_get_bus_info(struct e1000_hw *hw);
 void e1000_clear_vfta(struct e1000_hw *hw);
 void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value);
-s32  e1000_force_mac_fc(struct e1000_hw *hw);
-s32  e1000_check_for_link(struct e1000_hw *hw);
-s32  e1000_reset_hw(struct e1000_hw *hw);
-s32  e1000_init_hw(struct e1000_hw *hw);
-s32  e1000_setup_link(struct e1000_hw *hw);
-s32  e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed,
-                                u16 *duplex);
-s32  e1000_disable_pcie_master(struct e1000_hw *hw);
+s32 e1000_force_mac_fc(struct e1000_hw *hw);
+s32 e1000_check_for_link(struct e1000_hw *hw);
+s32 e1000_reset_hw(struct e1000_hw *hw);
+s32 e1000_init_hw(struct e1000_hw *hw);
+s32 e1000_setup_link(struct e1000_hw *hw);
+s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex);
+s32 e1000_disable_pcie_master(struct e1000_hw *hw);
 void e1000_config_collision_dist(struct e1000_hw *hw);
 void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);
-u32  e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr);
-void e1000_update_mc_addr_list(struct e1000_hw *hw,
-                               u8 *mc_addr_list, u32 mc_addr_count);
-s32  e1000_setup_led(struct e1000_hw *hw);
-s32  e1000_cleanup_led(struct e1000_hw *hw);
-s32  e1000_check_reset_block(struct e1000_hw *hw);
-s32  e1000_blink_led(struct e1000_hw *hw);
-s32  e1000_led_on(struct e1000_hw *hw);
-s32  e1000_led_off(struct e1000_hw *hw);
+u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr);
+void e1000_update_mc_addr_list(struct e1000_hw *hw, u8 *mc_addr_list,
+			       u32 mc_addr_count);
+s32 e1000_setup_led(struct e1000_hw *hw);
+s32 e1000_cleanup_led(struct e1000_hw *hw);
+s32 e1000_check_reset_block(struct e1000_hw *hw);
+s32 e1000_blink_led(struct e1000_hw *hw);
+s32 e1000_led_on(struct e1000_hw *hw);
+s32 e1000_led_off(struct e1000_hw *hw);
 s32 e1000_id_led_init(struct e1000_hw *hw);
 void e1000_reset_adaptive(struct e1000_hw *hw);
 void e1000_update_adaptive(struct e1000_hw *hw);
-s32  e1000_get_cable_length(struct e1000_hw *hw);
-s32  e1000_validate_mdi_setting(struct e1000_hw *hw);
-s32  e1000_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data);
-s32  e1000_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data);
-s32  e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg,
-                               u32 offset, u8 data);
-s32  e1000_get_phy_info(struct e1000_hw *hw);
+s32 e1000_get_cable_length(struct e1000_hw *hw);
+s32 e1000_validate_mdi_setting(struct e1000_hw *hw);
+s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data);
+s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data);
+s32 e1000_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, u32 offset,
+			      u8 data);
+s32 e1000_get_phy_info(struct e1000_hw *hw);
 void e1000_release_phy(struct e1000_hw *hw);
-s32  e1000_acquire_phy(struct e1000_hw *hw);
-s32  e1000_cfg_on_link_up(struct e1000_hw *hw);
-s32  e1000_phy_hw_reset(struct e1000_hw *hw);
-s32  e1000_phy_commit(struct e1000_hw *hw);
+s32 e1000_acquire_phy(struct e1000_hw *hw);
+s32 e1000_cfg_on_link_up(struct e1000_hw *hw);
+s32 e1000_phy_hw_reset(struct e1000_hw *hw);
+s32 e1000_phy_commit(struct e1000_hw *hw);
 void e1000_power_up_phy(struct e1000_hw *hw);
 void e1000_power_down_phy(struct e1000_hw *hw);
-s32  e1000_read_mac_addr(struct e1000_hw *hw);
-s32  e1000_read_pba_string(struct e1000_hw *hw, u8 *pba_num, 
-                           u32 pba_num_size);
-s32  e1000_read_pba_length(struct e1000_hw *hw, u32 *pba_num_size);
+s32 e1000_read_mac_addr(struct e1000_hw *hw);
+s32 e1000_read_pba_string(struct e1000_hw *hw, u8 *pba_num, u32 pba_num_size);
+s32 e1000_read_pba_length(struct e1000_hw *hw, u32 *pba_num_size);
 void e1000_reload_nvm(struct e1000_hw *hw);
-s32  e1000_update_nvm_checksum(struct e1000_hw *hw);
-s32  e1000_validate_nvm_checksum(struct e1000_hw *hw);
-s32  e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
-s32  e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
-s32  e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
-s32  e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words,
-                     u16 *data);
-s32  e1000_wait_autoneg(struct e1000_hw *hw);
-s32  e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
-s32  e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
+s32 e1000_update_nvm_checksum(struct e1000_hw *hw);
+s32 e1000_validate_nvm_checksum(struct e1000_hw *hw);
+s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
+s32 e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
+s32 e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
+s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
+s32 e1000_wait_autoneg(struct e1000_hw *hw);
+s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
+s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
 bool e1000_check_mng_mode(struct e1000_hw *hw);
 bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw);
-s32  e1000_mng_enable_host_if(struct e1000_hw *hw);
-s32  e1000_mng_host_if_write(struct e1000_hw *hw,
-                             u8 *buffer, u16 length, u16 offset, u8 *sum);
-s32  e1000_mng_write_cmd_header(struct e1000_hw *hw,
-                                struct e1000_host_mng_command_header *hdr);
-s32  e1000_mng_write_dhcp_info(struct e1000_hw * hw,
-                                    u8 *buffer, u16 length);
+s32 e1000_mng_enable_host_if(struct e1000_hw *hw);
+s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length,
+			    u16 offset, u8 *sum);
+s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
+			       struct e1000_host_mng_command_header *hdr);
+s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length);
 u32  e1000_translate_register_82542(u32 reg);
 
+
 /*
  * TBI_ACCEPT macro definition:
  *
@@ -152,14 +149,15 @@
 /* The carrier extension symbol, as received by the NIC. */
 #define CARRIER_EXTENSION   0x0F
 
-#define TBI_ACCEPT(a, status, errors, length, last_byte, min_frame_size, max_frame_size) \
-    (e1000_tbi_sbp_enabled_82543(a) && \
-     (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
-     ((last_byte) == CARRIER_EXTENSION) && \
-     (((status) & E1000_RXD_STAT_VP) ? \
-          (((length) > (min_frame_size - VLAN_TAG_SIZE)) && \
-           ((length) <= (max_frame_size + 1))) : \
-          (((length) > min_frame_size) && \
-           ((length) <= (max_frame_size + VLAN_TAG_SIZE + 1)))))
+#define TBI_ACCEPT(a, status, errors, length, last_byte, \
+		   min_frame_size, max_frame_size) \
+	(e1000_tbi_sbp_enabled_82543(a) && \
+	 (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
+	 ((last_byte) == CARRIER_EXTENSION) && \
+	 (((status) & E1000_RXD_STAT_VP) ? \
+	  (((length) > (min_frame_size - VLAN_TAG_SIZE)) && \
+	  ((length) <= (max_frame_size + 1))) : \
+	  (((length) > min_frame_size) && \
+	  ((length) <= (max_frame_size + VLAN_TAG_SIZE + 1)))))
 
 #endif
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/e1000/e1000_defines.h
--- a/head/sys/dev/e1000/e1000_defines.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/e1000/e1000_defines.h	Thu Dec 15 12:59:38 2011 +0200
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD: head/sys/dev/e1000/e1000_defines.h 228386 2011-12-10 06:55:02Z jfv $*/
 
 #ifndef _E1000_DEFINES_H_
 #define _E1000_DEFINES_H_
@@ -41,815 +41,826 @@
 
 /* Definitions for power management and wakeup registers */
 /* Wake Up Control */
-#define E1000_WUC_APME       0x00000001 /* APM Enable */
-#define E1000_WUC_PME_EN     0x00000002 /* PME Enable */
-#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
-#define E1000_WUC_APMPME     0x00000008 /* Assert PME on APM Wakeup */
-#define E1000_WUC_LSCWE      0x00000010 /* Link Status wake up enable */
-#define E1000_WUC_PPROXYE    0x00000010 /* Protocol Proxy Enable */
-#define E1000_WUC_LSCWO      0x00000020 /* Link Status wake up override */
-#define E1000_WUC_SPM        0x80000000 /* Enable SPM */
-#define E1000_WUC_PHY_WAKE   0x00000100 /* if PHY supports wakeup */
-#define E1000_WUC_FLX6_PHY  0x4000 /* Flexible Filter 6 Enable */
-#define E1000_WUC_FLX7_PHY  0x8000 /* Flexible Filter 7 Enable */
+#define E1000_WUC_APME		0x00000001 /* APM Enable */
+#define E1000_WUC_PME_EN	0x00000002 /* PME Enable */
+#define E1000_WUC_PME_STATUS	0x00000004 /* PME Status */
+#define E1000_WUC_APMPME	0x00000008 /* Assert PME on APM Wakeup */
+#define E1000_WUC_LSCWE		0x00000010 /* Link Status wake up enable */
+#define E1000_WUC_PPROXYE	0x00000010 /* Protocol Proxy Enable */
+#define E1000_WUC_LSCWO		0x00000020 /* Link Status wake up override */
+#define E1000_WUC_SPM		0x80000000 /* Enable SPM */
+#define E1000_WUC_PHY_WAKE	0x00000100 /* if PHY supports wakeup */
+#define E1000_WUC_FLX6_PHY	0x4000 /* Flexible Filter 6 Enable */
+#define E1000_WUC_FLX7_PHY	0x8000 /* Flexible Filter 7 Enable */
 
 /* Wake Up Filter Control */
-#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
-#define E1000_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
-#define E1000_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
-#define E1000_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
-#define E1000_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
-#define E1000_WUFC_ARP  0x00000020 /* ARP Request Packet Wakeup Enable */
-#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
-#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
+#define E1000_WUFC_LNKC	0x00000001 /* Link Status Change Wakeup Enable */
+#define E1000_WUFC_MAG	0x00000002 /* Magic Packet Wakeup Enable */
+#define E1000_WUFC_EX	0x00000004 /* Directed Exact Wakeup Enable */
+#define E1000_WUFC_MC	0x00000008 /* Directed Multicast Wakeup Enable */
+#define E1000_WUFC_BC	0x00000010 /* Broadcast Wakeup Enable */
+#define E1000_WUFC_ARP	0x00000020 /* ARP Request Packet Wakeup Enable */
+#define E1000_WUFC_IPV4	0x00000040 /* Directed IPv4 Packet Wakeup Enable */
+#define E1000_WUFC_IPV6	0x00000080 /* Directed IPv6 Packet Wakeup Enable */
 #define E1000_WUFC_IGNORE_TCO_PHY 0x00000800 /* Ignore WakeOn TCO packets */
-#define E1000_WUFC_FLX0_PHY      0x00001000 /* Flexible Filter 0 Enable */
-#define E1000_WUFC_FLX1_PHY      0x00002000 /* Flexible Filter 1 Enable */
-#define E1000_WUFC_FLX2_PHY      0x00004000 /* Flexible Filter 2 Enable */
-#define E1000_WUFC_FLX3_PHY      0x00008000 /* Flexible Filter 3 Enable */
-#define E1000_WUFC_FLX4_PHY      0x00000200 /* Flexible Filter 4 Enable */
-#define E1000_WUFC_FLX5_PHY      0x00000400 /* Flexible Filter 5 Enable */
-#define E1000_WUFC_IGNORE_TCO   0x00008000 /* Ignore WakeOn TCO packets */
-#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
-#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
-#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
-#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
-#define E1000_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
-#define E1000_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
-#define E1000_WUFC_FLX6 0x00400000 /* Flexible Filter 6 Enable */
-#define E1000_WUFC_FLX7 0x00800000 /* Flexible Filter 7 Enable */
-#define E1000_WUFC_FW_RST 0x80000000 /* Wake on FW Reset Enable */
-#define E1000_WUFC_ALL_FILTERS_PHY_4 0x0000F0FF /*Mask for all wakeup filters*/
-#define E1000_WUFC_FLX_OFFSET_PHY 12 /* Offset to the Flexible Filters bits */
-#define E1000_WUFC_FLX_FILTERS_PHY_4 0x0000F000 /*Mask for 4 flexible filters*/
-#define E1000_WUFC_ALL_FILTERS_PHY_6 0x0000F6FF /*Mask for 6 wakeup filters */
-#define E1000_WUFC_FLX_FILTERS_PHY_6 0x0000F600 /*Mask for 6 flexible filters*/
-#define E1000_WUFC_ALL_FILTERS  0x000F00FF /* Mask for all wakeup filters */
-#define E1000_WUFC_ALL_FILTERS_6  0x003F00FF /* Mask for all 6 wakeup filters*/
-#define E1000_WUFC_ALL_FILTERS_8  0x00FF00FF /* Mask for all 8 wakeup filters*/
-#define E1000_WUFC_FLX_OFFSET   16 /* Offset to the Flexible Filters bits */
-#define E1000_WUFC_FLX_FILTERS  0x000F0000 /*Mask for the 4 flexible filters */
-#define E1000_WUFC_FLX_FILTERS_6  0x003F0000 /* Mask for 6 flexible filters */
-#define E1000_WUFC_FLX_FILTERS_8  0x00FF0000 /* Mask for 8 flexible filters */
+#define E1000_WUFC_FLX0_PHY	0x00001000 /* Flexible Filter 0 Enable */
+#define E1000_WUFC_FLX1_PHY	0x00002000 /* Flexible Filter 1 Enable */
+#define E1000_WUFC_FLX2_PHY	0x00004000 /* Flexible Filter 2 Enable */
+#define E1000_WUFC_FLX3_PHY	0x00008000 /* Flexible Filter 3 Enable */
+#define E1000_WUFC_FLX4_PHY	0x00000200 /* Flexible Filter 4 Enable */
+#define E1000_WUFC_FLX5_PHY	0x00000400 /* Flexible Filter 5 Enable */
+#define E1000_WUFC_IGNORE_TCO	0x00008000 /* Ignore WakeOn TCO packets */
+#define E1000_WUFC_FLX0		0x00010000 /* Flexible Filter 0 Enable */
+#define E1000_WUFC_FLX1		0x00020000 /* Flexible Filter 1 Enable */
+#define E1000_WUFC_FLX2		0x00040000 /* Flexible Filter 2 Enable */
+#define E1000_WUFC_FLX3		0x00080000 /* Flexible Filter 3 Enable */
+#define E1000_WUFC_FLX4		0x00100000 /* Flexible Filter 4 Enable */
+#define E1000_WUFC_FLX5		0x00200000 /* Flexible Filter 5 Enable */
+#define E1000_WUFC_FLX6		0x00400000 /* Flexible Filter 6 Enable */
+#define E1000_WUFC_FLX7		0x00800000 /* Flexible Filter 7 Enable */
+#define E1000_WUFC_FW_RST	0x80000000 /* Wake on FW Reset Enable */
+#define E1000_WUFC_ALL_FILTERS_PHY_4	0x0000F0FF /* wakeup filters mask */
+#define E1000_WUFC_FLX_OFFSET_PHY	12 /* Flexible Filters bits offset */
+#define E1000_WUFC_FLX_FILTERS_PHY_4	0x0000F000 /* 4 flexible filters mask */
+#define E1000_WUFC_ALL_FILTERS_PHY_6	0x0000F6FF /* 6 wakeup filters mask */
+#define E1000_WUFC_FLX_FILTERS_PHY_6	0x0000F600 /* 6 flexible filters mask */
+#define E1000_WUFC_ALL_FILTERS		0x000F00FF /* all wakeup filters mask */
+#define E1000_WUFC_ALL_FILTERS_6	0x003F00FF /* Mask all 6 wu filters */
+#define E1000_WUFC_ALL_FILTERS_8	0x00FF00FF /* Mask all 8 wu filters */
+#define E1000_WUFC_FLX_OFFSET		16 /* Flexible Filters bits offset */
+#define E1000_WUFC_FLX_FILTERS		0x000F0000 /* 4 flexible filters mask */
+#define E1000_WUFC_FLX_FILTERS_6	0x003F0000 /* 6 flexible filters mask */
+#define E1000_WUFC_FLX_FILTERS_8	0x00FF0000 /* 8 flexible filters mask */
 /*
  * For 82576 to utilize Extended filter masks in addition to
  * existing (filter) masks
  */
-#define E1000_WUFC_EXT_FLX_FILTERS      0x00300000 /* Ext. FLX filter mask */
+#define E1000_WUFC_EXT_FLX_FILTERS	0x00300000 /* Ext. FLX filter mask */
 
 /* Wake Up Status */
-#define E1000_WUS_LNKC         E1000_WUFC_LNKC
-#define E1000_WUS_MAG          E1000_WUFC_MAG
-#define E1000_WUS_EX           E1000_WUFC_EX
-#define E1000_WUS_MC           E1000_WUFC_MC
-#define E1000_WUS_BC           E1000_WUFC_BC
-#define E1000_WUS_ARP          E1000_WUFC_ARP
-#define E1000_WUS_IPV4         E1000_WUFC_IPV4
-#define E1000_WUS_IPV6         E1000_WUFC_IPV6
-#define E1000_WUS_FLX0_PHY      E1000_WUFC_FLX0_PHY
-#define E1000_WUS_FLX1_PHY      E1000_WUFC_FLX1_PHY
-#define E1000_WUS_FLX2_PHY      E1000_WUFC_FLX2_PHY
-#define E1000_WUS_FLX3_PHY      E1000_WUFC_FLX3_PHY
-#define E1000_WUS_FLX_FILTERS_PHY_4        E1000_WUFC_FLX_FILTERS_PHY_4
-#define E1000_WUS_FLX0         E1000_WUFC_FLX0
-#define E1000_WUS_FLX1         E1000_WUFC_FLX1
-#define E1000_WUS_FLX2         E1000_WUFC_FLX2
-#define E1000_WUS_FLX3         E1000_WUFC_FLX3
-#define E1000_WUS_FLX4         E1000_WUFC_FLX4
-#define E1000_WUS_FLX5         E1000_WUFC_FLX5
-#define E1000_WUS_FLX6         E1000_WUFC_FLX6
-#define E1000_WUS_FLX7         E1000_WUFC_FLX7
-#define E1000_WUS_FLX4_PHY         E1000_WUFC_FLX4_PHY
-#define E1000_WUS_FLX5_PHY         E1000_WUFC_FLX5_PHY
-#define E1000_WUS_FLX6_PHY         0x0400
-#define E1000_WUS_FLX7_PHY         0x0800
-#define E1000_WUS_FLX_FILTERS  E1000_WUFC_FLX_FILTERS
-#define E1000_WUS_FLX_FILTERS_6  E1000_WUFC_FLX_FILTERS_6
-#define E1000_WUS_FLX_FILTERS_8  E1000_WUFC_FLX_FILTERS_8
-#define E1000_WUS_FLX_FILTERS_PHY_6  E1000_WUFC_FLX_FILTERS_PHY_6
+#define E1000_WUS_LNKC		E1000_WUFC_LNKC
+#define E1000_WUS_MAG		E1000_WUFC_MAG
+#define E1000_WUS_EX		E1000_WUFC_EX
+#define E1000_WUS_MC		E1000_WUFC_MC
+#define E1000_WUS_BC		E1000_WUFC_BC
+#define E1000_WUS_ARP		E1000_WUFC_ARP
+#define E1000_WUS_IPV4		E1000_WUFC_IPV4
+#define E1000_WUS_IPV6		E1000_WUFC_IPV6
+#define E1000_WUS_FLX0_PHY	E1000_WUFC_FLX0_PHY
+#define E1000_WUS_FLX1_PHY	E1000_WUFC_FLX1_PHY
+#define E1000_WUS_FLX2_PHY	E1000_WUFC_FLX2_PHY
+#define E1000_WUS_FLX3_PHY	E1000_WUFC_FLX3_PHY
+#define E1000_WUS_FLX_FILTERS_PHY_4	E1000_WUFC_FLX_FILTERS_PHY_4
+#define E1000_WUS_FLX0		E1000_WUFC_FLX0
+#define E1000_WUS_FLX1		E1000_WUFC_FLX1
+#define E1000_WUS_FLX2		E1000_WUFC_FLX2
+#define E1000_WUS_FLX3		E1000_WUFC_FLX3
+#define E1000_WUS_FLX4		E1000_WUFC_FLX4
+#define E1000_WUS_FLX5		E1000_WUFC_FLX5
+#define E1000_WUS_FLX6		E1000_WUFC_FLX6
+#define E1000_WUS_FLX7		E1000_WUFC_FLX7
+#define E1000_WUS_FLX4_PHY	E1000_WUFC_FLX4_PHY
+#define E1000_WUS_FLX5_PHY	E1000_WUFC_FLX5_PHY
+#define E1000_WUS_FLX6_PHY	0x0400
+#define E1000_WUS_FLX7_PHY	0x0800
+#define E1000_WUS_FLX_FILTERS	E1000_WUFC_FLX_FILTERS
+#define E1000_WUS_FLX_FILTERS_6		E1000_WUFC_FLX_FILTERS_6
+#define E1000_WUS_FLX_FILTERS_8		E1000_WUFC_FLX_FILTERS_8
+#define E1000_WUS_FLX_FILTERS_PHY_6	E1000_WUFC_FLX_FILTERS_PHY_6
 
 /* Wake Up Packet Length */
-#define E1000_WUPL_LENGTH_MASK 0x0FFF   /* Only the lower 12 bits are valid */
+#define E1000_WUPL_LENGTH_MASK	0x0FFF   /* Only the lower 12 bits are valid */
 
 /* Four Flexible Filters are supported */
-#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
+#define E1000_FLEXIBLE_FILTER_COUNT_MAX		4
 /* Six Flexible Filters are supported */
-#define E1000_FLEXIBLE_FILTER_COUNT_MAX_6   6
+#define E1000_FLEXIBLE_FILTER_COUNT_MAX_6	6
 /* Eight Flexible Filters are supported */
-#define E1000_FLEXIBLE_FILTER_COUNT_MAX_8   8
+#define E1000_FLEXIBLE_FILTER_COUNT_MAX_8	8
 /* Two Extended Flexible Filters are supported (82576) */
-#define E1000_EXT_FLEXIBLE_FILTER_COUNT_MAX     2
-#define E1000_FHFT_LENGTH_OFFSET        0xFC /* Length byte in FHFT */
-#define E1000_FHFT_LENGTH_MASK          0x0FF /* Length in lower byte */
+#define E1000_EXT_FLEXIBLE_FILTER_COUNT_MAX	2
+#define E1000_FHFT_LENGTH_OFFSET	0xFC /* Length byte in FHFT */
+#define E1000_FHFT_LENGTH_MASK		0x0FF /* Length in lower byte */
 
 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
-#define E1000_FLEXIBLE_FILTER_SIZE_MAX  128
+#define E1000_FLEXIBLE_FILTER_SIZE_MAX	128
 
-#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
-#define E1000_FFLT_SIZE_6 E1000_FLEXIBLE_FILTER_COUNT_MAX_6
-#define E1000_FFLT_SIZE_8 E1000_FLEXIBLE_FILTER_COUNT_MAX_8
-#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
-#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
+#define E1000_FFLT_SIZE		E1000_FLEXIBLE_FILTER_COUNT_MAX
+#define E1000_FFLT_SIZE_6	E1000_FLEXIBLE_FILTER_COUNT_MAX_6
+#define E1000_FFLT_SIZE_8	E1000_FLEXIBLE_FILTER_COUNT_MAX_8
+#define E1000_FFMT_SIZE		E1000_FLEXIBLE_FILTER_SIZE_MAX
+#define E1000_FFVT_SIZE		E1000_FLEXIBLE_FILTER_SIZE_MAX
 
 /* Extended Device Control */
-#define E1000_CTRL_EXT_GPI0_EN   0x00000001 /* Maps SDP4 to GPI0 */
-#define E1000_CTRL_EXT_GPI1_EN   0x00000002 /* Maps SDP5 to GPI1 */
-#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
-#define E1000_CTRL_EXT_GPI2_EN   0x00000004 /* Maps SDP6 to GPI2 */
-#define E1000_CTRL_EXT_GPI3_EN   0x00000008 /* Maps SDP7 to GPI3 */
+#define E1000_CTRL_EXT_GPI0_EN		0x00000001 /* Maps SDP4 to GPI0 */
+#define E1000_CTRL_EXT_GPI1_EN		0x00000002 /* Maps SDP5 to GPI1 */
+#define E1000_CTRL_EXT_PHYINT_EN	E1000_CTRL_EXT_GPI1_EN
+#define E1000_CTRL_EXT_GPI2_EN		0x00000004 /* Maps SDP6 to GPI2 */
+#define E1000_CTRL_EXT_GPI3_EN		0x00000008 /* Maps SDP7 to GPI3 */
 /* Reserved (bits 4,5) in >= 82575 */
-#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Definable Pin 4 */
-#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Definable Pin 5 */
-#define E1000_CTRL_EXT_PHY_INT   E1000_CTRL_EXT_SDP5_DATA
-#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Definable Pin 6 */
-#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */
+#define E1000_CTRL_EXT_SDP4_DATA	0x00000010 /* SW Definable Pin 4 data */
+#define E1000_CTRL_EXT_SDP5_DATA	0x00000020 /* SW Definable Pin 5 data */
+#define E1000_CTRL_EXT_PHY_INT		E1000_CTRL_EXT_SDP5_DATA
+#define E1000_CTRL_EXT_SDP6_DATA	0x00000040 /* SW Definable Pin 6 data */
+#define E1000_CTRL_EXT_SDP3_DATA	0x00000080 /* SW Definable Pin 3 data */
 /* SDP 4/5 (bits 8,9) are reserved in >= 82575 */
-#define E1000_CTRL_EXT_SDP4_DIR  0x00000100 /* Direction of SDP4 0=in 1=out */
-#define E1000_CTRL_EXT_SDP5_DIR  0x00000200 /* Direction of SDP5 0=in 1=out */
-#define E1000_CTRL_EXT_SDP6_DIR  0x00000400 /* Direction of SDP6 0=in 1=out */
-#define E1000_CTRL_EXT_SDP3_DIR  0x00000800 /* Direction of SDP3 0=in 1=out */
-#define E1000_CTRL_EXT_ASDCHK    0x00001000 /* Initiate an ASD sequence */
-#define E1000_CTRL_EXT_EE_RST    0x00002000 /* Reinitialize from EEPROM */
-#define E1000_CTRL_EXT_IPS       0x00004000 /* Invert Power State */
+#define E1000_CTRL_EXT_SDP4_DIR	0x00000100 /* Direction of SDP4 0=in 1=out */
+#define E1000_CTRL_EXT_SDP5_DIR	0x00000200 /* Direction of SDP5 0=in 1=out */
+#define E1000_CTRL_EXT_SDP6_DIR	0x00000400 /* Direction of SDP6 0=in 1=out */
+#define E1000_CTRL_EXT_SDP3_DIR	0x00000800 /* Direction of SDP3 0=in 1=out */
+#define E1000_CTRL_EXT_ASDCHK	0x00001000 /* Initiate an ASD sequence */
+#define E1000_CTRL_EXT_EE_RST	0x00002000 /* Reinitialize from EEPROM */
+#define E1000_CTRL_EXT_IPS	0x00004000 /* Invert Power State */
 /* Physical Func Reset Done Indication */
-#define E1000_CTRL_EXT_PFRSTD    0x00004000
-#define E1000_CTRL_EXT_SPD_BYPS  0x00008000 /* Speed Select Bypass */
-#define E1000_CTRL_EXT_RO_DIS    0x00020000 /* Relaxed Ordering disable */
-#define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */
-#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
-#define E1000_CTRL_EXT_LINK_MODE_82580_MASK 0x01C00000 /*82580 bit 24:22*/
-#define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX  0x00400000
-#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
-#define E1000_CTRL_EXT_LINK_MODE_TBI  0x00C00000
-#define E1000_CTRL_EXT_LINK_MODE_KMRN    0x00000000
-#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES  0x00C00000
-#define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES  0x00800000
-#define E1000_CTRL_EXT_LINK_MODE_SGMII   0x00800000
-#define E1000_CTRL_EXT_EIAME          0x01000000
-#define E1000_CTRL_EXT_IRCA           0x00000001
-#define E1000_CTRL_EXT_WR_WMARK_MASK  0x03000000
-#define E1000_CTRL_EXT_WR_WMARK_256   0x00000000
-#define E1000_CTRL_EXT_WR_WMARK_320   0x01000000
-#define E1000_CTRL_EXT_WR_WMARK_384   0x02000000
-#define E1000_CTRL_EXT_WR_WMARK_448   0x03000000
-#define E1000_CTRL_EXT_CANC           0x04000000 /* Int delay cancellation */
-#define E1000_CTRL_EXT_DRV_LOAD       0x10000000 /* Driver loaded bit for FW */
+#define E1000_CTRL_EXT_PFRSTD	0x00004000
+#define E1000_CTRL_EXT_SPD_BYPS	0x00008000 /* Speed Select Bypass */
+#define E1000_CTRL_EXT_RO_DIS	0x00020000 /* Relaxed Ordering disable */
+#define E1000_CTRL_EXT_DMA_DYN_CLK_EN	0x00080000 /* DMA Dynamic Clk Gating */
+#define E1000_CTRL_EXT_LINK_MODE_MASK	0x00C00000
+/* Offset of the link mode field in Ctrl Ext register */
+#define E1000_CTRL_EXT_LINK_MODE_OFFSET	22
+#define E1000_CTRL_EXT_LINK_MODE_82580_MASK	0x01C00000 /*82580 bit 24:22*/
+#define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX	0x00400000
+#define E1000_CTRL_EXT_LINK_MODE_GMII	0x00000000
+#define E1000_CTRL_EXT_LINK_MODE_TBI	0x00C00000
+#define E1000_CTRL_EXT_LINK_MODE_KMRN	0x00000000
+#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES	0x00C00000
+#define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES	0x00800000
+#define E1000_CTRL_EXT_LINK_MODE_SGMII	0x00800000
+#define E1000_CTRL_EXT_EIAME		0x01000000
+#define E1000_CTRL_EXT_IRCA		0x00000001
+#define E1000_CTRL_EXT_WR_WMARK_MASK	0x03000000
+#define E1000_CTRL_EXT_WR_WMARK_256	0x00000000
+#define E1000_CTRL_EXT_WR_WMARK_320	0x01000000
+#define E1000_CTRL_EXT_WR_WMARK_384	0x02000000
+#define E1000_CTRL_EXT_WR_WMARK_448	0x03000000
+#define E1000_CTRL_EXT_CANC		0x04000000 /* Int delay cancellation */
+#define E1000_CTRL_EXT_DRV_LOAD		0x10000000 /* Drv loaded bit for FW */
 /* IAME enable bit (27) was removed in >= 82575 */
-#define E1000_CTRL_EXT_IAME          0x08000000 /* Int acknowledge Auto-mask */
-#define E1000_CRTL_EXT_PB_PAREN       0x01000000 /* packet buffer parity error
-                                                  * detection enabled */
-#define E1000_CTRL_EXT_DF_PAREN       0x02000000 /* descriptor FIFO parity
-                                                  * error detection enable */
-#define E1000_CTRL_EXT_GHOST_PAREN    0x40000000
-#define E1000_CTRL_EXT_PBA_CLR        0x80000000 /* PBA Clear */
-#define E1000_CTRL_EXT_LSECCK         0x00001000
-#define E1000_CTRL_EXT_PHYPDEN        0x00100000
-#define E1000_I2CCMD_REG_ADDR_SHIFT   16
-#define E1000_I2CCMD_REG_ADDR         0x00FF0000
-#define E1000_I2CCMD_PHY_ADDR_SHIFT   24
-#define E1000_I2CCMD_PHY_ADDR         0x07000000
-#define E1000_I2CCMD_OPCODE_READ      0x08000000
-#define E1000_I2CCMD_OPCODE_WRITE     0x00000000
-#define E1000_I2CCMD_RESET            0x10000000
-#define E1000_I2CCMD_READY            0x20000000
-#define E1000_I2CCMD_INTERRUPT_ENA    0x40000000
-#define E1000_I2CCMD_ERROR            0x80000000
-#define E1000_MAX_SGMII_PHY_REG_ADDR  255
-#define E1000_I2CCMD_PHY_TIMEOUT      200
-#define E1000_IVAR_VALID        0x80
-#define E1000_GPIE_NSICR        0x00000001
-#define E1000_GPIE_MSIX_MODE    0x00000010
-#define E1000_GPIE_EIAME        0x40000000
-#define E1000_GPIE_PBA          0x80000000
+#define E1000_CTRL_EXT_IAME		0x08000000 /* Int ACK Auto-mask */
+/* packet buffer parity error detection enabled */
+#define E1000_CRTL_EXT_PB_PAREN		0x01000000
+/* descriptor FIFO parity error detection enable */
+#define E1000_CTRL_EXT_DF_PAREN		0x02000000
+#define E1000_CTRL_EXT_GHOST_PAREN	0x40000000
+#define E1000_CTRL_EXT_PBA_CLR		0x80000000 /* PBA Clear */
+#define E1000_CTRL_EXT_LSECCK		0x00001000
+#define E1000_CTRL_EXT_PHYPDEN		0x00100000
+#define E1000_I2CCMD_REG_ADDR_SHIFT	16
+#define E1000_I2CCMD_REG_ADDR		0x00FF0000
+#define E1000_I2CCMD_PHY_ADDR_SHIFT	24
+#define E1000_I2CCMD_PHY_ADDR		0x07000000
+#define E1000_I2CCMD_OPCODE_READ	0x08000000
+#define E1000_I2CCMD_OPCODE_WRITE	0x00000000
+#define E1000_I2CCMD_RESET		0x10000000
+#define E1000_I2CCMD_READY		0x20000000
+#define E1000_I2CCMD_INTERRUPT_ENA	0x40000000
+#define E1000_I2CCMD_ERROR		0x80000000
+#define E1000_I2CCMD_SFP_DATA_ADDR(a)	(0x0000 + (a))
+#define E1000_I2CCMD_SFP_DIAG_ADDR(a)	(0x0100 + (a))
+#define E1000_MAX_SGMII_PHY_REG_ADDR	255
+#define E1000_I2CCMD_PHY_TIMEOUT	200
+#define E1000_IVAR_VALID	0x80
+#define E1000_GPIE_NSICR	0x00000001
+#define E1000_GPIE_MSIX_MODE	0x00000010
+#define E1000_GPIE_EIAME	0x40000000
+#define E1000_GPIE_PBA		0x80000000
 
 /* Receive Descriptor bit definitions */
-#define E1000_RXD_STAT_DD       0x01    /* Descriptor Done */
-#define E1000_RXD_STAT_EOP      0x02    /* End of Packet */
-#define E1000_RXD_STAT_IXSM     0x04    /* Ignore checksum */
-#define E1000_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */
-#define E1000_RXD_STAT_UDPCS    0x10    /* UDP xsum calculated */
-#define E1000_RXD_STAT_TCPCS    0x20    /* TCP xsum calculated */
-#define E1000_RXD_STAT_IPCS     0x40    /* IP xsum calculated */
-#define E1000_RXD_STAT_PIF      0x80    /* passed in-exact filter */
-#define E1000_RXD_STAT_CRCV     0x100   /* Speculative CRC Valid */
-#define E1000_RXD_STAT_IPIDV    0x200   /* IP identification valid */
-#define E1000_RXD_STAT_UDPV     0x400   /* Valid UDP checksum */
-#define E1000_RXD_STAT_DYNINT   0x800   /* Pkt caused INT via DYNINT */
-#define E1000_RXD_STAT_ACK      0x8000  /* ACK Packet indication */
-#define E1000_RXD_ERR_CE        0x01    /* CRC Error */
-#define E1000_RXD_ERR_SE        0x02    /* Symbol Error */
-#define E1000_RXD_ERR_SEQ       0x04    /* Sequence Error */
-#define E1000_RXD_ERR_CXE       0x10    /* Carrier Extension Error */
-#define E1000_RXD_ERR_TCPE      0x20    /* TCP/UDP Checksum Error */
-#define E1000_RXD_ERR_IPE       0x40    /* IP Checksum Error */
-#define E1000_RXD_ERR_RXE       0x80    /* Rx Data Error */
-#define E1000_RXD_SPC_VLAN_MASK 0x0FFF  /* VLAN ID is in lower 12 bits */
-#define E1000_RXD_SPC_PRI_MASK  0xE000  /* Priority is in upper 3 bits */
-#define E1000_RXD_SPC_PRI_SHIFT 13
-#define E1000_RXD_SPC_CFI_MASK  0x1000  /* CFI is bit 12 */
-#define E1000_RXD_SPC_CFI_SHIFT 12
+#define E1000_RXD_STAT_DD	0x01    /* Descriptor Done */
+#define E1000_RXD_STAT_EOP	0x02    /* End of Packet */
+#define E1000_RXD_STAT_IXSM	0x04    /* Ignore checksum */
+#define E1000_RXD_STAT_VP	0x08    /* IEEE VLAN Packet */
+#define E1000_RXD_STAT_UDPCS	0x10    /* UDP xsum calculated */
+#define E1000_RXD_STAT_TCPCS	0x20    /* TCP xsum calculated */
+#define E1000_RXD_STAT_IPCS	0x40    /* IP xsum calculated */
+#define E1000_RXD_STAT_PIF	0x80    /* passed in-exact filter */
+#define E1000_RXD_STAT_CRCV	0x100   /* Speculative CRC Valid */
+#define E1000_RXD_STAT_IPIDV	0x200   /* IP identification valid */
+#define E1000_RXD_STAT_UDPV	0x400   /* Valid UDP checksum */
+#define E1000_RXD_STAT_DYNINT	0x800   /* Pkt caused INT via DYNINT */
+#define E1000_RXD_STAT_ACK	0x8000  /* ACK Packet indication */
+#define E1000_RXD_ERR_CE	0x01    /* CRC Error */
+#define E1000_RXD_ERR_SE	0x02    /* Symbol Error */
+#define E1000_RXD_ERR_SEQ	0x04    /* Sequence Error */
+#define E1000_RXD_ERR_CXE	0x10    /* Carrier Extension Error */
+#define E1000_RXD_ERR_TCPE	0x20    /* TCP/UDP Checksum Error */
+#define E1000_RXD_ERR_IPE	0x40    /* IP Checksum Error */
+#define E1000_RXD_ERR_RXE	0x80    /* Rx Data Error */
+#define E1000_RXD_SPC_VLAN_MASK	0x0FFF  /* VLAN ID is in lower 12 bits */
+#define E1000_RXD_SPC_PRI_MASK	0xE000  /* Priority is in upper 3 bits */
+#define E1000_RXD_SPC_PRI_SHIFT	13
+#define E1000_RXD_SPC_CFI_MASK	0x1000  /* CFI is bit 12 */
+#define E1000_RXD_SPC_CFI_SHIFT	12
 
-#define E1000_RXDEXT_STATERR_LB    0x00040000
-#define E1000_RXDEXT_STATERR_CE    0x01000000
-#define E1000_RXDEXT_STATERR_SE    0x02000000
-#define E1000_RXDEXT_STATERR_SEQ   0x04000000
-#define E1000_RXDEXT_STATERR_CXE   0x10000000
-#define E1000_RXDEXT_STATERR_TCPE  0x20000000
-#define E1000_RXDEXT_STATERR_IPE   0x40000000
-#define E1000_RXDEXT_STATERR_RXE   0x80000000
+#define E1000_RXDEXT_STATERR_LB		0x00040000
+#define E1000_RXDEXT_STATERR_CE		0x01000000
+#define E1000_RXDEXT_STATERR_SE		0x02000000
+#define E1000_RXDEXT_STATERR_SEQ	0x04000000
+#define E1000_RXDEXT_STATERR_CXE	0x10000000
+#define E1000_RXDEXT_STATERR_TCPE	0x20000000
+#define E1000_RXDEXT_STATERR_IPE	0x40000000
+#define E1000_RXDEXT_STATERR_RXE	0x80000000
 
-#define E1000_RXDEXT_LSECH                0x01000000
-#define E1000_RXDEXT_LSECE_MASK           0x60000000
-#define E1000_RXDEXT_LSECE_NO_ERROR       0x00000000
-#define E1000_RXDEXT_LSECE_NO_SA_MATCH    0x20000000
-#define E1000_RXDEXT_LSECE_REPLAY_DETECT  0x40000000
-#define E1000_RXDEXT_LSECE_BAD_SIG        0x60000000
+#define E1000_RXDEXT_LSECH		0x01000000
+#define E1000_RXDEXT_LSECE_MASK		0x60000000
+#define E1000_RXDEXT_LSECE_NO_ERROR	0x00000000
+#define E1000_RXDEXT_LSECE_NO_SA_MATCH	0x20000000
+#define E1000_RXDEXT_LSECE_REPLAY_DETECT 0x40000000
+#define E1000_RXDEXT_LSECE_BAD_SIG	0x60000000
 
 /* mask to determine if packets should be dropped due to frame errors */
 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \
-    E1000_RXD_ERR_CE  |                \
-    E1000_RXD_ERR_SE  |                \
-    E1000_RXD_ERR_SEQ |                \
-    E1000_RXD_ERR_CXE |                \
-    E1000_RXD_ERR_RXE)
+	E1000_RXD_ERR_CE  |		\
+	E1000_RXD_ERR_SE  |		\
+	E1000_RXD_ERR_SEQ |		\
+	E1000_RXD_ERR_CXE |		\
+	E1000_RXD_ERR_RXE)
 
 /* Same mask, but for extended and packet split descriptors */
 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
-    E1000_RXDEXT_STATERR_CE  |            \
-    E1000_RXDEXT_STATERR_SE  |            \
-    E1000_RXDEXT_STATERR_SEQ |            \
-    E1000_RXDEXT_STATERR_CXE |            \
-    E1000_RXDEXT_STATERR_RXE)
+	E1000_RXDEXT_STATERR_CE  |	\
+	E1000_RXDEXT_STATERR_SE  |	\
+	E1000_RXDEXT_STATERR_SEQ |	\
+	E1000_RXDEXT_STATERR_CXE |	\
+	E1000_RXDEXT_STATERR_RXE)
 
-#define E1000_MRQC_ENABLE_MASK                 0x00000007
-#define E1000_MRQC_ENABLE_RSS_2Q               0x00000001
-#define E1000_MRQC_ENABLE_RSS_INT              0x00000004
-#define E1000_MRQC_RSS_FIELD_MASK              0xFFFF0000
-#define E1000_MRQC_RSS_FIELD_IPV4_TCP          0x00010000
-#define E1000_MRQC_RSS_FIELD_IPV4              0x00020000
-#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX       0x00040000
-#define E1000_MRQC_RSS_FIELD_IPV6_EX           0x00080000
-#define E1000_MRQC_RSS_FIELD_IPV6              0x00100000
-#define E1000_MRQC_RSS_FIELD_IPV6_TCP          0x00200000
+#define E1000_MRQC_ENABLE_MASK			0x00000007
+#define E1000_MRQC_ENABLE_RSS_2Q		0x00000001
+#define E1000_MRQC_ENABLE_RSS_INT		0x00000004
+#define E1000_MRQC_RSS_FIELD_MASK		0xFFFF0000
+#define E1000_MRQC_RSS_FIELD_IPV4_TCP		0x00010000
+#define E1000_MRQC_RSS_FIELD_IPV4		0x00020000
+#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX	0x00040000
+#define E1000_MRQC_RSS_FIELD_IPV6_EX		0x00080000
+#define E1000_MRQC_RSS_FIELD_IPV6		0x00100000
+#define E1000_MRQC_RSS_FIELD_IPV6_TCP		0x00200000
 
-#define E1000_RXDPS_HDRSTAT_HDRSP              0x00008000
-#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK        0x000003FF
+#define E1000_RXDPS_HDRSTAT_HDRSP		0x00008000
+#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK		0x000003FF
 
 /* Management Control */
-#define E1000_MANC_SMBUS_EN      0x00000001 /* SMBus Enabled - RO */
-#define E1000_MANC_ASF_EN        0x00000002 /* ASF Enabled - RO */
-#define E1000_MANC_R_ON_FORCE    0x00000004 /* Reset on Force TCO - RO */
-#define E1000_MANC_RMCP_EN       0x00000100 /* Enable RCMP 026Fh Filtering */
-#define E1000_MANC_0298_EN       0x00000200 /* Enable RCMP 0298h Filtering */
-#define E1000_MANC_IPV4_EN       0x00000400 /* Enable IPv4 */
-#define E1000_MANC_IPV6_EN       0x00000800 /* Enable IPv6 */
-#define E1000_MANC_SNAP_EN       0x00001000 /* Accept LLC/SNAP */
-#define E1000_MANC_ARP_EN        0x00002000 /* Enable ARP Request Filtering */
+#define E1000_MANC_SMBUS_EN	0x00000001 /* SMBus Enabled - RO */
+#define E1000_MANC_ASF_EN	0x00000002 /* ASF Enabled - RO */
+#define E1000_MANC_R_ON_FORCE	0x00000004 /* Reset on Force TCO - RO */
+#define E1000_MANC_RMCP_EN	0x00000100 /* Enable RCMP 026Fh Filtering */
+#define E1000_MANC_0298_EN	0x00000200 /* Enable RCMP 0298h Filtering */
+#define E1000_MANC_IPV4_EN	0x00000400 /* Enable IPv4 */
+#define E1000_MANC_IPV6_EN	0x00000800 /* Enable IPv6 */
+#define E1000_MANC_SNAP_EN	0x00001000 /* Accept LLC/SNAP */
+#define E1000_MANC_ARP_EN	0x00002000 /* Enable ARP Request Filtering */
 /* Enable Neighbor Discovery Filtering */
-#define E1000_MANC_NEIGHBOR_EN   0x00004000
-#define E1000_MANC_ARP_RES_EN    0x00008000 /* Enable ARP response Filtering */
-#define E1000_MANC_TCO_RESET     0x00010000 /* TCO Reset Occurred */
-#define E1000_MANC_RCV_TCO_EN    0x00020000 /* Receive TCO Packets Enabled */
+#define E1000_MANC_NEIGHBOR_EN	0x00004000
+#define E1000_MANC_ARP_RES_EN	0x00008000 /* Enable ARP response Filtering */
+#define E1000_MANC_TCO_RESET	0x00010000 /* TCO Reset Occurred */
+#define E1000_MANC_RCV_TCO_EN	0x00020000 /* Receive TCO Packets Enabled */
 #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
-#define E1000_MANC_RCV_ALL       0x00080000 /* Receive All Enabled */
-#define E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000 /* Block phy resets */
+#define E1000_MANC_RCV_ALL	0x00080000 /* Receive All Enabled */
+#define E1000_MANC_BLK_PHY_RST_ON_IDE	0x00040000 /* Block phy resets */
 /* Enable MAC address filtering */
-#define E1000_MANC_EN_MAC_ADDR_FILTER   0x00100000
+#define E1000_MANC_EN_MAC_ADDR_FILTER	0x00100000
 /* Enable MNG packets to host memory */
-#define E1000_MANC_EN_MNG2HOST   0x00200000
+#define E1000_MANC_EN_MNG2HOST		0x00200000
 /* Enable IP address filtering */
-#define E1000_MANC_EN_IP_ADDR_FILTER    0x00400000
-#define E1000_MANC_EN_XSUM_FILTER   0x00800000 /* Enable checksum filtering */
-#define E1000_MANC_BR_EN            0x01000000 /* Enable broadcast filtering */
-#define E1000_MANC_SMB_REQ       0x01000000 /* SMBus Request */
-#define E1000_MANC_SMB_GNT       0x02000000 /* SMBus Grant */
-#define E1000_MANC_SMB_CLK_IN    0x04000000 /* SMBus Clock In */
-#define E1000_MANC_SMB_DATA_IN   0x08000000 /* SMBus Data In */
-#define E1000_MANC_SMB_DATA_OUT  0x10000000 /* SMBus Data Out */
-#define E1000_MANC_SMB_CLK_OUT   0x20000000 /* SMBus Clock Out */
-#define E1000_MANC_MPROXYE       0x40000000 /* Mngment Proxy Enable */
-#define E1000_MANC_EN_BMC2OS     0x10000000 /* OS2BMC is enabled or not */
+#define E1000_MANC_EN_IP_ADDR_FILTER	0x00400000
+#define E1000_MANC_EN_XSUM_FILTER	0x00800000 /* Ena checksum filtering */
+#define E1000_MANC_BR_EN		0x01000000 /* Ena broadcast filtering */
+#define E1000_MANC_SMB_REQ		0x01000000 /* SMBus Request */
+#define E1000_MANC_SMB_GNT		0x02000000 /* SMBus Grant */
+#define E1000_MANC_SMB_CLK_IN		0x04000000 /* SMBus Clock In */
+#define E1000_MANC_SMB_DATA_IN		0x08000000 /* SMBus Data In */
+#define E1000_MANC_SMB_DATA_OUT		0x10000000 /* SMBus Data Out */
+#define E1000_MANC_SMB_CLK_OUT		0x20000000 /* SMBus Clock Out */
+#define E1000_MANC_MPROXYE		0x40000000 /* Mngment Proxy Enable */
+#define E1000_MANC_EN_BMC2OS		0x10000000 /* OS2BMC is enabld or not */
 
-#define E1000_MANC_SMB_DATA_OUT_SHIFT  28 /* SMBus Data Out Shift */
-#define E1000_MANC_SMB_CLK_OUT_SHIFT   29 /* SMBus Clock Out Shift */
+#define E1000_MANC_SMB_DATA_OUT_SHIFT	28 /* SMBus Data Out Shift */
+#define E1000_MANC_SMB_CLK_OUT_SHIFT	29 /* SMBus Clock Out Shift */
 
-#define E1000_MANC2H_PORT_623    0x00000020 /* Port 0x26f */
-#define E1000_MANC2H_PORT_664    0x00000040 /* Port 0x298 */
-#define E1000_MDEF_PORT_623      0x00000800 /* Port 0x26f */
-#define E1000_MDEF_PORT_664      0x00000400 /* Port 0x298 */
+#define E1000_MANC2H_PORT_623		0x00000020 /* Port 0x26f */
+#define E1000_MANC2H_PORT_664		0x00000040 /* Port 0x298 */
+#define E1000_MDEF_PORT_623		0x00000800 /* Port 0x26f */
+#define E1000_MDEF_PORT_664		0x00000400 /* Port 0x298 */
 
 /* Receive Control */
-#define E1000_RCTL_RST            0x00000001    /* Software reset */
-#define E1000_RCTL_EN             0x00000002    /* enable */
-#define E1000_RCTL_SBP            0x00000004    /* store bad packet */
-#define E1000_RCTL_UPE            0x00000008    /* unicast promisc enable */
-#define E1000_RCTL_MPE            0x00000010    /* multicast promisc enable */
-#define E1000_RCTL_LPE            0x00000020    /* long packet enable */
-#define E1000_RCTL_LBM_NO         0x00000000    /* no loopback mode */
-#define E1000_RCTL_LBM_MAC        0x00000040    /* MAC loopback mode */
-#define E1000_RCTL_LBM_SLP        0x00000080    /* serial link loopback mode */
-#define E1000_RCTL_LBM_TCVR       0x000000C0    /* tcvr loopback mode */
-#define E1000_RCTL_DTYP_MASK      0x00000C00    /* Descriptor type mask */
-#define E1000_RCTL_DTYP_PS        0x00000400    /* Packet Split descriptor */
-#define E1000_RCTL_RDMTS_HALF     0x00000000    /* Rx desc min thresh size */
-#define E1000_RCTL_RDMTS_QUAT     0x00000100    /* Rx desc min thresh size */
-#define E1000_RCTL_RDMTS_EIGTH    0x00000200    /* Rx desc min thresh size */
-#define E1000_RCTL_MO_SHIFT       12            /* multicast offset shift */
-#define E1000_RCTL_MO_0           0x00000000    /* multicast offset 11:0 */
-#define E1000_RCTL_MO_1           0x00001000    /* multicast offset 12:1 */
-#define E1000_RCTL_MO_2           0x00002000    /* multicast offset 13:2 */
-#define E1000_RCTL_MO_3           0x00003000    /* multicast offset 15:4 */
-#define E1000_RCTL_MDR            0x00004000    /* multicast desc ring 0 */
-#define E1000_RCTL_BAM            0x00008000    /* broadcast enable */
+#define E1000_RCTL_RST		0x00000001 /* Software reset */
+#define E1000_RCTL_EN		0x00000002 /* enable */
+#define E1000_RCTL_SBP		0x00000004 /* store bad packet */
+#define E1000_RCTL_UPE		0x00000008 /* unicast promisc enable */
+#define E1000_RCTL_MPE		0x00000010 /* multicast promisc enable */
+#define E1000_RCTL_LPE		0x00000020 /* long packet enable */
+#define E1000_RCTL_LBM_NO	0x00000000 /* no loopback mode */
+#define E1000_RCTL_LBM_MAC	0x00000040 /* MAC loopback mode */
+#define E1000_RCTL_LBM_SLP	0x00000080 /* serial link loopback mode */
+#define E1000_RCTL_LBM_TCVR	0x000000C0 /* tcvr loopback mode */
+#define E1000_RCTL_DTYP_MASK	0x00000C00 /* Descriptor type mask */
+#define E1000_RCTL_DTYP_PS	0x00000400 /* Packet Split descriptor */
+#define E1000_RCTL_RDMTS_HALF	0x00000000 /* Rx desc min thresh size */
+#define E1000_RCTL_RDMTS_QUAT	0x00000100 /* Rx desc min thresh size */
+#define E1000_RCTL_RDMTS_EIGTH	0x00000200 /* Rx desc min thresh size */
+#define E1000_RCTL_MO_SHIFT	12 /* multicast offset shift */
+#define E1000_RCTL_MO_0		0x00000000 /* multicast offset 11:0 */
+#define E1000_RCTL_MO_1		0x00001000 /* multicast offset 12:1 */
+#define E1000_RCTL_MO_2		0x00002000 /* multicast offset 13:2 */
+#define E1000_RCTL_MO_3		0x00003000 /* multicast offset 15:4 */
+#define E1000_RCTL_MDR		0x00004000 /* multicast desc ring 0 */
+#define E1000_RCTL_BAM		0x00008000 /* broadcast enable */
 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
-#define E1000_RCTL_SZ_2048        0x00000000    /* Rx buffer size 2048 */
-#define E1000_RCTL_SZ_1024        0x00010000    /* Rx buffer size 1024 */
-#define E1000_RCTL_SZ_512         0x00020000    /* Rx buffer size 512 */
-#define E1000_RCTL_SZ_256         0x00030000    /* Rx buffer size 256 */
+#define E1000_RCTL_SZ_2048	0x00000000 /* Rx buffer size 2048 */
+#define E1000_RCTL_SZ_1024	0x00010000 /* Rx buffer size 1024 */
+#define E1000_RCTL_SZ_512	0x00020000 /* Rx buffer size 512 */
+#define E1000_RCTL_SZ_256	0x00030000 /* Rx buffer size 256 */
 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
-#define E1000_RCTL_SZ_16384       0x00010000    /* Rx buffer size 16384 */
-#define E1000_RCTL_SZ_8192        0x00020000    /* Rx buffer size 8192 */
-#define E1000_RCTL_SZ_4096        0x00030000    /* Rx buffer size 4096 */
-#define E1000_RCTL_VFE            0x00040000    /* vlan filter enable */
-#define E1000_RCTL_CFIEN          0x00080000    /* canonical form enable */
-#define E1000_RCTL_CFI            0x00100000    /* canonical form indicator */
-#define E1000_RCTL_DPF            0x00400000    /* discard pause frames */
-#define E1000_RCTL_PMCF           0x00800000    /* pass MAC control frames */
-#define E1000_RCTL_BSEX           0x02000000    /* Buffer size extension */
-#define E1000_RCTL_SECRC          0x04000000    /* Strip Ethernet CRC */
-#define E1000_RCTL_FLXBUF_MASK    0x78000000    /* Flexible buffer size */
-#define E1000_RCTL_FLXBUF_SHIFT   27            /* Flexible buffer shift */
+#define E1000_RCTL_SZ_16384	0x00010000 /* Rx buffer size 16384 */
+#define E1000_RCTL_SZ_8192	0x00020000 /* Rx buffer size 8192 */
+#define E1000_RCTL_SZ_4096	0x00030000 /* Rx buffer size 4096 */
+#define E1000_RCTL_VFE		0x00040000 /* vlan filter enable */
+#define E1000_RCTL_CFIEN	0x00080000 /* canonical form enable */
+#define E1000_RCTL_CFI		0x00100000 /* canonical form indicator */
+#define E1000_RCTL_DPF		0x00400000 /* discard pause frames */
+#define E1000_RCTL_PMCF		0x00800000 /* pass MAC control frames */
+#define E1000_RCTL_BSEX		0x02000000 /* Buffer size extension */
+#define E1000_RCTL_SECRC	0x04000000 /* Strip Ethernet CRC */
+#define E1000_RCTL_FLXBUF_MASK	0x78000000 /* Flexible buffer size */
+#define E1000_RCTL_FLXBUF_SHIFT	27 /* Flexible buffer shift */
 
 /*
  * Use byte values for the following shift parameters
  * Usage:
  *     psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
- *                  E1000_PSRCTL_BSIZE0_MASK) |
- *                ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
- *                  E1000_PSRCTL_BSIZE1_MASK) |
- *                ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
- *                  E1000_PSRCTL_BSIZE2_MASK) |
- *                ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
- *                  E1000_PSRCTL_BSIZE3_MASK))
+ *		  E1000_PSRCTL_BSIZE0_MASK) |
+ *		((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
+ *		  E1000_PSRCTL_BSIZE1_MASK) |
+ *		((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
+ *		  E1000_PSRCTL_BSIZE2_MASK) |
+ *		((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
+ *		  E1000_PSRCTL_BSIZE3_MASK))
  * where value0 = [128..16256],  default=256
  *       value1 = [1024..64512], default=4096
  *       value2 = [0..64512],    default=4096
  *       value3 = [0..64512],    default=0
  */
 
-#define E1000_PSRCTL_BSIZE0_MASK   0x0000007F
-#define E1000_PSRCTL_BSIZE1_MASK   0x00003F00
-#define E1000_PSRCTL_BSIZE2_MASK   0x003F0000
-#define E1000_PSRCTL_BSIZE3_MASK   0x3F000000
+#define E1000_PSRCTL_BSIZE0_MASK	0x0000007F
+#define E1000_PSRCTL_BSIZE1_MASK	0x00003F00
+#define E1000_PSRCTL_BSIZE2_MASK	0x003F0000
+#define E1000_PSRCTL_BSIZE3_MASK	0x3F000000
 
-#define E1000_PSRCTL_BSIZE0_SHIFT  7            /* Shift _right_ 7 */
-#define E1000_PSRCTL_BSIZE1_SHIFT  2            /* Shift _right_ 2 */
-#define E1000_PSRCTL_BSIZE2_SHIFT  6            /* Shift _left_ 6 */
-#define E1000_PSRCTL_BSIZE3_SHIFT 14            /* Shift _left_ 14 */
+#define E1000_PSRCTL_BSIZE0_SHIFT	7    /* Shift _right_ 7 */
+#define E1000_PSRCTL_BSIZE1_SHIFT	2    /* Shift _right_ 2 */
+#define E1000_PSRCTL_BSIZE2_SHIFT	6    /* Shift _left_ 6 */
+#define E1000_PSRCTL_BSIZE3_SHIFT	14   /* Shift _left_ 14 */
 
 /* SWFW_SYNC Definitions */
-#define E1000_SWFW_EEP_SM   0x01
-#define E1000_SWFW_PHY0_SM  0x02
-#define E1000_SWFW_PHY1_SM  0x04
-#define E1000_SWFW_CSR_SM   0x08
-#define E1000_SWFW_PHY2_SM  0x20
-#define E1000_SWFW_PHY3_SM  0x40
-#define E1000_SWFW_SW_MNG_SM 0x400
+#define E1000_SWFW_EEP_SM	0x01
+#define E1000_SWFW_PHY0_SM	0x02
+#define E1000_SWFW_PHY1_SM	0x04
+#define E1000_SWFW_CSR_SM	0x08
+#define E1000_SWFW_PHY2_SM	0x20
+#define E1000_SWFW_PHY3_SM	0x40
+#define E1000_SWFW_SW_MNG_SM	0x400
 
 /* FACTPS Definitions */
-#define E1000_FACTPS_LFS    0x40000000  /* LAN Function Select */
+#define E1000_FACTPS_LFS	0x40000000  /* LAN Function Select */
 /* Device Control */
-#define E1000_CTRL_FD       0x00000001  /* Full duplex.0=half; 1=full */
-#define E1000_CTRL_BEM      0x00000002  /* Endian Mode.0=little,1=big */
-#define E1000_CTRL_PRIOR    0x00000004  /* Priority on PCI. 0=rx,1=fair */
+#define E1000_CTRL_FD		0x00000001  /* Full duplex.0=half; 1=full */
+#define E1000_CTRL_BEM		0x00000002  /* Endian Mode.0=little,1=big */
+#define E1000_CTRL_PRIOR	0x00000004  /* Priority on PCI. 0=rx,1=fair */
 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */
-#define E1000_CTRL_LRST     0x00000008  /* Link reset. 0=normal,1=reset */
-#define E1000_CTRL_TME      0x00000010  /* Test mode. 0=normal,1=test */
-#define E1000_CTRL_SLE      0x00000020  /* Serial Link on 0=dis,1=en */
-#define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */
-#define E1000_CTRL_SLU      0x00000040  /* Set link up (Force Link) */
-#define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */
-#define E1000_CTRL_SPD_SEL  0x00000300  /* Speed Select Mask */
-#define E1000_CTRL_SPD_10   0x00000000  /* Force 10Mb */
-#define E1000_CTRL_SPD_100  0x00000100  /* Force 100Mb */
-#define E1000_CTRL_SPD_1000 0x00000200  /* Force 1Gb */
-#define E1000_CTRL_BEM32    0x00000400  /* Big Endian 32 mode */
-#define E1000_CTRL_FRCSPD   0x00000800  /* Force Speed */
-#define E1000_CTRL_FRCDPX   0x00001000  /* Force Duplex */
-#define E1000_CTRL_D_UD_EN  0x00002000  /* Dock/Undock enable */
-#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock
-                                             * indication in SDP[0] */
-#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through
-                                               * PHYRST_N pin */
-#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external
-                                           * LINK_0 and LINK_1 pins */
-#define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */
-#define E1000_CTRL_LANPHYPC_VALUE    0x00020000 /* SW value of LANPHYPC */
-#define E1000_CTRL_SWDPIN0  0x00040000  /* SWDPIN 0 value */
-#define E1000_CTRL_SWDPIN1  0x00080000  /* SWDPIN 1 value */
-#define E1000_CTRL_SWDPIN2  0x00100000  /* SWDPIN 2 value */
-#define E1000_CTRL_ADVD3WUC 0x00100000  /* D3 WUC */
-#define E1000_CTRL_SWDPIN3  0x00200000  /* SWDPIN 3 value */
-#define E1000_CTRL_SWDPIO0  0x00400000  /* SWDPIN 0 Input or output */
-#define E1000_CTRL_SWDPIO1  0x00800000  /* SWDPIN 1 input or output */
-#define E1000_CTRL_SWDPIO2  0x01000000  /* SWDPIN 2 input or output */
-#define E1000_CTRL_SWDPIO3  0x02000000  /* SWDPIN 3 input or output */
-#define E1000_CTRL_RST      0x04000000  /* Global reset */
-#define E1000_CTRL_RFCE     0x08000000  /* Receive Flow Control enable */
-#define E1000_CTRL_TFCE     0x10000000  /* Transmit flow control enable */
-#define E1000_CTRL_RTE      0x20000000  /* Routing tag enable */
-#define E1000_CTRL_VME      0x40000000  /* IEEE VLAN mode enable */
-#define E1000_CTRL_PHY_RST  0x80000000  /* PHY Reset */
-#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to ME */
-#define E1000_CTRL_I2C_ENA  0x02000000  /* I2C enable */
+#define E1000_CTRL_LRST		0x00000008  /* Link reset. 0=normal,1=reset */
+#define E1000_CTRL_TME		0x00000010  /* Test mode. 0=normal,1=test */
+#define E1000_CTRL_SLE		0x00000020  /* Serial Link on 0=dis,1=en */
+#define E1000_CTRL_ASDE		0x00000020  /* Auto-speed detect enable */
+#define E1000_CTRL_SLU		0x00000040  /* Set link up (Force Link) */
+#define E1000_CTRL_ILOS		0x00000080  /* Invert Loss-Of Signal */
+#define E1000_CTRL_SPD_SEL	0x00000300  /* Speed Select Mask */
+#define E1000_CTRL_SPD_10	0x00000000  /* Force 10Mb */
+#define E1000_CTRL_SPD_100	0x00000100  /* Force 100Mb */
+#define E1000_CTRL_SPD_1000	0x00000200  /* Force 1Gb */
+#define E1000_CTRL_BEM32	0x00000400  /* Big Endian 32 mode */
+#define E1000_CTRL_FRCSPD	0x00000800  /* Force Speed */
+#define E1000_CTRL_FRCDPX	0x00001000  /* Force Duplex */
+#define E1000_CTRL_D_UD_EN	0x00002000  /* Dock/Undock enable */
+/* Defined polarity of Dock/Undock indication in SDP[0] */
+#define E1000_CTRL_D_UD_POLARITY	0x00004000
+/* Reset both PHY ports, through PHYRST_N pin */
+#define E1000_CTRL_FORCE_PHY_RESET	0x00008000
+/* enable link status from external LINK_0 and LINK_1 pins */
+#define E1000_CTRL_EXT_LINK_EN		0x00010000
+#define E1000_CTRL_LANPHYPC_OVERRIDE	0x00010000 /* SW control of LANPHYPC */
+#define E1000_CTRL_LANPHYPC_VALUE	0x00020000 /* SW value of LANPHYPC */
+#define E1000_CTRL_SWDPIN0	0x00040000 /* SWDPIN 0 value */
+#define E1000_CTRL_SWDPIN1	0x00080000 /* SWDPIN 1 value */
+#define E1000_CTRL_SWDPIN2	0x00100000 /* SWDPIN 2 value */
+#define E1000_CTRL_ADVD3WUC	0x00100000 /* D3 WUC */
+#define E1000_CTRL_SWDPIN3	0x00200000 /* SWDPIN 3 value */
+#define E1000_CTRL_SWDPIO0	0x00400000 /* SWDPIN 0 Input or output */
+#define E1000_CTRL_SWDPIO1	0x00800000 /* SWDPIN 1 input or output */
+#define E1000_CTRL_SWDPIO2	0x01000000 /* SWDPIN 2 input or output */
+#define E1000_CTRL_SWDPIO3	0x02000000 /* SWDPIN 3 input or output */
+#define E1000_CTRL_RST		0x04000000 /* Global reset */
+#define E1000_CTRL_RFCE		0x08000000 /* Receive Flow Control enable */
+#define E1000_CTRL_TFCE		0x10000000 /* Transmit flow control enable */
+#define E1000_CTRL_RTE		0x20000000 /* Routing tag enable */
+#define E1000_CTRL_VME		0x40000000 /* IEEE VLAN mode enable */
+#define E1000_CTRL_PHY_RST	0x80000000 /* PHY Reset */
+#define E1000_CTRL_SW2FW_INT	0x02000000 /* Initiate an interrupt to ME */
+#define E1000_CTRL_I2C_ENA	0x02000000 /* I2C enable */
 
 /*
  * Bit definitions for the Management Data IO (MDIO) and Management Data
  * Clock (MDC) pins in the Device Control Register.
  */
-#define E1000_CTRL_PHY_RESET_DIR  E1000_CTRL_SWDPIO0
-#define E1000_CTRL_PHY_RESET      E1000_CTRL_SWDPIN0
-#define E1000_CTRL_MDIO_DIR       E1000_CTRL_SWDPIO2
-#define E1000_CTRL_MDIO           E1000_CTRL_SWDPIN2
-#define E1000_CTRL_MDC_DIR        E1000_CTRL_SWDPIO3
-#define E1000_CTRL_MDC            E1000_CTRL_SWDPIN3
-#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
-#define E1000_CTRL_PHY_RESET4     E1000_CTRL_EXT_SDP4_DATA
+#define E1000_CTRL_PHY_RESET_DIR	E1000_CTRL_SWDPIO0
+#define E1000_CTRL_PHY_RESET		E1000_CTRL_SWDPIN0
+#define E1000_CTRL_MDIO_DIR		E1000_CTRL_SWDPIO2
+#define E1000_CTRL_MDIO			E1000_CTRL_SWDPIN2
+#define E1000_CTRL_MDC_DIR		E1000_CTRL_SWDPIO3
+#define E1000_CTRL_MDC			E1000_CTRL_SWDPIN3
+#define E1000_CTRL_PHY_RESET_DIR4	E1000_CTRL_EXT_SDP4_DIR
+#define E1000_CTRL_PHY_RESET4		E1000_CTRL_EXT_SDP4_DATA
 
-#define E1000_CONNSW_ENRGSRC             0x4
-#define E1000_PCS_CFG_PCS_EN             8
-#define E1000_PCS_LCTL_FLV_LINK_UP       1
-#define E1000_PCS_LCTL_FSV_10            0
-#define E1000_PCS_LCTL_FSV_100           2
-#define E1000_PCS_LCTL_FSV_1000          4
-#define E1000_PCS_LCTL_FDV_FULL          8
-#define E1000_PCS_LCTL_FSD               0x10
-#define E1000_PCS_LCTL_FORCE_LINK        0x20
-#define E1000_PCS_LCTL_LOW_LINK_LATCH    0x40
-#define E1000_PCS_LCTL_FORCE_FCTRL       0x80
-#define E1000_PCS_LCTL_AN_ENABLE         0x10000
-#define E1000_PCS_LCTL_AN_RESTART        0x20000
-#define E1000_PCS_LCTL_AN_TIMEOUT        0x40000
-#define E1000_PCS_LCTL_AN_SGMII_BYPASS   0x80000
-#define E1000_PCS_LCTL_AN_SGMII_TRIGGER  0x100000
-#define E1000_PCS_LCTL_FAST_LINK_TIMER   0x1000000
-#define E1000_PCS_LCTL_LINK_OK_FIX       0x2000000
-#define E1000_PCS_LCTL_CRS_ON_NI         0x4000000
-#define E1000_ENABLE_SERDES_LOOPBACK     0x0410
+#define E1000_CONNSW_ENRGSRC		0x4
+#define E1000_PCS_CFG_PCS_EN		8
+#define E1000_PCS_LCTL_FLV_LINK_UP	1
+#define E1000_PCS_LCTL_FSV_10		0
+#define E1000_PCS_LCTL_FSV_100		2
+#define E1000_PCS_LCTL_FSV_1000		4
+#define E1000_PCS_LCTL_FDV_FULL		8
+#define E1000_PCS_LCTL_FSD		0x10
+#define E1000_PCS_LCTL_FORCE_LINK	0x20
+#define E1000_PCS_LCTL_LOW_LINK_LATCH	0x40
+#define E1000_PCS_LCTL_FORCE_FCTRL	0x80
+#define E1000_PCS_LCTL_AN_ENABLE	0x10000
+#define E1000_PCS_LCTL_AN_RESTART	0x20000
+#define E1000_PCS_LCTL_AN_TIMEOUT	0x40000
+#define E1000_PCS_LCTL_AN_SGMII_BYPASS	0x80000
+#define E1000_PCS_LCTL_AN_SGMII_TRIGGER	0x100000
+#define E1000_PCS_LCTL_FAST_LINK_TIMER	0x1000000
+#define E1000_PCS_LCTL_LINK_OK_FIX	0x2000000
+#define E1000_PCS_LCTL_CRS_ON_NI	0x4000000
+#define E1000_ENABLE_SERDES_LOOPBACK	0x0410
 
-#define E1000_PCS_LSTS_LINK_OK           1
-#define E1000_PCS_LSTS_SPEED_10          0
-#define E1000_PCS_LSTS_SPEED_100         2
-#define E1000_PCS_LSTS_SPEED_1000        4
-#define E1000_PCS_LSTS_DUPLEX_FULL       8
-#define E1000_PCS_LSTS_SYNK_OK           0x10
-#define E1000_PCS_LSTS_AN_COMPLETE       0x10000
-#define E1000_PCS_LSTS_AN_PAGE_RX        0x20000
-#define E1000_PCS_LSTS_AN_TIMED_OUT      0x40000
-#define E1000_PCS_LSTS_AN_REMOTE_FAULT   0x80000
-#define E1000_PCS_LSTS_AN_ERROR_RWS      0x100000
+#define E1000_PCS_LSTS_LINK_OK		1
+#define E1000_PCS_LSTS_SPEED_10		0
+#define E1000_PCS_LSTS_SPEED_100	2
+#define E1000_PCS_LSTS_SPEED_1000	4
+#define E1000_PCS_LSTS_DUPLEX_FULL	8
+#define E1000_PCS_LSTS_SYNK_OK		0x10
+#define E1000_PCS_LSTS_AN_COMPLETE	0x10000
+#define E1000_PCS_LSTS_AN_PAGE_RX	0x20000
+#define E1000_PCS_LSTS_AN_TIMED_OUT	0x40000
+#define E1000_PCS_LSTS_AN_REMOTE_FAULT	0x80000
+#define E1000_PCS_LSTS_AN_ERROR_RWS	0x100000
 
 /* Device Status */
-#define E1000_STATUS_FD         0x00000001      /* Full duplex.0=half,1=full */
-#define E1000_STATUS_LU         0x00000002      /* Link up.0=no,1=link */
-#define E1000_STATUS_FUNC_MASK  0x0000000C      /* PCI Function Mask */
-#define E1000_STATUS_FUNC_SHIFT 2
-#define E1000_STATUS_FUNC_0     0x00000000      /* Function 0 */
-#define E1000_STATUS_FUNC_1     0x00000004      /* Function 1 */
-#define E1000_STATUS_TXOFF      0x00000010      /* transmission paused */
-#define E1000_STATUS_TBIMODE    0x00000020      /* TBI mode */
-#define E1000_STATUS_SPEED_MASK 0x000000C0
-#define E1000_STATUS_SPEED_10   0x00000000      /* Speed 10Mb/s */
-#define E1000_STATUS_SPEED_100  0x00000040      /* Speed 100Mb/s */
-#define E1000_STATUS_SPEED_1000 0x00000080      /* Speed 1000Mb/s */
-#define E1000_STATUS_LAN_INIT_DONE 0x00000200  /* Lan Init Completion by NVM */
-#define E1000_STATUS_ASDV       0x00000300      /* Auto speed detect value */
-#define E1000_STATUS_PHYRA      0x00000400      /* PHY Reset Asserted */
-#define E1000_STATUS_DOCK_CI    0x00000800      /* Change in Dock/Undock state.
-                                                 * Clear on write '0'. */
-#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */
-#define E1000_STATUS_MTXCKOK    0x00000400      /* MTX clock running OK */
-#define E1000_STATUS_PCI66      0x00000800      /* In 66Mhz slot */
-#define E1000_STATUS_BUS64      0x00001000      /* In 64 bit slot */
-#define E1000_STATUS_PCIX_MODE  0x00002000      /* PCI-X mode */
-#define E1000_STATUS_PCIX_SPEED 0x0000C000      /* PCI-X bus speed */
-#define E1000_STATUS_BMC_SKU_0  0x00100000 /* BMC USB redirect disabled */
-#define E1000_STATUS_BMC_SKU_1  0x00200000 /* BMC SRAM disabled */
-#define E1000_STATUS_BMC_SKU_2  0x00400000 /* BMC SDRAM disabled */
-#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */
-#define E1000_STATUS_BMC_LITE   0x01000000 /* BMC external code execution
-                                            * disabled */
-#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */
-#define E1000_STATUS_FUSE_8       0x04000000
-#define E1000_STATUS_FUSE_9       0x08000000
-#define E1000_STATUS_SERDES0_DIS  0x10000000 /* SERDES disabled on port 0 */
-#define E1000_STATUS_SERDES1_DIS  0x20000000 /* SERDES disabled on port 1 */
+#define E1000_STATUS_FD			0x00000001 /* Duplex 0=half 1=full */
+#define E1000_STATUS_LU			0x00000002 /* Link up.0=no,1=link */
+#define E1000_STATUS_FUNC_MASK		0x0000000C /* PCI Function Mask */
+#define E1000_STATUS_FUNC_SHIFT		2
+#define E1000_STATUS_FUNC_0		0x00000000 /* Function 0 */
+#define E1000_STATUS_FUNC_1		0x00000004 /* Function 1 */
+#define E1000_STATUS_TXOFF		0x00000010 /* transmission paused */
+#define E1000_STATUS_TBIMODE		0x00000020 /* TBI mode */
+#define E1000_STATUS_SPEED_MASK		0x000000C0
+#define E1000_STATUS_SPEED_10		0x00000000 /* Speed 10Mb/s */
+#define E1000_STATUS_SPEED_100		0x00000040 /* Speed 100Mb/s */
+#define E1000_STATUS_SPEED_1000		0x00000080 /* Speed 1000Mb/s */
+#define E1000_STATUS_LAN_INIT_DONE	0x00000200 /* Lan Init Compltn by NVM */
+#define E1000_STATUS_ASDV		0x00000300 /* Auto speed detect value */
+#define E1000_STATUS_PHYRA		0x00000400 /* PHY Reset Asserted */
+/* Change in Dock/Undock state clear on write '0'. */
+#define E1000_STATUS_DOCK_CI		0x00000800
+#define E1000_STATUS_GIO_MASTER_ENABLE	0x00080000 /* Master request status */
+#define E1000_STATUS_MTXCKOK		0x00000400 /* MTX clock running OK */
+#define E1000_STATUS_PCI66		0x00000800 /* In 66Mhz slot */
+#define E1000_STATUS_BUS64		0x00001000 /* In 64 bit slot */
+#define E1000_STATUS_PCIX_MODE		0x00002000 /* PCI-X mode */
+#define E1000_STATUS_PCIX_SPEED		0x0000C000 /* PCI-X bus speed */
+#define E1000_STATUS_BMC_SKU_0		0x00100000 /* BMC USB redirect disbld */
+#define E1000_STATUS_BMC_SKU_1		0x00200000 /* BMC SRAM disabled */
+#define E1000_STATUS_BMC_SKU_2		0x00400000 /* BMC SDRAM disabled */
+#define E1000_STATUS_BMC_CRYPTO		0x00800000 /* BMC crypto disabled */
+/* BMC external code execution disabled */
+#define E1000_STATUS_BMC_LITE		0x01000000
+#define E1000_STATUS_RGMII_ENABLE	0x02000000 /* RGMII disabled */
+#define E1000_STATUS_FUSE_8		0x04000000
+#define E1000_STATUS_FUSE_9		0x08000000
+#define E1000_STATUS_SERDES0_DIS	0x10000000 /* SERDES disbld on port 0 */
+#define E1000_STATUS_SERDES1_DIS	0x20000000 /* SERDES disbld on port 1 */
 
 /* Constants used to interpret the masked PCI-X bus speed. */
-#define E1000_STATUS_PCIX_SPEED_66  0x00000000 /* PCI-X bus speed 50-66 MHz */
-#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
-#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /*PCI-X bus speed 100-133 MHz*/
+#define E1000_STATUS_PCIX_SPEED_66	0x00000000 /* PCI-X bus spd 50-66MHz */
+#define E1000_STATUS_PCIX_SPEED_100	0x00004000 /* PCI-X bus spd 66-100MHz */
+#define E1000_STATUS_PCIX_SPEED_133	0x00008000 /* PCI-X bus spd 100-133MHz*/
 
-#define SPEED_10    10
-#define SPEED_100   100
-#define SPEED_1000  1000
-#define HALF_DUPLEX 1
-#define FULL_DUPLEX 2
+#define SPEED_10	10
+#define SPEED_100	100
+#define SPEED_1000	1000
+#define HALF_DUPLEX	1
+#define FULL_DUPLEX	2
 
-#define PHY_FORCE_TIME   20
+#define PHY_FORCE_TIME	20
 
-#define ADVERTISE_10_HALF                 0x0001
-#define ADVERTISE_10_FULL                 0x0002
-#define ADVERTISE_100_HALF                0x0004
-#define ADVERTISE_100_FULL                0x0008
-#define ADVERTISE_1000_HALF               0x0010 /* Not used, just FYI */
-#define ADVERTISE_1000_FULL               0x0020
+#define ADVERTISE_10_HALF		0x0001
+#define ADVERTISE_10_FULL		0x0002
+#define ADVERTISE_100_HALF		0x0004
+#define ADVERTISE_100_FULL		0x0008
+#define ADVERTISE_1000_HALF		0x0010 /* Not used, just FYI */
+#define ADVERTISE_1000_FULL		0x0020
 
 /* 1000/H is not supported, nor spec-compliant. */
-#define E1000_ALL_SPEED_DUPLEX  (ADVERTISE_10_HALF |   ADVERTISE_10_FULL | \
-                                ADVERTISE_100_HALF |  ADVERTISE_100_FULL | \
-                                                     ADVERTISE_1000_FULL)
-#define E1000_ALL_NOT_GIG       (ADVERTISE_10_HALF |   ADVERTISE_10_FULL | \
-                                ADVERTISE_100_HALF |  ADVERTISE_100_FULL)
-#define E1000_ALL_100_SPEED    (ADVERTISE_100_HALF |  ADVERTISE_100_FULL)
-#define E1000_ALL_10_SPEED      (ADVERTISE_10_HALF |   ADVERTISE_10_FULL)
-#define E1000_ALL_FULL_DUPLEX   (ADVERTISE_10_FULL |  ADVERTISE_100_FULL | \
-                                                     ADVERTISE_1000_FULL)
-#define E1000_ALL_HALF_DUPLEX   (ADVERTISE_10_HALF |  ADVERTISE_100_HALF)
+#define E1000_ALL_SPEED_DUPLEX	( \
+	ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
+	ADVERTISE_100_FULL | ADVERTISE_1000_FULL)
+#define E1000_ALL_NOT_GIG	( \
+	ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
+	ADVERTISE_100_FULL)
+#define E1000_ALL_100_SPEED	(ADVERTISE_100_HALF | ADVERTISE_100_FULL)
+#define E1000_ALL_10_SPEED	(ADVERTISE_10_HALF | ADVERTISE_10_FULL)
+#define E1000_ALL_FULL_DUPLEX	( \
+	ADVERTISE_10_FULL | ADVERTISE_100_FULL | ADVERTISE_1000_FULL)
+#define E1000_ALL_HALF_DUPLEX	(ADVERTISE_10_HALF | ADVERTISE_100_HALF)
 
-#define AUTONEG_ADVERTISE_SPEED_DEFAULT   E1000_ALL_SPEED_DUPLEX
+#define AUTONEG_ADVERTISE_SPEED_DEFAULT		E1000_ALL_SPEED_DUPLEX
 
 /* LED Control */
-#define E1000_PHY_LED0_MODE_MASK          0x00000007
-#define E1000_PHY_LED0_IVRT               0x00000008
-#define E1000_PHY_LED0_BLINK              0x00000010
-#define E1000_PHY_LED0_MASK               0x0000001F
+#define E1000_PHY_LED0_MODE_MASK	0x00000007
+#define E1000_PHY_LED0_IVRT		0x00000008
+#define E1000_PHY_LED0_BLINK		0x00000010
+#define E1000_PHY_LED0_MASK		0x0000001F
 
-#define E1000_LEDCTL_LED0_MODE_MASK       0x0000000F
-#define E1000_LEDCTL_LED0_MODE_SHIFT      0
-#define E1000_LEDCTL_LED0_BLINK_RATE      0x00000020
-#define E1000_LEDCTL_LED0_IVRT            0x00000040
-#define E1000_LEDCTL_LED0_BLINK           0x00000080
-#define E1000_LEDCTL_LED1_MODE_MASK       0x00000F00
-#define E1000_LEDCTL_LED1_MODE_SHIFT      8
-#define E1000_LEDCTL_LED1_BLINK_RATE      0x00002000
-#define E1000_LEDCTL_LED1_IVRT            0x00004000
-#define E1000_LEDCTL_LED1_BLINK           0x00008000
-#define E1000_LEDCTL_LED2_MODE_MASK       0x000F0000
-#define E1000_LEDCTL_LED2_MODE_SHIFT      16
-#define E1000_LEDCTL_LED2_BLINK_RATE      0x00200000
-#define E1000_LEDCTL_LED2_IVRT            0x00400000
-#define E1000_LEDCTL_LED2_BLINK           0x00800000
-#define E1000_LEDCTL_LED3_MODE_MASK       0x0F000000
-#define E1000_LEDCTL_LED3_MODE_SHIFT      24
-#define E1000_LEDCTL_LED3_BLINK_RATE      0x20000000
-#define E1000_LEDCTL_LED3_IVRT            0x40000000
-#define E1000_LEDCTL_LED3_BLINK           0x80000000
+#define E1000_LEDCTL_LED0_MODE_MASK	0x0000000F
+#define E1000_LEDCTL_LED0_MODE_SHIFT	0
+#define E1000_LEDCTL_LED0_BLINK_RATE	0x00000020
+#define E1000_LEDCTL_LED0_IVRT		0x00000040
+#define E1000_LEDCTL_LED0_BLINK		0x00000080
+#define E1000_LEDCTL_LED1_MODE_MASK	0x00000F00
+#define E1000_LEDCTL_LED1_MODE_SHIFT	8
+#define E1000_LEDCTL_LED1_BLINK_RATE	0x00002000
+#define E1000_LEDCTL_LED1_IVRT		0x00004000
+#define E1000_LEDCTL_LED1_BLINK		0x00008000
+#define E1000_LEDCTL_LED2_MODE_MASK	0x000F0000
+#define E1000_LEDCTL_LED2_MODE_SHIFT	16
+#define E1000_LEDCTL_LED2_BLINK_RATE	0x00200000
+#define E1000_LEDCTL_LED2_IVRT		0x00400000
+#define E1000_LEDCTL_LED2_BLINK		0x00800000
+#define E1000_LEDCTL_LED3_MODE_MASK	0x0F000000
+#define E1000_LEDCTL_LED3_MODE_SHIFT	24
+#define E1000_LEDCTL_LED3_BLINK_RATE	0x20000000
+#define E1000_LEDCTL_LED3_IVRT		0x40000000
+#define E1000_LEDCTL_LED3_BLINK		0x80000000
 
-#define E1000_LEDCTL_MODE_LINK_10_1000  0x0
-#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
-#define E1000_LEDCTL_MODE_LINK_UP       0x2
-#define E1000_LEDCTL_MODE_ACTIVITY      0x3
-#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
-#define E1000_LEDCTL_MODE_LINK_10       0x5
-#define E1000_LEDCTL_MODE_LINK_100      0x6
-#define E1000_LEDCTL_MODE_LINK_1000     0x7
-#define E1000_LEDCTL_MODE_PCIX_MODE     0x8
-#define E1000_LEDCTL_MODE_FULL_DUPLEX   0x9
-#define E1000_LEDCTL_MODE_COLLISION     0xA
-#define E1000_LEDCTL_MODE_BUS_SPEED     0xB
-#define E1000_LEDCTL_MODE_BUS_SIZE      0xC
-#define E1000_LEDCTL_MODE_PAUSED        0xD
-#define E1000_LEDCTL_MODE_LED_ON        0xE
-#define E1000_LEDCTL_MODE_LED_OFF       0xF
+#define E1000_LEDCTL_MODE_LINK_10_1000	0x0
+#define E1000_LEDCTL_MODE_LINK_100_1000	0x1
+#define E1000_LEDCTL_MODE_LINK_UP	0x2
+#define E1000_LEDCTL_MODE_ACTIVITY	0x3
+#define E1000_LEDCTL_MODE_LINK_ACTIVITY	0x4
+#define E1000_LEDCTL_MODE_LINK_10	0x5
+#define E1000_LEDCTL_MODE_LINK_100	0x6
+#define E1000_LEDCTL_MODE_LINK_1000	0x7
+#define E1000_LEDCTL_MODE_PCIX_MODE	0x8
+#define E1000_LEDCTL_MODE_FULL_DUPLEX	0x9
+#define E1000_LEDCTL_MODE_COLLISION	0xA
+#define E1000_LEDCTL_MODE_BUS_SPEED	0xB
+#define E1000_LEDCTL_MODE_BUS_SIZE	0xC
+#define E1000_LEDCTL_MODE_PAUSED	0xD
+#define E1000_LEDCTL_MODE_LED_ON	0xE
+#define E1000_LEDCTL_MODE_LED_OFF	0xF
 
 /* Transmit Descriptor bit definitions */
-#define E1000_TXD_DTYP_D     0x00100000 /* Data Descriptor */
-#define E1000_TXD_DTYP_C     0x00000000 /* Context Descriptor */
-#define E1000_TXD_POPTS_SHIFT 8         /* POPTS shift */
-#define E1000_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
-#define E1000_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
-#define E1000_TXD_CMD_EOP    0x01000000 /* End of Packet */
-#define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
-#define E1000_TXD_CMD_IC     0x04000000 /* Insert Checksum */
-#define E1000_TXD_CMD_RS     0x08000000 /* Report Status */
-#define E1000_TXD_CMD_RPS    0x10000000 /* Report Packet Sent */
-#define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
-#define E1000_TXD_CMD_VLE    0x40000000 /* Add VLAN tag */
-#define E1000_TXD_CMD_IDE    0x80000000 /* Enable Tidv register */
-#define E1000_TXD_STAT_DD    0x00000001 /* Descriptor Done */
-#define E1000_TXD_STAT_EC    0x00000002 /* Excess Collisions */
-#define E1000_TXD_STAT_LC    0x00000004 /* Late Collisions */
-#define E1000_TXD_STAT_TU    0x00000008 /* Transmit underrun */
-#define E1000_TXD_CMD_TCP    0x01000000 /* TCP packet */
-#define E1000_TXD_CMD_IP     0x02000000 /* IP packet */
-#define E1000_TXD_CMD_TSE    0x04000000 /* TCP Seg enable */
-#define E1000_TXD_STAT_TC    0x00000004 /* Tx Underrun */
+#define E1000_TXD_DTYP_D	0x00100000 /* Data Descriptor */
+#define E1000_TXD_DTYP_C	0x00000000 /* Context Descriptor */
+#define E1000_TXD_POPTS_SHIFT	8          /* POPTS shift */
+#define E1000_TXD_POPTS_IXSM	0x01       /* Insert IP checksum */
+#define E1000_TXD_POPTS_TXSM	0x02       /* Insert TCP/UDP checksum */
+#define E1000_TXD_CMD_EOP	0x01000000 /* End of Packet */
+#define E1000_TXD_CMD_IFCS	0x02000000 /* Insert FCS (Ethernet CRC) */
+#define E1000_TXD_CMD_IC	0x04000000 /* Insert Checksum */
+#define E1000_TXD_CMD_RS	0x08000000 /* Report Status */
+#define E1000_TXD_CMD_RPS	0x10000000 /* Report Packet Sent */
+#define E1000_TXD_CMD_DEXT	0x20000000 /* Desc extension (0 = legacy) */
+#define E1000_TXD_CMD_VLE	0x40000000 /* Add VLAN tag */
+#define E1000_TXD_CMD_IDE	0x80000000 /* Enable Tidv register */
+#define E1000_TXD_STAT_DD	0x00000001 /* Descriptor Done */
+#define E1000_TXD_STAT_EC	0x00000002 /* Excess Collisions */
+#define E1000_TXD_STAT_LC	0x00000004 /* Late Collisions */
+#define E1000_TXD_STAT_TU	0x00000008 /* Transmit underrun */
+#define E1000_TXD_CMD_TCP	0x01000000 /* TCP packet */
+#define E1000_TXD_CMD_IP	0x02000000 /* IP packet */
+#define E1000_TXD_CMD_TSE	0x04000000 /* TCP Seg enable */
+#define E1000_TXD_STAT_TC	0x00000004 /* Tx Underrun */
 /* Extended desc bits for Linksec and timesync */
-#define E1000_TXD_CMD_LINKSEC     0x10000000 /* Apply LinkSec on packet */
-#define E1000_TXD_EXTCMD_TSTAMP   0x00000010 /* IEEE1588 Timestamp packet */
+#define E1000_TXD_CMD_LINKSEC	0x10000000 /* Apply LinkSec on packet */
+#define E1000_TXD_EXTCMD_TSTAMP	0x00000010 /* IEEE1588 Timestamp packet */
 
 /* Transmit Control */
-#define E1000_TCTL_RST    0x00000001    /* software reset */
-#define E1000_TCTL_EN     0x00000002    /* enable Tx */
-#define E1000_TCTL_BCE    0x00000004    /* busy check enable */
-#define E1000_TCTL_PSP    0x00000008    /* pad short packets */
-#define E1000_TCTL_CT     0x00000ff0    /* collision threshold */
-#define E1000_TCTL_COLD   0x003ff000    /* collision distance */
-#define E1000_TCTL_SWXOFF 0x00400000    /* SW Xoff transmission */
-#define E1000_TCTL_PBE    0x00800000    /* Packet Burst Enable */
-#define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
-#define E1000_TCTL_NRTU   0x02000000    /* No Re-transmit on underrun */
-#define E1000_TCTL_MULR   0x10000000    /* Multiple request support */
+#define E1000_TCTL_RST		0x00000001 /* software reset */
+#define E1000_TCTL_EN		0x00000002 /* enable Tx */
+#define E1000_TCTL_BCE		0x00000004 /* busy check enable */
+#define E1000_TCTL_PSP		0x00000008 /* pad short packets */
+#define E1000_TCTL_CT		0x00000ff0 /* collision threshold */
+#define E1000_TCTL_COLD		0x003ff000 /* collision distance */
+#define E1000_TCTL_SWXOFF	0x00400000 /* SW Xoff transmission */
+#define E1000_TCTL_PBE		0x00800000 /* Packet Burst Enable */
+#define E1000_TCTL_RTLC		0x01000000 /* Re-transmit on late collision */
+#define E1000_TCTL_NRTU		0x02000000 /* No Re-transmit on underrun */
+#define E1000_TCTL_MULR		0x10000000 /* Multiple request support */
 
 /* Transmit Arbitration Count */
-#define E1000_TARC0_ENABLE     0x00000400   /* Enable Tx Queue 0 */
+#define E1000_TARC0_ENABLE	0x00000400 /* Enable Tx Queue 0 */
 
 /* SerDes Control */
-#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
+#define E1000_SCTL_DISABLE_SERDES_LOOPBACK	0x0400
 
 /* Receive Checksum Control */
-#define E1000_RXCSUM_PCSS_MASK 0x000000FF   /* Packet Checksum Start */
-#define E1000_RXCSUM_IPOFL     0x00000100   /* IPv4 checksum offload */
-#define E1000_RXCSUM_TUOFL     0x00000200   /* TCP / UDP checksum offload */
-#define E1000_RXCSUM_IPV6OFL   0x00000400   /* IPv6 checksum offload */
-#define E1000_RXCSUM_CRCOFL    0x00000800   /* CRC32 offload enable */
-#define E1000_RXCSUM_IPPCSE    0x00001000   /* IP payload checksum enable */
-#define E1000_RXCSUM_PCSD      0x00002000   /* packet checksum disabled */
+#define E1000_RXCSUM_PCSS_MASK	0x000000FF /* Packet Checksum Start */
+#define E1000_RXCSUM_IPOFL	0x00000100 /* IPv4 checksum offload */
+#define E1000_RXCSUM_TUOFL	0x00000200 /* TCP / UDP checksum offload */
+#define E1000_RXCSUM_IPV6OFL	0x00000400 /* IPv6 checksum offload */
+#define E1000_RXCSUM_CRCOFL	0x00000800 /* CRC32 offload enable */
+#define E1000_RXCSUM_IPPCSE	0x00001000 /* IP payload checksum enable */
+#define E1000_RXCSUM_PCSD	0x00002000 /* packet checksum disabled */
 
 /* Header split receive */
-#define E1000_RFCTL_ISCSI_DIS           0x00000001
-#define E1000_RFCTL_ISCSI_DWC_MASK      0x0000003E
-#define E1000_RFCTL_ISCSI_DWC_SHIFT     1
-#define E1000_RFCTL_NFSW_DIS            0x00000040
-#define E1000_RFCTL_NFSR_DIS            0x00000080
-#define E1000_RFCTL_NFS_VER_MASK        0x00000300
-#define E1000_RFCTL_NFS_VER_SHIFT       8
-#define E1000_RFCTL_IPV6_DIS            0x00000400
-#define E1000_RFCTL_IPV6_XSUM_DIS       0x00000800
-#define E1000_RFCTL_ACK_DIS             0x00001000
-#define E1000_RFCTL_ACKD_DIS            0x00002000
-#define E1000_RFCTL_IPFRSP_DIS          0x00004000
-#define E1000_RFCTL_EXTEN               0x00008000
-#define E1000_RFCTL_IPV6_EX_DIS         0x00010000
-#define E1000_RFCTL_NEW_IPV6_EXT_DIS    0x00020000
-#define E1000_RFCTL_LEF                 0x00040000
+#define E1000_RFCTL_ISCSI_DIS		0x00000001
+#define E1000_RFCTL_ISCSI_DWC_MASK	0x0000003E
+#define E1000_RFCTL_ISCSI_DWC_SHIFT	1
+#define E1000_RFCTL_NFSW_DIS		0x00000040
+#define E1000_RFCTL_NFSR_DIS		0x00000080
+#define E1000_RFCTL_NFS_VER_MASK	0x00000300
+#define E1000_RFCTL_NFS_VER_SHIFT	8
+#define E1000_RFCTL_IPV6_DIS		0x00000400
+#define E1000_RFCTL_IPV6_XSUM_DIS	0x00000800
+#define E1000_RFCTL_ACK_DIS		0x00001000
+#define E1000_RFCTL_ACKD_DIS		0x00002000
+#define E1000_RFCTL_IPFRSP_DIS		0x00004000
+#define E1000_RFCTL_EXTEN		0x00008000
+#define E1000_RFCTL_IPV6_EX_DIS		0x00010000
+#define E1000_RFCTL_NEW_IPV6_EXT_DIS	0x00020000
+#define E1000_RFCTL_LEF			0x00040000
 
 /* Collision related configuration parameters */
-#define E1000_COLLISION_THRESHOLD       15
-#define E1000_CT_SHIFT                  4
-#define E1000_COLLISION_DISTANCE        63
-#define E1000_COLD_SHIFT                12
+#define E1000_COLLISION_THRESHOLD	15
+#define E1000_CT_SHIFT			4
+#define E1000_COLLISION_DISTANCE	63
+#define E1000_COLD_SHIFT		12
 
 /* Default values for the transmit IPG register */
-#define DEFAULT_82542_TIPG_IPGT        10
-#define DEFAULT_82543_TIPG_IPGT_FIBER  9
-#define DEFAULT_82543_TIPG_IPGT_COPPER 8
+#define DEFAULT_82542_TIPG_IPGT		10
+#define DEFAULT_82543_TIPG_IPGT_FIBER	9
+#define DEFAULT_82543_TIPG_IPGT_COPPER	8
 
-#define E1000_TIPG_IPGT_MASK  0x000003FF
-#define E1000_TIPG_IPGR1_MASK 0x000FFC00
-#define E1000_TIPG_IPGR2_MASK 0x3FF00000
+#define E1000_TIPG_IPGT_MASK		0x000003FF
+#define E1000_TIPG_IPGR1_MASK		0x000FFC00
+#define E1000_TIPG_IPGR2_MASK		0x3FF00000
 
-#define DEFAULT_82542_TIPG_IPGR1 2
-#define DEFAULT_82543_TIPG_IPGR1 8
-#define E1000_TIPG_IPGR1_SHIFT  10
+#define DEFAULT_82542_TIPG_IPGR1	2
+#define DEFAULT_82543_TIPG_IPGR1	8
+#define E1000_TIPG_IPGR1_SHIFT		10
 
-#define DEFAULT_82542_TIPG_IPGR2 10
-#define DEFAULT_82543_TIPG_IPGR2 6
-#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
-#define E1000_TIPG_IPGR2_SHIFT  20
+#define DEFAULT_82542_TIPG_IPGR2	10
+#define DEFAULT_82543_TIPG_IPGR2	6
+#define DEFAULT_80003ES2LAN_TIPG_IPGR2	7
+#define E1000_TIPG_IPGR2_SHIFT		20
 
 /* Ethertype field values */
-#define ETHERNET_IEEE_VLAN_TYPE 0x8100  /* 802.3ac packet */
+#define ETHERNET_IEEE_VLAN_TYPE		0x8100  /* 802.3ac packet */
 
-#define ETHERNET_FCS_SIZE       4
-#define MAX_JUMBO_FRAME_SIZE    0x3F00
+#define ETHERNET_FCS_SIZE		4
+#define MAX_JUMBO_FRAME_SIZE		0x3F00
 
 /* Extended Configuration Control and Size */
-#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP      0x00000020
-#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE       0x00000001
-#define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE       0x00000008
-#define E1000_EXTCNF_CTRL_SWFLAG                 0x00000020
-#define E1000_EXTCNF_CTRL_GATE_PHY_CFG           0x00000080
-#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK   0x00FF0000
-#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT          16
-#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK   0x0FFF0000
-#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT          16
+#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP	0x00000020
+#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE	0x00000001
+#define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE	0x00000008
+#define E1000_EXTCNF_CTRL_SWFLAG		0x00000020
+#define E1000_EXTCNF_CTRL_GATE_PHY_CFG		0x00000080
+#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK	0x00FF0000
+#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT	16
+#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK	0x0FFF0000
+#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT	16
 
-#define E1000_PHY_CTRL_SPD_EN             0x00000001
-#define E1000_PHY_CTRL_D0A_LPLU           0x00000002
-#define E1000_PHY_CTRL_NOND0A_LPLU        0x00000004
-#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
-#define E1000_PHY_CTRL_GBE_DISABLE        0x00000040
+#define E1000_PHY_CTRL_SPD_EN			0x00000001
+#define E1000_PHY_CTRL_D0A_LPLU			0x00000002
+#define E1000_PHY_CTRL_NOND0A_LPLU		0x00000004
+#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE	0x00000008
+#define E1000_PHY_CTRL_GBE_DISABLE		0x00000040
 
-#define E1000_KABGTXD_BGSQLBIAS           0x00050000
+#define E1000_KABGTXD_BGSQLBIAS			0x00050000
 
 /* PBA constants */
-#define E1000_PBA_6K  0x0006    /* 6KB */
-#define E1000_PBA_8K  0x0008    /* 8KB */
-#define E1000_PBA_10K 0x000A    /* 10KB */
-#define E1000_PBA_12K 0x000C    /* 12KB */
-#define E1000_PBA_14K 0x000E    /* 14KB */
-#define E1000_PBA_16K 0x0010    /* 16KB */
-#define E1000_PBA_18K 0x0012
-#define E1000_PBA_20K 0x0014
-#define E1000_PBA_22K 0x0016
-#define E1000_PBA_24K 0x0018
-#define E1000_PBA_26K 0x001A
-#define E1000_PBA_30K 0x001E
-#define E1000_PBA_32K 0x0020
-#define E1000_PBA_34K 0x0022
-#define E1000_PBA_35K 0x0023
-#define E1000_PBA_38K 0x0026
-#define E1000_PBA_40K 0x0028
-#define E1000_PBA_48K 0x0030    /* 48KB */
-#define E1000_PBA_64K 0x0040    /* 64KB */
+#define E1000_PBA_6K		0x0006    /* 6KB */
+#define E1000_PBA_8K		0x0008    /* 8KB */
+#define E1000_PBA_10K		0x000A    /* 10KB */
+#define E1000_PBA_12K		0x000C    /* 12KB */
+#define E1000_PBA_14K		0x000E    /* 14KB */
+#define E1000_PBA_16K		0x0010    /* 16KB */
+#define E1000_PBA_18K		0x0012
+#define E1000_PBA_20K		0x0014
+#define E1000_PBA_22K		0x0016
+#define E1000_PBA_24K		0x0018
+#define E1000_PBA_26K		0x001A
+#define E1000_PBA_30K		0x001E
+#define E1000_PBA_32K		0x0020
+#define E1000_PBA_34K		0x0022
+#define E1000_PBA_35K		0x0023
+#define E1000_PBA_38K		0x0026
+#define E1000_PBA_40K		0x0028
+#define E1000_PBA_48K		0x0030    /* 48KB */
+#define E1000_PBA_64K		0x0040    /* 64KB */
 
-#define E1000_PBS_16K E1000_PBA_16K
-#define E1000_PBS_24K E1000_PBA_24K
+#define E1000_PBA_RXA_MASK	0xFFFF;
 
-#define IFS_MAX       80
-#define IFS_MIN       40
-#define IFS_RATIO     4
-#define IFS_STEP      10
-#define MIN_NUM_XMITS 1000
+#define E1000_PBS_16K		E1000_PBA_16K
+#define E1000_PBS_24K		E1000_PBA_24K
+
+#define IFS_MAX			80
+#define IFS_MIN			40
+#define IFS_RATIO		4
+#define IFS_STEP		10
+#define MIN_NUM_XMITS		1000
 
 /* SW Semaphore Register */
-#define E1000_SWSM_SMBI         0x00000001 /* Driver Semaphore bit */
-#define E1000_SWSM_SWESMBI      0x00000002 /* FW Semaphore bit */
-#define E1000_SWSM_WMNG         0x00000004 /* Wake MNG Clock */
-#define E1000_SWSM_DRV_LOAD     0x00000008 /* Driver Loaded Bit */
+#define E1000_SWSM_SMBI		0x00000001 /* Driver Semaphore bit */
+#define E1000_SWSM_SWESMBI	0x00000002 /* FW Semaphore bit */
+#define E1000_SWSM_WMNG		0x00000004 /* Wake MNG Clock */
+#define E1000_SWSM_DRV_LOAD	0x00000008 /* Driver Loaded Bit */
 
-#define E1000_SWSM2_LOCK        0x00000002 /* Secondary driver semaphore bit */
+#define E1000_SWSM2_LOCK	0x00000002 /* Secondary driver semaphore bit */
 
 /* Interrupt Cause Read */
-#define E1000_ICR_TXDW          0x00000001 /* Transmit desc written back */
-#define E1000_ICR_TXQE          0x00000002 /* Transmit Queue empty */
-#define E1000_ICR_LSC           0x00000004 /* Link Status Change */
-#define E1000_ICR_RXSEQ         0x00000008 /* Rx sequence error */
-#define E1000_ICR_RXDMT0        0x00000010 /* Rx desc min. threshold (0) */
-#define E1000_ICR_RXO           0x00000040 /* Rx overrun */
-#define E1000_ICR_RXT0          0x00000080 /* Rx timer intr (ring 0) */
-#define E1000_ICR_VMMB          0x00000100 /* VM MB event */
-#define E1000_ICR_MDAC          0x00000200 /* MDIO access complete */
-#define E1000_ICR_RXCFG         0x00000400 /* Rx /c/ ordered set */
-#define E1000_ICR_GPI_EN0       0x00000800 /* GP Int 0 */
-#define E1000_ICR_GPI_EN1       0x00001000 /* GP Int 1 */
-#define E1000_ICR_GPI_EN2       0x00002000 /* GP Int 2 */
-#define E1000_ICR_GPI_EN3       0x00004000 /* GP Int 3 */
-#define E1000_ICR_TXD_LOW       0x00008000
-#define E1000_ICR_SRPD          0x00010000
-#define E1000_ICR_ACK           0x00020000 /* Receive Ack frame */
-#define E1000_ICR_MNG           0x00040000 /* Manageability event */
-#define E1000_ICR_DOCK          0x00080000 /* Dock/Undock */
-#define E1000_ICR_DRSTA         0x40000000 /* Device Reset Asserted */
-#define E1000_ICR_INT_ASSERTED  0x80000000 /* If this bit asserted, the driver
-                                            * should claim the interrupt */
-#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* Q0 Rx desc FIFO parity error */
-#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* Q0 Tx desc FIFO parity error */
-#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity err */
-#define E1000_ICR_PB_PAR        0x00800000 /* packet buffer parity error */
-#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* Q1 Rx desc FIFO parity error */
-#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* Q1 Tx desc FIFO parity error */
-#define E1000_ICR_ALL_PARITY    0x03F00000 /* all parity error bits */
-#define E1000_ICR_DSW           0x00000020 /* FW changed the status of DISSW
-                                            * bit in the FWSM */
-#define E1000_ICR_PHYINT        0x00001000 /* LAN connected device generates
-                                            * an interrupt */
-#define E1000_ICR_DOUTSYNC      0x10000000 /* NIC DMA out of sync */
-#define E1000_ICR_EPRST         0x00100000 /* ME hardware reset occurs */
-#define E1000_ICR_RXQ0          0x00100000 /* Rx Queue 0 Interrupt */
-#define E1000_ICR_RXQ1          0x00200000 /* Rx Queue 1 Interrupt */
-#define E1000_ICR_TXQ0          0x00400000 /* Tx Queue 0 Interrupt */
-#define E1000_ICR_TXQ1          0x00800000 /* Tx Queue 1 Interrupt */
-#define E1000_ICR_OTHER         0x01000000 /* Other Interrupts */
-#define E1000_ICR_FER           0x00400000 /* Fatal Error */
+#define E1000_ICR_TXDW		0x00000001 /* Transmit desc written back */
+#define E1000_ICR_TXQE		0x00000002 /* Transmit Queue empty */
+#define E1000_ICR_LSC		0x00000004 /* Link Status Change */
+#define E1000_ICR_RXSEQ		0x00000008 /* Rx sequence error */
+#define E1000_ICR_RXDMT0	0x00000010 /* Rx desc min. threshold (0) */
+#define E1000_ICR_RXO		0x00000040 /* Rx overrun */
+#define E1000_ICR_RXT0		0x00000080 /* Rx timer intr (ring 0) */
+#define E1000_ICR_VMMB		0x00000100 /* VM MB event */
+#define E1000_ICR_MDAC		0x00000200 /* MDIO access complete */
+#define E1000_ICR_RXCFG		0x00000400 /* Rx /c/ ordered set */
+#define E1000_ICR_GPI_EN0	0x00000800 /* GP Int 0 */
+#define E1000_ICR_GPI_EN1	0x00001000 /* GP Int 1 */
+#define E1000_ICR_GPI_EN2	0x00002000 /* GP Int 2 */
+#define E1000_ICR_GPI_EN3	0x00004000 /* GP Int 3 */
+#define E1000_ICR_TXD_LOW	0x00008000
+#define E1000_ICR_SRPD		0x00010000
+#define E1000_ICR_ACK		0x00020000 /* Receive Ack frame */
+#define E1000_ICR_MNG		0x00040000 /* Manageability event */
+#define E1000_ICR_DOCK		0x00080000 /* Dock/Undock */
+#define E1000_ICR_DRSTA		0x40000000 /* Device Reset Asserted */
+/* If this bit asserted, the driver should claim the interrupt */
+#define E1000_ICR_INT_ASSERTED	0x80000000
+#define E1000_ICR_RXD_FIFO_PAR0	0x00100000 /* Q0 Rx desc FIFO parity error */
+#define E1000_ICR_TXD_FIFO_PAR0	0x00200000 /* Q0 Tx desc FIFO parity error */
+#define E1000_ICR_HOST_ARB_PAR	0x00400000 /* host arb read buffer parity err */
+#define E1000_ICR_PB_PAR	0x00800000 /* packet buffer parity error */
+#define E1000_ICR_RXD_FIFO_PAR1	0x01000000 /* Q1 Rx desc FIFO parity error */
+#define E1000_ICR_TXD_FIFO_PAR1	0x02000000 /* Q1 Tx desc FIFO parity error */
+#define E1000_ICR_ALL_PARITY	0x03F00000 /* all parity error bits */
+/* FW changed the status of DISSW bit in the FWSM */
+#define E1000_ICR_DSW		0x00000020
+/* LAN connected device generates an interrupt */
+#define E1000_ICR_PHYINT	0x00001000
+#define E1000_ICR_DOUTSYNC	0x10000000 /* NIC DMA out of sync */
+#define E1000_ICR_EPRST		0x00100000 /* ME hardware reset occurs */
+#define E1000_ICR_RXQ0		0x00100000 /* Rx Queue 0 Interrupt */
+#define E1000_ICR_RXQ1		0x00200000 /* Rx Queue 1 Interrupt */
+#define E1000_ICR_TXQ0		0x00400000 /* Tx Queue 0 Interrupt */
+#define E1000_ICR_TXQ1		0x00800000 /* Tx Queue 1 Interrupt */
+#define E1000_ICR_OTHER		0x01000000 /* Other Interrupts */
+#define E1000_ICR_FER		0x00400000 /* Fatal Error */
 
-#define E1000_ICR_THS           0x00800000 /* ICR.THS: Thermal Sensor Event*/
-#define E1000_ICR_MDDET         0x10000000 /* Malicious Driver Detect */
+#define E1000_ICR_THS		0x00800000 /* ICR.THS: Thermal Sensor Event*/
+#define E1000_ICR_MDDET		0x10000000 /* Malicious Driver Detect */
+
+#define E1000_ITR_MASK		0x000FFFFF /* ITR value bitfield */
+#define E1000_ITR_MULT		256 /* ITR mulitplier in nsec */
+
 /* PBA ECC Register */
-#define E1000_PBA_ECC_COUNTER_MASK  0xFFF00000 /* ECC counter mask */
-#define E1000_PBA_ECC_COUNTER_SHIFT 20         /* ECC counter shift value */
-#define E1000_PBA_ECC_CORR_EN   0x00000001 /* Enable ECC error correction */
-#define E1000_PBA_ECC_STAT_CLR  0x00000002 /* Clear ECC error counter */
-#define E1000_PBA_ECC_INT_EN    0x00000004 /* Enable ICR bit 5 on ECC error */
+#define E1000_PBA_ECC_COUNTER_MASK	0xFFF00000 /* ECC counter mask */
+#define E1000_PBA_ECC_COUNTER_SHIFT	20 /* ECC counter shift value */
+#define E1000_PBA_ECC_CORR_EN	0x00000001 /* Enable ECC error correction */
+#define E1000_PBA_ECC_STAT_CLR	0x00000002 /* Clear ECC error counter */
+#define E1000_PBA_ECC_INT_EN	0x00000004 /* Enable ICR bit 5 on ECC error */
 
 /* Extended Interrupt Cause Read */
-#define E1000_EICR_RX_QUEUE0    0x00000001 /* Rx Queue 0 Interrupt */
-#define E1000_EICR_RX_QUEUE1    0x00000002 /* Rx Queue 1 Interrupt */
-#define E1000_EICR_RX_QUEUE2    0x00000004 /* Rx Queue 2 Interrupt */
-#define E1000_EICR_RX_QUEUE3    0x00000008 /* Rx Queue 3 Interrupt */
-#define E1000_EICR_TX_QUEUE0    0x00000100 /* Tx Queue 0 Interrupt */
-#define E1000_EICR_TX_QUEUE1    0x00000200 /* Tx Queue 1 Interrupt */
-#define E1000_EICR_TX_QUEUE2    0x00000400 /* Tx Queue 2 Interrupt */
-#define E1000_EICR_TX_QUEUE3    0x00000800 /* Tx Queue 3 Interrupt */
-#define E1000_EICR_TCP_TIMER    0x40000000 /* TCP Timer */
-#define E1000_EICR_OTHER        0x80000000 /* Interrupt Cause Active */
+#define E1000_EICR_RX_QUEUE0	0x00000001 /* Rx Queue 0 Interrupt */
+#define E1000_EICR_RX_QUEUE1	0x00000002 /* Rx Queue 1 Interrupt */
+#define E1000_EICR_RX_QUEUE2	0x00000004 /* Rx Queue 2 Interrupt */
+#define E1000_EICR_RX_QUEUE3	0x00000008 /* Rx Queue 3 Interrupt */
+#define E1000_EICR_TX_QUEUE0	0x00000100 /* Tx Queue 0 Interrupt */
+#define E1000_EICR_TX_QUEUE1	0x00000200 /* Tx Queue 1 Interrupt */
+#define E1000_EICR_TX_QUEUE2	0x00000400 /* Tx Queue 2 Interrupt */
+#define E1000_EICR_TX_QUEUE3	0x00000800 /* Tx Queue 3 Interrupt */
+#define E1000_EICR_TCP_TIMER	0x40000000 /* TCP Timer */
+#define E1000_EICR_OTHER	0x80000000 /* Interrupt Cause Active */
 /* TCP Timer */
-#define E1000_TCPTIMER_KS       0x00000100 /* KickStart */
-#define E1000_TCPTIMER_COUNT_ENABLE       0x00000200 /* Count Enable */
-#define E1000_TCPTIMER_COUNT_FINISH       0x00000400 /* Count finish */
-#define E1000_TCPTIMER_LOOP     0x00000800 /* Loop */
+#define E1000_TCPTIMER_KS	0x00000100 /* KickStart */
+#define E1000_TCPTIMER_COUNT_ENABLE	0x00000200 /* Count Enable */
+#define E1000_TCPTIMER_COUNT_FINISH	0x00000400 /* Count finish */
+#define E1000_TCPTIMER_LOOP	0x00000800 /* Loop */
 
 /*
  * This defines the bits that are set in the Interrupt Mask
@@ -858,8 +869,8 @@
  *   o RXSEQ  = Receive Sequence Error
  */
 #define POLL_IMS_ENABLE_MASK ( \
-    E1000_IMS_RXDMT0 |    \
-    E1000_IMS_RXSEQ)
+	E1000_IMS_RXDMT0 |    \
+	E1000_IMS_RXSEQ)
 
 /*
  * This defines the bits that are set in the Interrupt Mask
@@ -871,142 +882,142 @@
  *   o LSC    = Link Status Change
  */
 #define IMS_ENABLE_MASK ( \
-    E1000_IMS_RXT0   |    \
-    E1000_IMS_TXDW   |    \
-    E1000_IMS_RXDMT0 |    \
-    E1000_IMS_RXSEQ  |    \
-    E1000_IMS_LSC)
+	E1000_IMS_RXT0   |    \
+	E1000_IMS_TXDW   |    \
+	E1000_IMS_RXDMT0 |    \
+	E1000_IMS_RXSEQ  |    \
+	E1000_IMS_LSC)
 
 /* Interrupt Mask Set */
-#define E1000_IMS_TXDW      E1000_ICR_TXDW      /* Tx desc written back */
-#define E1000_IMS_TXQE      E1000_ICR_TXQE      /* Transmit Queue empty */
-#define E1000_IMS_LSC       E1000_ICR_LSC       /* Link Status Change */
-#define E1000_IMS_VMMB      E1000_ICR_VMMB      /* Mail box activity */
-#define E1000_IMS_RXSEQ     E1000_ICR_RXSEQ     /* Rx sequence error */
-#define E1000_IMS_RXDMT0    E1000_ICR_RXDMT0    /* Rx desc min. threshold */
-#define E1000_IMS_RXO       E1000_ICR_RXO       /* Rx overrun */
-#define E1000_IMS_RXT0      E1000_ICR_RXT0      /* Rx timer intr */
-#define E1000_IMS_MDAC      E1000_ICR_MDAC      /* MDIO access complete */
-#define E1000_IMS_RXCFG     E1000_ICR_RXCFG     /* Rx /c/ ordered set */
-#define E1000_IMS_GPI_EN0   E1000_ICR_GPI_EN0   /* GP Int 0 */
-#define E1000_IMS_GPI_EN1   E1000_ICR_GPI_EN1   /* GP Int 1 */
-#define E1000_IMS_GPI_EN2   E1000_ICR_GPI_EN2   /* GP Int 2 */
-#define E1000_IMS_GPI_EN3   E1000_ICR_GPI_EN3   /* GP Int 3 */
-#define E1000_IMS_TXD_LOW   E1000_ICR_TXD_LOW
-#define E1000_IMS_SRPD      E1000_ICR_SRPD
-#define E1000_IMS_ACK       E1000_ICR_ACK       /* Receive Ack frame */
-#define E1000_IMS_MNG       E1000_ICR_MNG       /* Manageability event */
-#define E1000_IMS_DOCK      E1000_ICR_DOCK      /* Dock/Undock */
-#define E1000_IMS_DRSTA     E1000_ICR_DRSTA     /* Device Reset Asserted */
-#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO
-                                                         * parity error */
-#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO
-                                                         * parity error */
-#define E1000_IMS_HOST_ARB_PAR  E1000_ICR_HOST_ARB_PAR  /* host arb read buffer
-                                                         * parity error */
-#define E1000_IMS_PB_PAR        E1000_ICR_PB_PAR        /* packet buffer parity
-                                                         * error */
-#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* Q1 Rx desc FIFO
-                                                         * parity error */
-#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* Q1 Tx desc FIFO
-                                                         * parity error */
-#define E1000_IMS_DSW       E1000_ICR_DSW
-#define E1000_IMS_PHYINT    E1000_ICR_PHYINT
-#define E1000_IMS_DOUTSYNC  E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
-#define E1000_IMS_EPRST     E1000_ICR_EPRST
-#define E1000_IMS_RXQ0          E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */
-#define E1000_IMS_RXQ1          E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */
-#define E1000_IMS_TXQ0          E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */
-#define E1000_IMS_TXQ1          E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */
-#define E1000_IMS_OTHER         E1000_ICR_OTHER /* Other Interrupts */
-#define E1000_IMS_FER           E1000_ICR_FER /* Fatal Error */
+#define E1000_IMS_TXDW		E1000_ICR_TXDW    /* Tx desc written back */
+#define E1000_IMS_TXQE		E1000_ICR_TXQE    /* Transmit Queue empty */
+#define E1000_IMS_LSC		E1000_ICR_LSC     /* Link Status Change */
+#define E1000_IMS_VMMB		E1000_ICR_VMMB    /* Mail box activity */
+#define E1000_IMS_RXSEQ		E1000_ICR_RXSEQ   /* Rx sequence error */
+#define E1000_IMS_RXDMT0	E1000_ICR_RXDMT0  /* Rx desc min. threshold */
+#define E1000_IMS_RXO		E1000_ICR_RXO     /* Rx overrun */
+#define E1000_IMS_RXT0		E1000_ICR_RXT0    /* Rx timer intr */
+#define E1000_IMS_MDAC		E1000_ICR_MDAC    /* MDIO access complete */
+#define E1000_IMS_RXCFG		E1000_ICR_RXCFG   /* Rx /c/ ordered set */
+#define E1000_IMS_GPI_EN0	E1000_ICR_GPI_EN0 /* GP Int 0 */
+#define E1000_IMS_GPI_EN1	E1000_ICR_GPI_EN1 /* GP Int 1 */
+#define E1000_IMS_GPI_EN2	E1000_ICR_GPI_EN2 /* GP Int 2 */
+#define E1000_IMS_GPI_EN3	E1000_ICR_GPI_EN3 /* GP Int 3 */
+#define E1000_IMS_TXD_LOW	E1000_ICR_TXD_LOW
+#define E1000_IMS_SRPD		E1000_ICR_SRPD
+#define E1000_IMS_ACK		E1000_ICR_ACK     /* Receive Ack frame */
+#define E1000_IMS_MNG		E1000_ICR_MNG     /* Manageability event */
+#define E1000_IMS_DOCK		E1000_ICR_DOCK    /* Dock/Undock */
+#define E1000_IMS_DRSTA		E1000_ICR_DRSTA   /* Device Reset Asserted */
+/* Q0 Rx desc FIFO parity error */
+#define E1000_IMS_RXD_FIFO_PAR0	E1000_ICR_RXD_FIFO_PAR0
+/* Q0 Tx desc FIFO parity error */
+#define E1000_IMS_TXD_FIFO_PAR0	E1000_ICR_TXD_FIFO_PAR0
+/* host arb read buffer parity error */
+#define E1000_IMS_HOST_ARB_PAR	E1000_ICR_HOST_ARB_PAR
+/* packet buffer parity error */
+#define E1000_IMS_PB_PAR	E1000_ICR_PB_PAR
+/* Q1 Rx desc FIFO parity error */
+#define E1000_IMS_RXD_FIFO_PAR1	E1000_ICR_RXD_FIFO_PAR1
+/* Q1 Tx desc FIFO parity error */
+#define E1000_IMS_TXD_FIFO_PAR1	E1000_ICR_TXD_FIFO_PAR1
+#define E1000_IMS_DSW		E1000_ICR_DSW
+#define E1000_IMS_PHYINT	E1000_ICR_PHYINT
+#define E1000_IMS_DOUTSYNC	E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
+#define E1000_IMS_EPRST		E1000_ICR_EPRST
+#define E1000_IMS_RXQ0		E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */
+#define E1000_IMS_RXQ1		E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */
+#define E1000_IMS_TXQ0		E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */
+#define E1000_IMS_TXQ1		E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */
+#define E1000_IMS_OTHER		E1000_ICR_OTHER /* Other Interrupts */
+#define E1000_IMS_FER		E1000_ICR_FER /* Fatal Error */
 
-#define E1000_IMS_THS           E1000_ICR_THS /* ICR.TS: Thermal Sensor Event*/
-#define E1000_IMS_MDDET         E1000_ICR_MDDET /* Malicious Driver Detect */
+#define E1000_IMS_THS		E1000_ICR_THS /* ICR.TS: Thermal Sensor Event*/
+#define E1000_IMS_MDDET		E1000_ICR_MDDET /* Malicious Driver Detect */
 /* Extended Interrupt Mask Set */
-#define E1000_EIMS_RX_QUEUE0    E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
-#define E1000_EIMS_RX_QUEUE1    E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
-#define E1000_EIMS_RX_QUEUE2    E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
-#define E1000_EIMS_RX_QUEUE3    E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
-#define E1000_EIMS_TX_QUEUE0    E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
-#define E1000_EIMS_TX_QUEUE1    E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
-#define E1000_EIMS_TX_QUEUE2    E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
-#define E1000_EIMS_TX_QUEUE3    E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
-#define E1000_EIMS_TCP_TIMER    E1000_EICR_TCP_TIMER /* TCP Timer */
-#define E1000_EIMS_OTHER        E1000_EICR_OTHER   /* Interrupt Cause Active */
+#define E1000_EIMS_RX_QUEUE0	E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
+#define E1000_EIMS_RX_QUEUE1	E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
+#define E1000_EIMS_RX_QUEUE2	E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
+#define E1000_EIMS_RX_QUEUE3	E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
+#define E1000_EIMS_TX_QUEUE0	E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
+#define E1000_EIMS_TX_QUEUE1	E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
+#define E1000_EIMS_TX_QUEUE2	E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
+#define E1000_EIMS_TX_QUEUE3	E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
+#define E1000_EIMS_TCP_TIMER	E1000_EICR_TCP_TIMER /* TCP Timer */
+#define E1000_EIMS_OTHER	E1000_EICR_OTHER   /* Interrupt Cause Active */
 
 /* Interrupt Cause Set */
-#define E1000_ICS_TXDW      E1000_ICR_TXDW      /* Tx desc written back */
-#define E1000_ICS_TXQE      E1000_ICR_TXQE      /* Transmit Queue empty */
-#define E1000_ICS_LSC       E1000_ICR_LSC       /* Link Status Change */
-#define E1000_ICS_RXSEQ     E1000_ICR_RXSEQ     /* Rx sequence error */
-#define E1000_ICS_RXDMT0    E1000_ICR_RXDMT0    /* Rx desc min. threshold */
-#define E1000_ICS_RXO       E1000_ICR_RXO       /* Rx overrun */
-#define E1000_ICS_RXT0      E1000_ICR_RXT0      /* Rx timer intr */
-#define E1000_ICS_MDAC      E1000_ICR_MDAC      /* MDIO access complete */
-#define E1000_ICS_RXCFG     E1000_ICR_RXCFG     /* Rx /c/ ordered set */
-#define E1000_ICS_GPI_EN0   E1000_ICR_GPI_EN0   /* GP Int 0 */
-#define E1000_ICS_GPI_EN1   E1000_ICR_GPI_EN1   /* GP Int 1 */
-#define E1000_ICS_GPI_EN2   E1000_ICR_GPI_EN2   /* GP Int 2 */
-#define E1000_ICS_GPI_EN3   E1000_ICR_GPI_EN3   /* GP Int 3 */
-#define E1000_ICS_TXD_LOW   E1000_ICR_TXD_LOW
-#define E1000_ICS_SRPD      E1000_ICR_SRPD
-#define E1000_ICS_ACK       E1000_ICR_ACK       /* Receive Ack frame */
-#define E1000_ICS_MNG       E1000_ICR_MNG       /* Manageability event */
-#define E1000_ICS_DOCK      E1000_ICR_DOCK      /* Dock/Undock */
-#define E1000_ICS_DRSTA     E1000_ICR_DRSTA     /* Device Reset Aserted */
-#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO
-                                                         * parity error */
-#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO
-                                                         * parity error */
-#define E1000_ICS_HOST_ARB_PAR  E1000_ICR_HOST_ARB_PAR  /* host arb read buffer
-                                                         * parity error */
-#define E1000_ICS_PB_PAR        E1000_ICR_PB_PAR        /* packet buffer parity
-                                                         * error */
-#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* Q1 Rx desc FIFO
-                                                         * parity error */
-#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* Q1 Tx desc FIFO
-                                                         * parity error */
-#define E1000_ICS_DSW       E1000_ICR_DSW
-#define E1000_ICS_DOUTSYNC  E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
-#define E1000_ICS_PHYINT    E1000_ICR_PHYINT
-#define E1000_ICS_EPRST     E1000_ICR_EPRST
+#define E1000_ICS_TXDW		E1000_ICR_TXDW      /* Tx desc written back */
+#define E1000_ICS_TXQE		E1000_ICR_TXQE      /* Transmit Queue empty */
+#define E1000_ICS_LSC		E1000_ICR_LSC       /* Link Status Change */
+#define E1000_ICS_RXSEQ		E1000_ICR_RXSEQ     /* Rx sequence error */
+#define E1000_ICS_RXDMT0	E1000_ICR_RXDMT0    /* Rx desc min. threshold */
+#define E1000_ICS_RXO		E1000_ICR_RXO       /* Rx overrun */
+#define E1000_ICS_RXT0		E1000_ICR_RXT0      /* Rx timer intr */
+#define E1000_ICS_MDAC		E1000_ICR_MDAC      /* MDIO access complete */
+#define E1000_ICS_RXCFG		E1000_ICR_RXCFG     /* Rx /c/ ordered set */
+#define E1000_ICS_GPI_EN0	E1000_ICR_GPI_EN0   /* GP Int 0 */
+#define E1000_ICS_GPI_EN1	E1000_ICR_GPI_EN1   /* GP Int 1 */
+#define E1000_ICS_GPI_EN2	E1000_ICR_GPI_EN2   /* GP Int 2 */
+#define E1000_ICS_GPI_EN3	E1000_ICR_GPI_EN3   /* GP Int 3 */
+#define E1000_ICS_TXD_LOW	E1000_ICR_TXD_LOW
+#define E1000_ICS_SRPD		E1000_ICR_SRPD
+#define E1000_ICS_ACK		E1000_ICR_ACK       /* Receive Ack frame */
+#define E1000_ICS_MNG		E1000_ICR_MNG       /* Manageability event */
+#define E1000_ICS_DOCK		E1000_ICR_DOCK      /* Dock/Undock */
+#define E1000_ICS_DRSTA		E1000_ICR_DRSTA     /* Device Reset Aserted */
+/* Q0 Rx desc FIFO parity error */
+#define E1000_ICS_RXD_FIFO_PAR0	E1000_ICR_RXD_FIFO_PAR0
+/* Q0 Tx desc FIFO parity error */
+#define E1000_ICS_TXD_FIFO_PAR0	E1000_ICR_TXD_FIFO_PAR0
+/* host arb read buffer parity error */
+#define E1000_ICS_HOST_ARB_PAR	E1000_ICR_HOST_ARB_PAR
+/* packet buffer parity error */
+#define E1000_ICS_PB_PAR	E1000_ICR_PB_PAR
+/* Q1 Rx desc FIFO parity error */
+#define E1000_ICS_RXD_FIFO_PAR1	E1000_ICR_RXD_FIFO_PAR1
+/* Q1 Tx desc FIFO parity error */
+#define E1000_ICS_TXD_FIFO_PAR1	E1000_ICR_TXD_FIFO_PAR1
+#define E1000_ICS_DSW		E1000_ICR_DSW
+#define E1000_ICS_DOUTSYNC	E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
+#define E1000_ICS_PHYINT	E1000_ICR_PHYINT
+#define E1000_ICS_EPRST		E1000_ICR_EPRST
 
 /* Extended Interrupt Cause Set */
-#define E1000_EICS_RX_QUEUE0    E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
-#define E1000_EICS_RX_QUEUE1    E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
-#define E1000_EICS_RX_QUEUE2    E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
-#define E1000_EICS_RX_QUEUE3    E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
-#define E1000_EICS_TX_QUEUE0    E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
-#define E1000_EICS_TX_QUEUE1    E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
-#define E1000_EICS_TX_QUEUE2    E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
-#define E1000_EICS_TX_QUEUE3    E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
-#define E1000_EICS_TCP_TIMER    E1000_EICR_TCP_TIMER /* TCP Timer */
-#define E1000_EICS_OTHER        E1000_EICR_OTHER   /* Interrupt Cause Active */
+#define E1000_EICS_RX_QUEUE0	E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
+#define E1000_EICS_RX_QUEUE1	E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
+#define E1000_EICS_RX_QUEUE2	E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
+#define E1000_EICS_RX_QUEUE3	E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
+#define E1000_EICS_TX_QUEUE0	E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
+#define E1000_EICS_TX_QUEUE1	E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
+#define E1000_EICS_TX_QUEUE2	E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
+#define E1000_EICS_TX_QUEUE3	E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
+#define E1000_EICS_TCP_TIMER	E1000_EICR_TCP_TIMER /* TCP Timer */
+#define E1000_EICS_OTHER	E1000_EICR_OTHER   /* Interrupt Cause Active */
 
-#define E1000_EITR_ITR_INT_MASK 0x0000FFFF
+#define E1000_EITR_ITR_INT_MASK	0x0000FFFF
 /* E1000_EITR_CNT_IGNR is only for 82576 and newer */
-#define E1000_EITR_CNT_IGNR     0x80000000 /* Don't reset counters on write */
+#define E1000_EITR_CNT_IGNR	0x80000000 /* Don't reset counters on write */
 
 /* Transmit Descriptor Control */
-#define E1000_TXDCTL_PTHRESH    0x0000003F /* TXDCTL Prefetch Threshold */
-#define E1000_TXDCTL_HTHRESH    0x00003F00 /* TXDCTL Host Threshold */
-#define E1000_TXDCTL_WTHRESH    0x003F0000 /* TXDCTL Writeback Threshold */
-#define E1000_TXDCTL_GRAN       0x01000000 /* TXDCTL Granularity */
-#define E1000_TXDCTL_LWTHRESH   0xFE000000 /* TXDCTL Low Threshold */
-#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
+#define E1000_TXDCTL_PTHRESH	0x0000003F /* TXDCTL Prefetch Threshold */
+#define E1000_TXDCTL_HTHRESH	0x00003F00 /* TXDCTL Host Threshold */
+#define E1000_TXDCTL_WTHRESH	0x003F0000 /* TXDCTL Writeback Threshold */
+#define E1000_TXDCTL_GRAN	0x01000000 /* TXDCTL Granularity */
+#define E1000_TXDCTL_LWTHRESH	0xFE000000 /* TXDCTL Low Threshold */
+#define E1000_TXDCTL_FULL_TX_DESC_WB	0x01010000 /* GRAN=1, WTHRESH=1 */
 #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
 /* Enable the counting of descriptors still to be processed. */
-#define E1000_TXDCTL_COUNT_DESC 0x00400000
+#define E1000_TXDCTL_COUNT_DESC	0x00400000
 
 /* Flow Control Constants */
-#define FLOW_CONTROL_ADDRESS_LOW  0x00C28001
-#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
-#define FLOW_CONTROL_TYPE         0x8808
+#define FLOW_CONTROL_ADDRESS_LOW	0x00C28001
+#define FLOW_CONTROL_ADDRESS_HIGH	0x00000100
+#define FLOW_CONTROL_TYPE		0x8808
 
 /* 802.1q VLAN Packet Size */
-#define VLAN_TAG_SIZE              4    /* 802.3ac tag (not DMA'd) */
-#define E1000_VLAN_FILTER_TBL_SIZE 128  /* VLAN Filter Table (4096 bits) */
+#define VLAN_TAG_SIZE			4    /* 802.3ac tag (not DMA'd) */
+#define E1000_VLAN_FILTER_TBL_SIZE	128  /* VLAN Filter Table (4096 bits) */
 
 /* Receive Address */
 /*
@@ -1016,529 +1027,550 @@
  * (RAR[15]) for our directed address used by controllers with
  * manageability enabled, allowing us room for 15 multicast addresses.
  */
-#define E1000_RAR_ENTRIES     15
-#define E1000_RAH_AV  0x80000000        /* Receive descriptor valid */
-#define E1000_RAL_MAC_ADDR_LEN 4
-#define E1000_RAH_MAC_ADDR_LEN 2
-#define E1000_RAH_QUEUE_MASK_82575 0x000C0000
-#define E1000_RAH_POOL_MASK     0x03FC0000
-#define E1000_RAH_POOL_SHIFT    18
-#define E1000_RAH_POOL_1        0x00040000
+#define E1000_RAR_ENTRIES	15
+#define E1000_RAH_AV		0x80000000 /* Receive descriptor valid */
+#define E1000_RAL_MAC_ADDR_LEN	4
+#define E1000_RAH_MAC_ADDR_LEN	2
+#define E1000_RAH_QUEUE_MASK_82575	0x000C0000
+#define E1000_RAH_POOL_MASK	0x03FC0000
+#define E1000_RAH_POOL_SHIFT	18
+#define E1000_RAH_POOL_1	0x00040000
 
 /* Error Codes */
-#define E1000_SUCCESS      0
-#define E1000_ERR_NVM      1
-#define E1000_ERR_PHY      2
-#define E1000_ERR_CONFIG   3
-#define E1000_ERR_PARAM    4
-#define E1000_ERR_MAC_INIT 5
-#define E1000_ERR_PHY_TYPE 6
-#define E1000_ERR_RESET   9
-#define E1000_ERR_MASTER_REQUESTS_PENDING 10
-#define E1000_ERR_HOST_INTERFACE_COMMAND 11
-#define E1000_BLK_PHY_RESET   12
-#define E1000_ERR_SWFW_SYNC 13
-#define E1000_NOT_IMPLEMENTED 14
-#define E1000_ERR_MBX      15
-#define E1000_ERR_INVALID_ARGUMENT  16
-#define E1000_ERR_NO_SPACE          17
-#define E1000_ERR_NVM_PBA_SECTION   18
+#define E1000_SUCCESS			0
+#define E1000_ERR_NVM			1
+#define E1000_ERR_PHY			2
+#define E1000_ERR_CONFIG		3
+#define E1000_ERR_PARAM			4
+#define E1000_ERR_MAC_INIT		5
+#define E1000_ERR_PHY_TYPE		6
+#define E1000_ERR_RESET			9
+#define E1000_ERR_MASTER_REQUESTS_PENDING	10
+#define E1000_ERR_HOST_INTERFACE_COMMAND	11
+#define E1000_BLK_PHY_RESET		12
+#define E1000_ERR_SWFW_SYNC		13
+#define E1000_NOT_IMPLEMENTED		14
+#define E1000_ERR_MBX			15
+#define E1000_ERR_INVALID_ARGUMENT	16
+#define E1000_ERR_NO_SPACE		17
+#define E1000_ERR_NVM_PBA_SECTION	18
+#define E1000_ERR_I2C			19
+#define E1000_ERR_INVM_VALUE_NOT_FOUND	20
 
 /* Loop limit on how long we wait for auto-negotiation to complete */
-#define FIBER_LINK_UP_LIMIT               50
-#define COPPER_LINK_UP_LIMIT              10
-#define PHY_AUTO_NEG_LIMIT                45
-#define PHY_FORCE_LIMIT                   20
+#define FIBER_LINK_UP_LIMIT		50
+#define COPPER_LINK_UP_LIMIT		10
+#define PHY_AUTO_NEG_LIMIT		45
+#define PHY_FORCE_LIMIT			20
 /* Number of 100 microseconds we wait for PCI Express master disable */
-#define MASTER_DISABLE_TIMEOUT      800
+#define MASTER_DISABLE_TIMEOUT		800
 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
-#define PHY_CFG_TIMEOUT             100
+#define PHY_CFG_TIMEOUT			100
 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
-#define MDIO_OWNERSHIP_TIMEOUT      10
+#define MDIO_OWNERSHIP_TIMEOUT		10
 /* Number of milliseconds for NVM auto read done after MAC reset. */
-#define AUTO_READ_DONE_TIMEOUT      10
+#define AUTO_READ_DONE_TIMEOUT		10
 
 /* Flow Control */
-#define E1000_FCRTH_RTH  0x0000FFF8     /* Mask Bits[15:3] for RTH */
-#define E1000_FCRTH_XFCE 0x80000000     /* External Flow Control Enable */
-#define E1000_FCRTL_RTL  0x0000FFF8     /* Mask Bits[15:3] for RTL */
-#define E1000_FCRTL_XONE 0x80000000     /* Enable XON frame transmission */
+#define E1000_FCRTH_RTH		0x0000FFF8 /* Mask Bits[15:3] for RTH */
+#define E1000_FCRTH_XFCE	0x80000000 /* External Flow Control Enable */
+#define E1000_FCRTL_RTL		0x0000FFF8 /* Mask Bits[15:3] for RTL */
+#define E1000_FCRTL_XONE	0x80000000 /* Enable XON frame transmission */
 
 /* Transmit Configuration Word */
-#define E1000_TXCW_FD         0x00000020        /* TXCW full duplex */
-#define E1000_TXCW_HD         0x00000040        /* TXCW half duplex */
-#define E1000_TXCW_PAUSE      0x00000080        /* TXCW sym pause request */
-#define E1000_TXCW_ASM_DIR    0x00000100        /* TXCW astm pause direction */
-#define E1000_TXCW_PAUSE_MASK 0x00000180        /* TXCW pause request mask */
-#define E1000_TXCW_RF         0x00003000        /* TXCW remote fault */
-#define E1000_TXCW_NP         0x00008000        /* TXCW next page */
-#define E1000_TXCW_CW         0x0000ffff        /* TxConfigWord mask */
-#define E1000_TXCW_TXC        0x40000000        /* Transmit Config control */
-#define E1000_TXCW_ANE        0x80000000        /* Auto-neg enable */
+#define E1000_TXCW_FD		0x00000020 /* TXCW full duplex */
+#define E1000_TXCW_HD		0x00000040 /* TXCW half duplex */
+#define E1000_TXCW_PAUSE	0x00000080 /* TXCW sym pause request */
+#define E1000_TXCW_ASM_DIR	0x00000100 /* TXCW astm pause direction */
+#define E1000_TXCW_PAUSE_MASK	0x00000180 /* TXCW pause request mask */
+#define E1000_TXCW_RF		0x00003000 /* TXCW remote fault */
+#define E1000_TXCW_NP		0x00008000 /* TXCW next page */
+#define E1000_TXCW_CW		0x0000ffff /* TxConfigWord mask */
+#define E1000_TXCW_TXC		0x40000000 /* Transmit Config control */
+#define E1000_TXCW_ANE		0x80000000 /* Auto-neg enable */
 
 /* Receive Configuration Word */
-#define E1000_RXCW_CW         0x0000ffff        /* RxConfigWord mask */
-#define E1000_RXCW_NC         0x04000000        /* Receive config no carrier */
-#define E1000_RXCW_IV         0x08000000        /* Receive config invalid */
-#define E1000_RXCW_CC         0x10000000        /* Receive config change */
-#define E1000_RXCW_C          0x20000000        /* Receive config */
-#define E1000_RXCW_SYNCH      0x40000000        /* Receive config synch */
-#define E1000_RXCW_ANC        0x80000000        /* Auto-neg complete */
+#define E1000_RXCW_CW		0x0000ffff /* RxConfigWord mask */
+#define E1000_RXCW_NC		0x04000000 /* Receive config no carrier */
+#define E1000_RXCW_IV		0x08000000 /* Receive config invalid */
+#define E1000_RXCW_CC		0x10000000 /* Receive config change */
+#define E1000_RXCW_C		0x20000000 /* Receive config */
+#define E1000_RXCW_SYNCH	0x40000000 /* Receive config synch */
+#define E1000_RXCW_ANC		0x80000000 /* Auto-neg complete */
 
-#define E1000_TSYNCTXCTL_VALID    0x00000001 /* Tx timestamp valid */
-#define E1000_TSYNCTXCTL_ENABLED  0x00000010 /* enable Tx timestamping */
+#define E1000_TSYNCTXCTL_VALID		0x00000001 /* Tx timestamp valid */
+#define E1000_TSYNCTXCTL_ENABLED	0x00000010 /* enable Tx timestamping */
 
-#define E1000_TSYNCRXCTL_VALID      0x00000001 /* Rx timestamp valid */
-#define E1000_TSYNCRXCTL_TYPE_MASK  0x0000000E /* Rx type mask */
-#define E1000_TSYNCRXCTL_TYPE_L2_V2       0x00
-#define E1000_TSYNCRXCTL_TYPE_L4_V1       0x02
-#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2    0x04
-#define E1000_TSYNCRXCTL_TYPE_ALL         0x08
-#define E1000_TSYNCRXCTL_TYPE_EVENT_V2    0x0A
-#define E1000_TSYNCRXCTL_ENABLED    0x00000010 /* enable Rx timestamping */
+#define E1000_TSYNCRXCTL_VALID		0x00000001 /* Rx timestamp valid */
+#define E1000_TSYNCRXCTL_TYPE_MASK	0x0000000E /* Rx type mask */
+#define E1000_TSYNCRXCTL_TYPE_L2_V2	0x00
+#define E1000_TSYNCRXCTL_TYPE_L4_V1	0x02
+#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2	0x04
+#define E1000_TSYNCRXCTL_TYPE_ALL	0x08
+#define E1000_TSYNCRXCTL_TYPE_EVENT_V2	0x0A
+#define E1000_TSYNCRXCTL_ENABLED	0x00000010 /* enable Rx timestamping */
 
-#define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK   0x000000FF
-#define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE       0x00
-#define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE  0x01
-#define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE   0x02
-#define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03
-#define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04
+#define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK		0x000000FF
+#define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE		0x00
+#define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE	0x01
+#define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE	0x02
+#define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE	0x03
+#define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE	0x04
 
-#define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK               0x00000F00
-#define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE                 0x0000
-#define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE            0x0100
-#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE       0x0200
-#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE      0x0300
-#define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE             0x0800
-#define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE           0x0900
-#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE  0x0A00
-#define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE             0x0B00
-#define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE           0x0C00
-#define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE           0x0D00
+#define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK		0x00000F00
+#define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE		0x0000
+#define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE	0x0100
+#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE	0x0200
+#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE	0x0300
+#define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE	0x0800
+#define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE	0x0900
+#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00
+#define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE	0x0B00
+#define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE	0x0C00
+#define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE	0x0D00
 
-#define E1000_TIMINCA_16NS_SHIFT 24
+#define E1000_TIMINCA_16NS_SHIFT	24
 /* TUPLE Filtering Configuration */
-#define E1000_TTQF_DISABLE_MASK   0xF0008000     /* TTQF Disable Mask */
-#define E1000_TTQF_QUEUE_ENABLE   0x100          /* TTQF Queue Enable Bit */
-#define E1000_TTQF_PROTOCOL_MASK  0xFF           /* TTQF Protocol Mask */
+#define E1000_TTQF_DISABLE_MASK		0xF0008000 /* TTQF Disable Mask */
+#define E1000_TTQF_QUEUE_ENABLE		0x100   /* TTQF Queue Enable Bit */
+#define E1000_TTQF_PROTOCOL_MASK	0xFF    /* TTQF Protocol Mask */
 /* TTQF TCP Bit, shift with E1000_TTQF_PROTOCOL SHIFT */
-#define E1000_TTQF_PROTOCOL_TCP   0x0
+#define E1000_TTQF_PROTOCOL_TCP		0x0
 /* TTQF UDP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
-#define E1000_TTQF_PROTOCOL_UDP   0x1
+#define E1000_TTQF_PROTOCOL_UDP		0x1
 /* TTQF SCTP Bit, shift with E1000_TTQF_PROTOCOL_SHIFT */
-#define E1000_TTQF_PROTOCOL_SCTP  0x2
-#define E1000_TTQF_PROTOCOL_SHIFT 5              /* TTQF Protocol Shift */
-#define E1000_TTQF_QUEUE_SHIFT    16             /* TTQF Queue Shfit */
-#define E1000_TTQF_RX_QUEUE_MASK  0x70000        /* TTQF Queue Mask */
-#define E1000_TTQF_MASK_ENABLE    0x10000000     /* TTQF Mask Enable Bit */
-#define E1000_IMIR_CLEAR_MASK     0xF001FFFF     /* IMIR Reg Clear Mask */
-#define E1000_IMIR_PORT_BYPASS    0x20000        /* IMIR Port Bypass Bit */
-#define E1000_IMIR_PRIORITY_SHIFT 29             /* IMIR Priority Shift */
-#define E1000_IMIREXT_CLEAR_MASK  0x7FFFF        /* IMIREXT Reg Clear Mask */
+#define E1000_TTQF_PROTOCOL_SCTP	0x2
+#define E1000_TTQF_PROTOCOL_SHIFT	5       /* TTQF Protocol Shift */
+#define E1000_TTQF_QUEUE_SHIFT		16      /* TTQF Queue Shfit */
+#define E1000_TTQF_RX_QUEUE_MASK	0x70000 /* TTQF Queue Mask */
+#define E1000_TTQF_MASK_ENABLE		0x10000000 /* TTQF Mask Enable Bit */
+#define E1000_IMIR_CLEAR_MASK		0xF001FFFF /* IMIR Reg Clear Mask */
+#define E1000_IMIR_PORT_BYPASS		0x20000 /* IMIR Port Bypass Bit */
+#define E1000_IMIR_PRIORITY_SHIFT	29 /* IMIR Priority Shift */
+#define E1000_IMIREXT_CLEAR_MASK	0x7FFFF /* IMIREXT Reg Clear Mask */
 
-#define E1000_MDICNFG_EXT_MDIO    0x80000000      /* MDI ext/int destination */
-#define E1000_MDICNFG_COM_MDIO    0x40000000      /* MDI shared w/ lan 0 */
-#define E1000_MDICNFG_PHY_MASK    0x03E00000
-#define E1000_MDICNFG_PHY_SHIFT   21
+#define E1000_MDICNFG_EXT_MDIO		0x80000000 /* MDI ext/int destination */
+#define E1000_MDICNFG_COM_MDIO		0x40000000 /* MDI shared w/ lan 0 */
+#define E1000_MDICNFG_PHY_MASK		0x03E00000
+#define E1000_MDICNFG_PHY_SHIFT		21
 
-#define E1000_THSTAT_LOW_EVENT      0x20000000  /* Low thermal threshold */
-#define E1000_THSTAT_MID_EVENT      0x00200000  /* Mid thermal threshold */
-#define E1000_THSTAT_HIGH_EVENT     0x00002000  /* High thermal threshold */
-#define E1000_THSTAT_PWR_DOWN       0x00000001  /* Power Down Event */
-#define E1000_THSTAT_LINK_THROTTLE  0x00000002  /* Link Speed Throttle Event */
+#define E1000_THSTAT_LOW_EVENT		0x20000000 /* Low thermal threshold */
+#define E1000_THSTAT_MID_EVENT		0x00200000 /* Mid thermal threshold */
+#define E1000_THSTAT_HIGH_EVENT		0x00002000 /* High thermal threshold */
+#define E1000_THSTAT_PWR_DOWN		0x00000001 /* Power Down Event */
+#define E1000_THSTAT_LINK_THROTTLE	0x00000002 /* Link Spd Throttle Event */
 
-/* Powerville EEE defines */
-#define E1000_IPCNFG_EEE_1G_AN      0x00000008  /* IPCNFG EEE Enable 1G AN */
-#define E1000_IPCNFG_EEE_100M_AN    0x00000004  /* IPCNFG EEE Enable 100M AN */
-#define E1000_EEER_TX_LPI_EN        0x00010000  /* EEER Tx LPI Enable */
-#define E1000_EEER_RX_LPI_EN        0x00020000  /* EEER Rx LPI Enable */
-#define E1000_EEER_LPI_FC           0x00040000  /* EEER Enable on Flow Control*/
+/* I350 EEE defines */
+#define E1000_IPCNFG_EEE_1G_AN		0x00000008 /* IPCNFG EEE Ena 1G AN */
+#define E1000_IPCNFG_EEE_100M_AN	0x00000004 /* IPCNFG EEE Ena 100M AN */
+#define E1000_EEER_TX_LPI_EN		0x00010000 /* EEER Tx LPI Enable */
+#define E1000_EEER_RX_LPI_EN		0x00020000 /* EEER Rx LPI Enable */
+#define E1000_EEER_LPI_FC		0x00040000 /* EEER Ena on Flow Cntrl */
 /* EEE status */
-#define E1000_EEER_EEE_NEG          0x20000000  /* EEE capability negotiated */
-#define E1000_EEER_RX_LPI_STATUS    0x40000000  /* Rx in LPI state */
-#define E1000_EEER_TX_LPI_STATUS    0x80000000  /* Tx in LPI state */
+#define E1000_EEER_EEE_NEG		0x20000000 /* EEE capability nego */
+#define E1000_EEER_RX_LPI_STATUS	0x40000000 /* Rx in LPI state */
+#define E1000_EEER_TX_LPI_STATUS	0x80000000 /* Tx in LPI state */
 
 /* PCI Express Control */
-#define E1000_GCR_RXD_NO_SNOOP          0x00000001
-#define E1000_GCR_RXDSCW_NO_SNOOP       0x00000002
-#define E1000_GCR_RXDSCR_NO_SNOOP       0x00000004
-#define E1000_GCR_TXD_NO_SNOOP          0x00000008
-#define E1000_GCR_TXDSCW_NO_SNOOP       0x00000010
-#define E1000_GCR_TXDSCR_NO_SNOOP       0x00000020
-#define E1000_GCR_CMPL_TMOUT_MASK       0x0000F000
-#define E1000_GCR_CMPL_TMOUT_10ms       0x00001000
-#define E1000_GCR_CMPL_TMOUT_RESEND     0x00010000
-#define E1000_GCR_CAP_VER2              0x00040000
+#define E1000_GCR_RXD_NO_SNOOP		0x00000001
+#define E1000_GCR_RXDSCW_NO_SNOOP	0x00000002
+#define E1000_GCR_RXDSCR_NO_SNOOP	0x00000004
+#define E1000_GCR_TXD_NO_SNOOP		0x00000008
+#define E1000_GCR_TXDSCW_NO_SNOOP	0x00000010
+#define E1000_GCR_TXDSCR_NO_SNOOP	0x00000020
+#define E1000_GCR_CMPL_TMOUT_MASK	0x0000F000
+#define E1000_GCR_CMPL_TMOUT_10ms	0x00001000
+#define E1000_GCR_CMPL_TMOUT_RESEND	0x00010000
+#define E1000_GCR_CAP_VER2		0x00040000
 
-#define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP         | \
-                           E1000_GCR_RXDSCW_NO_SNOOP      | \
-                           E1000_GCR_RXDSCR_NO_SNOOP      | \
-                           E1000_GCR_TXD_NO_SNOOP         | \
-                           E1000_GCR_TXDSCW_NO_SNOOP      | \
-                           E1000_GCR_TXDSCR_NO_SNOOP)
+#define PCIE_NO_SNOOP_ALL	(E1000_GCR_RXD_NO_SNOOP | \
+				 E1000_GCR_RXDSCW_NO_SNOOP | \
+				 E1000_GCR_RXDSCR_NO_SNOOP | \
+				 E1000_GCR_TXD_NO_SNOOP    | \
+				 E1000_GCR_TXDSCW_NO_SNOOP | \
+				 E1000_GCR_TXDSCR_NO_SNOOP)
+
+/* mPHY address control and data registers */
+#define E1000_MPHY_ADDR_CTL		0x0024 /* Address Control Reg */
+#define E1000_MPHY_ADDR_CTL_OFFSET_MASK	0xFFFF0000
+#define E1000_MPHY_DATA			0x0E10 /* Data Register */
+
+/* AFE CSR Offset for PCS CLK */
+#define E1000_MPHY_PCS_CLK_REG_OFFSET	0x0004
+/* Override for near end digital loopback. */
+#define E1000_MPHY_PCS_CLK_REG_DIGINELBEN	0x10
 
 /* PHY Control Register */
-#define MII_CR_SPEED_SELECT_MSB 0x0040  /* bits 6,13: 10=1000, 01=100, 00=10 */
-#define MII_CR_COLL_TEST_ENABLE 0x0080  /* Collision test enable */
-#define MII_CR_FULL_DUPLEX      0x0100  /* FDX =1, half duplex =0 */
-#define MII_CR_RESTART_AUTO_NEG 0x0200  /* Restart auto negotiation */
-#define MII_CR_ISOLATE          0x0400  /* Isolate PHY from MII */
-#define MII_CR_POWER_DOWN       0x0800  /* Power down */
-#define MII_CR_AUTO_NEG_EN      0x1000  /* Auto Neg Enable */
-#define MII_CR_SPEED_SELECT_LSB 0x2000  /* bits 6,13: 10=1000, 01=100, 00=10 */
-#define MII_CR_LOOPBACK         0x4000  /* 0 = normal, 1 = loopback */
-#define MII_CR_RESET            0x8000  /* 0 = normal, 1 = PHY reset */
-#define MII_CR_SPEED_1000       0x0040
-#define MII_CR_SPEED_100        0x2000
-#define MII_CR_SPEED_10         0x0000
+#define MII_CR_SPEED_SELECT_MSB	0x0040  /* bits 6,13: 10=1000, 01=100, 00=10 */
+#define MII_CR_COLL_TEST_ENABLE	0x0080  /* Collision test enable */
+#define MII_CR_FULL_DUPLEX	0x0100  /* FDX =1, half duplex =0 */
+#define MII_CR_RESTART_AUTO_NEG	0x0200  /* Restart auto negotiation */
+#define MII_CR_ISOLATE		0x0400  /* Isolate PHY from MII */
+#define MII_CR_POWER_DOWN	0x0800  /* Power down */
+#define MII_CR_AUTO_NEG_EN	0x1000  /* Auto Neg Enable */
+#define MII_CR_SPEED_SELECT_LSB	0x2000  /* bits 6,13: 10=1000, 01=100, 00=10 */
+#define MII_CR_LOOPBACK		0x4000  /* 0 = normal, 1 = loopback */
+#define MII_CR_RESET		0x8000  /* 0 = normal, 1 = PHY reset */
+#define MII_CR_SPEED_1000	0x0040
+#define MII_CR_SPEED_100	0x2000
+#define MII_CR_SPEED_10		0x0000
 
 /* PHY Status Register */
-#define MII_SR_EXTENDED_CAPS     0x0001 /* Extended register capabilities */
-#define MII_SR_JABBER_DETECT     0x0002 /* Jabber Detected */
-#define MII_SR_LINK_STATUS       0x0004 /* Link Status 1 = link */
-#define MII_SR_AUTONEG_CAPS      0x0008 /* Auto Neg Capable */
-#define MII_SR_REMOTE_FAULT      0x0010 /* Remote Fault Detect */
-#define MII_SR_AUTONEG_COMPLETE  0x0020 /* Auto Neg Complete */
+#define MII_SR_EXTENDED_CAPS	0x0001 /* Extended register capabilities */
+#define MII_SR_JABBER_DETECT	0x0002 /* Jabber Detected */
+#define MII_SR_LINK_STATUS	0x0004 /* Link Status 1 = link */
+#define MII_SR_AUTONEG_CAPS	0x0008 /* Auto Neg Capable */
+#define MII_SR_REMOTE_FAULT	0x0010 /* Remote Fault Detect */
+#define MII_SR_AUTONEG_COMPLETE	0x0020 /* Auto Neg Complete */
 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
-#define MII_SR_EXTENDED_STATUS   0x0100 /* Ext. status info in Reg 0x0F */
-#define MII_SR_100T2_HD_CAPS     0x0200 /* 100T2 Half Duplex Capable */
-#define MII_SR_100T2_FD_CAPS     0x0400 /* 100T2 Full Duplex Capable */
-#define MII_SR_10T_HD_CAPS       0x0800 /* 10T   Half Duplex Capable */
-#define MII_SR_10T_FD_CAPS       0x1000 /* 10T   Full Duplex Capable */
-#define MII_SR_100X_HD_CAPS      0x2000 /* 100X  Half Duplex Capable */
-#define MII_SR_100X_FD_CAPS      0x4000 /* 100X  Full Duplex Capable */
-#define MII_SR_100T4_CAPS        0x8000 /* 100T4 Capable */
+#define MII_SR_EXTENDED_STATUS	0x0100 /* Ext. status info in Reg 0x0F */
+#define MII_SR_100T2_HD_CAPS	0x0200 /* 100T2 Half Duplex Capable */
+#define MII_SR_100T2_FD_CAPS	0x0400 /* 100T2 Full Duplex Capable */
+#define MII_SR_10T_HD_CAPS	0x0800 /* 10T   Half Duplex Capable */
+#define MII_SR_10T_FD_CAPS	0x1000 /* 10T   Full Duplex Capable */
+#define MII_SR_100X_HD_CAPS	0x2000 /* 100X  Half Duplex Capable */
+#define MII_SR_100X_FD_CAPS	0x4000 /* 100X  Full Duplex Capable */
+#define MII_SR_100T4_CAPS	0x8000 /* 100T4 Capable */
 
 /* Autoneg Advertisement Register */
-#define NWAY_AR_SELECTOR_FIELD   0x0001   /* indicates IEEE 802.3 CSMA/CD */
-#define NWAY_AR_10T_HD_CAPS      0x0020   /* 10T   Half Duplex Capable */
-#define NWAY_AR_10T_FD_CAPS      0x0040   /* 10T   Full Duplex Capable */
-#define NWAY_AR_100TX_HD_CAPS    0x0080   /* 100TX Half Duplex Capable */
-#define NWAY_AR_100TX_FD_CAPS    0x0100   /* 100TX Full Duplex Capable */
-#define NWAY_AR_100T4_CAPS       0x0200   /* 100T4 Capable */
-#define NWAY_AR_PAUSE            0x0400   /* Pause operation desired */
-#define NWAY_AR_ASM_DIR          0x0800   /* Asymmetric Pause Direction bit */
-#define NWAY_AR_REMOTE_FAULT     0x2000   /* Remote Fault detected */
-#define NWAY_AR_NEXT_PAGE        0x8000   /* Next Page ability supported */
+#define NWAY_AR_SELECTOR_FIELD	0x0001   /* indicates IEEE 802.3 CSMA/CD */
+#define NWAY_AR_10T_HD_CAPS	0x0020   /* 10T   Half Duplex Capable */
+#define NWAY_AR_10T_FD_CAPS	0x0040   /* 10T   Full Duplex Capable */
+#define NWAY_AR_100TX_HD_CAPS	0x0080   /* 100TX Half Duplex Capable */
+#define NWAY_AR_100TX_FD_CAPS	0x0100   /* 100TX Full Duplex Capable */
+#define NWAY_AR_100T4_CAPS	0x0200   /* 100T4 Capable */
+#define NWAY_AR_PAUSE		0x0400   /* Pause operation desired */
+#define NWAY_AR_ASM_DIR		0x0800   /* Asymmetric Pause Direction bit */
+#define NWAY_AR_REMOTE_FAULT	0x2000   /* Remote Fault detected */
+#define NWAY_AR_NEXT_PAGE	0x8000   /* Next Page ability supported */
 
 /* Link Partner Ability Register (Base Page) */
-#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
-#define NWAY_LPAR_10T_HD_CAPS    0x0020 /* LP is 10T   Half Duplex Capable */
-#define NWAY_LPAR_10T_FD_CAPS    0x0040 /* LP is 10T   Full Duplex Capable */
-#define NWAY_LPAR_100TX_HD_CAPS  0x0080 /* LP is 100TX Half Duplex Capable */
-#define NWAY_LPAR_100TX_FD_CAPS  0x0100 /* LP is 100TX Full Duplex Capable */
-#define NWAY_LPAR_100T4_CAPS     0x0200 /* LP is 100T4 Capable */
-#define NWAY_LPAR_PAUSE          0x0400 /* LP Pause operation desired */
-#define NWAY_LPAR_ASM_DIR        0x0800 /* LP Asymmetric Pause Direction bit */
-#define NWAY_LPAR_REMOTE_FAULT   0x2000 /* LP has detected Remote Fault */
-#define NWAY_LPAR_ACKNOWLEDGE    0x4000 /* LP has rx'd link code word */
-#define NWAY_LPAR_NEXT_PAGE      0x8000 /* Next Page ability supported */
+#define NWAY_LPAR_SELECTOR_FIELD	0x0000 /* LP protocol selector field */
+#define NWAY_LPAR_10T_HD_CAPS		0x0020 /* LP 10T Half Dplx Capable */
+#define NWAY_LPAR_10T_FD_CAPS		0x0040 /* LP 10T Full Dplx Capable */
+#define NWAY_LPAR_100TX_HD_CAPS		0x0080 /* LP 100TX Half Dplx Capable */
+#define NWAY_LPAR_100TX_FD_CAPS		0x0100 /* LP 100TX Full Dplx Capable */
+#define NWAY_LPAR_100T4_CAPS		0x0200 /* LP is 100T4 Capable */
+#define NWAY_LPAR_PAUSE			0x0400 /* LP Pause operation desired */
+#define NWAY_LPAR_ASM_DIR		0x0800 /* LP Asym Pause Direction bit */
+#define NWAY_LPAR_REMOTE_FAULT		0x2000 /* LP detected Remote Fault */
+#define NWAY_LPAR_ACKNOWLEDGE		0x4000 /* LP rx'd link code word */
+#define NWAY_LPAR_NEXT_PAGE		0x8000 /* Next Page ability supported */
 
 /* Autoneg Expansion Register */
-#define NWAY_ER_LP_NWAY_CAPS      0x0001 /* LP has Auto Neg Capability */
-#define NWAY_ER_PAGE_RXD          0x0002 /* LP is 10T   Half Duplex Capable */
-#define NWAY_ER_NEXT_PAGE_CAPS    0x0004 /* LP is 10T   Full Duplex Capable */
-#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
-#define NWAY_ER_PAR_DETECT_FAULT  0x0010 /* LP is 100TX Full Duplex Capable */
+#define NWAY_ER_LP_NWAY_CAPS		0x0001 /* LP has Auto Neg Capability */
+#define NWAY_ER_PAGE_RXD		0x0002 /* LP 10T Half Dplx Capable */
+#define NWAY_ER_NEXT_PAGE_CAPS		0x0004 /* LP 10T Full Dplx Capable */
+#define NWAY_ER_LP_NEXT_PAGE_CAPS	0x0008 /* LP 100TX Half Dplx Capable */
+#define NWAY_ER_PAR_DETECT_FAULT	0x0010 /* LP 100TX Full Dplx Capable */
 
 /* 1000BASE-T Control Register */
-#define CR_1000T_ASYM_PAUSE      0x0080 /* Advertise asymmetric pause bit */
-#define CR_1000T_HD_CAPS         0x0100 /* Advertise 1000T HD capability */
-#define CR_1000T_FD_CAPS         0x0200 /* Advertise 1000T FD capability  */
-#define CR_1000T_REPEATER_DTE    0x0400 /* 1=Repeater/switch device port */
-                                        /* 0=DTE device */
-#define CR_1000T_MS_VALUE        0x0800 /* 1=Configure PHY as Master */
-                                        /* 0=Configure PHY as Slave */
-#define CR_1000T_MS_ENABLE      0x1000 /* 1=Master/Slave manual config value */
-                                        /* 0=Automatic Master/Slave config */
+#define CR_1000T_ASYM_PAUSE	0x0080 /* Advertise asymmetric pause bit */
+#define CR_1000T_HD_CAPS	0x0100 /* Advertise 1000T HD capability */
+#define CR_1000T_FD_CAPS	0x0200 /* Advertise 1000T FD capability  */
+/* 1=Repeater/switch device port 0=DTE device */
+#define CR_1000T_REPEATER_DTE	0x0400
+/* 1=Configure PHY as Master 0=Configure PHY as Slave */
+#define CR_1000T_MS_VALUE	0x0800
+/* 1=Master/Slave manual config value 0=Automatic Master/Slave config */
+#define CR_1000T_MS_ENABLE	0x1000
 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
-#define CR_1000T_TEST_MODE_1     0x2000 /* Transmit Waveform test */
-#define CR_1000T_TEST_MODE_2     0x4000 /* Master Transmit Jitter test */
-#define CR_1000T_TEST_MODE_3     0x6000 /* Slave Transmit Jitter test */
-#define CR_1000T_TEST_MODE_4     0x8000 /* Transmitter Distortion test */
+#define CR_1000T_TEST_MODE_1	0x2000 /* Transmit Waveform test */
+#define CR_1000T_TEST_MODE_2	0x4000 /* Master Transmit Jitter test */
+#define CR_1000T_TEST_MODE_3	0x6000 /* Slave Transmit Jitter test */
+#define CR_1000T_TEST_MODE_4	0x8000 /* Transmitter Distortion test */
 
 /* 1000BASE-T Status Register */
-#define SR_1000T_IDLE_ERROR_CNT   0x00FF /* Num idle errors since last read */
-#define SR_1000T_ASYM_PAUSE_DIR  0x0100 /* LP asymmetric pause direction bit */
-#define SR_1000T_LP_HD_CAPS       0x0400 /* LP is 1000T HD capable */
-#define SR_1000T_LP_FD_CAPS       0x0800 /* LP is 1000T FD capable */
-#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
-#define SR_1000T_LOCAL_RX_STATUS  0x2000 /* Local receiver OK */
-#define SR_1000T_MS_CONFIG_RES    0x4000 /* 1=Local Tx is Master, 0=Slave */
-#define SR_1000T_MS_CONFIG_FAULT  0x8000 /* Master/Slave config fault */
+#define SR_1000T_IDLE_ERROR_CNT		0x00FF /* Num idle err since last rd */
+#define SR_1000T_ASYM_PAUSE_DIR		0x0100 /* LP asym pause direction bit */
+#define SR_1000T_LP_HD_CAPS		0x0400 /* LP is 1000T HD capable */
+#define SR_1000T_LP_FD_CAPS		0x0800 /* LP is 1000T FD capable */
+#define SR_1000T_REMOTE_RX_STATUS	0x1000 /* Remote receiver OK */
+#define SR_1000T_LOCAL_RX_STATUS	0x2000 /* Local receiver OK */
+#define SR_1000T_MS_CONFIG_RES		0x4000 /* 1=Local Tx Master, 0=Slave */
+#define SR_1000T_MS_CONFIG_FAULT	0x8000 /* Master/Slave config fault */
 
-#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
+#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT	5
 
 /* PHY 1000 MII Register/Bit Definitions */
 /* PHY Registers defined by IEEE */
-#define PHY_CONTROL      0x00 /* Control Register */
-#define PHY_STATUS       0x01 /* Status Register */
-#define PHY_ID1          0x02 /* Phy Id Reg (word 1) */
-#define PHY_ID2          0x03 /* Phy Id Reg (word 2) */
-#define PHY_AUTONEG_ADV  0x04 /* Autoneg Advertisement */
-#define PHY_LP_ABILITY   0x05 /* Link Partner Ability (Base Page) */
-#define PHY_AUTONEG_EXP  0x06 /* Autoneg Expansion Reg */
-#define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */
-#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
-#define PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */
-#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
-#define PHY_EXT_STATUS   0x0F /* Extended Status Reg */
+#define PHY_CONTROL		0x00 /* Control Register */
+#define PHY_STATUS		0x01 /* Status Register */
+#define PHY_ID1			0x02 /* Phy Id Reg (word 1) */
+#define PHY_ID2			0x03 /* Phy Id Reg (word 2) */
+#define PHY_AUTONEG_ADV		0x04 /* Autoneg Advertisement */
+#define PHY_LP_ABILITY		0x05 /* Link Partner Ability (Base Page) */
+#define PHY_AUTONEG_EXP		0x06 /* Autoneg Expansion Reg */
+#define PHY_NEXT_PAGE_TX	0x07 /* Next Page Tx */
+#define PHY_LP_NEXT_PAGE	0x08 /* Link Partner Next Page */
+#define PHY_1000T_CTRL		0x09 /* 1000Base-T Control Reg */
+#define PHY_1000T_STATUS	0x0A /* 1000Base-T Status Reg */
+#define PHY_EXT_STATUS		0x0F /* Extended Status Reg */
 
-#define PHY_CONTROL_LB   0x4000 /* PHY Loopback bit */
+#define PHY_CONTROL_LB		0x4000 /* PHY Loopback bit */
 
 /* NVM Control */
-#define E1000_EECD_SK        0x00000001 /* NVM Clock */
-#define E1000_EECD_CS        0x00000002 /* NVM Chip Select */
-#define E1000_EECD_DI        0x00000004 /* NVM Data In */
-#define E1000_EECD_DO        0x00000008 /* NVM Data Out */
-#define E1000_EECD_FWE_MASK  0x00000030
-#define E1000_EECD_FWE_DIS   0x00000010 /* Disable FLASH writes */
-#define E1000_EECD_FWE_EN    0x00000020 /* Enable FLASH writes */
-#define E1000_EECD_FWE_SHIFT 4
-#define E1000_EECD_REQ       0x00000040 /* NVM Access Request */
-#define E1000_EECD_GNT       0x00000080 /* NVM Access Grant */
-#define E1000_EECD_PRES      0x00000100 /* NVM Present */
-#define E1000_EECD_SIZE      0x00000200 /* NVM Size (0=64 word 1=256 word) */
+#define E1000_EECD_SK		0x00000001 /* NVM Clock */
+#define E1000_EECD_CS		0x00000002 /* NVM Chip Select */
+#define E1000_EECD_DI		0x00000004 /* NVM Data In */
+#define E1000_EECD_DO		0x00000008 /* NVM Data Out */
+#define E1000_EECD_FWE_MASK	0x00000030
+#define E1000_EECD_FWE_DIS	0x00000010 /* Disable FLASH writes */
+#define E1000_EECD_FWE_EN	0x00000020 /* Enable FLASH writes */
+#define E1000_EECD_FWE_SHIFT	4
+#define E1000_EECD_REQ		0x00000040 /* NVM Access Request */
+#define E1000_EECD_GNT		0x00000080 /* NVM Access Grant */
+#define E1000_EECD_PRES		0x00000100 /* NVM Present */
+#define E1000_EECD_SIZE		0x00000200 /* NVM Size (0=64 word 1=256 word) */
+#define E1000_EECD_BLOCKED	0x00008000 /* Bit banging access blocked flag */
+#define E1000_EECD_ABORT	0x00010000 /* NVM operation aborted flag */
+#define E1000_EECD_TIMEOUT	0x00020000 /* NVM read operation timeout flag */
+#define E1000_EECD_ERROR_CLR	0x00040000 /* NVM error status clear bit */
 /* NVM Addressing bits based on type 0=small, 1=large */
-#define E1000_EECD_ADDR_BITS 0x00000400
-#define E1000_EECD_TYPE      0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
+#define E1000_EECD_ADDR_BITS	0x00000400
+#define E1000_EECD_TYPE		0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
 #ifndef E1000_NVM_GRANT_ATTEMPTS
-#define E1000_NVM_GRANT_ATTEMPTS   1000 /* NVM # attempts to gain grant */
+#define E1000_NVM_GRANT_ATTEMPTS	1000 /* NVM # attempts to gain grant */
 #endif
-#define E1000_EECD_AUTO_RD          0x00000200  /* NVM Auto Read done */
-#define E1000_EECD_SIZE_EX_MASK     0x00007800  /* NVM Size */
-#define E1000_EECD_SIZE_EX_SHIFT     11
-#define E1000_EECD_NVADDS    0x00018000 /* NVM Address Size */
-#define E1000_EECD_SELSHAD   0x00020000 /* Select Shadow RAM */
-#define E1000_EECD_INITSRAM  0x00040000 /* Initialize Shadow RAM */
-#define E1000_EECD_FLUPD     0x00080000 /* Update FLASH */
-#define E1000_EECD_AUPDEN    0x00100000 /* Enable Autonomous FLASH update */
-#define E1000_EECD_SHADV     0x00200000 /* Shadow RAM Data Valid */
-#define E1000_EECD_SEC1VAL   0x00400000 /* Sector One Valid */
-#define E1000_EECD_SECVAL_SHIFT      22
-#define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
+#define E1000_EECD_AUTO_RD		0x00000200  /* NVM Auto Read done */
+#define E1000_EECD_SIZE_EX_MASK		0x00007800  /* NVM Size */
+#define E1000_EECD_SIZE_EX_SHIFT	11
+#define E1000_EECD_NVADDS		0x00018000 /* NVM Address Size */
+#define E1000_EECD_SELSHAD		0x00020000 /* Select Shadow RAM */
+#define E1000_EECD_INITSRAM		0x00040000 /* Initialize Shadow RAM */
+#define E1000_EECD_FLUPD		0x00080000 /* Update FLASH */
+#define E1000_EECD_AUPDEN		0x00100000 /* Ena Auto FLASH update */
+#define E1000_EECD_SHADV		0x00200000 /* Shadow RAM Data Valid */
+#define E1000_EECD_SEC1VAL		0x00400000 /* Sector One Valid */
+#define E1000_EECD_SECVAL_SHIFT		22
+#define E1000_EECD_SEC1VAL_VALID_MASK	(E1000_EECD_AUTO_RD | E1000_EECD_PRES)
 
-#define E1000_NVM_SWDPIN0   0x0001   /* SWDPIN 0 NVM Value */
-#define E1000_NVM_LED_LOGIC 0x0020   /* Led Logic Word */
-#define E1000_NVM_RW_REG_DATA   16  /* Offset to data in NVM read/write regs */
-#define E1000_NVM_RW_REG_DONE   2    /* Offset to READ/WRITE done bit */
-#define E1000_NVM_RW_REG_START  1    /* Start operation */
-#define E1000_NVM_RW_ADDR_SHIFT 2    /* Shift to the address bits */
-#define E1000_NVM_POLL_WRITE    1    /* Flag for polling for write complete */
-#define E1000_NVM_POLL_READ     0    /* Flag for polling for read complete */
-#define E1000_FLASH_UPDATES  2000
+#define E1000_NVM_SWDPIN0	0x0001 /* SWDPIN 0 NVM Value */
+#define E1000_NVM_LED_LOGIC	0x0020 /* Led Logic Word */
+#define E1000_NVM_RW_REG_DATA	16  /* Offset to data in NVM read/write regs */
+#define E1000_NVM_RW_REG_DONE	2   /* Offset to READ/WRITE done bit */
+#define E1000_NVM_RW_REG_START	1   /* Start operation */
+#define E1000_NVM_RW_ADDR_SHIFT	2   /* Shift to the address bits */
+#define E1000_NVM_POLL_WRITE	1   /* Flag for polling for write complete */
+#define E1000_NVM_POLL_READ	0   /* Flag for polling for read complete */
+#define E1000_FLASH_UPDATES	2000
 
 /* NVM Word Offsets */
-#define NVM_COMPAT                 0x0003
-#define NVM_ID_LED_SETTINGS        0x0004
-#define NVM_VERSION                0x0005
-#define NVM_SERDES_AMPLITUDE       0x0006 /* SERDES output amplitude */
-#define NVM_PHY_CLASS_WORD         0x0007
-#define NVM_INIT_CONTROL1_REG      0x000A
-#define NVM_INIT_CONTROL2_REG      0x000F
-#define NVM_SWDEF_PINS_CTRL_PORT_1 0x0010
-#define NVM_INIT_CONTROL3_PORT_B   0x0014
-#define NVM_INIT_3GIO_3            0x001A
-#define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020
-#define NVM_INIT_CONTROL3_PORT_A   0x0024
-#define NVM_CFG                    0x0012
-#define NVM_FLASH_VERSION          0x0032
-#define NVM_ALT_MAC_ADDR_PTR       0x0037
-#define NVM_CHECKSUM_REG           0x003F
-#define NVM_COMPATIBILITY_REG_3    0x0003
-#define NVM_COMPATIBILITY_BIT_MASK 0x8000
+#define NVM_COMPAT			0x0003
+#define NVM_ID_LED_SETTINGS		0x0004
+#define NVM_VERSION			0x0005
+#define NVM_SERDES_AMPLITUDE		0x0006 /* SERDES output amplitude */
+#define NVM_PHY_CLASS_WORD		0x0007
+#define NVM_INIT_CONTROL1_REG		0x000A
+#define NVM_INIT_CONTROL2_REG		0x000F
+#define NVM_SWDEF_PINS_CTRL_PORT_1	0x0010
+#define NVM_INIT_CONTROL3_PORT_B	0x0014
+#define NVM_INIT_3GIO_3			0x001A
+#define NVM_SWDEF_PINS_CTRL_PORT_0	0x0020
+#define NVM_INIT_CONTROL3_PORT_A	0x0024
+#define NVM_CFG				0x0012
+#define NVM_FLASH_VERSION		0x0032
+#define NVM_ALT_MAC_ADDR_PTR		0x0037
+#define NVM_CHECKSUM_REG		0x003F
+#define NVM_COMPATIBILITY_REG_3		0x0003
+#define NVM_COMPATIBILITY_BIT_MASK	0x8000
 
-#define E1000_NVM_CFG_DONE_PORT_0  0x040000 /* MNG config cycle done */
-#define E1000_NVM_CFG_DONE_PORT_1  0x080000 /* ...for second port */
-#define E1000_NVM_CFG_DONE_PORT_2  0x100000 /* ...for third port */
-#define E1000_NVM_CFG_DONE_PORT_3  0x200000 /* ...for fourth port */
+#define E1000_NVM_CFG_DONE_PORT_0	0x040000 /* MNG config cycle done */
+#define E1000_NVM_CFG_DONE_PORT_1	0x080000 /* ...for second port */
+#define E1000_NVM_CFG_DONE_PORT_2	0x100000 /* ...for third port */
+#define E1000_NVM_CFG_DONE_PORT_3	0x200000 /* ...for fourth port */
 
-#define NVM_82580_LAN_FUNC_OFFSET(a) (a ? (0x40 + (0x40 * a)) : 0)
+#define NVM_82580_LAN_FUNC_OFFSET(a)	(a ? (0x40 + (0x40 * a)) : 0)
 
 /* Mask bits for fields in Word 0x24 of the NVM */
-#define NVM_WORD24_COM_MDIO         0x0008 /* MDIO interface shared */
-#define NVM_WORD24_EXT_MDIO         0x0004 /* MDIO accesses routed external */
+#define NVM_WORD24_COM_MDIO		0x0008 /* MDIO interface shared */
+#define NVM_WORD24_EXT_MDIO		0x0004 /* MDIO accesses routed extrnl */
+/* Offset of Link Mode bits for 82575 up to Kawela */
+#define NVM_WORD24_LNK_MODE_OFFSET	8
+/* Offset of Link Mode bits for 82580 up */
+#define NVM_WORD24_82580_LNK_MODE_OFFSET	4
+
 
 /* Mask bits for fields in Word 0x0f of the NVM */
-#define NVM_WORD0F_PAUSE_MASK       0x3000
-#define NVM_WORD0F_PAUSE            0x1000
-#define NVM_WORD0F_ASM_DIR          0x2000
-#define NVM_WORD0F_ANE              0x0800
-#define NVM_WORD0F_SWPDIO_EXT_MASK  0x00F0
-#define NVM_WORD0F_LPLU             0x0001
+#define NVM_WORD0F_PAUSE_MASK		0x3000
+#define NVM_WORD0F_PAUSE		0x1000
+#define NVM_WORD0F_ASM_DIR		0x2000
+#define NVM_WORD0F_ANE			0x0800
+#define NVM_WORD0F_SWPDIO_EXT_MASK	0x00F0
+#define NVM_WORD0F_LPLU			0x0001
 
 /* Mask bits for fields in Word 0x1a of the NVM */
-#define NVM_WORD1A_ASPM_MASK  0x000C
+#define NVM_WORD1A_ASPM_MASK		0x000C
 
 /* Mask bits for fields in Word 0x03 of the EEPROM */
-#define NVM_COMPAT_LOM    0x0800
+#define NVM_COMPAT_LOM			0x0800
 
 /* length of string needed to store PBA number */
-#define E1000_PBANUM_LENGTH             11
+#define E1000_PBANUM_LENGTH		11
 
 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
-#define NVM_SUM                    0xBABA
+#define NVM_SUM				0xBABA
 
-#define NVM_MAC_ADDR_OFFSET        0
-#define NVM_PBA_OFFSET_0           8
-#define NVM_PBA_OFFSET_1           9
-#define NVM_PBA_PTR_GUARD          0xFAFA
-#define NVM_RESERVED_WORD          0xFFFF
-#define NVM_PHY_CLASS_A            0x8000
-#define NVM_SERDES_AMPLITUDE_MASK  0x000F
-#define NVM_SIZE_MASK              0x1C00
-#define NVM_SIZE_SHIFT             10
-#define NVM_WORD_SIZE_BASE_SHIFT   6
-#define NVM_SWDPIO_EXT_SHIFT       4
+#define NVM_MAC_ADDR_OFFSET		0
+#define NVM_PBA_OFFSET_0		8
+#define NVM_PBA_OFFSET_1		9
+#define NVM_PBA_PTR_GUARD		0xFAFA
+#define NVM_RESERVED_WORD		0xFFFF
+#define NVM_PHY_CLASS_A			0x8000
+#define NVM_SERDES_AMPLITUDE_MASK	0x000F
+#define NVM_SIZE_MASK			0x1C00
+#define NVM_SIZE_SHIFT			10
+#define NVM_WORD_SIZE_BASE_SHIFT	6
+#define NVM_SWDPIO_EXT_SHIFT		4
 
 /* NVM Commands - Microwire */
-#define NVM_READ_OPCODE_MICROWIRE  0x6  /* NVM read opcode */
-#define NVM_WRITE_OPCODE_MICROWIRE 0x5  /* NVM write opcode */
-#define NVM_ERASE_OPCODE_MICROWIRE 0x7  /* NVM erase opcode */
-#define NVM_EWEN_OPCODE_MICROWIRE  0x13 /* NVM erase/write enable */
-#define NVM_EWDS_OPCODE_MICROWIRE  0x10 /* NVM erase/write disable */
+#define NVM_READ_OPCODE_MICROWIRE	0x6  /* NVM read opcode */
+#define NVM_WRITE_OPCODE_MICROWIRE	0x5  /* NVM write opcode */
+#define NVM_ERASE_OPCODE_MICROWIRE	0x7  /* NVM erase opcode */
+#define NVM_EWEN_OPCODE_MICROWIRE	0x13 /* NVM erase/write enable */
+#define NVM_EWDS_OPCODE_MICROWIRE	0x10 /* NVM erase/write disable */
 
 /* NVM Commands - SPI */
-#define NVM_MAX_RETRY_SPI          5000 /* Max wait of 5ms, for RDY signal */
-#define NVM_READ_OPCODE_SPI        0x03 /* NVM read opcode */
-#define NVM_WRITE_OPCODE_SPI       0x02 /* NVM write opcode */
-#define NVM_A8_OPCODE_SPI          0x08 /* opcode bit-3 = address bit-8 */
-#define NVM_WREN_OPCODE_SPI        0x06 /* NVM set Write Enable latch */
-#define NVM_WRDI_OPCODE_SPI        0x04 /* NVM reset Write Enable latch */
-#define NVM_RDSR_OPCODE_SPI        0x05 /* NVM read Status register */
-#define NVM_WRSR_OPCODE_SPI        0x01 /* NVM write Status register */
+#define NVM_MAX_RETRY_SPI	5000 /* Max wait of 5ms, for RDY signal */
+#define NVM_READ_OPCODE_SPI	0x03 /* NVM read opcode */
+#define NVM_WRITE_OPCODE_SPI	0x02 /* NVM write opcode */
+#define NVM_A8_OPCODE_SPI	0x08 /* opcode bit-3 = address bit-8 */
+#define NVM_WREN_OPCODE_SPI	0x06 /* NVM set Write Enable latch */
+#define NVM_WRDI_OPCODE_SPI	0x04 /* NVM reset Write Enable latch */
+#define NVM_RDSR_OPCODE_SPI	0x05 /* NVM read Status register */
+#define NVM_WRSR_OPCODE_SPI	0x01 /* NVM write Status register */
 
 /* SPI NVM Status Register */
-#define NVM_STATUS_RDY_SPI         0x01
-#define NVM_STATUS_WEN_SPI         0x02
-#define NVM_STATUS_BP0_SPI         0x04
-#define NVM_STATUS_BP1_SPI         0x08
-#define NVM_STATUS_WPEN_SPI        0x80
+#define NVM_STATUS_RDY_SPI	0x01
+#define NVM_STATUS_WEN_SPI	0x02
+#define NVM_STATUS_BP0_SPI	0x04
+#define NVM_STATUS_BP1_SPI	0x08
+#define NVM_STATUS_WPEN_SPI	0x80
 
 /* Word definitions for ID LED Settings */
-#define ID_LED_RESERVED_0000 0x0000
-#define ID_LED_RESERVED_FFFF 0xFFFF
-#define ID_LED_DEFAULT       ((ID_LED_OFF1_ON2  << 12) | \
-                              (ID_LED_OFF1_OFF2 <<  8) | \
-                              (ID_LED_DEF1_DEF2 <<  4) | \
-                              (ID_LED_DEF1_DEF2))
-#define ID_LED_DEF1_DEF2     0x1
-#define ID_LED_DEF1_ON2      0x2
-#define ID_LED_DEF1_OFF2     0x3
-#define ID_LED_ON1_DEF2      0x4
-#define ID_LED_ON1_ON2       0x5
-#define ID_LED_ON1_OFF2      0x6
-#define ID_LED_OFF1_DEF2     0x7
-#define ID_LED_OFF1_ON2      0x8
-#define ID_LED_OFF1_OFF2     0x9
+#define ID_LED_RESERVED_0000	0x0000
+#define ID_LED_RESERVED_FFFF	0xFFFF
+#define ID_LED_DEFAULT		((ID_LED_OFF1_ON2  << 12) | \
+				 (ID_LED_OFF1_OFF2 <<  8) | \
+				 (ID_LED_DEF1_DEF2 <<  4) | \
+				 (ID_LED_DEF1_DEF2))
+#define ID_LED_DEF1_DEF2	0x1
+#define ID_LED_DEF1_ON2		0x2
+#define ID_LED_DEF1_OFF2	0x3
+#define ID_LED_ON1_DEF2		0x4
+#define ID_LED_ON1_ON2		0x5
+#define ID_LED_ON1_OFF2		0x6
+#define ID_LED_OFF1_DEF2	0x7
+#define ID_LED_OFF1_ON2		0x8
+#define ID_LED_OFF1_OFF2	0x9
 
-#define IGP_ACTIVITY_LED_MASK   0xFFFFF0FF
-#define IGP_ACTIVITY_LED_ENABLE 0x0300
-#define IGP_LED3_MODE           0x07000000
+#define IGP_ACTIVITY_LED_MASK	0xFFFFF0FF
+#define IGP_ACTIVITY_LED_ENABLE	0x0300
+#define IGP_LED3_MODE		0x07000000
 
 /* PCI/PCI-X/PCI-EX Config space */
-#define PCIX_COMMAND_REGISTER        0xE6
-#define PCIX_STATUS_REGISTER_LO      0xE8
-#define PCIX_STATUS_REGISTER_HI      0xEA
-#define PCI_HEADER_TYPE_REGISTER     0x0E
-#define PCIE_LINK_STATUS             0x12
-#define PCIE_DEVICE_CONTROL2         0x28
+#define PCIX_COMMAND_REGISTER		0xE6
+#define PCIX_STATUS_REGISTER_LO		0xE8
+#define PCIX_STATUS_REGISTER_HI		0xEA
+#define PCI_HEADER_TYPE_REGISTER	0x0E
+#define PCIE_LINK_STATUS		0x12
+#define PCIE_DEVICE_CONTROL2		0x28
 
-#define PCIX_COMMAND_MMRBC_MASK      0x000C
-#define PCIX_COMMAND_MMRBC_SHIFT     0x2
-#define PCIX_STATUS_HI_MMRBC_MASK    0x0060
-#define PCIX_STATUS_HI_MMRBC_SHIFT   0x5
-#define PCIX_STATUS_HI_MMRBC_4K      0x3
-#define PCIX_STATUS_HI_MMRBC_2K      0x2
-#define PCIX_STATUS_LO_FUNC_MASK     0x7
-#define PCI_HEADER_TYPE_MULTIFUNC    0x80
-#define PCIE_LINK_WIDTH_MASK         0x3F0
-#define PCIE_LINK_WIDTH_SHIFT        4
-#define PCIE_LINK_SPEED_MASK         0x0F
-#define PCIE_LINK_SPEED_2500         0x01
-#define PCIE_LINK_SPEED_5000         0x02
-#define PCIE_DEVICE_CONTROL2_16ms    0x0005
+#define PCIX_COMMAND_MMRBC_MASK		0x000C
+#define PCIX_COMMAND_MMRBC_SHIFT	0x2
+#define PCIX_STATUS_HI_MMRBC_MASK	0x0060
+#define PCIX_STATUS_HI_MMRBC_SHIFT	0x5
+#define PCIX_STATUS_HI_MMRBC_4K		0x3
+#define PCIX_STATUS_HI_MMRBC_2K		0x2
+#define PCIX_STATUS_LO_FUNC_MASK	0x7
+#define PCI_HEADER_TYPE_MULTIFUNC	0x80
+#define PCIE_LINK_WIDTH_MASK		0x3F0
+#define PCIE_LINK_WIDTH_SHIFT		4
+#define PCIE_LINK_SPEED_MASK		0x0F
+#define PCIE_LINK_SPEED_2500		0x01
+#define PCIE_LINK_SPEED_5000		0x02
+#define PCIE_DEVICE_CONTROL2_16ms	0x0005
 
 #ifndef ETH_ADDR_LEN
-#define ETH_ADDR_LEN                 6
+#define ETH_ADDR_LEN			6
 #endif
 
-#define PHY_REVISION_MASK      0xFFFFFFF0
-#define MAX_PHY_REG_ADDRESS    0x1F  /* 5 bit address bus (0-0x1F) */
-#define MAX_PHY_MULTI_PAGE_REG 0xF
+#define PHY_REVISION_MASK		0xFFFFFFF0
+#define MAX_PHY_REG_ADDRESS		0x1F  /* 5 bit address bus (0-0x1F) */
+#define MAX_PHY_MULTI_PAGE_REG		0xF
 
 /* Bit definitions for valid PHY IDs. */
 /*
  * I = Integrated
  * E = External
  */
-#define M88E1000_E_PHY_ID    0x01410C50
-#define M88E1000_I_PHY_ID    0x01410C30
-#define M88E1011_I_PHY_ID    0x01410C20
-#define IGP01E1000_I_PHY_ID  0x02A80380
-#define M88E1011_I_REV_4     0x04
-#define M88E1111_I_PHY_ID    0x01410CC0
-#define M88E1112_E_PHY_ID    0x01410C90
-#define I347AT4_E_PHY_ID     0x01410DC0
-#define M88E1340M_E_PHY_ID   0x01410DF0
-#define GG82563_E_PHY_ID     0x01410CA0
-#define IGP03E1000_E_PHY_ID  0x02A80390
-#define IFE_E_PHY_ID         0x02A80330
-#define IFE_PLUS_E_PHY_ID    0x02A80320
-#define IFE_C_E_PHY_ID       0x02A80310
-#define BME1000_E_PHY_ID     0x01410CB0
-#define BME1000_E_PHY_ID_R2  0x01410CB1
-#define I82577_E_PHY_ID 0x01540050
-#define I82578_E_PHY_ID 0x004DD040
-#define I82579_E_PHY_ID    0x01540090
-#define I82580_I_PHY_ID      0x015403A0
-#define I350_I_PHY_ID        0x015403B0
-#define IGP04E1000_E_PHY_ID  0x02A80391
-#define M88_VENDOR           0x0141
+#define M88E1000_E_PHY_ID	0x01410C50
+#define M88E1000_I_PHY_ID	0x01410C30
+#define M88E1011_I_PHY_ID	0x01410C20
+#define IGP01E1000_I_PHY_ID	0x02A80380
+#define M88E1011_I_REV_4	0x04
+#define M88E1111_I_PHY_ID	0x01410CC0
+#define M88E1112_E_PHY_ID	0x01410C90
+#define I347AT4_E_PHY_ID	0x01410DC0
+#define M88E1340M_E_PHY_ID	0x01410DF0
+#define GG82563_E_PHY_ID	0x01410CA0
+#define IGP03E1000_E_PHY_ID	0x02A80390
+#define IFE_E_PHY_ID		0x02A80330
+#define IFE_PLUS_E_PHY_ID	0x02A80320
+#define IFE_C_E_PHY_ID		0x02A80310
+#define BME1000_E_PHY_ID	0x01410CB0
+#define BME1000_E_PHY_ID_R2	0x01410CB1
+#define I82577_E_PHY_ID		0x01540050
+#define I82578_E_PHY_ID		0x004DD040
+#define I82579_E_PHY_ID		0x01540090
+#define I82580_I_PHY_ID		0x015403A0
+#define I350_I_PHY_ID		0x015403B0
+#define IGP04E1000_E_PHY_ID	0x02A80391
+#define M88_VENDOR		0x0141
 
 /* M88E1000 Specific Registers */
-#define M88E1000_PHY_SPEC_CTRL     0x10  /* PHY Specific Control Register */
-#define M88E1000_PHY_SPEC_STATUS   0x11  /* PHY Specific Status Register */
-#define M88E1000_INT_ENABLE        0x12  /* Interrupt Enable Register */
-#define M88E1000_INT_STATUS        0x13  /* Interrupt Status Register */
-#define M88E1000_EXT_PHY_SPEC_CTRL 0x14  /* Extended PHY Specific Control */
-#define M88E1000_RX_ERR_CNTR       0x15  /* Receive Error Counter */
+#define M88E1000_PHY_SPEC_CTRL		0x10  /* PHY Specific Control Reg */
+#define M88E1000_PHY_SPEC_STATUS	0x11  /* PHY Specific Status Reg */
+#define M88E1000_INT_ENABLE		0x12  /* Interrupt Enable Reg */
+#define M88E1000_INT_STATUS		0x13  /* Interrupt Status Reg */
+#define M88E1000_EXT_PHY_SPEC_CTRL	0x14  /* Extended PHY Specific Cntrl */
+#define M88E1000_RX_ERR_CNTR		0x15  /* Receive Error Counter */
 
-#define M88E1000_PHY_EXT_CTRL      0x1A  /* PHY extend control register */
-#define M88E1000_PHY_PAGE_SELECT   0x1D  /* Reg 29 for page number setting */
-#define M88E1000_PHY_GEN_CONTROL   0x1E  /* Its meaning depends on reg 29 */
-#define M88E1000_PHY_VCO_REG_BIT8  0x100 /* Bits 8 & 11 are adjusted for */
-#define M88E1000_PHY_VCO_REG_BIT11 0x800    /* improved BER performance */
+#define M88E1000_PHY_EXT_CTRL		0x1A  /* PHY extend control register */
+#define M88E1000_PHY_PAGE_SELECT	0x1D  /* Reg 29 for pg number setting */
+#define M88E1000_PHY_GEN_CONTROL	0x1E  /* meaning depends on reg 29 */
+#define M88E1000_PHY_VCO_REG_BIT8	0x100 /* Bits 8 & 11 are adjusted for */
+#define M88E1000_PHY_VCO_REG_BIT11	0x800 /* improved BER performance */
 
 /* M88E1000 PHY Specific Control Register */
-#define M88E1000_PSCR_JABBER_DISABLE    0x0001 /* 1=Jabber Function disabled */
-#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */
-#define M88E1000_PSCR_SQE_TEST          0x0004 /* 1=SQE Test enabled */
+#define M88E1000_PSCR_JABBER_DISABLE	0x0001 /* 1=Jabber Function disabled */
+#define M88E1000_PSCR_POLARITY_REVERSAL	0x0002 /* 1=Polarity Reverse enabled */
+#define M88E1000_PSCR_SQE_TEST		0x0004 /* 1=SQE Test enabled */
 /* 1=CLK125 low, 0=CLK125 toggling */
-#define M88E1000_PSCR_CLK125_DISABLE    0x0010
-#define M88E1000_PSCR_MDI_MANUAL_MODE  0x0000 /* MDI Crossover Mode bits 6:5 */
-                                               /* Manual MDI configuration */
-#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020  /* Manual MDIX configuration */
+#define M88E1000_PSCR_CLK125_DISABLE	0x0010
+/* MDI Crossover Mode bits 6:5 Manual MDI configuration */
+#define M88E1000_PSCR_MDI_MANUAL_MODE	0x0000
+#define M88E1000_PSCR_MDIX_MANUAL_MODE	0x0020  /* Manual MDIX configuration */
 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
-#define M88E1000_PSCR_AUTO_X_1000T     0x0040
+#define M88E1000_PSCR_AUTO_X_1000T	0x0040
 /* Auto crossover enabled all speeds */
-#define M88E1000_PSCR_AUTO_X_MODE      0x0060
+#define M88E1000_PSCR_AUTO_X_MODE	0x0060
 /*
  * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
  * 0=Normal 10BASE-T Rx Threshold
  */
-#define M88E1000_PSCR_EN_10BT_EXT_DIST 0x0080
+#define M88E1000_PSCR_EN_10BT_EXT_DIST	0x0080
 /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
-#define M88E1000_PSCR_MII_5BIT_ENABLE      0x0100
-#define M88E1000_PSCR_SCRAMBLER_DISABLE    0x0200 /* 1=Scrambler disable */
-#define M88E1000_PSCR_FORCE_LINK_GOOD      0x0400 /* 1=Force link good */
-#define M88E1000_PSCR_ASSERT_CRS_ON_TX     0x0800 /* 1=Assert CRS on Tx */
+#define M88E1000_PSCR_MII_5BIT_ENABLE	0x0100
+#define M88E1000_PSCR_SCRAMBLER_DISABLE	0x0200 /* 1=Scrambler disable */
+#define M88E1000_PSCR_FORCE_LINK_GOOD	0x0400 /* 1=Force link good */
+#define M88E1000_PSCR_ASSERT_CRS_ON_TX	0x0800 /* 1=Assert CRS on Tx */
 
 /* M88E1000 PHY Specific Status Register */
-#define M88E1000_PSSR_JABBER             0x0001 /* 1=Jabber */
-#define M88E1000_PSSR_REV_POLARITY       0x0002 /* 1=Polarity reversed */
-#define M88E1000_PSSR_DOWNSHIFT          0x0020 /* 1=Downshifted */
-#define M88E1000_PSSR_MDIX               0x0040 /* 1=MDIX; 0=MDI */
+#define M88E1000_PSSR_JABBER		0x0001 /* 1=Jabber */
+#define M88E1000_PSSR_REV_POLARITY	0x0002 /* 1=Polarity reversed */
+#define M88E1000_PSSR_DOWNSHIFT		0x0020 /* 1=Downshifted */
+#define M88E1000_PSSR_MDIX		0x0040 /* 1=MDIX; 0=MDI */
 /*
  * 0 = <50M
  * 1 = 50-80M
@@ -1546,62 +1578,62 @@
  * 3 = 110-140M
  * 4 = >140M
  */
-#define M88E1000_PSSR_CABLE_LENGTH       0x0380
-#define M88E1000_PSSR_LINK               0x0400 /* 1=Link up, 0=Link down */
-#define M88E1000_PSSR_SPD_DPLX_RESOLVED  0x0800 /* 1=Speed & Duplex resolved */
-#define M88E1000_PSSR_PAGE_RCVD          0x1000 /* 1=Page received */
-#define M88E1000_PSSR_DPLX               0x2000 /* 1=Duplex 0=Half Duplex */
-#define M88E1000_PSSR_SPEED              0xC000 /* Speed, bits 14:15 */
-#define M88E1000_PSSR_10MBS              0x0000 /* 00=10Mbs */
-#define M88E1000_PSSR_100MBS             0x4000 /* 01=100Mbs */
-#define M88E1000_PSSR_1000MBS            0x8000 /* 10=1000Mbs */
+#define M88E1000_PSSR_CABLE_LENGTH	0x0380
+#define M88E1000_PSSR_LINK		0x0400 /* 1=Link up, 0=Link down */
+#define M88E1000_PSSR_SPD_DPLX_RESOLVED	0x0800 /* 1=Speed & Duplex resolved */
+#define M88E1000_PSSR_PAGE_RCVD		0x1000 /* 1=Page received */
+#define M88E1000_PSSR_DPLX		0x2000 /* 1=Duplex 0=Half Duplex */
+#define M88E1000_PSSR_SPEED		0xC000 /* Speed, bits 14:15 */
+#define M88E1000_PSSR_10MBS		0x0000 /* 00=10Mbs */
+#define M88E1000_PSSR_100MBS		0x4000 /* 01=100Mbs */
+#define M88E1000_PSSR_1000MBS		0x8000 /* 10=1000Mbs */
 
-#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
+#define M88E1000_PSSR_CABLE_LENGTH_SHIFT	7
 
 /* M88E1000 Extended PHY Specific Control Register */
-#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
+#define M88E1000_EPSCR_FIBER_LOOPBACK	0x4000 /* 1=Fiber loopback */
 /*
  * 1 = Lost lock detect enabled.
  * Will assert lost lock and bring
  * link down if idle not seen
  * within 1ms in 1000BASE-T
  */
-#define M88E1000_EPSCR_DOWN_NO_IDLE   0x8000
+#define M88E1000_EPSCR_DOWN_NO_IDLE	0x8000
 /*
  * Number of times we will attempt to autonegotiate before downshifting if we
  * are the master
  */
-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X   0x0000
-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X   0x0400
-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X   0x0800
-#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X   0x0C00
+#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK	0x0C00
+#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X	0x0000
+#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X	0x0400
+#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X	0x0800
+#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X	0x0C00
 /*
  * Number of times we will attempt to autonegotiate before downshifting if we
  * are the slave
  */
-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK  0x0300
-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS   0x0000
-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X    0x0100
-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X    0x0200
-#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X    0x0300
-#define M88E1000_EPSCR_TX_CLK_2_5       0x0060 /* 2.5 MHz TX_CLK */
-#define M88E1000_EPSCR_TX_CLK_25        0x0070 /* 25  MHz TX_CLK */
-#define M88E1000_EPSCR_TX_CLK_0         0x0000 /* NO  TX_CLK */
+#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK	0x0300
+#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS	0x0000
+#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X	0x0100
+#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X	0x0200
+#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X	0x0300
+#define M88E1000_EPSCR_TX_CLK_2_5	0x0060 /* 2.5 MHz TX_CLK */
+#define M88E1000_EPSCR_TX_CLK_25	0x0070 /* 25  MHz TX_CLK */
+#define M88E1000_EPSCR_TX_CLK_0		0x0000 /* NO  TX_CLK */
 
 /* M88E1111 Specific Registers */
-#define M88E1111_PHY_PAGE_SELECT1       0x16  /* for registers 0-28 */
-#define M88E1111_PHY_PAGE_SELECT2       0x1D  /* for registers 30-31 */
+#define M88E1111_PHY_PAGE_SELECT1	0x16  /* for registers 0-28 */
+#define M88E1111_PHY_PAGE_SELECT2	0x1D  /* for registers 30-31 */
 
 /* M88E1111 page select register mask */
-#define M88E1111_PHY_PAGE_SELECT_MASK1  0xFF
-#define M88E1111_PHY_PAGE_SELECT_MASK2  0x3F
+#define M88E1111_PHY_PAGE_SELECT_MASK1	0xFF
+#define M88E1111_PHY_PAGE_SELECT_MASK2	0x3F
 
 /* Intel I347AT4 Registers */
 
-#define I347AT4_PCDL            0x10 /* PHY Cable Diagnostics Length */
-#define I347AT4_PCDC            0x15 /* PHY Cable Diagnostics Control */
-#define I347AT4_PAGE_SELECT     0x16
+#define I347AT4_PCDL		0x10 /* PHY Cable Diagnostics Length */
+#define I347AT4_PCDC		0x15 /* PHY Cable Diagnostics Control */
+#define I347AT4_PAGE_SELECT	0x16
 
 /* I347AT4 Extended PHY Specific Control Register */
 
@@ -1609,213 +1641,220 @@
  * Number of times we will attempt to autonegotiate before downshifting if we
  * are the master
  */
-#define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800
-#define I347AT4_PSCR_DOWNSHIFT_MASK   0x7000
-#define I347AT4_PSCR_DOWNSHIFT_1X     0x0000
-#define I347AT4_PSCR_DOWNSHIFT_2X     0x1000
-#define I347AT4_PSCR_DOWNSHIFT_3X     0x2000
-#define I347AT4_PSCR_DOWNSHIFT_4X     0x3000
-#define I347AT4_PSCR_DOWNSHIFT_5X     0x4000
-#define I347AT4_PSCR_DOWNSHIFT_6X     0x5000
-#define I347AT4_PSCR_DOWNSHIFT_7X     0x6000
-#define I347AT4_PSCR_DOWNSHIFT_8X     0x7000
+#define I347AT4_PSCR_DOWNSHIFT_ENABLE	0x0800
+#define I347AT4_PSCR_DOWNSHIFT_MASK	0x7000
+#define I347AT4_PSCR_DOWNSHIFT_1X	0x0000
+#define I347AT4_PSCR_DOWNSHIFT_2X	0x1000
+#define I347AT4_PSCR_DOWNSHIFT_3X	0x2000
+#define I347AT4_PSCR_DOWNSHIFT_4X	0x3000
+#define I347AT4_PSCR_DOWNSHIFT_5X	0x4000
+#define I347AT4_PSCR_DOWNSHIFT_6X	0x5000
+#define I347AT4_PSCR_DOWNSHIFT_7X	0x6000
+#define I347AT4_PSCR_DOWNSHIFT_8X	0x7000
 
 /* I347AT4 PHY Cable Diagnostics Control */
-#define I347AT4_PCDC_CABLE_LENGTH_UNIT  0x0400 /* 0=cm 1=meters */
+#define I347AT4_PCDC_CABLE_LENGTH_UNIT	0x0400 /* 0=cm 1=meters */
 
 /* M88E1112 only registers */
-#define M88E1112_VCT_DSP_DISTANCE       0x001A
+#define M88E1112_VCT_DSP_DISTANCE	0x001A
 
 /* M88EC018 Rev 2 specific DownShift settings */
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK  0x0E00
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X    0x0000
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X    0x0200
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X    0x0400
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X    0x0600
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X    0x0800
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X    0x0A00
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X    0x0C00
-#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X    0x0E00
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK	0x0E00
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X	0x0000
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X	0x0200
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X	0x0400
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X	0x0600
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X	0x0800
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X	0x0A00
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X	0x0C00
+#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X	0x0E00
 
-#define I82578_EPSCR_DOWNSHIFT_ENABLE          0x0020
-#define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK    0x001C
+#define I82578_EPSCR_DOWNSHIFT_ENABLE		0x0020
+#define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK	0x001C
 
 /* BME1000 PHY Specific Control Register */
-#define BME1000_PSCR_ENABLE_DOWNSHIFT   0x0800 /* 1 = enable downshift */
+#define BME1000_PSCR_ENABLE_DOWNSHIFT	0x0800 /* 1 = enable downshift */
 
 /*
  * Bits...
  * 15-5: page
  * 4-0: register offset
  */
-#define GG82563_PAGE_SHIFT        5
-#define GG82563_REG(page, reg)    \
-        (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
-#define GG82563_MIN_ALT_REG       30
+#define GG82563_PAGE_SHIFT	5
+#define GG82563_REG(page, reg)	\
+	(((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
+#define GG82563_MIN_ALT_REG	30
 
 /* GG82563 Specific Registers */
-#define GG82563_PHY_SPEC_CTRL           \
-        GG82563_REG(0, 16) /* PHY Specific Control */
-#define GG82563_PHY_SPEC_STATUS         \
-        GG82563_REG(0, 17) /* PHY Specific Status */
-#define GG82563_PHY_INT_ENABLE          \
-        GG82563_REG(0, 18) /* Interrupt Enable */
-#define GG82563_PHY_SPEC_STATUS_2       \
-        GG82563_REG(0, 19) /* PHY Specific Status 2 */
-#define GG82563_PHY_RX_ERR_CNTR         \
-        GG82563_REG(0, 21) /* Receive Error Counter */
-#define GG82563_PHY_PAGE_SELECT         \
-        GG82563_REG(0, 22) /* Page Select */
-#define GG82563_PHY_SPEC_CTRL_2         \
-        GG82563_REG(0, 26) /* PHY Specific Control 2 */
-#define GG82563_PHY_PAGE_SELECT_ALT     \
-        GG82563_REG(0, 29) /* Alternate Page Select */
-#define GG82563_PHY_TEST_CLK_CTRL       \
-        GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
+#define GG82563_PHY_SPEC_CTRL		GG82563_REG(0, 16) /* PHY Spec Cntrl */
+#define GG82563_PHY_SPEC_STATUS		GG82563_REG(0, 17) /* PHY Spec Status */
+#define GG82563_PHY_INT_ENABLE		GG82563_REG(0, 18) /* Interrupt Ena */
+#define GG82563_PHY_SPEC_STATUS_2	GG82563_REG(0, 19) /* PHY Spec Stat2 */
+#define GG82563_PHY_RX_ERR_CNTR		GG82563_REG(0, 21) /* Rx Err Counter */
+#define GG82563_PHY_PAGE_SELECT		GG82563_REG(0, 22) /* Page Select */
+#define GG82563_PHY_SPEC_CTRL_2		GG82563_REG(0, 26) /* PHY Spec Cntrl2 */
+#define GG82563_PHY_PAGE_SELECT_ALT	GG82563_REG(0, 29) /* Alt Page Select */
+/* Test Clock Control (use reg. 29 to select) */
+#define GG82563_PHY_TEST_CLK_CTRL	GG82563_REG(0, 30)
 
-#define GG82563_PHY_MAC_SPEC_CTRL       \
-        GG82563_REG(2, 21) /* MAC Specific Control Register */
-#define GG82563_PHY_MAC_SPEC_CTRL_2     \
-        GG82563_REG(2, 26) /* MAC Specific Control 2 */
+/* MAC Specific Control Register */
+#define GG82563_PHY_MAC_SPEC_CTRL	GG82563_REG(2, 21)
+#define GG82563_PHY_MAC_SPEC_CTRL_2	GG82563_REG(2, 26) /* MAC Spec Ctrl 2 */
 
-#define GG82563_PHY_DSP_DISTANCE    \
-        GG82563_REG(5, 26) /* DSP Distance */
+#define GG82563_PHY_DSP_DISTANCE	GG82563_REG(5, 26) /* DSP Distance */
 
 /* Page 193 - Port Control Registers */
-#define GG82563_PHY_KMRN_MODE_CTRL   \
-        GG82563_REG(193, 16) /* Kumeran Mode Control */
-#define GG82563_PHY_PORT_RESET          \
-        GG82563_REG(193, 17) /* Port Reset */
-#define GG82563_PHY_REVISION_ID         \
-        GG82563_REG(193, 18) /* Revision ID */
-#define GG82563_PHY_DEVICE_ID           \
-        GG82563_REG(193, 19) /* Device ID */
-#define GG82563_PHY_PWR_MGMT_CTRL       \
-        GG82563_REG(193, 20) /* Power Management Control */
-#define GG82563_PHY_RATE_ADAPT_CTRL     \
-        GG82563_REG(193, 25) /* Rate Adaptation Control */
+/* Kumeran Mode Control */
+#define GG82563_PHY_KMRN_MODE_CTRL	GG82563_REG(193, 16)
+#define GG82563_PHY_PORT_RESET		GG82563_REG(193, 17) /* Port Reset */
+#define GG82563_PHY_REVISION_ID		GG82563_REG(193, 18) /* Revision ID */
+#define GG82563_PHY_DEVICE_ID		GG82563_REG(193, 19) /* Device ID */
+#define GG82563_PHY_PWR_MGMT_CTRL	GG82563_REG(193, 20) /* Pwr Mgt Ctrl */
+/* Rate Adaptation Control */
+#define GG82563_PHY_RATE_ADAPT_CTRL	GG82563_REG(193, 25)
 
 /* Page 194 - KMRN Registers */
-#define GG82563_PHY_KMRN_FIFO_CTRL_STAT \
-        GG82563_REG(194, 16) /* FIFO's Control/Status */
-#define GG82563_PHY_KMRN_CTRL           \
-        GG82563_REG(194, 17) /* Control */
-#define GG82563_PHY_INBAND_CTRL         \
-        GG82563_REG(194, 18) /* Inband Control */
-#define GG82563_PHY_KMRN_DIAGNOSTIC     \
-        GG82563_REG(194, 19) /* Diagnostic */
-#define GG82563_PHY_ACK_TIMEOUTS        \
-        GG82563_REG(194, 20) /* Acknowledge Timeouts */
-#define GG82563_PHY_ADV_ABILITY         \
-        GG82563_REG(194, 21) /* Advertised Ability */
-#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \
-        GG82563_REG(194, 23) /* Link Partner Advertised Ability */
-#define GG82563_PHY_ADV_NEXT_PAGE       \
-        GG82563_REG(194, 24) /* Advertised Next Page */
-#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \
-        GG82563_REG(194, 25) /* Link Partner Advertised Next page */
-#define GG82563_PHY_KMRN_MISC           \
-        GG82563_REG(194, 26) /* Misc. */
+/* FIFO's Control/Status */
+#define GG82563_PHY_KMRN_FIFO_CTRL_STAT	GG82563_REG(194, 16)
+#define GG82563_PHY_KMRN_CTRL		GG82563_REG(194, 17) /* Control */
+#define GG82563_PHY_INBAND_CTRL		GG82563_REG(194, 18) /* Inband Ctrl */
+#define GG82563_PHY_KMRN_DIAGNOSTIC	GG82563_REG(194, 19) /* Diagnostic */
+#define GG82563_PHY_ACK_TIMEOUTS	GG82563_REG(194, 20) /* Ack Timeouts */
+#define GG82563_PHY_ADV_ABILITY		GG82563_REG(194, 21) /* Adver Ability */
+/* Link Partner Advertised Ability */
+#define GG82563_PHY_LINK_PARTNER_ADV_ABILITY	GG82563_REG(194, 23)
+#define GG82563_PHY_ADV_NEXT_PAGE	GG82563_REG(194, 24) /* Adver Next Pg */
+/* Link Partner Advertised Next page */
+#define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE	GG82563_REG(194, 25)
+#define GG82563_PHY_KMRN_MISC		GG82563_REG(194, 26) /* Misc. */
 
 /* MDI Control */
-#define E1000_MDIC_DATA_MASK 0x0000FFFF
-#define E1000_MDIC_REG_MASK  0x001F0000
-#define E1000_MDIC_REG_SHIFT 16
-#define E1000_MDIC_PHY_MASK  0x03E00000
-#define E1000_MDIC_PHY_SHIFT 21
-#define E1000_MDIC_OP_WRITE  0x04000000
-#define E1000_MDIC_OP_READ   0x08000000
-#define E1000_MDIC_READY     0x10000000
-#define E1000_MDIC_INT_EN    0x20000000
-#define E1000_MDIC_ERROR     0x40000000
-#define E1000_MDIC_DEST      0x80000000
+#define E1000_MDIC_DATA_MASK	0x0000FFFF
+#define E1000_MDIC_REG_MASK	0x001F0000
+#define E1000_MDIC_REG_SHIFT	16
+#define E1000_MDIC_PHY_MASK	0x03E00000
+#define E1000_MDIC_PHY_SHIFT	21
+#define E1000_MDIC_OP_WRITE	0x04000000
+#define E1000_MDIC_OP_READ	0x08000000
+#define E1000_MDIC_READY	0x10000000
+#define E1000_MDIC_INT_EN	0x20000000
+#define E1000_MDIC_ERROR	0x40000000
+#define E1000_MDIC_DEST		0x80000000
 
 /* SerDes Control */
-#define E1000_GEN_CTL_READY             0x80000000
-#define E1000_GEN_CTL_ADDRESS_SHIFT     8
-#define E1000_GEN_POLL_TIMEOUT          640
+#define E1000_GEN_CTL_READY		0x80000000
+#define E1000_GEN_CTL_ADDRESS_SHIFT	8
+#define E1000_GEN_POLL_TIMEOUT		640
 
 /* LinkSec register fields */
-#define E1000_LSECTXCAP_SUM_MASK        0x00FF0000
-#define E1000_LSECTXCAP_SUM_SHIFT       16
-#define E1000_LSECRXCAP_SUM_MASK        0x00FF0000
-#define E1000_LSECRXCAP_SUM_SHIFT       16
+#define E1000_LSECTXCAP_SUM_MASK	0x00FF0000
+#define E1000_LSECTXCAP_SUM_SHIFT	16
+#define E1000_LSECRXCAP_SUM_MASK	0x00FF0000
+#define E1000_LSECRXCAP_SUM_SHIFT	16
 
-#define E1000_LSECTXCTRL_EN_MASK        0x00000003
-#define E1000_LSECTXCTRL_DISABLE        0x0
-#define E1000_LSECTXCTRL_AUTH           0x1
-#define E1000_LSECTXCTRL_AUTH_ENCRYPT   0x2
-#define E1000_LSECTXCTRL_AISCI          0x00000020
-#define E1000_LSECTXCTRL_PNTHRSH_MASK   0xFFFFFF00
-#define E1000_LSECTXCTRL_RSV_MASK       0x000000D8
+#define E1000_LSECTXCTRL_EN_MASK	0x00000003
+#define E1000_LSECTXCTRL_DISABLE	0x0
+#define E1000_LSECTXCTRL_AUTH		0x1
+#define E1000_LSECTXCTRL_AUTH_ENCRYPT	0x2
+#define E1000_LSECTXCTRL_AISCI		0x00000020
+#define E1000_LSECTXCTRL_PNTHRSH_MASK	0xFFFFFF00
+#define E1000_LSECTXCTRL_RSV_MASK	0x000000D8
 
-#define E1000_LSECRXCTRL_EN_MASK        0x0000000C
-#define E1000_LSECRXCTRL_EN_SHIFT       2
-#define E1000_LSECRXCTRL_DISABLE        0x0
-#define E1000_LSECRXCTRL_CHECK          0x1
-#define E1000_LSECRXCTRL_STRICT         0x2
-#define E1000_LSECRXCTRL_DROP           0x3
-#define E1000_LSECRXCTRL_PLSH           0x00000040
-#define E1000_LSECRXCTRL_RP             0x00000080
-#define E1000_LSECRXCTRL_RSV_MASK       0xFFFFFF33
+#define E1000_LSECRXCTRL_EN_MASK	0x0000000C
+#define E1000_LSECRXCTRL_EN_SHIFT	2
+#define E1000_LSECRXCTRL_DISABLE	0x0
+#define E1000_LSECRXCTRL_CHECK		0x1
+#define E1000_LSECRXCTRL_STRICT		0x2
+#define E1000_LSECRXCTRL_DROP		0x3
+#define E1000_LSECRXCTRL_PLSH		0x00000040
+#define E1000_LSECRXCTRL_RP		0x00000080
+#define E1000_LSECRXCTRL_RSV_MASK	0xFFFFFF33
 
 /* Tx Rate-Scheduler Config fields */
 #define E1000_RTTBCNRC_RS_ENA		0x80000000
 #define E1000_RTTBCNRC_RF_DEC_MASK	0x00003FFF
-#define E1000_RTTBCNRC_RF_INT_SHIFT     14
+#define E1000_RTTBCNRC_RF_INT_SHIFT	14
 #define E1000_RTTBCNRC_RF_INT_MASK	\
 	(E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT)
 
 /* DMA Coalescing register fields */
-#define E1000_DMACR_DMACWT_MASK         0x00003FFF /* DMA Coalescing
-                                                    * Watchdog Timer */
-#define E1000_DMACR_DMACTHR_MASK        0x00FF0000 /* DMA Coalescing Rx
-                                                    * Threshold */
-#define E1000_DMACR_DMACTHR_SHIFT       16
-#define E1000_DMACR_DMAC_LX_MASK        0x30000000 /* Lx when no PCIe
-                                                    * transactions */
-#define E1000_DMACR_DMAC_LX_SHIFT       28
-#define E1000_DMACR_DMAC_EN             0x80000000 /* Enable DMA Coalescing */
+/* DMA Coalescing Watchdog Timer */
+#define E1000_DMACR_DMACWT_MASK		0x00003FFF
+/* DMA Coalescing Rx Threshold */
+#define E1000_DMACR_DMACTHR_MASK	0x00FF0000
+#define E1000_DMACR_DMACTHR_SHIFT	16
+/* Lx when no PCIe transactions */
+#define E1000_DMACR_DMAC_LX_MASK	0x30000000
+#define E1000_DMACR_DMAC_LX_SHIFT	28
+#define E1000_DMACR_DMAC_EN		0x80000000 /* Enable DMA Coalescing */
 
-#define E1000_DMCTXTH_DMCTTHR_MASK      0x00000FFF /* DMA Coalescing Transmit
-                                                    * Threshold */
+/* DMA Coalescing Transmit Threshold */
+#define E1000_DMCTXTH_DMCTTHR_MASK	0x00000FFF
 
-#define E1000_DMCTLX_TTLX_MASK          0x00000FFF /* Time to LX request */
+#define E1000_DMCTLX_TTLX_MASK		0x00000FFF /* Time to LX request */
 
-#define E1000_DMCRTRH_UTRESH_MASK       0x0007FFFF /* Rx Traffic Rate
-                                                    * Threshold */
-#define E1000_DMCRTRH_LRPRCW            0x80000000 /* Rx packet rate in
-                                                    * current window */
+/* Rx Traffic Rate Threshold */
+#define E1000_DMCRTRH_UTRESH_MASK	0x0007FFFF
+/* Rx packet rate in current window */
+#define E1000_DMCRTRH_LRPRCW		0x80000000
 
-#define E1000_DMCCNT_CCOUNT_MASK        0x01FFFFFF /* DMA Coal Rx Traffic
-                                                    * Current Cnt */
+/* DMA Coal Rx Traffic Current Count */
+#define E1000_DMCCNT_CCOUNT_MASK	0x01FFFFFF
 
-#define E1000_FCRTC_RTH_COAL_MASK       0x0003FFF0 /* Flow ctrl Rx Threshold
-                                                    * High val */
-#define E1000_FCRTC_RTH_COAL_SHIFT      4
-#define E1000_PCIEMISC_LX_DECISION      0x00000080 /* Lx power decision based
-                                                      on DMA coal */
+/* Flow ctrl Rx Threshold High val */
+#define E1000_FCRTC_RTH_COAL_MASK	0x0003FFF0
+#define E1000_FCRTC_RTH_COAL_SHIFT	4
+/* Lx power decision based on DMA coal */
+#define E1000_PCIEMISC_LX_DECISION	0x00000080
+
+#define E1000_LTRC_EEEMS_EN		0x00000005 /* Enable EEE LTR max send */
+#define E1000_RXPBS_SIZE_I210_MASK	0x0000003F /* Rx packet buffer size */
+/* Minimum time for 1000BASE-T where no data will be transmit following move out
+ * of EEE LPI Tx state
+ */
+#define E1000_TW_SYSTEM_1000_MASK	0x000000FF
+/* Minimum time for 100BASE-T where no data will be transmit following move out
+ * of EEE LPI Tx state
+ */
+#define E1000_TW_SYSTEM_100_MASK	0x0000FF00
+#define E1000_TW_SYSTEM_100_SHIFT	8
+#define E1000_LTRMINV_LTRV_MASK		0x000003FF /* LTR minimum value */
+#define E1000_LTRMAXV_LTRV_MASK		0x000003FF /* LTR maximum value */
+#define E1000_LTRMINV_SCALE_MASK	0x00001C00 /* LTR minimum scale */
+#define E1000_LTRMINV_SCALE_SHIFT	10
+/* Reg val to set scale to 1024 nsec */
+#define E1000_LTRMINV_SCALE_1024	2
+/* Reg val to set scale to 32768 nsec */
+#define E1000_LTRMINV_SCALE_32768	3
+#define E1000_LTRMAXV_SCALE_MASK	0x00001C00 /* LTR maximum scale */
+#define E1000_LTRMAXV_SCALE_SHIFT	10
+/* Reg val to set scale to 1024 nsec */
+#define E1000_LTRMAXV_SCALE_1024	2
+/* Reg val to set scale to 32768 nsec */
+#define E1000_LTRMAXV_SCALE_32768	3
+#define E1000_DOBFFCTL_OBFFTHR_MASK	0x000000FF /* OBFF threshold */
+#define E1000_DOBFFCTL_EXIT_ACT_MASK	0x01000000 /* Exit active CB */
 
 /* Proxy Filer Control */
-#define E1000_PROXYFC_D0               0x00000001  /* Enable offload in D0 */
-#define E1000_PROXYFC_EX               0x00000004  /* Directed exact proxy */
-#define E1000_PROXYFC_MC               0x00000008  /* Directed Multicast
-                                                    * Proxy */
-#define E1000_PROXYFC_BC               0x00000010  /* Broadcast Proxy Enable */
-#define E1000_PROXYFC_ARP_DIRECTED     0x00000020  /* Directed ARP Proxy
-                                                    * Enable */
-#define E1000_PROXYFC_IPV4             0x00000040  /* Directed IPv4 Enable */
-#define E1000_PROXYFC_IPV6             0x00000080  /* Directed IPv6 Enable */
-#define E1000_PROXYFC_NS               0x00000200  /* IPv4 Neighborhood
-                                                    * Solicitation */
-#define E1000_PROXYFC_ARP              0x00000800  /* ARP Request Proxy
-                                                    * Enable */
+#define E1000_PROXYFC_D0		0x00000001 /* Enable offload in D0 */
+#define E1000_PROXYFC_EX		0x00000004 /* Directed exact proxy */
+#define E1000_PROXYFC_MC		0x00000008 /* Directed MC Proxy */
+#define E1000_PROXYFC_BC		0x00000010 /* Broadcast Proxy Enable */
+#define E1000_PROXYFC_ARP_DIRECTED	0x00000020 /* Directed ARP Proxy Ena */
+#define E1000_PROXYFC_IPV4		0x00000040 /* Directed IPv4 Enable */
+#define E1000_PROXYFC_IPV6		0x00000080 /* Directed IPv6 Enable */
+#define E1000_PROXYFC_NS		0x00000200 /* IPv4 NBRHD Solicitation */
+#define E1000_PROXYFC_ARP		0x00000800 /* ARP Request Proxy Ena */
 /* Proxy Status */
-#define E1000_PROXYS_CLEAR             0xFFFFFFFF  /* Clear */
+#define E1000_PROXYS_CLEAR		0xFFFFFFFF /* Clear */
 
 /* Firmware Status */
-#define E1000_FWSTS_FWRI               0x80000000 /* Firmware Reset
-                                                   * Indication */
+#define E1000_FWSTS_FWRI		0x80000000 /* FW Reset Indication */
+/* VF Control */
+#define E1000_VTCTRL_RST		0x04000000 /* Reset VF */
 
-
+#define E1000_STATUS_LAN_ID_MASK	0x00000000C /* Mask for Lan ID field */
+/* Lan ID bit field offset in status register */
+#define E1000_STATUS_LAN_ID_OFFSET	2
+#define E1000_VFTA_ENTRIES		128
 #endif /* _E1000_DEFINES_H_ */
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/e1000/e1000_hw.h
--- a/head/sys/dev/e1000/e1000_hw.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/e1000/e1000_hw.h	Thu Dec 15 12:59:38 2011 +0200
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD: head/sys/dev/e1000/e1000_hw.h 228441 2011-12-12 18:27:34Z mdf $*/
 
 #ifndef _E1000_HW_H_
 #define _E1000_HW_H_
@@ -41,139 +41,138 @@
 
 struct e1000_hw;
 
-#define E1000_DEV_ID_82542                    0x1000
-#define E1000_DEV_ID_82543GC_FIBER            0x1001
-#define E1000_DEV_ID_82543GC_COPPER           0x1004
-#define E1000_DEV_ID_82544EI_COPPER           0x1008
-#define E1000_DEV_ID_82544EI_FIBER            0x1009
-#define E1000_DEV_ID_82544GC_COPPER           0x100C
-#define E1000_DEV_ID_82544GC_LOM              0x100D
-#define E1000_DEV_ID_82540EM                  0x100E
-#define E1000_DEV_ID_82540EM_LOM              0x1015
-#define E1000_DEV_ID_82540EP_LOM              0x1016
-#define E1000_DEV_ID_82540EP                  0x1017
-#define E1000_DEV_ID_82540EP_LP               0x101E
-#define E1000_DEV_ID_82545EM_COPPER           0x100F
-#define E1000_DEV_ID_82545EM_FIBER            0x1011
-#define E1000_DEV_ID_82545GM_COPPER           0x1026
-#define E1000_DEV_ID_82545GM_FIBER            0x1027
-#define E1000_DEV_ID_82545GM_SERDES           0x1028
-#define E1000_DEV_ID_82546EB_COPPER           0x1010
-#define E1000_DEV_ID_82546EB_FIBER            0x1012
-#define E1000_DEV_ID_82546EB_QUAD_COPPER      0x101D
-#define E1000_DEV_ID_82546GB_COPPER           0x1079
-#define E1000_DEV_ID_82546GB_FIBER            0x107A
-#define E1000_DEV_ID_82546GB_SERDES           0x107B
-#define E1000_DEV_ID_82546GB_PCIE             0x108A
-#define E1000_DEV_ID_82546GB_QUAD_COPPER      0x1099
-#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
-#define E1000_DEV_ID_82541EI                  0x1013
-#define E1000_DEV_ID_82541EI_MOBILE           0x1018
-#define E1000_DEV_ID_82541ER_LOM              0x1014
-#define E1000_DEV_ID_82541ER                  0x1078
-#define E1000_DEV_ID_82541GI                  0x1076
-#define E1000_DEV_ID_82541GI_LF               0x107C
-#define E1000_DEV_ID_82541GI_MOBILE           0x1077
-#define E1000_DEV_ID_82547EI                  0x1019
-#define E1000_DEV_ID_82547EI_MOBILE           0x101A
-#define E1000_DEV_ID_82547GI                  0x1075
-#define E1000_DEV_ID_82571EB_COPPER           0x105E
-#define E1000_DEV_ID_82571EB_FIBER            0x105F
-#define E1000_DEV_ID_82571EB_SERDES           0x1060
-#define E1000_DEV_ID_82571EB_SERDES_DUAL      0x10D9
-#define E1000_DEV_ID_82571EB_SERDES_QUAD      0x10DA
-#define E1000_DEV_ID_82571EB_QUAD_COPPER      0x10A4
-#define E1000_DEV_ID_82571PT_QUAD_COPPER      0x10D5
-#define E1000_DEV_ID_82571EB_QUAD_FIBER       0x10A5
-#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP   0x10BC
-#define E1000_DEV_ID_82572EI_COPPER           0x107D
-#define E1000_DEV_ID_82572EI_FIBER            0x107E
-#define E1000_DEV_ID_82572EI_SERDES           0x107F
-#define E1000_DEV_ID_82572EI                  0x10B9
-#define E1000_DEV_ID_82573E                   0x108B
-#define E1000_DEV_ID_82573E_IAMT              0x108C
-#define E1000_DEV_ID_82573L                   0x109A
-#define E1000_DEV_ID_82574L                   0x10D3
-#define E1000_DEV_ID_82574LA                  0x10F6
-#define E1000_DEV_ID_82583V                   0x150C
-#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT   0x1096
-#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT   0x1098
-#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT   0x10BA
-#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT   0x10BB
-#define E1000_DEV_ID_ICH8_82567V_3            0x1501
-#define E1000_DEV_ID_ICH8_IGP_M_AMT           0x1049
-#define E1000_DEV_ID_ICH8_IGP_AMT             0x104A
-#define E1000_DEV_ID_ICH8_IGP_C               0x104B
-#define E1000_DEV_ID_ICH8_IFE                 0x104C
-#define E1000_DEV_ID_ICH8_IFE_GT              0x10C4
-#define E1000_DEV_ID_ICH8_IFE_G               0x10C5
-#define E1000_DEV_ID_ICH8_IGP_M               0x104D
-#define E1000_DEV_ID_ICH9_IGP_M               0x10BF
-#define E1000_DEV_ID_ICH9_IGP_M_AMT           0x10F5
-#define E1000_DEV_ID_ICH9_IGP_M_V             0x10CB
-#define E1000_DEV_ID_ICH9_IGP_AMT             0x10BD
-#define E1000_DEV_ID_ICH9_BM                  0x10E5
-#define E1000_DEV_ID_ICH9_IGP_C               0x294C
-#define E1000_DEV_ID_ICH9_IFE                 0x10C0
-#define E1000_DEV_ID_ICH9_IFE_GT              0x10C3
-#define E1000_DEV_ID_ICH9_IFE_G               0x10C2
-#define E1000_DEV_ID_ICH10_R_BM_LM            0x10CC
-#define E1000_DEV_ID_ICH10_R_BM_LF            0x10CD
-#define E1000_DEV_ID_ICH10_R_BM_V             0x10CE
-#define E1000_DEV_ID_ICH10_HANKSVILLE         0xF0FE
-#define E1000_DEV_ID_ICH10_D_BM_LM            0x10DE
-#define E1000_DEV_ID_ICH10_D_BM_LF            0x10DF
-#define E1000_DEV_ID_ICH10_D_BM_V             0x1525
+#define E1000_DEV_ID_82542			0x1000
+#define E1000_DEV_ID_82543GC_FIBER		0x1001
+#define E1000_DEV_ID_82543GC_COPPER		0x1004
+#define E1000_DEV_ID_82544EI_COPPER		0x1008
+#define E1000_DEV_ID_82544EI_FIBER		0x1009
+#define E1000_DEV_ID_82544GC_COPPER		0x100C
+#define E1000_DEV_ID_82544GC_LOM		0x100D
+#define E1000_DEV_ID_82540EM			0x100E
+#define E1000_DEV_ID_82540EM_LOM		0x1015
+#define E1000_DEV_ID_82540EP_LOM		0x1016
+#define E1000_DEV_ID_82540EP			0x1017
+#define E1000_DEV_ID_82540EP_LP			0x101E
+#define E1000_DEV_ID_82545EM_COPPER		0x100F
+#define E1000_DEV_ID_82545EM_FIBER		0x1011
+#define E1000_DEV_ID_82545GM_COPPER		0x1026
+#define E1000_DEV_ID_82545GM_FIBER		0x1027
+#define E1000_DEV_ID_82545GM_SERDES		0x1028
+#define E1000_DEV_ID_82546EB_COPPER		0x1010
+#define E1000_DEV_ID_82546EB_FIBER		0x1012
+#define E1000_DEV_ID_82546EB_QUAD_COPPER	0x101D
+#define E1000_DEV_ID_82546GB_COPPER		0x1079
+#define E1000_DEV_ID_82546GB_FIBER		0x107A
+#define E1000_DEV_ID_82546GB_SERDES		0x107B
+#define E1000_DEV_ID_82546GB_PCIE		0x108A
+#define E1000_DEV_ID_82546GB_QUAD_COPPER	0x1099
+#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3	0x10B5
+#define E1000_DEV_ID_82541EI			0x1013
+#define E1000_DEV_ID_82541EI_MOBILE		0x1018
+#define E1000_DEV_ID_82541ER_LOM		0x1014
+#define E1000_DEV_ID_82541ER			0x1078
+#define E1000_DEV_ID_82541GI			0x1076
+#define E1000_DEV_ID_82541GI_LF			0x107C
+#define E1000_DEV_ID_82541GI_MOBILE		0x1077
+#define E1000_DEV_ID_82547EI			0x1019
+#define E1000_DEV_ID_82547EI_MOBILE		0x101A
+#define E1000_DEV_ID_82547GI			0x1075
+#define E1000_DEV_ID_82571EB_COPPER		0x105E
+#define E1000_DEV_ID_82571EB_FIBER		0x105F
+#define E1000_DEV_ID_82571EB_SERDES		0x1060
+#define E1000_DEV_ID_82571EB_SERDES_DUAL	0x10D9
+#define E1000_DEV_ID_82571EB_SERDES_QUAD	0x10DA
+#define E1000_DEV_ID_82571EB_QUAD_COPPER	0x10A4
+#define E1000_DEV_ID_82571PT_QUAD_COPPER	0x10D5
+#define E1000_DEV_ID_82571EB_QUAD_FIBER		0x10A5
+#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP	0x10BC
+#define E1000_DEV_ID_82572EI_COPPER		0x107D
+#define E1000_DEV_ID_82572EI_FIBER		0x107E
+#define E1000_DEV_ID_82572EI_SERDES		0x107F
+#define E1000_DEV_ID_82572EI			0x10B9
+#define E1000_DEV_ID_82573E			0x108B
+#define E1000_DEV_ID_82573E_IAMT		0x108C
+#define E1000_DEV_ID_82573L			0x109A
+#define E1000_DEV_ID_82574L			0x10D3
+#define E1000_DEV_ID_82574LA			0x10F6
+#define E1000_DEV_ID_82583V			0x150C
+#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT	0x1096
+#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT	0x1098
+#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT	0x10BA
+#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT	0x10BB
+#define E1000_DEV_ID_ICH8_82567V_3		0x1501
+#define E1000_DEV_ID_ICH8_IGP_M_AMT		0x1049
+#define E1000_DEV_ID_ICH8_IGP_AMT		0x104A
+#define E1000_DEV_ID_ICH8_IGP_C			0x104B
+#define E1000_DEV_ID_ICH8_IFE			0x104C
+#define E1000_DEV_ID_ICH8_IFE_GT		0x10C4
+#define E1000_DEV_ID_ICH8_IFE_G			0x10C5
+#define E1000_DEV_ID_ICH8_IGP_M			0x104D
+#define E1000_DEV_ID_ICH9_IGP_M			0x10BF
+#define E1000_DEV_ID_ICH9_IGP_M_AMT		0x10F5
+#define E1000_DEV_ID_ICH9_IGP_M_V		0x10CB
+#define E1000_DEV_ID_ICH9_IGP_AMT		0x10BD
+#define E1000_DEV_ID_ICH9_BM			0x10E5
+#define E1000_DEV_ID_ICH9_IGP_C			0x294C
+#define E1000_DEV_ID_ICH9_IFE			0x10C0
+#define E1000_DEV_ID_ICH9_IFE_GT		0x10C3
+#define E1000_DEV_ID_ICH9_IFE_G			0x10C2
+#define E1000_DEV_ID_ICH10_R_BM_LM		0x10CC
+#define E1000_DEV_ID_ICH10_R_BM_LF		0x10CD
+#define E1000_DEV_ID_ICH10_R_BM_V		0x10CE
+#define E1000_DEV_ID_ICH10_D_BM_LM		0x10DE
+#define E1000_DEV_ID_ICH10_D_BM_LF		0x10DF
+#define E1000_DEV_ID_ICH10_D_BM_V		0x1525
 
-#define E1000_DEV_ID_PCH_M_HV_LM              0x10EA
-#define E1000_DEV_ID_PCH_M_HV_LC              0x10EB
-#define E1000_DEV_ID_PCH_D_HV_DM              0x10EF
-#define E1000_DEV_ID_PCH_D_HV_DC              0x10F0
-#define E1000_DEV_ID_PCH2_LV_LM               0x1502
-#define E1000_DEV_ID_PCH2_LV_V                0x1503
-#define E1000_DEV_ID_82576                    0x10C9
-#define E1000_DEV_ID_82576_FIBER              0x10E6
-#define E1000_DEV_ID_82576_SERDES             0x10E7
-#define E1000_DEV_ID_82576_QUAD_COPPER        0x10E8
-#define E1000_DEV_ID_82576_QUAD_COPPER_ET2    0x1526
-#define E1000_DEV_ID_82576_NS                 0x150A
-#define E1000_DEV_ID_82576_NS_SERDES          0x1518
-#define E1000_DEV_ID_82576_SERDES_QUAD        0x150D
-#define E1000_DEV_ID_82576_VF                 0x10CA
-#define E1000_DEV_ID_I350_VF                  0x1520
-#define E1000_DEV_ID_82575EB_COPPER           0x10A7
-#define E1000_DEV_ID_82575EB_FIBER_SERDES     0x10A9
-#define E1000_DEV_ID_82575GB_QUAD_COPPER      0x10D6
-#define E1000_DEV_ID_82575GB_QUAD_COPPER_PM   0x10E2
-#define E1000_DEV_ID_82580_COPPER             0x150E
-#define E1000_DEV_ID_82580_FIBER              0x150F
-#define E1000_DEV_ID_82580_SERDES             0x1510
-#define E1000_DEV_ID_82580_SGMII              0x1511
-#define E1000_DEV_ID_82580_COPPER_DUAL        0x1516
-#define E1000_DEV_ID_82580_QUAD_FIBER         0x1527
-#define E1000_DEV_ID_I350_COPPER              0x1521
-#define E1000_DEV_ID_I350_FIBER               0x1522
-#define E1000_DEV_ID_I350_SERDES              0x1523
-#define E1000_DEV_ID_I350_SGMII               0x1524
-#define E1000_DEV_ID_DH89XXCC_SGMII           0x0438
-#define E1000_DEV_ID_DH89XXCC_SERDES          0x043A
-#define E1000_DEV_ID_DH89XXCC_BACKPLANE       0x043C
-#define E1000_DEV_ID_DH89XXCC_SFP             0x0440
-#define E1000_REVISION_0 0
-#define E1000_REVISION_1 1
-#define E1000_REVISION_2 2
-#define E1000_REVISION_3 3
-#define E1000_REVISION_4 4
+#define E1000_DEV_ID_PCH_M_HV_LM		0x10EA
+#define E1000_DEV_ID_PCH_M_HV_LC		0x10EB
+#define E1000_DEV_ID_PCH_D_HV_DM		0x10EF
+#define E1000_DEV_ID_PCH_D_HV_DC		0x10F0
+#define E1000_DEV_ID_PCH2_LV_LM			0x1502
+#define E1000_DEV_ID_PCH2_LV_V			0x1503
+#define E1000_DEV_ID_82576			0x10C9
+#define E1000_DEV_ID_82576_FIBER		0x10E6
+#define E1000_DEV_ID_82576_SERDES		0x10E7
+#define E1000_DEV_ID_82576_QUAD_COPPER		0x10E8
+#define E1000_DEV_ID_82576_QUAD_COPPER_ET2	0x1526
+#define E1000_DEV_ID_82576_NS			0x150A
+#define E1000_DEV_ID_82576_NS_SERDES		0x1518
+#define E1000_DEV_ID_82576_SERDES_QUAD		0x150D
+#define E1000_DEV_ID_82576_VF			0x10CA
+#define E1000_DEV_ID_I350_VF			0x1520
+#define E1000_DEV_ID_82575EB_COPPER		0x10A7
+#define E1000_DEV_ID_82575EB_FIBER_SERDES	0x10A9
+#define E1000_DEV_ID_82575GB_QUAD_COPPER	0x10D6
+#define E1000_DEV_ID_82580_COPPER		0x150E
+#define E1000_DEV_ID_82580_FIBER		0x150F
+#define E1000_DEV_ID_82580_SERDES		0x1510
+#define E1000_DEV_ID_82580_SGMII		0x1511
+#define E1000_DEV_ID_82580_COPPER_DUAL		0x1516
+#define E1000_DEV_ID_82580_QUAD_FIBER		0x1527
+#define E1000_DEV_ID_I350_COPPER		0x1521
+#define E1000_DEV_ID_I350_FIBER			0x1522
+#define E1000_DEV_ID_I350_SERDES		0x1523
+#define E1000_DEV_ID_I350_SGMII			0x1524
+#define E1000_DEV_ID_I350_DA4			0x1546
+#define E1000_DEV_ID_DH89XXCC_SGMII		0x0438
+#define E1000_DEV_ID_DH89XXCC_SERDES		0x043A
+#define E1000_DEV_ID_DH89XXCC_BACKPLANE		0x043C
+#define E1000_DEV_ID_DH89XXCC_SFP		0x0440
+#define E1000_REVISION_0	0
+#define E1000_REVISION_1	1
+#define E1000_REVISION_2	2
+#define E1000_REVISION_3	3
+#define E1000_REVISION_4	4
 
-#define E1000_FUNC_0     0
-#define E1000_FUNC_1     1
-#define E1000_FUNC_2     2
-#define E1000_FUNC_3     3
+#define E1000_FUNC_0		0
+#define E1000_FUNC_1		1
+#define E1000_FUNC_2		2
+#define E1000_FUNC_3		3
 
-#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0
-#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
-#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2   6
-#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3   9
+#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0	0
+#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1	3
+#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2	6
+#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3	9
 
 enum e1000_mac_type {
 	e1000_undefined = 0,
@@ -342,9 +341,9 @@
 struct e1000_rx_desc {
 	__le64 buffer_addr; /* Address of the descriptor's data buffer */
 	__le16 length;      /* Length of data DMAed into data buffer */
-	__le16 csum;        /* Packet checksum */
-	u8  status;         /* Descriptor status */
-	u8  errors;         /* Descriptor Errors */
+	__le16 csum; /* Packet checksum */
+	u8  status;  /* Descriptor status */
+	u8  errors;  /* Descriptor Errors */
 	__le16 special;
 };
 
@@ -356,9 +355,9 @@
 	} read;
 	struct {
 		struct {
-			__le32 mrq;           /* Multiple Rx Queues */
+			__le32 mrq; /* Multiple Rx Queues */
 			union {
-				__le32 rss;         /* RSS Hash */
+				__le32 rss; /* RSS Hash */
 				struct {
 					__le16 ip_id;  /* IP id */
 					__le16 csum;   /* Packet Checksum */
@@ -368,7 +367,7 @@
 		struct {
 			__le32 status_error;  /* ext status/error */
 			__le16 length;
-			__le16 vlan;          /* VLAN tag */
+			__le16 vlan; /* VLAN tag */
 		} upper;
 	} wb;  /* writeback */
 };
@@ -382,9 +381,9 @@
 	} read;
 	struct {
 		struct {
-			__le32 mrq;           /* Multiple Rx Queues */
+			__le32 mrq;  /* Multiple Rx Queues */
 			union {
-				__le32 rss;           /* RSS Hash */
+				__le32 rss; /* RSS Hash */
 				struct {
 					__le16 ip_id;    /* IP id */
 					__le16 csum;     /* Packet Checksum */
@@ -393,8 +392,8 @@
 		} lower;
 		struct {
 			__le32 status_error;  /* ext status/error */
-			__le16 length0;       /* length of buffer 0 */
-			__le16 vlan;          /* VLAN tag */
+			__le16 length0;  /* length of buffer 0 */
+			__le16 vlan;  /* VLAN tag */
 		} middle;
 		struct {
 			__le16 header_status;
@@ -410,16 +409,16 @@
 	union {
 		__le32 data;
 		struct {
-			__le16 length;    /* Data buffer length */
-			u8 cso;           /* Checksum offset */
-			u8 cmd;           /* Descriptor control */
+			__le16 length;  /* Data buffer length */
+			u8 cso;  /* Checksum offset */
+			u8 cmd;  /* Descriptor control */
 		} flags;
 	} lower;
 	union {
 		__le32 data;
 		struct {
-			u8 status;        /* Descriptor status */
-			u8 css;           /* Checksum start */
+			u8 status; /* Descriptor status */
+			u8 css;  /* Checksum start */
 			__le16 special;
 		} fields;
 	} upper;
@@ -430,37 +429,37 @@
 	union {
 		__le32 ip_config;
 		struct {
-			u8 ipcss;         /* IP checksum start */
-			u8 ipcso;         /* IP checksum offset */
-			__le16 ipcse;     /* IP checksum end */
+			u8 ipcss;  /* IP checksum start */
+			u8 ipcso;  /* IP checksum offset */
+			__le16 ipcse;  /* IP checksum end */
 		} ip_fields;
 	} lower_setup;
 	union {
 		__le32 tcp_config;
 		struct {
-			u8 tucss;         /* TCP checksum start */
-			u8 tucso;         /* TCP checksum offset */
-			__le16 tucse;     /* TCP checksum end */
+			u8 tucss;  /* TCP checksum start */
+			u8 tucso;  /* TCP checksum offset */
+			__le16 tucse;  /* TCP checksum end */
 		} tcp_fields;
 	} upper_setup;
 	__le32 cmd_and_length;
 	union {
 		__le32 data;
 		struct {
-			u8 status;        /* Descriptor status */
-			u8 hdr_len;       /* Header length */
-			__le16 mss;       /* Maximum segment size */
+			u8 status;  /* Descriptor status */
+			u8 hdr_len;  /* Header length */
+			__le16 mss;  /* Maximum segment size */
 		} fields;
 	} tcp_seg_setup;
 };
 
 /* Offload data descriptor */
 struct e1000_data_desc {
-	__le64 buffer_addr;   /* Address of the descriptor's buffer address */
+	__le64 buffer_addr;  /* Address of the descriptor's buffer address */
 	union {
 		__le32 data;
 		struct {
-			__le16 length;    /* Data buffer length */
+			__le16 length;  /* Data buffer length */
 			u8 typ_len_ext;
 			u8 cmd;
 		} flags;
@@ -468,8 +467,8 @@
 	union {
 		__le32 data;
 		struct {
-			u8 status;        /* Descriptor status */
-			u8 popts;         /* Packet Options */
+			u8 status;  /* Descriptor status */
+			u8 popts;  /* Packet Options */
 			__le16 special;
 		} fields;
 	} upper;
@@ -553,6 +552,10 @@
 	u64 scvpc;
 	u64 hrmpc;
 	u64 doosync;
+	u64 o2bgptc;
+	u64 o2bspc;
+	u64 b2ospc;
+	u64 b2ogprc;
 };
 
 struct e1000_vf_stats {
@@ -611,7 +614,7 @@
 	u8 checksum;
 };
 
-#define E1000_HI_MAX_DATA_LENGTH     252
+#define E1000_HI_MAX_DATA_LENGTH	252
 struct e1000_host_command_info {
 	struct e1000_host_command_header command_header;
 	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
@@ -626,7 +629,7 @@
 	u16 command_length;
 };
 
-#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
+#define E1000_HI_MAX_MNG_DATA_LENGTH	0x6F8
 struct e1000_host_mng_command_info {
 	struct e1000_host_mng_command_header command_header;
 	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
@@ -668,11 +671,26 @@
 	s32  (*validate_mdi_setting)(struct e1000_hw *);
 	s32  (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
 	s32  (*mng_write_cmd_header)(struct e1000_hw *hw,
-                      struct e1000_host_mng_command_header*);
+				     struct e1000_host_mng_command_header*);
 	s32  (*mng_enable_host_if)(struct e1000_hw *);
 	s32  (*wait_autoneg)(struct e1000_hw *);
 };
 
+/*
+ * When to use various PHY register access functions:
+ *
+ *                 Func   Caller
+ *   Function      Does   Does    When to use
+ *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *   X_reg         L,P,A  n/a     for simple PHY reg accesses
+ *   X_reg_locked  P,A    L       for multiple accesses of different regs
+ *                                on different pages
+ *   X_reg_page    A      L,P     for multiple accesses of different regs
+ *                                on the same page
+ *
+ * Where X=[read|write], L=locking, P=sets page, A=register access
+ *
+ */
 struct e1000_phy_operations {
 	s32  (*init_params)(struct e1000_hw *);
 	s32  (*acquire)(struct e1000_hw *);
@@ -684,16 +702,21 @@
 	s32  (*get_cfg_done)(struct e1000_hw *hw);
 	s32  (*get_cable_length)(struct e1000_hw *);
 	s32  (*get_info)(struct e1000_hw *);
+	s32  (*set_page)(struct e1000_hw *, u16);
 	s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 	s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
+	s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
 	void (*release)(struct e1000_hw *);
 	s32  (*reset)(struct e1000_hw *);
 	s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 	s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 	s32  (*write_reg)(struct e1000_hw *, u32, u16);
 	s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
+	s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
 	void (*power_up)(struct e1000_hw *);
 	void (*power_down)(struct e1000_hw *);
+	s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
+	s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
 };
 
 struct e1000_nvm_operations {
@@ -781,7 +804,6 @@
 	bool disable_polarity_correction;
 	bool is_mdix;
 	bool polarity_correction;
-	bool reset_disable;
 	bool speed_downgraded;
 	bool autoneg_wait_to_complete;
 };
@@ -811,14 +833,14 @@
 };
 
 struct e1000_fc_info {
-	u32 high_water;          /* Flow control high-water mark */
-	u32 low_water;           /* Flow control low-water mark */
-	u16 pause_time;          /* Flow control pause timer */
-	u16 refresh_time;        /* Flow control refresh timer */
-	bool send_xon;           /* Flow control send XON */
-	bool strict_ieee;        /* Strict IEEE mode */
-	enum e1000_fc_mode current_mode; /* FC mode in effect */
-	enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
+	u32 high_water;  /* Flow control high-water mark */
+	u32 low_water;  /* Flow control low-water mark */
+	u16 pause_time;  /* Flow control pause timer */
+	u16 refresh_time;  /* Flow control refresh timer */
+	bool send_xon;  /* Flow control send XON */
+	bool strict_ieee;  /* Strict IEEE mode */
+	enum e1000_fc_mode current_mode;  /* FC mode in effect */
+	enum e1000_fc_mode requested_mode;  /* FC mode requested by caller */
 };
 
 struct e1000_mbx_operations {
@@ -889,13 +911,15 @@
 	E1000_MUTEX nvm_mutex;
 	E1000_MUTEX swflag_mutex;
 	bool nvm_k1_enabled;
-	bool eee_disable;
+	int eee_disable;
 };
 
 struct e1000_dev_spec_82575 {
 	bool sgmii_active;
 	bool global_device_reset;
-	bool eee_disable;
+	int eee_disable;
+	bool module_plugged;
+	u32 mtu;
 };
 
 struct e1000_dev_spec_vf {
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/e1000/e1000_ich8lan.c
--- a/head/sys/dev/e1000/e1000_ich8lan.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/e1000/e1000_ich8lan.c	Thu Dec 15 12:59:38 2011 +0200
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD: head/sys/dev/e1000/e1000_ich8lan.c 228386 2011-12-10 06:55:02Z jfv $*/
 
 /*
  * 82562G 10/100 Network Connection
@@ -76,23 +76,23 @@
 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
-                                              u8 *mc_addr_list,
-                                              u32 mc_addr_count);
+					      u8 *mc_addr_list,
+					      u32 mc_addr_count);
 static s32  e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
 static s32  e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
 static s32  e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 static s32  e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
-                                            bool active);
+					    bool active);
 static s32  e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
-                                            bool active);
+					    bool active);
 static s32  e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
-                                   u16 words, u16 *data);
+				   u16 words, u16 *data);
 static s32  e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
-                                    u16 words, u16 *data);
+				    u16 words, u16 *data);
 static s32  e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
 static s32  e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
 static s32  e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
-                                            u16 *data);
+					    u16 *data);
 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 static s32  e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
 static s32  e1000_reset_hw_ich8lan(struct e1000_hw *hw);
@@ -100,7 +100,7 @@
 static s32  e1000_setup_link_ich8lan(struct e1000_hw *hw);
 static s32  e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 static s32  e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
-                                           u16 *speed, u16 *duplex);
+					   u16 *speed, u16 *duplex);
 static s32  e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 static s32  e1000_led_on_ich8lan(struct e1000_hw *hw);
 static s32  e1000_led_off_ich8lan(struct e1000_hw *hw);
@@ -116,17 +116,17 @@
 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 static s32  e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 static s32  e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
-                                          u32 offset, u8 *data);
+					  u32 offset, u8 *data);
 static s32  e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
-                                          u8 size, u16 *data);
+					  u8 size, u16 *data);
 static s32  e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
-                                          u32 offset, u16 *data);
+					  u32 offset, u16 *data);
 static s32  e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
-                                                 u32 offset, u8 byte);
+						 u32 offset, u8 byte);
 static s32  e1000_write_flash_byte_ich8lan(struct e1000_hw *hw,
-                                           u32 offset, u8 data);
+					   u32 offset, u8 data);
 static s32  e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
-                                           u8 size, u16 data);
+					   u8 size, u16 data);
 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
@@ -135,20 +135,23 @@
 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
+#if defined(NAHUM6_HW) && (defined(LTR_SUPPORT) || defined(OBFF_SUPPORT))
+
+#endif /* NAHUM6_HW && (LTR_SUPPORT || OBFF_SUPPORT) */
 
 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 /* Offset 04h HSFSTS */
 union ich8_hws_flash_status {
 	struct ich8_hsfsts {
-		u16 flcdone    :1; /* bit 0 Flash Cycle Done */
-		u16 flcerr     :1; /* bit 1 Flash Cycle Error */
-		u16 dael       :1; /* bit 2 Direct Access error Log */
-		u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
-		u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
-		u16 reserved1  :2; /* bit 13:6 Reserved */
-		u16 reserved2  :6; /* bit 13:6 Reserved */
-		u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
-		u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
+		u16 flcdone:1; /* bit 0 Flash Cycle Done */
+		u16 flcerr:1; /* bit 1 Flash Cycle Error */
+		u16 dael:1; /* bit 2 Direct Access error Log */
+		u16 berasesz:2; /* bit 4:3 Sector Erase Size */
+		u16 flcinprog:1; /* bit 5 flash cycle in Progress */
+		u16 reserved1:2; /* bit 13:6 Reserved */
+		u16 reserved2:6; /* bit 13:6 Reserved */
+		u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
+		u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
 	} hsf_status;
 	u16 regval;
 };
@@ -157,11 +160,11 @@
 /* Offset 06h FLCTL */
 union ich8_hws_flash_ctrl {
 	struct ich8_hsflctl {
-		u16 flcgo      :1;   /* 0 Flash Cycle Go */
-		u16 flcycle    :2;   /* 2:1 Flash Cycle */
-		u16 reserved   :5;   /* 7:3 Reserved  */
-		u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
-		u16 flockdn    :6;   /* 15:10 Reserved */
+		u16 flcgo:1;   /* 0 Flash Cycle Go */
+		u16 flcycle:2;   /* 2:1 Flash Cycle */
+		u16 reserved:5;   /* 7:3 Reserved  */
+		u16 fldbcount:2;   /* 9:8 Flash Data Byte Count */
+		u16 flockdn:6;   /* 15:10 Reserved */
 	} hsf_ctrl;
 	u16 regval;
 };
@@ -169,14 +172,30 @@
 /* ICH Flash Region Access Permissions */
 union ich8_hws_flash_regacc {
 	struct ich8_flracc {
-		u32 grra      :8; /* 0:7 GbE region Read Access */
-		u32 grwa      :8; /* 8:15 GbE region Write Access */
-		u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
-		u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
+		u32 grra:8; /* 0:7 GbE region Read Access */
+		u32 grwa:8; /* 8:15 GbE region Write Access */
+		u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
+		u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
 	} hsf_flregacc;
 	u16 regval;
 };
 
+static void e1000_toggle_lanphypc_value_ich8lan(struct e1000_hw *hw)
+{
+	u32 ctrl;
+
+	DEBUGFUNC("e1000_toggle_lanphypc_value_ich8lan");
+
+	ctrl = E1000_READ_REG(hw, E1000_CTRL);
+	ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
+	ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
+	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
+	E1000_WRITE_FLUSH(hw);
+	usec_delay(10);
+	ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
+	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
+}
+
 /**
  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
  *  @hw: pointer to the HW structure
@@ -186,70 +205,66 @@
 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 {
 	struct e1000_phy_info *phy = &hw->phy;
-	u32 ctrl, fwsm;
 	s32 ret_val = E1000_SUCCESS;
 
 	DEBUGFUNC("e1000_init_phy_params_pchlan");
 
-	phy->addr                     = 1;
-	phy->reset_delay_us           = 100;
-
-	phy->ops.acquire              = e1000_acquire_swflag_ich8lan;
-	phy->ops.check_reset_block    = e1000_check_reset_block_ich8lan;
-	phy->ops.get_cfg_done         = e1000_get_cfg_done_ich8lan;
-	phy->ops.read_reg             = e1000_read_phy_reg_hv;
-	phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;
-	phy->ops.release              = e1000_release_swflag_ich8lan;
-	phy->ops.reset                = e1000_phy_hw_reset_ich8lan;
-	phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
-	phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
-	phy->ops.write_reg            = e1000_write_phy_reg_hv;
-	phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;
-	phy->ops.power_up             = e1000_power_up_phy_copper;
-	phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
-	phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
-
-	/*
-	 * The MAC-PHY interconnect may still be in SMBus mode
-	 * after Sx->S0.  If the manageability engine (ME) is
-	 * disabled, then toggle the LANPHYPC Value bit to force
-	 * the interconnect to PCIe mode.
-	 */
-	fwsm = E1000_READ_REG(hw, E1000_FWSM);
-	if (!(fwsm & E1000_ICH_FWSM_FW_VALID) &&
-	    !(hw->phy.ops.check_reset_block(hw))) {
-		ctrl = E1000_READ_REG(hw, E1000_CTRL);
-		ctrl |=  E1000_CTRL_LANPHYPC_OVERRIDE;
-		ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
-		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
-		usec_delay(10);
-		ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
-		E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
+	phy->addr		= 1;
+	phy->reset_delay_us	= 100;
+
+	phy->ops.acquire	= e1000_acquire_swflag_ich8lan;
+	phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
+	phy->ops.get_cfg_done	= e1000_get_cfg_done_ich8lan;
+	phy->ops.set_page	= e1000_set_page_igp;
+	phy->ops.read_reg	= e1000_read_phy_reg_hv;
+	phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
+	phy->ops.read_reg_page	= e1000_read_phy_reg_page_hv;
+	phy->ops.release	= e1000_release_swflag_ich8lan;
+	phy->ops.reset		= e1000_phy_hw_reset_ich8lan;
+	phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
+	phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
+	phy->ops.write_reg	= e1000_write_phy_reg_hv;
+	phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
+	phy->ops.write_reg_page	= e1000_write_phy_reg_page_hv;
+	phy->ops.power_up	= e1000_power_up_phy_copper;
+	phy->ops.power_down	= e1000_power_down_phy_copper_ich8lan;
+	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;
+
+	if (!hw->phy.ops.check_reset_block(hw)) {
+		u32 fwsm = E1000_READ_REG(hw, E1000_FWSM);
+
+		/*
+		 * The MAC-PHY interconnect may still be in SMBus mode after
+		 * Sx->S0.  If resetting the PHY is not blocked, toggle the
+		 * LANPHYPC Value bit to force the interconnect to PCIe mode.
+		 */
+		e1000_toggle_lanphypc_value_ich8lan(hw);
 		msec_delay(50);
 
 		/*
 		 * Gate automatic PHY configuration by hardware on
 		 * non-managed 82579
 		 */
-		if (hw->mac.type == e1000_pch2lan)
+		if ((hw->mac.type == e1000_pch2lan) &&
+		    !(fwsm & E1000_ICH_FWSM_FW_VALID))
 			e1000_gate_hw_phy_config_ich8lan(hw, TRUE);
-	}
-
-	/*
-	 * Reset the PHY before any acccess to it.  Doing so, ensures that
-	 * the PHY is in a known good state before we read/write PHY registers.
-	 * The generic reset is sufficient here, because we haven't determined
-	 * the PHY type yet.
-	 */
-	ret_val = e1000_phy_hw_reset_generic(hw);
-	if (ret_val)
-		goto out;
-
-	/* Ungate automatic PHY configuration on non-managed 82579 */
-	if ((hw->mac.type == e1000_pch2lan)  &&
-	    !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
-		msec_delay(10);
-		e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
+
+		/*
+		 * Reset the PHY before any access to it.  Doing so, ensures
+		 * that the PHY is in a known good state before we read/write
+		 * PHY registers.  The generic reset is sufficient here,
+		 * because we haven't determined the PHY type yet.
+		 */
+		ret_val = e1000_phy_hw_reset_generic(hw);
+		if (ret_val)
+			goto out;
+
+		/* Ungate automatic PHY configuration on non-managed 82579 */
+		if ((hw->mac.type == e1000_pch2lan) &&
+		    !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
+			msec_delay(10);
+			e1000_gate_hw_phy_config_ich8lan(hw, FALSE);
+		}
 	}
 
 	phy->id = e1000_phy_unknown;
@@ -315,21 +330,21 @@
 
 	DEBUGFUNC("e1000_init_phy_params_ich8lan");
 
-	phy->addr                     = 1;
-	phy->reset_delay_us           = 100;
-
-	phy->ops.acquire              = e1000_acquire_swflag_ich8lan;
-	phy->ops.check_reset_block    = e1000_check_reset_block_ich8lan;
-	phy->ops.get_cable_length     = e1000_get_cable_length_igp_2;
-	phy->ops.get_cfg_done         = e1000_get_cfg_done_ich8lan;
-	phy->ops.read_reg             = e1000_read_phy_reg_igp;
-	phy->ops.release              = e1000_release_swflag_ich8lan;
-	phy->ops.reset                = e1000_phy_hw_reset_ich8lan;
-	phy->ops.set_d0_lplu_state    = e1000_set_d0_lplu_state_ich8lan;
-	phy->ops.set_d3_lplu_state    = e1000_set_d3_lplu_state_ich8lan;
-	phy->ops.write_reg            = e1000_write_phy_reg_igp;
-	phy->ops.power_up             = e1000_power_up_phy_copper;
-	phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
+	phy->addr		= 1;
+	phy->reset_delay_us	= 100;
+
+	phy->ops.acquire	= e1000_acquire_swflag_ich8lan;
+	phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
+	phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
+	phy->ops.get_cfg_done	= e1000_get_cfg_done_ich8lan;
+	phy->ops.read_reg	= e1000_read_phy_reg_igp;
+	phy->ops.release	= e1000_release_swflag_ich8lan;
+	phy->ops.reset		= e1000_phy_hw_reset_ich8lan;
+	phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
+	phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
+	phy->ops.write_reg	= e1000_write_phy_reg_igp;
+	phy->ops.power_up	= e1000_power_up_phy_copper;
+	phy->ops.power_down	= e1000_power_down_phy_copper_ich8lan;
 
 	/*
 	 * We may need to do this twice - once for IGP and if that fails,
@@ -438,7 +453,7 @@
 	 * size represents two separate NVM banks.
 	 */
 	nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
-	                          << FLASH_SECTOR_ADDR_SHIFT;
+				<< FLASH_SECTOR_ADDR_SHIFT;
 	nvm->flash_bank_size /= 2;
 	/* Adjust to word count */
 	nvm->flash_bank_size /= sizeof(u16);
@@ -455,13 +470,13 @@
 	E1000_MUTEX_INIT(&dev_spec->swflag_mutex);
 
 	/* Function Pointers */
-	nvm->ops.acquire       = e1000_acquire_nvm_ich8lan;
-	nvm->ops.release       = e1000_release_nvm_ich8lan;
-	nvm->ops.read          = e1000_read_nvm_ich8lan;
-	nvm->ops.update        = e1000_update_nvm_checksum_ich8lan;
+	nvm->ops.acquire	= e1000_acquire_nvm_ich8lan;
+	nvm->ops.release	= e1000_release_nvm_ich8lan;
+	nvm->ops.read		= e1000_read_nvm_ich8lan;
+	nvm->ops.update		= e1000_update_nvm_checksum_ich8lan;
 	nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
-	nvm->ops.validate      = e1000_validate_nvm_checksum_ich8lan;
-	nvm->ops.write         = e1000_write_nvm_ich8lan;
+	nvm->ops.validate	= e1000_validate_nvm_checksum_ich8lan;
+	nvm->ops.write		= e1000_write_nvm_ich8lan;
 
 out:
 	return ret_val;
@@ -477,7 +492,6 @@
 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 {
 	struct e1000_mac_info *mac = &hw->mac;
-	u16 pci_cfg;
 
 	DEBUGFUNC("e1000_init_mac_params_ich8lan");
 
@@ -549,9 +563,6 @@
 			e1000_update_mc_addr_list_pch2lan;
 		/* fall-through */
 	case e1000_pchlan:
-		/* save PCH revision_id */
-		e1000_read_pci_cfg(hw, 0x2, &pci_cfg);
-		hw->revision_id = (u8)(pci_cfg &= 0x000F);
 		/* check management mode */
 		mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 		/* ID LED init */
@@ -568,6 +579,11 @@
 		break;
 	}
 
+#if defined(NAHUM6_HW) && (defined(LTR_SUPPORT) || defined(OBFF_SUPPORT))
+	if (mac->type == e1000_pch_lpt) {
+	}
+
+#endif /* NAHUM6_HW && (LTR_SUPPORT || OBFF_SUPPORT) */
 	/* Enable PCS Lock-loss workaround for ICH8 */
 	if (mac->type == e1000_ich8lan)
 		e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE);
@@ -589,6 +605,7 @@
  **/
 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 {
+	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 	s32 ret_val = E1000_SUCCESS;
 	u16 phy_reg;
 
@@ -601,7 +618,7 @@
 	if (ret_val)
 		goto out;
 
-	if (hw->dev_spec.ich8lan.eee_disable)
+	if (dev_spec->eee_disable)
 		phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
 	else
 		phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
@@ -624,6 +641,7 @@
 	struct e1000_mac_info *mac = &hw->mac;
 	s32 ret_val;
 	bool link;
+	u16 phy_reg;
 
 	DEBUGFUNC("e1000_check_for_copper_link_ich8lan");
 
@@ -653,21 +671,46 @@
 			goto out;
 	}
 
+#if defined(NAHUM6_HW) && (defined(LTR_SUPPORT) || defined(OBFF_SUPPORT))
+	if (hw->mac.type == e1000_pch_lpt) {
+	}
+
+#endif /* NAHUM6_HW && (LTR_SUPPORT || OBFF_SUPPORT) */
 	if (!link)
 		goto out; /* No link detected */
 
 	mac->get_link_status = FALSE;
 
-	if (hw->phy.type == e1000_phy_82578) {
-		ret_val = e1000_link_stall_workaround_hv(hw);
-		if (ret_val)
-			goto out;
-	}
-
-	if (hw->mac.type == e1000_pch2lan) {
+	switch (hw->mac.type) {
+	case e1000_pch2lan:
 		ret_val = e1000_k1_workaround_lv(hw);
 		if (ret_val)
 			goto out;
+		/* fall-thru */
+	case e1000_pchlan:
+		if (hw->phy.type == e1000_phy_82578) {
+			ret_val = e1000_link_stall_workaround_hv(hw);
+			if (ret_val)
+				goto out;
+		}
+
+		/*
+		 * Workaround for PCHx parts in half-duplex:
+		 * Set the number of preambles removed from the packet
+		 * when it is passed from the PHY to the MAC to prevent
+		 * the MAC from misinterpreting the packet type.
+		 */
+		hw->phy.ops.read_reg(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
+		phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
+
+		if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_FD) !=
+		    E1000_STATUS_FD)
+			phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
+
+		hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
+		break;
+	default:
+		break;
 	}
 
 	/*
@@ -794,7 +837,7 @@
 	}
 
 	if (!timeout) {
-		DEBUGOUT("SW/FW/HW has locked the resource for too long.\n");
+		DEBUGOUT("SW has already locked the resource.\n");
 		ret_val = -E1000_ERR_CONFIG;
 		goto out;
 	}
@@ -814,7 +857,8 @@
 	}
 
 	if (!timeout) {
-		DEBUGOUT("Failed to acquire the semaphore.\n");
+		DEBUGOUT2("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
+			  E1000_READ_REG(hw, E1000_FWSM), extcnf_ctrl);
 		extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 		E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
 		ret_val = -E1000_ERR_CONFIG;
@@ -918,8 +962,8 @@
 	 * from network order (big endian) to little endian
 	 */
 	rar_low = ((u32) addr[0] |
-	           ((u32) addr[1] << 8) |
-	           ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
+		   ((u32) addr[1] << 8) |
+		   ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
 
 	rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
 
@@ -963,22 +1007,38 @@
  *  The caller must have a packed mc_addr_list of multicast addresses.
  **/
 static void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw,
-                                              u8 *mc_addr_list,
-                                              u32 mc_addr_count)
+					      u8 *mc_addr_list,
+					      u32 mc_addr_count)
 {
+	u16 phy_reg = 0;
 	int i;
+	s32 ret_val;
 
 	DEBUGFUNC("e1000_update_mc_addr_list_pch2lan");
 
 	e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count);
 
+	ret_val = hw->phy.ops.acquire(hw);
+	if (ret_val)
+		return;
+
+	ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
+	if (ret_val)
+		goto release;
+
 	for (i = 0; i < hw->mac.mta_reg_count; i++) {
-		hw->phy.ops.write_reg(hw, BM_MTA(i),
-		                   (u16)(hw->mac.mta_shadow[i] & 0xFFFF));
-		hw->phy.ops.write_reg(hw, (BM_MTA(i) + 1),
-		                      (u16)((hw->mac.mta_shadow[i] >> 16) &
-		                       0xFFFF));
+		hw->phy.ops.write_reg_page(hw, BM_MTA(i),
+					   (u16)(hw->mac.mta_shadow[i] &
+						 0xFFFF));
+		hw->phy.ops.write_reg_page(hw, (BM_MTA(i) + 1),
+					   (u16)((hw->mac.mta_shadow[i] >> 16) &
+						 0xFFFF));
 	}
+
+	e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
+
+release:
+	hw->phy.ops.release(hw);
 }
 
 /**
@@ -995,13 +1055,10 @@
 
 	DEBUGFUNC("e1000_check_reset_block_ich8lan");
 
-	if (hw->phy.reset_disable)
-		return E1000_BLK_PHY_RESET;
-
 	fwsm = E1000_READ_REG(hw, E1000_FWSM);
 
 	return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS
-	                                        : E1000_BLK_PHY_RESET;
+						: E1000_BLK_PHY_RESET;
 }
 
 /**
@@ -1187,46 +1244,46 @@
 	if (link) {
 		if (hw->phy.type == e1000_phy_82578) {
 			ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
-			                                      &status_reg);
+							      &status_reg);
 			if (ret_val)
 				goto release;
 
 			status_reg &= BM_CS_STATUS_LINK_UP |
-			              BM_CS_STATUS_RESOLVED |
-			              BM_CS_STATUS_SPEED_MASK;
+				      BM_CS_STATUS_RESOLVED |
+				      BM_CS_STATUS_SPEED_MASK;
 
 			if (status_reg == (BM_CS_STATUS_LINK_UP |
-			                   BM_CS_STATUS_RESOLVED |
-			                   BM_CS_STATUS_SPEED_1000))
+					   BM_CS_STATUS_RESOLVED |
+					   BM_CS_STATUS_SPEED_1000))
 				k1_enable = FALSE;
 		}
 
 		if (hw->phy.type == e1000_phy_82577) {
 			ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
-			                                      &status_reg);
+							      &status_reg);
 			if (ret_val)
 				goto release;
 
 			status_reg &= HV_M_STATUS_LINK_UP |
-			              HV_M_STATUS_AUTONEG_COMPLETE |
-			              HV_M_STATUS_SPEED_MASK;
+				      HV_M_STATUS_AUTONEG_COMPLETE |
+				      HV_M_STATUS_SPEED_MASK;
 
 			if (status_reg == (HV_M_STATUS_LINK_UP |
-			                   HV_M_STATUS_AUTONEG_COMPLETE |
-			                   HV_M_STATUS_SPEED_1000))
+					   HV_M_STATUS_AUTONEG_COMPLETE |
+					   HV_M_STATUS_SPEED_1000))
 				k1_enable = FALSE;
 		}
 
 		/* Link stall fix for link up */
 		ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
-		                                       0x0100);
+						       0x0100);
 		if (ret_val)
 			goto release;
 
 	} else {
 		/* Link stall fix for link down */
 		ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
-		                                       0x4100);
+						       0x4100);
 		if (ret_val)
 			goto release;
 	}
@@ -1259,9 +1316,8 @@
 
 	DEBUGFUNC("e1000_configure_k1_ich8lan");
 
-	ret_val = e1000_read_kmrn_reg_locked(hw,
-	                                     E1000_KMRNCTRLSTA_K1_CONFIG,
-	                                     &kmrn_reg);
+	ret_val = e1000_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
+					     &kmrn_reg);
 	if (ret_val)
 		goto out;
 
@@ -1270,9 +1326,8 @@
 	else
 		kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
 
-	ret_val = e1000_write_kmrn_reg_locked(hw,
-	                                      E1000_KMRNCTRLSTA_K1_CONFIG,
-	                                      kmrn_reg);
+	ret_val = e1000_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
+					      kmrn_reg);
 	if (ret_val)
 		goto out;
 
@@ -1285,9 +1340,11 @@
 	E1000_WRITE_REG(hw, E1000_CTRL, reg);
 
 	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
+	E1000_WRITE_FLUSH(hw);
 	usec_delay(20);
 	E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
 	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
+	E1000_WRITE_FLUSH(hw);
 	usec_delay(20);
 
 out:
@@ -1303,7 +1360,7 @@
  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
  **/
-s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
+static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
 {
 	s32 ret_val = 0;
 	u32 mac_reg;
@@ -1342,16 +1399,20 @@
 
 		if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
 			oem_reg |= HV_OEM_BITS_LPLU;
+
+		/* Set Restart auto-neg to activate the bits */
+		if (!hw->phy.ops.check_reset_block(hw))
+			oem_reg |= HV_OEM_BITS_RESTART_AN;
 	} else {
-		if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
+		if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
+		    E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
 			oem_reg |= HV_OEM_BITS_GBE_DIS;
 
-		if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
+		if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
+		    E1000_PHY_CTRL_NOND0A_LPLU))
 			oem_reg |= HV_OEM_BITS_LPLU;
 	}
-	/* Restart auto-neg to activate the bits */
-	if (!hw->phy.ops.check_reset_block(hw))
-		oem_reg |= HV_OEM_BITS_RESTART_AN;
+
 	ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
 
 out:
@@ -1362,20 +1423,6 @@
 
 
 /**
- *  e1000_hv_phy_powerdown_workaround_ich8lan - Power down workaround on Sx
- *  @hw: pointer to the HW structure
- **/
-s32 e1000_hv_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
-{
-	DEBUGFUNC("e1000_hv_phy_powerdown_workaround_ich8lan");
-
-	if ((hw->phy.type != e1000_phy_82577) || (hw->revision_id > 2))
-		return E1000_SUCCESS;
-
-	return hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0444);
-}
-
-/**
  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
  *  @hw:   pointer to the HW structure
  **/
@@ -1418,32 +1465,6 @@
 			goto out;
 	}
 
-	/* Hanksville M Phy init for IEEE. */
-	if ((hw->revision_id == 2) &&
-	    (hw->phy.type == e1000_phy_82577) &&
-	    ((hw->phy.revision == 2) || (hw->phy.revision == 3))) {
-		hw->phy.ops.write_reg(hw, 0x10, 0x8823);
-		hw->phy.ops.write_reg(hw, 0x11, 0x0018);
-		hw->phy.ops.write_reg(hw, 0x10, 0x8824);
-		hw->phy.ops.write_reg(hw, 0x11, 0x0016);
-		hw->phy.ops.write_reg(hw, 0x10, 0x8825);
-		hw->phy.ops.write_reg(hw, 0x11, 0x001A);
-		hw->phy.ops.write_reg(hw, 0x10, 0x888C);
-		hw->phy.ops.write_reg(hw, 0x11, 0x0007);
-		hw->phy.ops.write_reg(hw, 0x10, 0x888D);
-		hw->phy.ops.write_reg(hw, 0x11, 0x0007);
-		hw->phy.ops.write_reg(hw, 0x10, 0x888E);
-		hw->phy.ops.write_reg(hw, 0x11, 0x0007);
-		hw->phy.ops.write_reg(hw, 0x10, 0x8827);
-		hw->phy.ops.write_reg(hw, 0x11, 0x0001);
-		hw->phy.ops.write_reg(hw, 0x10, 0x8835);
-		hw->phy.ops.write_reg(hw, 0x11, 0x0001);
-		hw->phy.ops.write_reg(hw, 0x10, 0x8834);
-		hw->phy.ops.write_reg(hw, 0x11, 0x0001);
-		hw->phy.ops.write_reg(hw, 0x10, 0x8833);
-		hw->phy.ops.write_reg(hw, 0x11, 0x0002);
-	}
-
 	if (((hw->phy.type == e1000_phy_82577) &&
 	     ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
 	    ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
@@ -1453,26 +1474,13 @@
 			goto out;
 
 		/* Preamble tuning for SSC */
-		ret_val = hw->phy.ops.write_reg(hw, PHY_REG(770, 16), 0xA204);
+		ret_val = hw->phy.ops.write_reg(hw, HV_KMRN_FIFO_CTRLSTA,
+						0xA204);
 		if (ret_val)
 			goto out;
 	}
 
 	if (hw->phy.type == e1000_phy_82578) {
-		if (hw->revision_id < 3) {
-			/* PHY config */
-			ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x29,
-			                                0x66C0);
-			if (ret_val)
-				goto out;
-
-			/* PHY config */
-			ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x1E,
-			                                0xFFFF);
-			if (ret_val)
-				goto out;
-		}
-
 		/*
 		 * Return registers to default by doing a soft reset then
 		 * writing 0x3140 to the control register.
@@ -1480,25 +1488,10 @@
 		if (hw->phy.revision < 2) {
 			e1000_phy_sw_reset_generic(hw);
 			ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL,
-			                                0x3140);
+							0x3140);
 		}
 	}
 
-	if ((hw->revision_id == 2) &&
-	    (hw->phy.type == e1000_phy_82577) &&
-	    ((hw->phy.revision == 2) || (hw->phy.revision == 3))) {
-		/*
-		 * Workaround for OEM (GbE) not operating after reset -
-		 * restart AN (twice)
-		 */
-		ret_val = hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0400);
-		if (ret_val)
-			goto out;
-		ret_val = hw->phy.ops.write_reg(hw, PHY_REG(768, 25), 0x0400);
-		if (ret_val)
-			goto out;
-	}
-
 	/* Select page 0 */
 	ret_val = hw->phy.ops.acquire(hw);
 	if (ret_val)
@@ -1522,12 +1515,11 @@
 	ret_val = hw->phy.ops.acquire(hw);
 	if (ret_val)
 		goto out;
-	ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG_REG,
-	                                      &phy_data);
+	ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
 	if (ret_val)
 		goto release;
-	ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG_REG,
-	                                       phy_data & 0x00FF);
+	ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
+					       phy_data & 0x00FF);
 release:
 	hw->phy.ops.release(hw);
 out:
@@ -1541,19 +1533,38 @@
 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
 {
 	u32 mac_reg;
-	u16 i;
+	u16 i, phy_reg = 0;
+	s32 ret_val;
 
 	DEBUGFUNC("e1000_copy_rx_addrs_to_phy_ich8lan");
 
+	ret_val = hw->phy.ops.acquire(hw);
+	if (ret_val)
+		return;
+	ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
+	if (ret_val)
+		goto release;
+
 	/* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
 	for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
 		mac_reg = E1000_READ_REG(hw, E1000_RAL(i));
-		hw->phy.ops.write_reg(hw, BM_RAR_L(i), (u16)(mac_reg & 0xFFFF));
-		hw->phy.ops.write_reg(hw, BM_RAR_M(i), (u16)((mac_reg >> 16) & 0xFFFF));
+		hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
+					   (u16)(mac_reg & 0xFFFF));
+		hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
+					   (u16)((mac_reg >> 16) & 0xFFFF));
+
 		mac_reg = E1000_READ_REG(hw, E1000_RAH(i));
-		hw->phy.ops.write_reg(hw, BM_RAR_H(i), (u16)(mac_reg & 0xFFFF));
-		hw->phy.ops.write_reg(hw, BM_RAR_CTRL(i), (u16)((mac_reg >> 16) & 0x8000));
+		hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
+					   (u16)(mac_reg & 0xFFFF));
+		hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
+					   (u16)((mac_reg & E1000_RAH_AV)
+						 >> 16));
 	}
+
+	e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
+
+release:
+	hw->phy.ops.release(hw);
 }
 
 static u32 e1000_calc_rx_da_crc(u8 mac[])
@@ -1594,7 +1605,8 @@
 
 	/* disable Rx path while enabling/disabling workaround */
 	hw->phy.ops.read_reg(hw, PHY_REG(769, 20), &phy_reg);
-	ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
+	ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20),
+					phy_reg | (1 << 14));
 	if (ret_val)
 		goto out;
 
@@ -1676,11 +1688,12 @@
 		ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 20), data);
 		if (ret_val)
 			goto out;
-		ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xFE00);
+		ret_val = hw->phy.ops.write_reg(hw, PHY_REG(776, 23), 0xF100);
 		if (ret_val)
 			goto out;
 		hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
-		ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data | (1 << 10));
+		ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data |
+						(1 << 10));
 		if (ret_val)
 			goto out;
 	} else {
@@ -1737,13 +1750,15 @@
 		if (ret_val)
 			goto out;
 		hw->phy.ops.read_reg(hw, HV_PM_CTRL, &data);
-		ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data & ~(1 << 10));
+		ret_val = hw->phy.ops.write_reg(hw, HV_PM_CTRL, data &
+						~(1 << 10));
 		if (ret_val)
 			goto out;
 	}
 
 	/* re-enable Rx path after enabling/disabling workaround */
-	ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
+	ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 20), phy_reg &
+					~(1 << 14));
 
 out:
 	return ret_val;
@@ -1765,6 +1780,28 @@
 	/* Set MDIO slow mode before any other MDIO access */
 	ret_val = e1000_set_mdio_slow_mode_hv(hw);
 
+	ret_val = hw->phy.ops.acquire(hw);
+	if (ret_val)
+		goto out;
+	ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
+					       I82579_MSE_THRESHOLD);
+	if (ret_val)
+		goto release;
+	/* set MSE higher to enable link to stay up when noise is high */
+	ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
+					       0x0034);
+	if (ret_val)
+		goto release;
+	ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
+					       I82579_MSE_LINK_DOWN);
+	if (ret_val)
+		goto release;
+	/* drop link after 5 times MSE threshold was reached */
+	ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
+					       0x0005);
+release:
+	hw->phy.ops.release(hw);
+
 out:
 	return ret_val;
 }
@@ -1780,6 +1817,7 @@
 	s32 ret_val = E1000_SUCCESS;
 	u16 status_reg = 0;
 	u32 mac_reg;
+	u16 phy_reg;
 
 	DEBUGFUNC("e1000_k1_workaround_lv");
 
@@ -1796,12 +1834,19 @@
 		mac_reg = E1000_READ_REG(hw, E1000_FEXTNVM4);
 		mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
 
-		if (status_reg & HV_M_STATUS_SPEED_1000)
+		ret_val = hw->phy.ops.read_reg(hw, I82579_LPI_CTRL, &phy_reg);
+		if (ret_val)
+			goto out;
+
+		if (status_reg & HV_M_STATUS_SPEED_1000) {
 			mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
-		else
+			phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
+		} else {
 			mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
-
+			phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
+		}
 		E1000_WRITE_REG(hw, E1000_FEXTNVM4, mac_reg);
+		ret_val = hw->phy.ops.write_reg(hw, I82579_LPI_CTRL, phy_reg);
 	}
 
 out:
@@ -1837,34 +1882,6 @@
 }
 
 /**
- *  e1000_hv_phy_tuning_workaround_ich8lan - This is a Phy tuning work around
- *  needed for Nahum3 + Hanksville testing, requested by HW team
- **/
-static s32 e1000_hv_phy_tuning_workaround_ich8lan(struct e1000_hw *hw)
-{
-	s32 ret_val = E1000_SUCCESS;
-
-	DEBUGFUNC("e1000_hv_phy_tuning_workaround_ich8lan");
-
-	ret_val = hw->phy.ops.write_reg(hw, PHY_REG(769, 25), 0x4431);
-	if (ret_val)
-		goto out;
-
-	ret_val = hw->phy.ops.write_reg(hw, PHY_REG(770, 16), 0xA204);
-	if (ret_val)
-		goto out;
-
-	ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x29, 0x66C0);
-	if (ret_val)
-		goto out;
-
-	ret_val = hw->phy.ops.write_reg(hw, (1 << 6) | 0x1E, 0xFFFF);
-
-out:
-	return ret_val;
-}
-
-/**
  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
  *  @hw: pointer to the HW structure
  *
@@ -1931,16 +1948,13 @@
 		break;
 	}
 
-	if (hw->device_id == E1000_DEV_ID_ICH10_HANKSVILLE) {
-		ret_val = e1000_hv_phy_tuning_workaround_ich8lan(hw);
-		if (ret_val)
-			goto out;
+	/* Clear the host wakeup bit after lcd reset */
+	if (hw->mac.type >= e1000_pchlan) {
+		hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &reg);
+		reg &= ~BM_WUC_HOST_WU_BIT;
+		hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, reg);
 	}
 
-	/* Dummy read to clear the phy wakeup bit after lcd reset */
-	if (hw->mac.type >= e1000_pchlan)
-		hw->phy.ops.read_reg(hw, BM_WUC, &reg);
-
 	/* Configure the LCD with the extended configuration region in NVM */
 	ret_val = e1000_sw_lcd_config_ich8lan(hw);
 	if (ret_val)
@@ -2031,7 +2045,9 @@
 	else
 		oem_reg &= ~HV_OEM_BITS_LPLU;
 
-	oem_reg |= HV_OEM_BITS_RESTART_AN;
+	if (!hw->phy.ops.check_reset_block(hw))
+		oem_reg |= HV_OEM_BITS_RESTART_AN;
+
 	ret_val = hw->phy.ops.write_reg(hw, HV_OEM_BITS, oem_reg);
 
 out:
@@ -2081,12 +2097,12 @@
 
 		/* When LPLU is enabled, we should disable SmartSpeed */
 		ret_val = phy->ops.read_reg(hw,
-		                            IGP01E1000_PHY_PORT_CONFIG,
-		                            &data);
+					    IGP01E1000_PHY_PORT_CONFIG,
+					    &data);
 		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 		ret_val = phy->ops.write_reg(hw,
-		                             IGP01E1000_PHY_PORT_CONFIG,
-		                             data);
+					     IGP01E1000_PHY_PORT_CONFIG,
+					     data);
 		if (ret_val)
 			goto out;
 	} else {
@@ -2104,28 +2120,28 @@
 		 */
 		if (phy->smart_speed == e1000_smart_speed_on) {
 			ret_val = phy->ops.read_reg(hw,
-			                            IGP01E1000_PHY_PORT_CONFIG,
-			                            &data);
+						    IGP01E1000_PHY_PORT_CONFIG,
+						    &data);
 			if (ret_val)
 				goto out;
 
 			data |= IGP01E1000_PSCFR_SMART_SPEED;
 			ret_val = phy->ops.write_reg(hw,
-			                             IGP01E1000_PHY_PORT_CONFIG,
-			                             data);
+						     IGP01E1000_PHY_PORT_CONFIG,
+						     data);
 			if (ret_val)
 				goto out;
 		} else if (phy->smart_speed == e1000_smart_speed_off) {
 			ret_val = phy->ops.read_reg(hw,
-			                            IGP01E1000_PHY_PORT_CONFIG,
-			                            &data);
+						    IGP01E1000_PHY_PORT_CONFIG,
+						    &data);
 			if (ret_val)
 				goto out;
 
 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 			ret_val = phy->ops.write_reg(hw,
-			                             IGP01E1000_PHY_PORT_CONFIG,
-			                             data);
+						     IGP01E1000_PHY_PORT_CONFIG,
+						     data);
 			if (ret_val)
 				goto out;
 		}
@@ -2174,34 +2190,34 @@
 		 */
 		if (phy->smart_speed == e1000_smart_speed_on) {
 			ret_val = phy->ops.read_reg(hw,
-			                            IGP01E1000_PHY_PORT_CONFIG,
-			                            &data);
+						    IGP01E1000_PHY_PORT_CONFIG,
+						    &data);
 			if (ret_val)
 				goto out;
 
 			data |= IGP01E1000_PSCFR_SMART_SPEED;
 			ret_val = phy->ops.write_reg(hw,
-			                             IGP01E1000_PHY_PORT_CONFIG,
-			                             data);
+						     IGP01E1000_PHY_PORT_CONFIG,
+						     data);
 			if (ret_val)
 				goto out;
 		} else if (phy->smart_speed == e1000_smart_speed_off) {
 			ret_val = phy->ops.read_reg(hw,
-			                            IGP01E1000_PHY_PORT_CONFIG,
-			                            &data);
+						    IGP01E1000_PHY_PORT_CONFIG,
+						    &data);
 			if (ret_val)
 				goto out;
 
 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 			ret_val = phy->ops.write_reg(hw,
-			                             IGP01E1000_PHY_PORT_CONFIG,
-			                             data);
+						     IGP01E1000_PHY_PORT_CONFIG,
+						     data);
 			if (ret_val)
 				goto out;
 		}
 	} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
-	           (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
-	           (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
+		   (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
+		   (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 		phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
 		E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
 
@@ -2217,15 +2233,15 @@
 
 		/* When LPLU is enabled, we should disable SmartSpeed */
 		ret_val = phy->ops.read_reg(hw,
-		                            IGP01E1000_PHY_PORT_CONFIG,
-		                            &data);
+					    IGP01E1000_PHY_PORT_CONFIG,
+					    &data);
 		if (ret_val)
 			goto out;
 
 		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 		ret_val = phy->ops.write_reg(hw,
-		                             IGP01E1000_PHY_PORT_CONFIG,
-		                             data);
+					     IGP01E1000_PHY_PORT_CONFIG,
+					     data);
 	}
 
 out:
@@ -2264,8 +2280,7 @@
 
 			goto out;
 		}
-		DEBUGOUT("Unable to determine valid NVM bank via EEC - "
-		         "reading flash signature\n");
+		DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
 		/* fall-thru */
 	default:
 		/* set bank to 0 in case flash read fails */
@@ -2273,7 +2288,7 @@
 
 		/* Check bank 0 */
 		ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
-		                                        &sig_byte);
+							&sig_byte);
 		if (ret_val)
 			goto out;
 		if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
@@ -2284,8 +2299,8 @@
 
 		/* Check bank 1 */
 		ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
-		                                        bank1_offset,
-		                                        &sig_byte);
+							bank1_offset,
+							&sig_byte);
 		if (ret_val)
 			goto out;
 		if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
@@ -2312,7 +2327,7 @@
  *  Reads a word(s) from the NVM using the flash access registers.
  **/
 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
-                                  u16 *data)
+				  u16 *data)
 {
 	struct e1000_nvm_info *nvm = &hw->nvm;
 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
@@ -2343,13 +2358,12 @@
 
 	ret_val = E1000_SUCCESS;
 	for (i = 0; i < words; i++) {
-		if ((dev_spec->shadow_ram) &&
-		    (dev_spec->shadow_ram[offset+i].modified)) {
+		if (dev_spec->shadow_ram[offset+i].modified) {
 			data[i] = dev_spec->shadow_ram[offset+i].value;
 		} else {
 			ret_val = e1000_read_flash_word_ich8lan(hw,
-			                                        act_offset + i,
-			                                        &word);
+								act_offset + i,
+								&word);
 			if (ret_val)
 				break;
 			data[i] = word;
@@ -2383,8 +2397,7 @@
 
 	/* Check if the flash descriptor is valid */
 	if (hsfsts.hsf_status.fldesvalid == 0) {
-		DEBUGOUT("Flash descriptor invalid.  "
-		         "SW Sequencing must be used.");
+		DEBUGOUT("Flash descriptor invalid.  SW Sequencing must be used.\n");
 		goto out;
 	}
 
@@ -2421,7 +2434,7 @@
 		 */
 		for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
 			hsfsts.regval = E1000_READ_FLASH_REG16(hw,
-			                                      ICH_FLASH_HSFSTS);
+							      ICH_FLASH_HSFSTS);
 			if (hsfsts.hsf_status.flcinprog == 0) {
 				ret_val = E1000_SUCCESS;
 				break;
@@ -2435,9 +2448,9 @@
 			 */
 			hsfsts.hsf_status.flcdone = 1;
 			E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
-			                        hsfsts.regval);
+						hsfsts.regval);
 		} else {
-			DEBUGOUT("Flash controller busy, cannot get access");
+			DEBUGOUT("Flash controller busy, cannot get access\n");
 		}
 	}
 
@@ -2490,7 +2503,7 @@
  *  to bytes before read.
  **/
 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
-                                         u16 *data)
+					 u16 *data)
 {
 	s32 ret_val;
 
@@ -2519,7 +2532,7 @@
  *  Reads a single byte from the NVM using the flash access registers.
  **/
 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
-                                         u8 *data)
+					 u8 *data)
 {
 	s32 ret_val = E1000_SUCCESS;
 	u16 word = 0;
@@ -2544,7 +2557,7 @@
  *  Reads a byte or word from the NVM using the flash access registers.
  **/
 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
-                                         u8 size, u16 *data)
+					 u8 size, u16 *data)
 {
 	union ich8_hws_flash_status hsfsts;
 	union ich8_hws_flash_ctrl hsflctl;
@@ -2559,7 +2572,7 @@
 		goto out;
 
 	flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
-	                    hw->nvm.flash_base_addr;
+			    hw->nvm.flash_base_addr;
 
 	do {
 		usec_delay(1);
@@ -2577,7 +2590,7 @@
 		E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
 
 		ret_val = e1000_flash_cycle_ich8lan(hw,
-		                                ICH_FLASH_READ_COMMAND_TIMEOUT);
+						ICH_FLASH_READ_COMMAND_TIMEOUT);
 
 		/*
 		 * Check if FCERR is set to 1, if set to 1, clear it
@@ -2600,13 +2613,12 @@
 			 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
 			 */
 			hsfsts.regval = E1000_READ_FLASH_REG16(hw,
-			                                      ICH_FLASH_HSFSTS);
+							      ICH_FLASH_HSFSTS);
 			if (hsfsts.hsf_status.flcerr == 1) {
 				/* Repeat for some time before giving up. */
 				continue;
 			} else if (hsfsts.hsf_status.flcdone == 0) {
-				DEBUGOUT("Timeout error - flash cycle "
-				         "did not complete.");
+				DEBUGOUT("Timeout error - flash cycle did not complete.\n");
 				break;
 			}
 		}
@@ -2626,7 +2638,7 @@
  *  Writes a byte or word to the NVM using the flash access registers.
  **/
 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
-                                   u16 *data)
+				   u16 *data)
 {
 	struct e1000_nvm_info *nvm = &hw->nvm;
 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
@@ -2720,8 +2732,8 @@
 			data = dev_spec->shadow_ram[i].value;
 		} else {
 			ret_val = e1000_read_flash_word_ich8lan(hw, i +
-			                                        old_bank_offset,
-			                                        &data);
+								old_bank_offset,
+								&data);
 			if (ret_val)
 				break;
 		}
@@ -2743,15 +2755,15 @@
 		usec_delay(100);
 		/* Write the bytes to the new bank. */
 		ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
-		                                               act_offset,
-		                                               (u8)data);
+							       act_offset,
+							       (u8)data);
 		if (ret_val)
 			break;
 
 		usec_delay(100);
 		ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
-		                                          act_offset + 1,
-		                                          (u8)(data >> 8));
+							  act_offset + 1,
+							  (u8)(data >> 8));
 		if (ret_val)
 			break;
 	}
@@ -2778,8 +2790,8 @@
 
 	data &= 0xBFFF;
 	ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
-	                                               act_offset * 2 + 1,
-	                                               (u8)(data >> 8));
+						       act_offset * 2 + 1,
+						       (u8)(data >> 8));
 	if (ret_val)
 		goto release;
 
@@ -2870,7 +2882,7 @@
  *  Writes one/two bytes to the NVM using the flash access registers.
  **/
 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
-                                          u8 size, u16 data)
+					  u8 size, u16 data)
 {
 	union ich8_hws_flash_status hsfsts;
 	union ich8_hws_flash_ctrl hsflctl;
@@ -2886,7 +2898,7 @@
 		goto out;
 
 	flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
-	                    hw->nvm.flash_base_addr;
+			    hw->nvm.flash_base_addr;
 
 	do {
 		usec_delay(1);
@@ -2915,7 +2927,7 @@
 		 * and try the whole sequence a few more times else done
 		 */
 		ret_val = e1000_flash_cycle_ich8lan(hw,
-		                               ICH_FLASH_WRITE_COMMAND_TIMEOUT);
+					       ICH_FLASH_WRITE_COMMAND_TIMEOUT);
 		if (ret_val == E1000_SUCCESS)
 			break;
 
@@ -2930,8 +2942,7 @@
 			/* Repeat for some time before giving up. */
 			continue;
 		if (hsfsts.hsf_status.flcdone == 0) {
-			DEBUGOUT("Timeout error - flash cycle "
-				 "did not complete.");
+			DEBUGOUT("Timeout error - flash cycle did not complete.\n");
 			break;
 		}
 	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
@@ -2949,7 +2960,7 @@
  *  Writes a single byte to the NVM using the flash access registers.
  **/
 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
-                                          u8 data)
+					  u8 data)
 {
 	u16 word = (u16)data;
 
@@ -2968,7 +2979,7 @@
  *  Goes through a retry algorithm before giving up.
  **/
 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
-                                                u32 offset, u8 byte)
+						u32 offset, u8 byte)
 {
 	s32 ret_val;
 	u16 program_retries;
@@ -3071,10 +3082,10 @@
 			 * Cycle field in hw flash control
 			 */
 			hsflctl.regval = E1000_READ_FLASH_REG16(hw,
-			                                      ICH_FLASH_HSFCTL);
+							      ICH_FLASH_HSFCTL);
 			hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
 			E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
-			                        hsflctl.regval);
+						hsflctl.regval);
 
 			/*
 			 * Write the last 24 bits of an index within the
@@ -3083,10 +3094,10 @@
 			 */
 			flash_linear_addr += (j * sector_size);
 			E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
-			                      flash_linear_addr);
+					      flash_linear_addr);
 
 			ret_val = e1000_flash_cycle_ich8lan(hw,
-			                       ICH_FLASH_ERASE_COMMAND_TIMEOUT);
+					       ICH_FLASH_ERASE_COMMAND_TIMEOUT);
 			if (ret_val == E1000_SUCCESS)
 				break;
 
@@ -3130,8 +3141,7 @@
 		goto out;
 	}
 
-	if (*data == ID_LED_RESERVED_0000 ||
-	    *data == ID_LED_RESERVED_FFFF)
+	if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
 		*data = ID_LED_DEFAULT_ICH8LAN;
 
 out:
@@ -3218,7 +3228,7 @@
  *  @hw: pointer to the HW structure
  *
  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
- *  register, so the bus width is hard coded.
+ *  register, so the the bus width is hard coded.
  **/
 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
 {
@@ -3320,10 +3330,11 @@
 	ret_val = e1000_acquire_swflag_ich8lan(hw);
 	DEBUGOUT("Issuing a global reset to ich8lan\n");
 	E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
+	/* cannot issue a flush here because it hangs the hardware */
 	msec_delay(20);
 
 	if (!ret_val)
-		e1000_release_swflag_ich8lan(hw);
+		E1000_MUTEX_UNLOCK(&hw->dev_spec.ich8lan.swflag_mutex);
 
 	if (ctrl & E1000_CTRL_PHY_RST) {
 		ret_val = hw->phy.ops.get_cfg_done(hw);
@@ -3393,11 +3404,13 @@
 
 	/*
 	 * The 82578 Rx buffer will stall if wakeup is enabled in host and
-	 * the ME.  Reading the BM_WUC register will clear the host wakeup bit.
+	 * the ME.  Disable wakeup by clearing the host wakeup bit.
 	 * Reset the phy after disabling host wakeup to reset the Rx buffer.
 	 */
 	if (hw->phy.type == e1000_phy_82578) {
-		hw->phy.ops.read_reg(hw, BM_WUC, &i);
+		hw->phy.ops.read_reg(hw, BM_PORT_GEN_CFG, &i);
+		i &= ~BM_WUC_HOST_WU_BIT;
+		hw->phy.ops.write_reg(hw, BM_PORT_GEN_CFG, i);
 		ret_val = e1000_phy_hw_reset_ich8lan(hw);
 		if (ret_val)
 			return ret_val;
@@ -3411,13 +3424,13 @@
 	txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
 		 E1000_TXDCTL_FULL_TX_DESC_WB;
 	txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
-	         E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
+		 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
 	E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
 	txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
 	txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
 		 E1000_TXDCTL_FULL_TX_DESC_WB;
 	txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
-	         E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
+		 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
 	E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
 
 	/*
@@ -3557,8 +3570,8 @@
 		E1000_WRITE_REG(hw, E1000_FCRTV_PCH, hw->fc.refresh_time);
 
 		ret_val = hw->phy.ops.write_reg(hw,
-		                             PHY_REG(BM_PORT_CTRL_PAGE, 27),
-		                             hw->fc.pause_time);
+					     PHY_REG(BM_PORT_CTRL_PAGE, 27),
+					     hw->fc.pause_time);
 		if (ret_val)
 			goto out;
 	}
@@ -3596,18 +3609,18 @@
 	 * this fixes erroneous timeouts at 10Mbps.
 	 */
 	ret_val = e1000_write_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_TIMEOUTS,
-	                                       0xFFFF);
+					       0xFFFF);
 	if (ret_val)
 		goto out;
 	ret_val = e1000_read_kmrn_reg_generic(hw,
-	                                      E1000_KMRNCTRLSTA_INBAND_PARAM,
-	                                      &reg_data);
+					      E1000_KMRNCTRLSTA_INBAND_PARAM,
+					      &reg_data);
 	if (ret_val)
 		goto out;
 	reg_data |= 0x3F;
 	ret_val = e1000_write_kmrn_reg_generic(hw,
-	                                       E1000_KMRNCTRLSTA_INBAND_PARAM,
-	                                       reg_data);
+					       E1000_KMRNCTRLSTA_INBAND_PARAM,
+					       reg_data);
 	if (ret_val)
 		goto out;
 
@@ -3631,7 +3644,7 @@
 		break;
 	case e1000_phy_ife:
 		ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
-		                               &reg_data);
+					       &reg_data);
 		if (ret_val)
 			goto out;
 
@@ -3650,7 +3663,7 @@
 			break;
 		}
 		ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
-		                                reg_data);
+						reg_data);
 		if (ret_val)
 			goto out;
 		break;
@@ -3674,7 +3687,7 @@
  *  gigabit speeds.
  **/
 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
-                                          u16 *duplex)
+					  u16 *duplex)
 {
 	s32 ret_val;
 
@@ -3756,7 +3769,7 @@
 	/* Disable GigE link negotiation */
 	phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
 	phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
-	             E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
+		     E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
 	E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
 
 	/*
@@ -3781,7 +3794,7 @@
  *  /disabled - FALSE).
  **/
 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
-                                                 bool state)
+						 bool state)
 {
 	struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 
@@ -3823,7 +3836,7 @@
 		/* Disable link */
 		reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
 		reg |= (E1000_PHY_CTRL_GBE_DISABLE |
-		        E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
+			E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
 		E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
 
 		/*
@@ -3837,7 +3850,7 @@
 		hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
 		data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
 		hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
-		                   data | IGP3_VR_CTRL_MODE_SHUTDOWN);
+				      data | IGP3_VR_CTRL_MODE_SHUTDOWN);
 
 		/* Read it back and test */
 		hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
@@ -3863,7 +3876,7 @@
  *  LPLU, Gig disable, MDIC PHY reset):
  *    1) Set Kumeran Near-end loopback
  *    2) Clear Kumeran Near-end loopback
- *  Should only be called for ICH8[m] devices with IGP_3 Phy.
+ *  Should only be called for ICH8[m] devices with any 1G Phy.
  **/
 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
 {
@@ -3873,51 +3886,54 @@
 	DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
 
 	if ((hw->mac.type != e1000_ich8lan) ||
-	    (hw->phy.type != e1000_phy_igp_3))
+	    (hw->phy.type == e1000_phy_ife))
 		goto out;
 
 	ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
-	                                      &reg_data);
+					      &reg_data);
 	if (ret_val)
 		goto out;
 	reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
 	ret_val = e1000_write_kmrn_reg_generic(hw,
-	                                       E1000_KMRNCTRLSTA_DIAG_OFFSET,
-	                                       reg_data);
+					       E1000_KMRNCTRLSTA_DIAG_OFFSET,
+					       reg_data);
 	if (ret_val)
 		goto out;
 	reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
 	ret_val = e1000_write_kmrn_reg_generic(hw,
-	                                       E1000_KMRNCTRLSTA_DIAG_OFFSET,
-	                                       reg_data);
+					       E1000_KMRNCTRLSTA_DIAG_OFFSET,
+					       reg_data);
 out:
 	return;
 }
 
 /**
- *  e1000_disable_gig_wol_ich8lan - disable gig during WoL
+ *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
  *  @hw: pointer to the HW structure
  *
  *  During S0 to Sx transition, it is possible the link remains at gig
  *  instead of negotiating to a lower speed.  Before going to Sx, set
- *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
- *  to a lower speed.
- *
- *  Should only be called for applicable parts.
+ *  'Gig Disable' to force link speed negotiation to a lower speed based on
+ *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
+ *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
+ *  needs to be written.
  **/
-void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw)
+void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
 {
 	u32 phy_ctrl;
 	s32 ret_val;
 
-	DEBUGFUNC("e1000_disable_gig_wol_ich8lan");
+	DEBUGFUNC("e1000_suspend_workarounds_ich8lan");
 
 	phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
-	phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
+	phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
 	E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
+	if (hw->mac.type == e1000_ich8lan)
+		e1000_gig_downshift_workaround_ich8lan(hw);
 
 	if (hw->mac.type >= e1000_pchlan) {
 		e1000_oem_bits_config_ich8lan(hw, FALSE);
+		e1000_phy_hw_reset_ich8lan(hw);
 		ret_val = hw->phy.ops.acquire(hw);
 		if (ret_val)
 			return;
@@ -3929,6 +3945,58 @@
 }
 
 /**
+ *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
+ *  @hw: pointer to the HW structure
+ *
+ *  During Sx to S0 transitions on non-managed devices or managed devices
+ *  on which PHY resets are not blocked, if the PHY registers cannot be
+ *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
+ *  the PHY.
+ **/
+void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
+{
+	u16 phy_id1, phy_id2;
+	s32 ret_val;
+
+	DEBUGFUNC("e1000_resume_workarounds_pchlan");
+
+	if ((hw->mac.type != e1000_pch2lan) ||
+	    hw->phy.ops.check_reset_block(hw))
+		return;
+
+	ret_val = hw->phy.ops.acquire(hw);
+	if (ret_val) {
+		DEBUGOUT("Failed to acquire PHY semaphore in resume\n");
+		return;
+	}
+
+	/* Test access to the PHY registers by reading the ID regs */
+	ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_id1);
+	if (ret_val)
+		goto release;
+	ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_id2);
+	if (ret_val)
+		goto release;
+
+	if (hw->phy.id == ((u32)(phy_id1 << 16) |
+			   (u32)(phy_id2 & PHY_REVISION_MASK)))
+		goto release;
+
+	e1000_toggle_lanphypc_value_ich8lan(hw);
+
+	hw->phy.ops.release(hw);
+	msec_delay(50);
+	hw->phy.ops.reset(hw);
+	msec_delay(50);
+	return;
+
+release:
+	hw->phy.ops.release(hw);
+
+	return;
+}
+
+/**
  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
  *  @hw: pointer to the HW structure
  *
@@ -3940,7 +4008,7 @@
 
 	if (hw->phy.type == e1000_phy_ife)
 		return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
-		                             0);
+					     0);
 
 	E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
 	return E1000_SUCCESS;
@@ -3958,7 +4026,7 @@
 
 	if (hw->phy.type == e1000_phy_ife)
 		return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
-		                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
+				(IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
 
 	E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
 	return E1000_SUCCESS;
@@ -3976,7 +4044,7 @@
 
 	if (hw->phy.type == e1000_phy_ife)
 		return hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
-		               (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
+			       (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
 
 	E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
 	return E1000_SUCCESS;
@@ -3993,7 +4061,7 @@
 	DEBUGFUNC("e1000_setup_led_pchlan");
 
 	return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
-					(u16)hw->mac.ledctl_mode1);
+				     (u16)hw->mac.ledctl_mode1);
 }
 
 /**
@@ -4007,7 +4075,7 @@
 	DEBUGFUNC("e1000_cleanup_led_pchlan");
 
 	return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
-					(u16)hw->mac.ledctl_default);
+				     (u16)hw->mac.ledctl_default);
 }
 
 /**
@@ -4165,6 +4233,7 @@
 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
 {
 	u16 phy_data;
+	s32 ret_val;
 
 	DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
 
@@ -4188,20 +4257,29 @@
 	if ((hw->phy.type == e1000_phy_82578) ||
 	    (hw->phy.type == e1000_phy_82579) ||
 	    (hw->phy.type == e1000_phy_82577)) {
-		hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
-		hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
-		hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
-		hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
-		hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
-		hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
-		hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
-		hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
-		hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
-		hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
-		hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
-		hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
-		hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
-		hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
+		ret_val = hw->phy.ops.acquire(hw);
+		if (ret_val)
+			return;
+		ret_val = hw->phy.ops.set_page(hw,
+					       HV_STATS_PAGE << IGP_PAGE_SHIFT);
+		if (ret_val)
+			goto release;
+		hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
+		hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
+		hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
+		hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
+		hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
+		hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
+		hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
+		hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
+		hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
+		hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
+		hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
+		hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
+		hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
+		hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
+release:
+		hw->phy.ops.release(hw);
 	}
 }
 
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/e1000/e1000_ich8lan.h
--- a/head/sys/dev/e1000/e1000_ich8lan.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/e1000/e1000_ich8lan.h	Thu Dec 15 12:59:38 2011 +0200
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,187 +30,209 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD: head/sys/dev/e1000/e1000_ich8lan.h 228386 2011-12-10 06:55:02Z jfv $*/
 
 #ifndef _E1000_ICH8LAN_H_
 #define _E1000_ICH8LAN_H_
 
-#define ICH_FLASH_GFPREG                 0x0000
-#define ICH_FLASH_HSFSTS                 0x0004
-#define ICH_FLASH_HSFCTL                 0x0006
-#define ICH_FLASH_FADDR                  0x0008
-#define ICH_FLASH_FDATA0                 0x0010
+#define ICH_FLASH_GFPREG		0x0000
+#define ICH_FLASH_HSFSTS		0x0004
+#define ICH_FLASH_HSFCTL		0x0006
+#define ICH_FLASH_FADDR			0x0008
+#define ICH_FLASH_FDATA0		0x0010
 
 /* Requires up to 10 seconds when MNG might be accessing part. */
-#define ICH_FLASH_READ_COMMAND_TIMEOUT   10000000
-#define ICH_FLASH_WRITE_COMMAND_TIMEOUT  10000000
-#define ICH_FLASH_ERASE_COMMAND_TIMEOUT  10000000
-#define ICH_FLASH_LINEAR_ADDR_MASK       0x00FFFFFF
-#define ICH_FLASH_CYCLE_REPEAT_COUNT     10
+#define ICH_FLASH_READ_COMMAND_TIMEOUT	10000000
+#define ICH_FLASH_WRITE_COMMAND_TIMEOUT	10000000
+#define ICH_FLASH_ERASE_COMMAND_TIMEOUT	10000000
+#define ICH_FLASH_LINEAR_ADDR_MASK	0x00FFFFFF
+#define ICH_FLASH_CYCLE_REPEAT_COUNT	10
 
-#define ICH_CYCLE_READ                   0
-#define ICH_CYCLE_WRITE                  2
-#define ICH_CYCLE_ERASE                  3
+#define ICH_CYCLE_READ			0
+#define ICH_CYCLE_WRITE			2
+#define ICH_CYCLE_ERASE			3
 
-#define FLASH_GFPREG_BASE_MASK           0x1FFF
-#define FLASH_SECTOR_ADDR_SHIFT          12
+#define FLASH_GFPREG_BASE_MASK		0x1FFF
+#define FLASH_SECTOR_ADDR_SHIFT		12
 
-#define ICH_FLASH_SEG_SIZE_256           256
-#define ICH_FLASH_SEG_SIZE_4K            4096
-#define ICH_FLASH_SEG_SIZE_8K            8192
-#define ICH_FLASH_SEG_SIZE_64K           65536
-#define ICH_FLASH_SECTOR_SIZE            4096
+#define ICH_FLASH_SEG_SIZE_256		256
+#define ICH_FLASH_SEG_SIZE_4K		4096
+#define ICH_FLASH_SEG_SIZE_8K		8192
+#define ICH_FLASH_SEG_SIZE_64K		65536
+#define ICH_FLASH_SECTOR_SIZE		4096
 
-#define ICH_FLASH_REG_MAPSIZE            0x00A0
+#define ICH_FLASH_REG_MAPSIZE		0x00A0
 
-#define E1000_ICH_FWSM_RSPCIPHY          0x00000040 /* Reset PHY on PCI Reset */
-#define E1000_ICH_FWSM_DISSW             0x10000000 /* FW Disables SW Writes */
+#define E1000_ICH_FWSM_RSPCIPHY		0x00000040 /* Reset PHY on PCI Reset */
+#define E1000_ICH_FWSM_DISSW		0x10000000 /* FW Disables SW Writes */
 /* FW established a valid mode */
-#define E1000_ICH_FWSM_FW_VALID          0x00008000
+#define E1000_ICH_FWSM_FW_VALID		0x00008000
+#define E1000_ICH_FWSM_PCIM2PCI		0x01000000 /* ME PCIm-to-PCI active */
+#define E1000_ICH_FWSM_PCIM2PCI_COUNT	2000
 
-#define E1000_ICH_MNG_IAMT_MODE          0x2
+#define E1000_ICH_MNG_IAMT_MODE		0x2
 
-#define E1000_FWSM_PROXY_MODE            0x00000008 /* FW is in proxy mode */
+#define E1000_FWSM_PROXY_MODE		0x00000008 /* FW is in proxy mode */
+#define E1000_FWSM_MEMC			0x00000010 /* ME Messaging capable */
 
 /* Shared Receive Address Registers */
-#define E1000_SHRAL(_i)  (0x05438 + ((_i) * 8))
-#define E1000_SHRAH(_i)  (0x0543C + ((_i) * 8))
-#define E1000_SHRAH_AV   0x80000000 /* Addr Valid bit */
-#define E1000_SHRAH_MAV  0x40000000 /* Multicast Addr Valid bit */
+#define E1000_SHRAL(_i)		(0x05438 + ((_i) * 8))
+#define E1000_SHRAH(_i)		(0x0543C + ((_i) * 8))
+#define E1000_SHRAH_AV		0x80000000 /* Addr Valid bit */
+#define E1000_SHRAH_MAV		0x40000000 /* Multicast Addr Valid bit */
 
-#define E1000_H2ME             0x05B50    /* Host to ME */
-#define E1000_H2ME_LSECREQ     0x00000001 /* Linksec Request */
-#define E1000_H2ME_LSECA       0x00000002 /* Linksec Active */
-#define E1000_H2ME_LSECSF      0x00000004 /* Linksec Failed */
-#define E1000_H2ME_LSECD       0x00000008 /* Linksec Disabled */
-#define E1000_H2ME_SLCAPD      0x00000010 /* Start LCAPD */
-#define E1000_H2ME_IPV4_ARP_EN 0x00000020 /* Arp Offload enable bit */
-#define E1000_H2ME_IPV6_NS_EN  0x00000040 /* NS Offload enable bit */
+#define E1000_H2ME		0x05B50    /* Host to ME */
+#define E1000_H2ME_LSECREQ	0x00000001 /* Linksec Request */
+#define E1000_H2ME_LSECA	0x00000002 /* Linksec Active */
+#define E1000_H2ME_LSECSF	0x00000004 /* Linksec Failed */
+#define E1000_H2ME_LSECD	0x00000008 /* Linksec Disabled */
+#define E1000_H2ME_SLCAPD	0x00000010 /* Start LCAPD */
+#define E1000_H2ME_IPV4_ARP_EN	0x00000020 /* Arp Offload enable bit */
+#define E1000_H2ME_IPV6_NS_EN	0x00000040 /* NS Offload enable bit */
 
-#define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
-                                 (ID_LED_OFF1_OFF2 <<  8) | \
-                                 (ID_LED_OFF1_ON2  <<  4) | \
-                                 (ID_LED_DEF1_DEF2))
+#define ID_LED_DEFAULT_ICH8LAN	((ID_LED_DEF1_DEF2 << 12) | \
+				 (ID_LED_OFF1_OFF2 <<  8) | \
+				 (ID_LED_OFF1_ON2  <<  4) | \
+				 (ID_LED_DEF1_DEF2))
 
-#define E1000_ICH_NVM_SIG_WORD           0x13
-#define E1000_ICH_NVM_SIG_MASK           0xC000
-#define E1000_ICH_NVM_VALID_SIG_MASK     0xC0
-#define E1000_ICH_NVM_SIG_VALUE          0x80
+#define E1000_ICH_NVM_SIG_WORD		0x13
+#define E1000_ICH_NVM_SIG_MASK		0xC000
+#define E1000_ICH_NVM_VALID_SIG_MASK	0xC0
+#define E1000_ICH_NVM_SIG_VALUE		0x80
 
-#define E1000_ICH8_LAN_INIT_TIMEOUT      1500
+#define E1000_ICH8_LAN_INIT_TIMEOUT	1500
 
-#define E1000_FEXTNVM_SW_CONFIG        1
-#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M */
+#define E1000_FEXTNVM_SW_CONFIG		1
+#define E1000_FEXTNVM_SW_CONFIG_ICH8M	(1 << 27) /* Bit redefined for ICH8M */
 
-#define E1000_FEXTNVM4_BEACON_DURATION_MASK    0x7
-#define E1000_FEXTNVM4_BEACON_DURATION_8USEC   0x7
-#define E1000_FEXTNVM4_BEACON_DURATION_16USEC  0x3
+#define E1000_FEXTNVM4_BEACON_DURATION_MASK	0x7
+#define E1000_FEXTNVM4_BEACON_DURATION_8USEC	0x7
+#define E1000_FEXTNVM4_BEACON_DURATION_16USEC	0x3
 
-#define PCIE_ICH8_SNOOP_ALL   PCIE_NO_SNOOP_ALL
+#define PCIE_ICH8_SNOOP_ALL	PCIE_NO_SNOOP_ALL
 
-#define E1000_ICH_RAR_ENTRIES            7
-#define E1000_PCH2_RAR_ENTRIES           5 /* RAR[0], SHRA[0-3] */
+#define E1000_ICH_RAR_ENTRIES	7
+#define E1000_PCH2_RAR_ENTRIES	5 /* RAR[0], SHRA[0-3] */
 
-#define PHY_PAGE_SHIFT 5
-#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
-                           ((reg) & MAX_PHY_REG_ADDRESS))
-#define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
-#define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
-#define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */
-#define IGP3_PM_CTRL    PHY_REG(769, 20) /* Power Management Control */
+#define PHY_PAGE_SHIFT		5
+#define PHY_REG(page, reg)	(((page) << PHY_PAGE_SHIFT) | \
+				 ((reg) & MAX_PHY_REG_ADDRESS))
+#define IGP3_KMRN_DIAG		PHY_REG(770, 19) /* KMRN Diagnostic */
+#define IGP3_VR_CTRL		PHY_REG(776, 18) /* Voltage Regulator Control */
+#define IGP3_CAPABILITY		PHY_REG(776, 19) /* Capability */
+#define IGP3_PM_CTRL		PHY_REG(769, 20) /* Power Management Control */
 
-#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS         0x0002
-#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
-#define IGP3_VR_CTRL_MODE_SHUTDOWN           0x0200
-#define IGP3_PM_CTRL_FORCE_PWR_DOWN          0x0020
+#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS		0x0002
+#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK	0x0300
+#define IGP3_VR_CTRL_MODE_SHUTDOWN		0x0200
+#define IGP3_PM_CTRL_FORCE_PWR_DOWN		0x0020
 
 /* PHY Wakeup Registers and defines */
-#define BM_RCTL         PHY_REG(BM_WUC_PAGE, 0)
-#define BM_WUC          PHY_REG(BM_WUC_PAGE, 1)
-#define BM_WUFC         PHY_REG(BM_WUC_PAGE, 2)
-#define BM_WUS          PHY_REG(BM_WUC_PAGE, 3)
-#define BM_RAR_L(_i)    (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
-#define BM_RAR_M(_i)    (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
-#define BM_RAR_H(_i)    (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
-#define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
-#define BM_MTA(_i)      (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
-#define BM_IPAV         (BM_PHY_REG(BM_WUC_PAGE, 64))
-#define BM_IP4AT_L(_i)  (BM_PHY_REG(BM_WUC_PAGE, 82 + ((_i) * 2)))
-#define BM_IP4AT_H(_i)  (BM_PHY_REG(BM_WUC_PAGE, 83 + ((_i) * 2)))
+#define BM_PORT_GEN_CFG		PHY_REG(BM_PORT_CTRL_PAGE, 17)
+#define BM_RCTL			PHY_REG(BM_WUC_PAGE, 0)
+#define BM_WUC			PHY_REG(BM_WUC_PAGE, 1)
+#define BM_WUFC			PHY_REG(BM_WUC_PAGE, 2)
+#define BM_WUS			PHY_REG(BM_WUC_PAGE, 3)
+#define BM_RAR_L(_i)		(BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
+#define BM_RAR_M(_i)		(BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
+#define BM_RAR_H(_i)		(BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
+#define BM_RAR_CTRL(_i)		(BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
+#define BM_MTA(_i)		(BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
+#define BM_IPAV			(BM_PHY_REG(BM_WUC_PAGE, 64))
+#define BM_IP4AT_L(_i)		(BM_PHY_REG(BM_WUC_PAGE, 82 + ((_i) * 2)))
+#define BM_IP4AT_H(_i)		(BM_PHY_REG(BM_WUC_PAGE, 83 + ((_i) * 2)))
 
-#define BM_SHRAL_LOWER(_i) (BM_PHY_REG(BM_WUC_PAGE, 44 + ((_i) * 4)))
-#define BM_SHRAL_UPPER(_i) (BM_PHY_REG(BM_WUC_PAGE, 45 + ((_i) * 4)))
-#define BM_SHRAH_LOWER(_i) (BM_PHY_REG(BM_WUC_PAGE, 46 + ((_i) * 4)))
-#define BM_SHRAH_UPPER(_i) (BM_PHY_REG(BM_WUC_PAGE, 47 + ((_i) * 4)))
+#define BM_SHRAL_LOWER(_i)	(BM_PHY_REG(BM_WUC_PAGE, 44 + ((_i) * 4)))
+#define BM_SHRAL_UPPER(_i)	(BM_PHY_REG(BM_WUC_PAGE, 45 + ((_i) * 4)))
+#define BM_SHRAH_LOWER(_i)	(BM_PHY_REG(BM_WUC_PAGE, 46 + ((_i) * 4)))
+#define BM_SHRAH_UPPER(_i)	(BM_PHY_REG(BM_WUC_PAGE, 47 + ((_i) * 4)))
 
-#define BM_RCTL_UPE           0x0001          /* Unicast Promiscuous Mode */
-#define BM_RCTL_MPE           0x0002          /* Multicast Promiscuous Mode */
-#define BM_RCTL_MO_SHIFT      3               /* Multicast Offset Shift */
-#define BM_RCTL_MO_MASK       (3 << 3)        /* Multicast Offset Mask */
-#define BM_RCTL_BAM           0x0020          /* Broadcast Accept Mode */
-#define BM_RCTL_PMCF          0x0040          /* Pass MAC Control Frames */
-#define BM_RCTL_RFCE          0x0080          /* Rx Flow Control Enable */
+#define BM_RCTL_UPE		0x0001 /* Unicast Promiscuous Mode */
+#define BM_RCTL_MPE		0x0002 /* Multicast Promiscuous Mode */
+#define BM_RCTL_MO_SHIFT	3      /* Multicast Offset Shift */
+#define BM_RCTL_MO_MASK		(3 << 3) /* Multicast Offset Mask */
+#define BM_RCTL_BAM		0x0020 /* Broadcast Accept Mode */
+#define BM_RCTL_PMCF		0x0040 /* Pass MAC Control Frames */
+#define BM_RCTL_RFCE		0x0080 /* Rx Flow Control Enable */
 
-#define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
-#define HV_MUX_DATA_CTRL               PHY_REG(776, 16)
-#define HV_MUX_DATA_CTRL_GEN_TO_MAC    0x0400
-#define HV_MUX_DATA_CTRL_FORCE_SPEED   0x0004
-#define HV_SCC_UPPER            PHY_REG(778, 16) /* Single Collision Count */
-#define HV_SCC_LOWER            PHY_REG(778, 17)
-#define HV_ECOL_UPPER           PHY_REG(778, 18) /* Excessive Collision Count */
-#define HV_ECOL_LOWER           PHY_REG(778, 19)
-#define HV_MCC_UPPER            PHY_REG(778, 20) /* Multiple Collision Count */
-#define HV_MCC_LOWER            PHY_REG(778, 21)
-#define HV_LATECOL_UPPER        PHY_REG(778, 23) /* Late Collision Count */
-#define HV_LATECOL_LOWER        PHY_REG(778, 24)
-#define HV_COLC_UPPER           PHY_REG(778, 25) /* Collision Count */
-#define HV_COLC_LOWER           PHY_REG(778, 26)
-#define HV_DC_UPPER             PHY_REG(778, 27) /* Defer Count */
-#define HV_DC_LOWER             PHY_REG(778, 28)
-#define HV_TNCRS_UPPER          PHY_REG(778, 29) /* Transmit with no CRS */
-#define HV_TNCRS_LOWER          PHY_REG(778, 30)
+#define HV_LED_CONFIG		PHY_REG(768, 30) /* LED Configuration */
+#define HV_MUX_DATA_CTRL	PHY_REG(776, 16)
+#define HV_MUX_DATA_CTRL_GEN_TO_MAC	0x0400
+#define HV_MUX_DATA_CTRL_FORCE_SPEED	0x0004
+#define HV_STATS_PAGE	778
+#define HV_SCC_UPPER	PHY_REG(HV_STATS_PAGE, 16) /* Single Collision Count */
+#define HV_SCC_LOWER	PHY_REG(HV_STATS_PAGE, 17)
+#define HV_ECOL_UPPER	PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. Count */
+#define HV_ECOL_LOWER	PHY_REG(HV_STATS_PAGE, 19)
+#define HV_MCC_UPPER	PHY_REG(HV_STATS_PAGE, 20) /* Multiple Coll. Count */
+#define HV_MCC_LOWER	PHY_REG(HV_STATS_PAGE, 21)
+#define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision Count */
+#define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)
+#define HV_COLC_UPPER	PHY_REG(HV_STATS_PAGE, 25) /* Collision Count */
+#define HV_COLC_LOWER	PHY_REG(HV_STATS_PAGE, 26)
+#define HV_DC_UPPER	PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */
+#define HV_DC_LOWER	PHY_REG(HV_STATS_PAGE, 28)
+#define HV_TNCRS_UPPER	PHY_REG(HV_STATS_PAGE, 29) /* Transmit with no CRS */
+#define HV_TNCRS_LOWER	PHY_REG(HV_STATS_PAGE, 30)
 
-#define E1000_FCRTV_PCH     0x05F40 /* PCH Flow Control Refresh Timer Value */
+#define E1000_FCRTV_PCH	0x05F40 /* PCH Flow Control Refresh Timer Value */
 
-#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
-#define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
+/*
+ * For ICH, the name used for NVM word 17h is LED1 Config.
+ * For PCH, the word was re-named to OEM Config.
+ */
+#define E1000_NVM_LED1_CONFIG		0x17   /* NVM LED1/LPLU Config Word */
+#define E1000_NVM_LED1_CONFIG_LPLU_NONDOA 0x0400 /* NVM LPLU in non-D0a Bit */
+#define E1000_NVM_OEM_CONFIG		E1000_NVM_LED1_CONFIG
+#define E1000_NVM_OEM_CONFIG_LPLU_NONDOA E1000_NVM_LED1_CONFIG_LPLU_NONDOA
+
+#define E1000_NVM_K1_CONFIG	0x1B /* NVM K1 Config Word */
+#define E1000_NVM_K1_ENABLE	0x1  /* NVM Enable K1 bit */
 
 /* SMBus Address Phy Register */
-#define HV_SMB_ADDR            PHY_REG(768, 26)
-#define HV_SMB_ADDR_MASK       0x007F
-#define HV_SMB_ADDR_PEC_EN     0x0200
-#define HV_SMB_ADDR_VALID      0x0080
+#define HV_SMB_ADDR		PHY_REG(768, 26)
+#define HV_SMB_ADDR_MASK	0x007F
+#define HV_SMB_ADDR_PEC_EN	0x0200
+#define HV_SMB_ADDR_VALID	0x0080
 
 /* Strapping Option Register - RO */
-#define E1000_STRAP                     0x0000C
-#define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
-#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
+#define E1000_STRAP			0x0000C
+#define E1000_STRAP_SMBUS_ADDRESS_MASK	0x00FE0000
+#define E1000_STRAP_SMBUS_ADDRESS_SHIFT	17
 
 /* OEM Bits Phy Register */
-#define HV_OEM_BITS            PHY_REG(768, 25)
-#define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
-#define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
-#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
+#define HV_OEM_BITS		PHY_REG(768, 25)
+#define HV_OEM_BITS_LPLU	0x0004 /* Low Power Link Up */
+#define HV_OEM_BITS_GBE_DIS	0x0040 /* Gigabit Disable */
+#define HV_OEM_BITS_RESTART_AN	0x0400 /* Restart Auto-negotiation */
 
-#define LCD_CFG_PHY_ADDR_BIT   0x0020 /* Phy address bit from LCD Config word */
+#define LCD_CFG_PHY_ADDR_BIT	0x0020 /* Phy addr bit from LCD Config word */
 
 /* KMRN Mode Control */
-#define HV_KMRN_MODE_CTRL       PHY_REG(769, 16)
-#define HV_KMRN_MDIO_SLOW       0x0400
+#define HV_KMRN_MODE_CTRL	PHY_REG(769, 16)
+#define HV_KMRN_MDIO_SLOW	0x0400
+
+/* KMRN FIFO Control and Status */
+#define HV_KMRN_FIFO_CTRLSTA			PHY_REG(770, 16)
+#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK	0x7000
+#define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT	12
 
 /* PHY Power Management Control */
-#define HV_PM_CTRL              PHY_REG(770, 17)
+#define HV_PM_CTRL		PHY_REG(770, 17)
 
-#define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
+#define SW_FLAG_TIMEOUT		1000 /* SW Semaphore flag timeout in ms */
 
 /* PHY Low Power Idle Control */
-#define I82579_LPI_CTRL         PHY_REG(772, 20)
-#define I82579_LPI_CTRL_ENABLE_MASK     0x6000
+#define I82579_LPI_CTRL				PHY_REG(772, 20)
+#define I82579_LPI_CTRL_ENABLE_MASK		0x6000
+#define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT	0x80
 
 /* EMI Registers */
-#define I82579_EMI_ADDR         0x10
-#define I82579_EMI_DATA         0x11
-#define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */
+#define I82579_EMI_ADDR		0x10
+#define I82579_EMI_DATA		0x11
+#define I82579_LPI_UPDATE_TIMER	0x4805 /* in 40ns units + 40 ns base value */
+#define I82579_MSE_THRESHOLD	0x084F /* Mean Square Error Threshold */
+#define I82579_MSE_LINK_DOWN	0x2411 /* MSE count before dropping link */
 
 /*
  * Additional interrupts need to be handled for ICH family:
@@ -219,33 +241,32 @@
  *  EPRST = Manageability reset event
  */
 #define IMS_ICH_ENABLE_MASK (\
-    E1000_IMS_DSW   | \
-    E1000_IMS_PHYINT | \
-    E1000_IMS_EPRST)
+	E1000_IMS_DSW   | \
+	E1000_IMS_PHYINT | \
+	E1000_IMS_EPRST)
 
 /* Additional interrupt register bit definitions */
-#define E1000_ICR_LSECPNC       0x00004000          /* PN threshold - client */
-#define E1000_IMS_LSECPNC       E1000_ICR_LSECPNC   /* PN threshold - client */
-#define E1000_ICS_LSECPNC       E1000_ICR_LSECPNC   /* PN threshold - client */
+#define E1000_ICR_LSECPNC	0x00004000  /* PN threshold - client */
+#define E1000_IMS_LSECPNC	E1000_ICR_LSECPNC   /* PN threshold - client */
+#define E1000_ICS_LSECPNC	E1000_ICR_LSECPNC   /* PN threshold - client */
 
 /* Security Processing bit Indication */
-#define E1000_RXDEXT_LINKSEC_STATUS_LSECH       0x01000000
-#define E1000_RXDEXT_LINKSEC_ERROR_BIT_MASK     0x60000000
-#define E1000_RXDEXT_LINKSEC_ERROR_NO_SA_MATCH  0x20000000
-#define E1000_RXDEXT_LINKSEC_ERROR_REPLAY_ERROR 0x40000000
-#define E1000_RXDEXT_LINKSEC_ERROR_BAD_SIG      0x60000000
+#define E1000_RXDEXT_LINKSEC_STATUS_LSECH	0x01000000
+#define E1000_RXDEXT_LINKSEC_ERROR_BIT_MASK	0x60000000
+#define E1000_RXDEXT_LINKSEC_ERROR_NO_SA_MATCH	0x20000000
+#define E1000_RXDEXT_LINKSEC_ERROR_REPLAY_ERROR	0x40000000
+#define E1000_RXDEXT_LINKSEC_ERROR_BAD_SIG	0x60000000
 
 /* Receive Address Initial CRC Calculation */
-#define E1000_PCH_RAICC(_n)     (0x05F50 + ((_n) * 4))
+#define E1000_PCH_RAICC(_n)	(0x05F50 + ((_n) * 4))
 
 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
-                                                 bool state);
+						 bool state);
 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
-void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw);
+void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
+void e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
-s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_config);
-s32 e1000_hv_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
 #endif
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/e1000/e1000_mac.c
--- a/head/sys/dev/e1000/e1000_mac.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/e1000/e1000_mac.c	Thu Dec 15 12:59:38 2011 +0200
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD: head/sys/dev/e1000/e1000_mac.c 228386 2011-12-10 06:55:02Z jfv $*/
 
 #include "e1000_api.h"
 
@@ -177,8 +177,8 @@
 	/* Bus speed */
 	if (bus->type == e1000_bus_type_pci) {
 		bus->speed = (status & E1000_STATUS_PCI66)
-		             ? e1000_bus_speed_66
-		             : e1000_bus_speed_33;
+			     ? e1000_bus_speed_66
+			     : e1000_bus_speed_33;
 	} else {
 		switch (status & E1000_STATUS_PCIX_SPEED) {
 		case E1000_STATUS_PCIX_SPEED_66:
@@ -198,8 +198,8 @@
 
 	/* Bus width */
 	bus->width = (status & E1000_STATUS_BUS64)
-	             ? e1000_bus_width_64
-	             : e1000_bus_width_32;
+		     ? e1000_bus_width_64
+		     : e1000_bus_width_32;
 
 	/* Which PCI(-X) function? */
 	mac->ops.set_lan_id(hw);
@@ -226,9 +226,8 @@
 
 	bus->type = e1000_bus_type_pci_express;
 
-	ret_val = e1000_read_pcie_cap_reg(hw,
-	                                  PCIE_LINK_STATUS,
-	                                  &pcie_link_status);
+	ret_val = e1000_read_pcie_cap_reg(hw, PCIE_LINK_STATUS,
+					  &pcie_link_status);
 	if (ret_val) {
 		bus->width = e1000_bus_width_unknown;
 		bus->speed = e1000_bus_speed_unknown;
@@ -246,8 +245,7 @@
 		}
 
 		bus->width = (enum e1000_bus_width)((pcie_link_status &
-		                                PCIE_LINK_WIDTH_MASK) >>
-		                               PCIE_LINK_WIDTH_SHIFT);
+			      PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT);
 	}
 
 	mac->ops.set_lan_id(hw);
@@ -292,7 +290,7 @@
 	if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
 		status = E1000_READ_REG(hw, E1000_STATUS);
 		bus->func = (status & E1000_STATUS_FUNC_MASK)
-		            >> E1000_STATUS_FUNC_SHIFT;
+			    >> E1000_STATUS_FUNC_SHIFT;
 	} else {
 		bus->func = 0;
 	}
@@ -352,7 +350,7 @@
  *  @hw: pointer to the HW structure
  *  @rar_count: receive address registers
  *
- *  Setups the receive address registers by setting the base receive address
+ *  Setup the receive address registers by setting the base receive address
  *  register to the devices MAC address and clearing all the other receive
  *  address registers to 0.
  **/
@@ -399,23 +397,28 @@
 	if (ret_val)
 		goto out;
 
-	/* Check for LOM (vs. NIC) or one of two valid mezzanine cards */
-	if (!((nvm_data & NVM_COMPAT_LOM) ||
-	      (hw->device_id == E1000_DEV_ID_82571EB_SERDES_DUAL) ||
-	      (hw->device_id == E1000_DEV_ID_82571EB_SERDES_QUAD)))
+	/* not supported on older hardware or 82573 */
+	if ((hw->mac.type < e1000_82571) || (hw->mac.type == e1000_82573))
+		goto out;
+
+	/*
+	 * Alternate MAC address is handled by the option ROM for 82580
+	 * and newer. SW support not required.
+	 */
+	if (hw->mac.type >= e1000_82580)
 		goto out;
 
 	ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
-	                         &nvm_alt_mac_addr_offset);
+				   &nvm_alt_mac_addr_offset);
 	if (ret_val) {
 		DEBUGOUT("NVM Read Error\n");
 		goto out;
 	}
 
-	if (nvm_alt_mac_addr_offset == 0xFFFF) {
+	if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
+	    (nvm_alt_mac_addr_offset == 0x0000))
 		/* There is no Alternate MAC Address */
 		goto out;
-	}
 
 	if (hw->bus.func == E1000_FUNC_1)
 		nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
@@ -472,9 +475,8 @@
 	 * HW expects these in little endian so we reverse the byte order
 	 * from network order (big endian) to little endian
 	 */
-	rar_low = ((u32) addr[0] |
-	           ((u32) addr[1] << 8) |
-	           ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
+	rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
+		   ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
 
 	rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
 
@@ -503,7 +505,7 @@
  *  The caller must have a packed mc_addr_list of multicast addresses.
  **/
 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
-                                       u8 *mc_addr_list, u32 mc_addr_count)
+				       u8 *mc_addr_list, u32 mc_addr_count)
 {
 	u32 hash_value, hash_bit, hash_reg;
 	int i;
@@ -574,7 +576,7 @@
 	 * values resulting from each mc_filter_type...
 	 * [0] [1] [2] [3] [4] [5]
 	 * 01  AA  00  12  34  56
-	 * LSB                 MSB
+	 * LSB		 MSB
 	 *
 	 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
 	 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
@@ -597,7 +599,7 @@
 	}
 
 	hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
-	                          (((u16) mc_addr[5]) << bit_shift)));
+				  (((u16) mc_addr[5]) << bit_shift)));
 
 	return hash_value;
 }
@@ -627,9 +629,9 @@
 	e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
 	e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
 	cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >>
-	             PCIX_COMMAND_MMRBC_SHIFT;
+		     PCIX_COMMAND_MMRBC_SHIFT;
 	stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
-	              PCIX_STATUS_HI_MMRBC_SHIFT;
+		      PCIX_STATUS_HI_MMRBC_SHIFT;
 	if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
 		stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
 	if (cmd_mmrbc > stat_mmrbc) {
@@ -926,12 +928,10 @@
 			if (rxcw & E1000_RXCW_SYNCH) {
 				if (!(rxcw & E1000_RXCW_IV)) {
 					mac->serdes_has_link = TRUE;
-					DEBUGOUT("SERDES: Link up - autoneg "
-					   "completed sucessfully.\n");
+					DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n");
 				} else {
 					mac->serdes_has_link = FALSE;
-					DEBUGOUT("SERDES: Link down - invalid"
-					   "codewords detected in autoneg.\n");
+					DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n");
 				}
 			} else {
 				mac->serdes_has_link = FALSE;
@@ -1423,8 +1423,7 @@
 			goto out;
 
 		if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
-			DEBUGOUT("Copper PHY and Auto Neg "
-			         "has not completed.\n");
+			DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
 			goto out;
 		}
 
@@ -1436,11 +1435,11 @@
 		 * flow control was negotiated.
 		 */
 		ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
-		                             &mii_nway_adv_reg);
+					       &mii_nway_adv_reg);
 		if (ret_val)
 			goto out;
 		ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
-		                             &mii_nway_lp_ability_reg);
+					       &mii_nway_lp_ability_reg);
 		if (ret_val)
 			goto out;
 
@@ -1485,15 +1484,14 @@
 			 * of pause frames.  In this case, we had to advertise
 			 * FULL flow control because we could not advertise Rx
 			 * ONLY. Hence, we must now check to see if we need to
-			 * turn OFF  the TRANSMISSION of PAUSE frames.
+			 * turn OFF the TRANSMISSION of PAUSE frames.
 			 */
 			if (hw->fc.requested_mode == e1000_fc_full) {
 				hw->fc.current_mode = e1000_fc_full;
-				DEBUGOUT("Flow Control = FULL.\r\n");
+				DEBUGOUT("Flow Control = FULL.\n");
 			} else {
 				hw->fc.current_mode = e1000_fc_rx_pause;
-				DEBUGOUT("Flow Control = "
-				         "Rx PAUSE frames only.\r\n");
+				DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
 			}
 		}
 		/*
@@ -1505,11 +1503,11 @@
 		 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
 		 */
 		else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
-		          (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
-		          (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
-		          (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
+			  (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
+			  (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
+			  (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
 			hw->fc.current_mode = e1000_fc_tx_pause;
-			DEBUGOUT("Flow Control = Tx PAUSE frames only.\r\n");
+			DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
 		}
 		/*
 		 * For transmitting PAUSE frames ONLY.
@@ -1520,18 +1518,18 @@
 		 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
 		 */
 		else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
-		         (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
-		         !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
-		         (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
+			 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
+			 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
+			 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
 			hw->fc.current_mode = e1000_fc_rx_pause;
-			DEBUGOUT("Flow Control = Rx PAUSE frames only.\r\n");
+			DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
 		} else {
 			/*
 			 * Per the IEEE spec, at this point flow control
 			 * should be disabled.
 			 */
 			hw->fc.current_mode = e1000_fc_none;
-			DEBUGOUT("Flow Control = NONE.\r\n");
+			DEBUGOUT("Flow Control = NONE.\n");
 		}
 
 		/*
@@ -1573,7 +1571,7 @@
  *  speed and duplex for copper connections.
  **/
 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
-                                              u16 *duplex)
+					      u16 *duplex)
 {
 	u32 status;
 
@@ -1612,7 +1610,7 @@
  *  for fiber/serdes links.
  **/
 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw,
-                                                    u16 *speed, u16 *duplex)
+						    u16 *speed, u16 *duplex)
 {
 	DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
 
@@ -1843,11 +1841,10 @@
 		ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
 		hw->mac.ledctl_default = ledctl;
 		/* Turn off LED0 */
-		ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
-		            E1000_LEDCTL_LED0_BLINK |
-		            E1000_LEDCTL_LED0_MODE_MASK);
+		ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK |
+			    E1000_LEDCTL_LED0_MODE_MASK);
 		ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
-		           E1000_LEDCTL_LED0_MODE_SHIFT);
+			   E1000_LEDCTL_LED0_MODE_SHIFT);
 		E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
 	} else if (hw->phy.media_type == e1000_media_type_copper) {
 		E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
@@ -1899,7 +1896,7 @@
 			if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
 			    E1000_LEDCTL_MODE_LED_ON)
 				ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
-				                 (i * 8));
+						 (i * 8));
 	}
 
 	E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
@@ -2090,7 +2087,8 @@
 				else
 					mac->current_ifs_val +=
 						mac->ifs_step_size;
-				E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val);
+				E1000_WRITE_REG(hw, E1000_AIT,
+						mac->current_ifs_val);
 			}
 		}
 	} else {
@@ -2141,7 +2139,7 @@
  *  completion.
  **/
 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
-                                      u32 offset, u8 data)
+				      u32 offset, u8 data)
 {
 	u32 i, regvalue = 0;
 	s32 ret_val = E1000_SUCCESS;
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/e1000/e1000_nvm.c
--- a/head/sys/dev/e1000/e1000_nvm.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/e1000/e1000_nvm.c	Thu Dec 15 12:59:38 2011 +0200
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD: head/sys/dev/e1000/e1000_nvm.c 228386 2011-12-10 06:55:02Z jfv $*/
 
 #include "e1000_api.h"
 
@@ -313,8 +313,7 @@
 		usec_delay(nvm->delay_usec);
 
 		e1000_lower_eec_clk(hw, &eecd);
-	} else
-	if (nvm->type == e1000_nvm_eeprom_spi) {
+	} else if (nvm->type == e1000_nvm_eeprom_spi) {
 		/* Toggle CS to flush commands */
 		eecd |= E1000_EECD_CS;
 		E1000_WRITE_REG(hw, E1000_EECD, eecd);
@@ -394,13 +393,13 @@
 		/* Set CS */
 		eecd |= E1000_EECD_CS;
 		E1000_WRITE_REG(hw, E1000_EECD, eecd);
-	} else
-	if (nvm->type == e1000_nvm_eeprom_spi) {
+	} else if (nvm->type == e1000_nvm_eeprom_spi) {
 		u16 timeout = NVM_MAX_RETRY_SPI;
 
 		/* Clear SK and CS */
 		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
 		E1000_WRITE_REG(hw, E1000_EECD, eecd);
+		E1000_WRITE_FLUSH(hw);
 		usec_delay(1);
 
 		/*
@@ -411,7 +410,7 @@
 		 */
 		while (timeout) {
 			e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
-			                         hw->nvm.opcode_bits);
+						 hw->nvm.opcode_bits);
 			spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
 			if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
 				break;
@@ -506,7 +505,7 @@
  *  Reads a 16 bit word from the EEPROM.
  **/
 s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
-                             u16 *data)
+			     u16 *data)
 {
 	struct e1000_nvm_info *nvm = &hw->nvm;
 	u32 i = 0;
@@ -593,7 +592,7 @@
 			break;
 
 		data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
-		           E1000_NVM_RW_REG_DATA);
+			   E1000_NVM_RW_REG_DATA);
 	}
 
 out:
@@ -646,7 +645,7 @@
 
 		/* Send the WRITE ENABLE command (8 bit opcode) */
 		e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
-		                         nvm->opcode_bits);
+					 nvm->opcode_bits);
 
 		e1000_standby_nvm(hw);
 
@@ -660,7 +659,7 @@
 		/* Send the Write command (8-bit opcode + addr) */
 		e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
 		e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
-		                         nvm->address_bits);
+					 nvm->address_bits);
 
 		/* Loop to allow for up to whole page write of eeprom */
 		while (widx < words) {
@@ -697,7 +696,7 @@
  *  EEPROM will most likely contain an invalid checksum.
  **/
 s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
-                              u16 *data)
+			      u16 *data)
 {
 	struct e1000_nvm_info *nvm = &hw->nvm;
 	s32  ret_val;
@@ -727,7 +726,7 @@
 		goto release;
 
 	e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
-	                         (u16)(nvm->opcode_bits + 2));
+				 (u16)(nvm->opcode_bits + 2));
 
 	e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
 
@@ -735,10 +734,10 @@
 
 	while (words_written < words) {
 		e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
-		                         nvm->opcode_bits);
+					 nvm->opcode_bits);
 
 		e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
-		                         nvm->address_bits);
+					 nvm->address_bits);
 
 		e1000_shift_out_eec_bits(hw, data[words_written], 16);
 
@@ -763,7 +762,7 @@
 	}
 
 	e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
-	                         (u16)(nvm->opcode_bits + 2));
+				 (u16)(nvm->opcode_bits + 2));
 
 	e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
 
@@ -784,7 +783,7 @@
  *  the value in pba_num.
  **/
 s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
-                                  u32 pba_num_size)
+				  u32 pba_num_size)
 {
 	s32 ret_val;
 	u16 nvm_data;
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/e1000/e1000_nvm.h
--- a/head/sys/dev/e1000/e1000_nvm.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/e1000/e1000_nvm.h	Thu Dec 15 12:59:38 2011 +0200
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD: head/sys/dev/e1000/e1000_nvm.h 228386 2011-12-10 06:55:02Z jfv $*/
 
 #ifndef _E1000_NVM_H_
 #define _E1000_NVM_H_
@@ -45,25 +45,23 @@
 s32  e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
 s32  e1000_read_mac_addr_generic(struct e1000_hw *hw);
 s32  e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
-                                   u32 pba_num_size);
+				   u32 pba_num_size);
 s32  e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size);
 s32  e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
 s32  e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset,
-                              u16 words, u16 *data);
+			      u16 words, u16 *data);
 s32  e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words,
-                         u16 *data);
+			 u16 *data);
 s32  e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data);
 s32  e1000_validate_nvm_checksum_generic(struct e1000_hw *hw);
-s32  e1000_write_nvm_eewr(struct e1000_hw *hw, u16 offset,
-                          u16 words, u16 *data);
 s32  e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset,
-                               u16 words, u16 *data);
+			       u16 words, u16 *data);
 s32  e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words,
-                         u16 *data);
+			 u16 *data);
 s32  e1000_update_nvm_checksum_generic(struct e1000_hw *hw);
 void e1000_stop_nvm(struct e1000_hw *hw);
 void e1000_release_nvm_generic(struct e1000_hw *hw);
 
-#define E1000_STM_OPCODE  0xDB00
+#define E1000_STM_OPCODE	0xDB00
 
 #endif
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/e1000/e1000_osdep.h
--- a/head/sys/dev/e1000/e1000_osdep.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/e1000/e1000_osdep.h	Thu Dec 15 12:59:38 2011 +0200
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD: head/sys/dev/e1000/e1000_osdep.h 228441 2011-12-12 18:27:34Z mdf $*/
 
 
 #ifndef _FREEBSD_OS_H_
@@ -73,9 +73,11 @@
 
 #define STATIC			static
 #define FALSE			0
-#define false			FALSE 
 #define TRUE			1
+#ifndef __bool_true_false_are_defined
+#define false			FALSE
 #define true			TRUE
+#endif
 #define CMD_MEM_WRT_INVALIDATE	0x0010  /* BIT_4 */
 #define PCI_COMMAND_REGISTER	PCIR_COMMAND
 
@@ -96,7 +98,9 @@
 typedef int32_t		s32;
 typedef int16_t		s16;
 typedef int8_t		s8;
+#ifndef __bool_true_false_are_defined
 typedef boolean_t	bool;
+#endif
 
 #define __le16		u16
 #define __le32		u32
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/e1000/e1000_phy.c
--- a/head/sys/dev/e1000/e1000_phy.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/e1000/e1000_phy.c	Thu Dec 15 12:59:38 2011 +0200
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,23 +30,23 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD: head/sys/dev/e1000/e1000_phy.c 228386 2011-12-10 06:55:02Z jfv $*/
 
 #include "e1000_api.h"
 
 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
-                                          u16 *data, bool read);
+					  u16 *data, bool read, bool page_set);
 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
-                                          u16 *data, bool read);
+					  u16 *data, bool read);
 
 /* Cable length tables */
 static const u16 e1000_m88_cable_length_table[] = {
 	0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
-                (sizeof(e1000_m88_cable_length_table) / \
-                 sizeof(e1000_m88_cable_length_table[0]))
+		(sizeof(e1000_m88_cable_length_table) / \
+		 sizeof(e1000_m88_cable_length_table[0]))
 
 static const u16 e1000_igp_2_cable_length_table[] = {
 	0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
@@ -58,8 +58,8 @@
 	100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
 	124};
 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
-                (sizeof(e1000_igp_2_cable_length_table) / \
-                 sizeof(e1000_igp_2_cable_length_table[0]))
+		(sizeof(e1000_igp_2_cable_length_table) / \
+		 sizeof(e1000_igp_2_cable_length_table[0]))
 
 /**
  *  e1000_init_phy_ops_generic - Initialize PHY function pointers
@@ -82,20 +82,35 @@
 	phy->ops.get_cfg_done = e1000_null_ops_generic;
 	phy->ops.get_cable_length = e1000_null_ops_generic;
 	phy->ops.get_info = e1000_null_ops_generic;
+	phy->ops.set_page = e1000_null_set_page;
 	phy->ops.read_reg = e1000_null_read_reg;
 	phy->ops.read_reg_locked = e1000_null_read_reg;
+	phy->ops.read_reg_page = e1000_null_read_reg;
 	phy->ops.release = e1000_null_phy_generic;
 	phy->ops.reset = e1000_null_ops_generic;
 	phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
 	phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
 	phy->ops.write_reg = e1000_null_write_reg;
 	phy->ops.write_reg_locked = e1000_null_write_reg;
+	phy->ops.write_reg_page = e1000_null_write_reg;
 	phy->ops.power_up = e1000_null_phy_generic;
 	phy->ops.power_down = e1000_null_phy_generic;
+	phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
+	phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
 	phy->ops.cfg_on_link_up = e1000_null_ops_generic;
 }
 
 /**
+ *  e1000_null_set_page - No-op function, return 0
+ *  @hw: pointer to the HW structure
+ **/
+s32 e1000_null_set_page(struct e1000_hw *hw, u16 data)
+{
+	DEBUGFUNC("e1000_null_set_page");
+	return E1000_SUCCESS;
+}
+
+/**
  *  e1000_null_read_reg - No-op function, return 0
  *  @hw: pointer to the HW structure
  **/
@@ -250,8 +265,8 @@
 	 * PHY to retrieve the desired data.
 	 */
 	mdic = ((offset << E1000_MDIC_REG_SHIFT) |
-	        (phy->addr << E1000_MDIC_PHY_SHIFT) |
-	        (E1000_MDIC_OP_READ));
+		(phy->addr << E1000_MDIC_PHY_SHIFT) |
+		(E1000_MDIC_OP_READ));
 
 	E1000_WRITE_REG(hw, E1000_MDIC, mdic);
 
@@ -316,9 +331,9 @@
 	 * PHY to retrieve the desired data.
 	 */
 	mdic = (((u32)data) |
-	        (offset << E1000_MDIC_REG_SHIFT) |
-	        (phy->addr << E1000_MDIC_PHY_SHIFT) |
-	        (E1000_MDIC_OP_WRITE));
+		(offset << E1000_MDIC_REG_SHIFT) |
+		(phy->addr << E1000_MDIC_PHY_SHIFT) |
+		(E1000_MDIC_OP_WRITE));
 
 	E1000_WRITE_REG(hw, E1000_MDIC, mdic);
 
@@ -377,8 +392,8 @@
 	 * PHY to retrieve the desired data.
 	 */
 	i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
-	          (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
-	          (E1000_I2CCMD_OPCODE_READ));
+		  (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
+		  (E1000_I2CCMD_OPCODE_READ));
 
 	E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
 
@@ -420,6 +435,13 @@
 
 	DEBUGFUNC("e1000_write_phy_reg_i2c");
 
+	/* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/
+	if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
+		DEBUGOUT1("PHY I2C Address %d is out of range.\n",
+			  hw->phy.addr);
+		return -E1000_ERR_CONFIG;
+	}
+
 	/* Swap the data bytes for the I2C interface */
 	phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
 
@@ -429,9 +451,9 @@
 	 * PHY to retrieve the desired data.
 	 */
 	i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
-	          (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
-	          E1000_I2CCMD_OPCODE_WRITE |
-	          phy_data_swapped);
+		  (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
+		  E1000_I2CCMD_OPCODE_WRITE |
+		  phy_data_swapped);
 
 	E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
 
@@ -455,6 +477,139 @@
 }
 
 /**
+ *  e1000_read_sfp_data_byte - Reads SFP module data.
+ *  @hw: pointer to the HW structure
+ *  @offset: byte location offset to be read
+ *  @data: read data buffer pointer
+ *
+ *  Reads one byte from SFP module data stored
+ *  in SFP resided EEPROM memory or SFP diagnostic area.
+ *  Function should be called with
+ *  E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
+ *  E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
+ *  access
+ **/
+s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
+{
+	u32 i = 0;
+	u32 i2ccmd = 0;
+	u32 data_local = 0;
+
+	DEBUGFUNC("e1000_read_sfp_data_byte");
+
+	if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
+		DEBUGOUT("I2CCMD command address exceeds upper limit\n");
+		return -E1000_ERR_PHY;
+	}
+
+	/*
+	 * Set up Op-code, EEPROM Address,in the I2CCMD
+	 * register. The MAC will take care of interfacing with the
+	 * EEPROM to retrieve the desired data.
+	 */
+	i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
+		  E1000_I2CCMD_OPCODE_READ);
+
+	E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
+
+	/* Poll the ready bit to see if the I2C read completed */
+	for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
+		usec_delay(50);
+		data_local = E1000_READ_REG(hw, E1000_I2CCMD);
+		if (data_local & E1000_I2CCMD_READY)
+			break;
+	}
+	if (!(data_local & E1000_I2CCMD_READY)) {
+		DEBUGOUT("I2CCMD Read did not complete\n");
+		return -E1000_ERR_PHY;
+	}
+	if (data_local & E1000_I2CCMD_ERROR) {
+		DEBUGOUT("I2CCMD Error bit set\n");
+		return -E1000_ERR_PHY;
+	}
+	*data = (u8) data_local & 0xFF;
+
+	return E1000_SUCCESS;
+}
+
+/**
+ *  e1000_write_sfp_data_byte - Writes SFP module data.
+ *  @hw: pointer to the HW structure
+ *  @offset: byte location offset to write to
+ *  @data: data to write
+ *
+ *  Writes one byte to SFP module data stored
+ *  in SFP resided EEPROM memory or SFP diagnostic area.
+ *  Function should be called with
+ *  E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
+ *  E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
+ *  access
+ **/
+s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data)
+{
+	u32 i = 0;
+	u32 i2ccmd = 0;
+	u32 data_local = 0;
+
+	DEBUGFUNC("e1000_write_sfp_data_byte");
+
+	if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
+		DEBUGOUT("I2CCMD command address exceeds upper limit\n");
+		return -E1000_ERR_PHY;
+	}
+	/*
+	 * The programming interface is 16 bits wide
+	 * so we need to read the whole word first
+	 * then update appropriate byte lane and write
+	 * the updated word back.
+	 */
+	/*
+	 * Set up Op-code, EEPROM Address,in the I2CCMD
+	 * register. The MAC will take care of interfacing
+	 * with an EEPROM to write the data given.
+	 */
+	i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
+		  E1000_I2CCMD_OPCODE_READ);
+	/* Set a command to read single word */
+	E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
+	for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
+		usec_delay(50);
+		/*
+		 * Poll the ready bit to see if lastly
+		 * launched I2C operation completed
+		 */
+		i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
+		if (i2ccmd & E1000_I2CCMD_READY) {
+			/* Check if this is READ or WRITE phase */
+			if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) ==
+			    E1000_I2CCMD_OPCODE_READ) {
+				/*
+				 * Write the selected byte
+				 * lane and update whole word
+				 */
+				data_local = i2ccmd & 0xFF00;
+				data_local |= data;
+				i2ccmd = ((offset <<
+					E1000_I2CCMD_REG_ADDR_SHIFT) |
+					E1000_I2CCMD_OPCODE_WRITE | data_local);
+				E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
+			} else {
+				break;
+			}
+		}
+	}
+	if (!(i2ccmd & E1000_I2CCMD_READY)) {
+		DEBUGOUT("I2CCMD Write did not complete\n");
+		return -E1000_ERR_PHY;
+	}
+	if (i2ccmd & E1000_I2CCMD_ERROR) {
+		DEBUGOUT("I2CCMD Error bit set\n");
+		return -E1000_ERR_PHY;
+	}
+	return E1000_SUCCESS;
+}
+
+/**
  *  e1000_read_phy_reg_m88 - Read m88 PHY register
  *  @hw: pointer to the HW structure
  *  @offset: register offset to be read
@@ -478,7 +633,7 @@
 		goto out;
 
 	ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
-	                                  data);
+					  data);
 
 	hw->phy.ops.release(hw);
 
@@ -509,7 +664,7 @@
 		goto out;
 
 	ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
-	                                   data);
+					   data);
 
 	hw->phy.ops.release(hw);
 
@@ -518,6 +673,26 @@
 }
 
 /**
+ *  e1000_set_page_igp - Set page as on IGP-like PHY(s)
+ *  @hw: pointer to the HW structure
+ *  @page: page to set (shifted left when necessary)
+ *
+ *  Sets PHY page required for PHY register access.  Assumes semaphore is
+ *  already acquired.  Note, this function sets phy.addr to 1 so the caller
+ *  must set it appropriately (if necessary) after this function returns.
+ **/
+s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
+{
+	DEBUGFUNC("e1000_set_page_igp");
+
+	DEBUGOUT1("Setting page 0x%x\n", page);
+
+	hw->phy.addr = 1;
+
+	return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
+}
+
+/**
  *  __e1000_read_phy_reg_igp - Read igp PHY register
  *  @hw: pointer to the HW structure
  *  @offset: register offset to be read
@@ -529,7 +704,7 @@
  *  semaphores before exiting.
  **/
 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
-                                    bool locked)
+				    bool locked)
 {
 	s32 ret_val = E1000_SUCCESS;
 
@@ -546,14 +721,14 @@
 
 	if (offset > MAX_PHY_MULTI_PAGE_REG) {
 		ret_val = e1000_write_phy_reg_mdic(hw,
-		                                   IGP01E1000_PHY_PAGE_SELECT,
-		                                   (u16)offset);
+						   IGP01E1000_PHY_PAGE_SELECT,
+						   (u16)offset);
 		if (ret_val)
 			goto release;
 	}
 
 	ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
-	                                  data);
+					  data);
 
 release:
 	if (!locked)
@@ -602,7 +777,7 @@
  *  at the offset.  Release any acquired semaphores before exiting.
  **/
 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
-                                     bool locked)
+				     bool locked)
 {
 	s32 ret_val = E1000_SUCCESS;
 
@@ -619,14 +794,14 @@
 
 	if (offset > MAX_PHY_MULTI_PAGE_REG) {
 		ret_val = e1000_write_phy_reg_mdic(hw,
-		                                   IGP01E1000_PHY_PAGE_SELECT,
-		                                   (u16)offset);
+						   IGP01E1000_PHY_PAGE_SELECT,
+						   (u16)offset);
 		if (ret_val)
 			goto release;
 	}
 
 	ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
-	                                   data);
+					   data);
 
 release:
 	if (!locked)
@@ -676,7 +851,7 @@
  *  Release any acquired semaphores before exiting.
  **/
 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
-                                 bool locked)
+				 bool locked)
 {
 	u32 kmrnctrlsta;
 	s32 ret_val = E1000_SUCCESS;
@@ -693,8 +868,9 @@
 	}
 
 	kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
-	               E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
+		       E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
 	E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
+	E1000_WRITE_FLUSH(hw);
 
 	usec_delay(2);
 
@@ -750,7 +926,7 @@
  *  before exiting.
  **/
 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
-                                  bool locked)
+				  bool locked)
 {
 	u32 kmrnctrlsta;
 	s32 ret_val = E1000_SUCCESS;
@@ -767,8 +943,9 @@
 	}
 
 	kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
-	               E1000_KMRNCTRLSTA_OFFSET) | data;
+		       E1000_KMRNCTRLSTA_OFFSET) | data;
 	E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
+	E1000_WRITE_FLUSH(hw);
 
 	usec_delay(2);
 
@@ -820,11 +997,6 @@
 
 	DEBUGFUNC("e1000_copper_link_setup_82577");
 
-	if (hw->phy.reset_disable) {
-		ret_val = E1000_SUCCESS;
-		goto out;
-	}
-
 	if (hw->phy.type == e1000_phy_82580) {
 		ret_val = hw->phy.ops.reset(hw);
 		if (ret_val) {
@@ -844,6 +1016,37 @@
 	phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
 
 	ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
+	if (ret_val)
+		goto out;
+
+	/* Resolve Master/Slave mode */
+	ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
+	if (ret_val)
+		goto out;
+
+	/* load defaults for future use */
+	hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
+				   ((phy_data & CR_1000T_MS_VALUE) ?
+				   e1000_ms_force_master :
+				   e1000_ms_force_slave) : e1000_ms_auto;
+
+	switch (hw->phy.ms_type) {
+	case e1000_ms_force_master:
+		phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
+		break;
+	case e1000_ms_force_slave:
+		phy_data |= CR_1000T_MS_ENABLE;
+		phy_data &= ~(CR_1000T_MS_VALUE);
+		break;
+	case e1000_ms_auto:
+		phy_data &= ~CR_1000T_MS_ENABLE;
+	default:
+		break;
+	}
+
+	ret_val = hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
+	if (ret_val)
+		goto out;
 
 out:
 	return ret_val;
@@ -864,10 +1067,6 @@
 
 	DEBUGFUNC("e1000_copper_link_setup_m88");
 
-	if (phy->reset_disable) {
-		ret_val = E1000_SUCCESS;
-		goto out;
-	}
 
 	/* Enable CRS on Tx. This must be set for half-duplex operation. */
 	ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
@@ -931,7 +1130,7 @@
 		 * to 25MHz clock.
 		 */
 		ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
-		                             &phy_data);
+					    &phy_data);
 		if (ret_val)
 			goto out;
 
@@ -945,12 +1144,12 @@
 		} else {
 			/* Configure Master and Slave downshift values */
 			phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
-			             M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
+				     M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
 			phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
-			             M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
+				     M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
 		}
 		ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
-		                             phy_data);
+					     phy_data);
 		if (ret_val)
 			goto out;
 	}
@@ -976,7 +1175,7 @@
 
 	if (phy->type == e1000_phy_82578) {
 		ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
-		                            &phy_data);
+					    &phy_data);
 		if (ret_val)
 			goto out;
 
@@ -984,7 +1183,7 @@
 		phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
 		phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
 		ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
-		                             phy_data);
+					     phy_data);
 		if (ret_val)
 			goto out;
 	}
@@ -1008,10 +1207,6 @@
 
 	DEBUGFUNC("e1000_copper_link_setup_m88_gen2");
 
-	if (phy->reset_disable) {
-		ret_val = E1000_SUCCESS;
-		goto out;
-	}
 
 	/* Enable CRS on Tx. This must be set for half-duplex operation. */
 	ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
@@ -1093,10 +1288,6 @@
 
 	DEBUGFUNC("e1000_copper_link_setup_igp");
 
-	if (phy->reset_disable) {
-		ret_val = E1000_SUCCESS;
-		goto out;
-	}
 
 	ret_val = hw->phy.ops.reset(hw);
 	if (ret_val) {
@@ -1164,15 +1355,15 @@
 		if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
 			/* Disable SmartSpeed */
 			ret_val = phy->ops.read_reg(hw,
-			                             IGP01E1000_PHY_PORT_CONFIG,
-			                             &data);
+						    IGP01E1000_PHY_PORT_CONFIG,
+						    &data);
 			if (ret_val)
 				goto out;
 
 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 			ret_val = phy->ops.write_reg(hw,
-			                             IGP01E1000_PHY_PORT_CONFIG,
-			                             data);
+						     IGP01E1000_PHY_PORT_CONFIG,
+						     data);
 			if (ret_val)
 				goto out;
 
@@ -1278,8 +1469,7 @@
 	if (phy->autoneg_wait_to_complete) {
 		ret_val = hw->mac.ops.wait_autoneg(hw);
 		if (ret_val) {
-			DEBUGOUT("Error while waiting for "
-			         "autoneg to complete\n");
+			DEBUGOUT("Error while waiting for autoneg to complete\n");
 			goto out;
 		}
 	}
@@ -1318,7 +1508,7 @@
 	if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
 		/* Read the MII 1000Base-T Control Register (Address 9). */
 		ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
-		                            &mii_1000t_ctrl_reg);
+					    &mii_1000t_ctrl_reg);
 		if (ret_val)
 			goto out;
 	}
@@ -1337,9 +1527,9 @@
 	 * the  1000Base-T Control Register (Address 9).
 	 */
 	mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
-	                         NWAY_AR_100TX_HD_CAPS |
-	                         NWAY_AR_10T_FD_CAPS   |
-	                         NWAY_AR_10T_HD_CAPS);
+				 NWAY_AR_100TX_HD_CAPS |
+				 NWAY_AR_10T_FD_CAPS   |
+				 NWAY_AR_10T_HD_CAPS);
 	mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
 
 	DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
@@ -1445,9 +1635,8 @@
 	DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
 
 	if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
-		ret_val = phy->ops.write_reg(hw,
-		                              PHY_1000T_CTRL,
-		                              mii_1000t_ctrl_reg);
+		ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
+					     mii_1000t_ctrl_reg);
 		if (ret_val)
 			goto out;
 	}
@@ -1497,10 +1686,8 @@
 	 * Check link status. Wait up to 100 microseconds for link to become
 	 * valid.
 	 */
-	ret_val = e1000_phy_has_link_generic(hw,
-	                                     COPPER_LINK_UP_LIMIT,
-	                                     10,
-	                                     &link);
+	ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
+					     &link);
 	if (ret_val)
 		goto out;
 
@@ -1565,10 +1752,8 @@
 	if (phy->autoneg_wait_to_complete) {
 		DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
 
-		ret_val = e1000_phy_has_link_generic(hw,
-		                                     PHY_FORCE_LIMIT,
-		                                     100000,
-		                                     &link);
+		ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
+						     100000, &link);
 		if (ret_val)
 			goto out;
 
@@ -1576,10 +1761,8 @@
 			DEBUGOUT("Link taking longer than expected.\n");
 
 		/* Try once more */
-		ret_val = e1000_phy_has_link_generic(hw,
-		                                     PHY_FORCE_LIMIT,
-		                                     100000,
-		                                     &link);
+		ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
+						     100000, &link);
 		if (ret_val)
 			goto out;
 	}
@@ -1641,7 +1824,7 @@
 		DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
 
 		ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
-		                                     100000, &link);
+						     100000, &link);
 		if (ret_val)
 			goto out;
 
@@ -1669,7 +1852,7 @@
 
 		/* Try once more */
 		ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
-		                                     100000, &link);
+						     100000, &link);
 		if (ret_val)
 			goto out;
 	}
@@ -1755,10 +1938,8 @@
 	if (phy->autoneg_wait_to_complete) {
 		DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
 
-		ret_val = e1000_phy_has_link_generic(hw,
-		                                     PHY_FORCE_LIMIT,
-		                                     100000,
-		                                     &link);
+		ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
+						     100000, &link);
 		if (ret_val)
 			goto out;
 
@@ -1766,10 +1947,8 @@
 			DEBUGOUT("Link taking longer than expected.\n");
 
 		/* Try once more */
-		ret_val = e1000_phy_has_link_generic(hw,
-		                                     PHY_FORCE_LIMIT,
-		                                     100000,
-		                                     &link);
+		ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
+						     100000, &link);
 		if (ret_val)
 			goto out;
 	}
@@ -1872,7 +2051,7 @@
 	if (!active) {
 		data &= ~IGP02E1000_PM_D3_LPLU;
 		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
-		                             data);
+					     data);
 		if (ret_val)
 			goto out;
 		/*
@@ -1883,49 +2062,49 @@
 		 */
 		if (phy->smart_speed == e1000_smart_speed_on) {
 			ret_val = phy->ops.read_reg(hw,
-			                            IGP01E1000_PHY_PORT_CONFIG,
-			                            &data);
+						    IGP01E1000_PHY_PORT_CONFIG,
+						    &data);
 			if (ret_val)
 				goto out;
 
 			data |= IGP01E1000_PSCFR_SMART_SPEED;
 			ret_val = phy->ops.write_reg(hw,
-			                             IGP01E1000_PHY_PORT_CONFIG,
-			                             data);
+						     IGP01E1000_PHY_PORT_CONFIG,
+						     data);
 			if (ret_val)
 				goto out;
 		} else if (phy->smart_speed == e1000_smart_speed_off) {
 			ret_val = phy->ops.read_reg(hw,
-			                             IGP01E1000_PHY_PORT_CONFIG,
-			                             &data);
+						    IGP01E1000_PHY_PORT_CONFIG,
+						    &data);
 			if (ret_val)
 				goto out;
 
 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 			ret_val = phy->ops.write_reg(hw,
-			                             IGP01E1000_PHY_PORT_CONFIG,
-			                             data);
+						     IGP01E1000_PHY_PORT_CONFIG,
+						     data);
 			if (ret_val)
 				goto out;
 		}
 	} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
-	           (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
-	           (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
+		   (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
+		   (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 		data |= IGP02E1000_PM_D3_LPLU;
 		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
-		                              data);
+					     data);
 		if (ret_val)
 			goto out;
 
 		/* When LPLU is enabled, we should disable SmartSpeed */
 		ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-		                             &data);
+					    &data);
 		if (ret_val)
 			goto out;
 
 		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 		ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
-		                              data);
+					     data);
 	}
 
 out:
@@ -1953,14 +2132,14 @@
 	case e1000_phy_gg82563:
 	case e1000_phy_bm:
 	case e1000_phy_82578:
-		offset	= M88E1000_PHY_SPEC_STATUS;
-		mask	= M88E1000_PSSR_DOWNSHIFT;
+		offset = M88E1000_PHY_SPEC_STATUS;
+		mask = M88E1000_PSSR_DOWNSHIFT;
 		break;
 	case e1000_phy_igp:
 	case e1000_phy_igp_2:
 	case e1000_phy_igp_3:
-		offset	= IGP01E1000_PHY_LINK_HEALTH;
-		mask	= IGP01E1000_PLHR_SS_DOWNGRADE;
+		offset = IGP01E1000_PHY_LINK_HEALTH;
+		mask = IGP01E1000_PLHR_SS_DOWNGRADE;
 		break;
 	default:
 		/* speed downshift not supported */
@@ -1998,8 +2177,8 @@
 
 	if (!ret_val)
 		phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
-		                      ? e1000_rev_polarity_reversed
-		                      : e1000_rev_polarity_normal;
+				      ? e1000_rev_polarity_reversed
+				      : e1000_rev_polarity_normal;
 
 	return ret_val;
 }
@@ -2031,23 +2210,23 @@
 
 	if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
 	    IGP01E1000_PSSR_SPEED_1000MBPS) {
-		offset	= IGP01E1000_PHY_PCS_INIT_REG;
-		mask	= IGP01E1000_PHY_POLARITY_MASK;
+		offset = IGP01E1000_PHY_PCS_INIT_REG;
+		mask = IGP01E1000_PHY_POLARITY_MASK;
 	} else {
 		/*
 		 * This really only applies to 10Mbps since
 		 * there is no polarity for 100Mbps (always 0).
 		 */
-		offset	= IGP01E1000_PHY_PORT_STATUS;
-		mask	= IGP01E1000_PSSR_POLARITY_REVERSED;
+		offset = IGP01E1000_PHY_PORT_STATUS;
+		mask = IGP01E1000_PSSR_POLARITY_REVERSED;
 	}
 
 	ret_val = phy->ops.read_reg(hw, offset, &data);
 
 	if (!ret_val)
 		phy->cable_polarity = (data & mask)
-		                      ? e1000_rev_polarity_reversed
-		                      : e1000_rev_polarity_normal;
+				      ? e1000_rev_polarity_reversed
+				      : e1000_rev_polarity_normal;
 
 out:
 	return ret_val;
@@ -2082,8 +2261,8 @@
 
 	if (!ret_val)
 		phy->cable_polarity = (phy_data & mask)
-		                       ? e1000_rev_polarity_reversed
-		                       : e1000_rev_polarity_normal;
+				       ? e1000_rev_polarity_reversed
+				       : e1000_rev_polarity_normal;
 
 	return ret_val;
 }
@@ -2135,7 +2314,7 @@
  *  Polls the PHY status register for link, 'iterations' number of times.
  **/
 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
-                               u32 usec_interval, bool *success)
+			       u32 usec_interval, bool *success)
 {
 	s32 ret_val = E1000_SUCCESS;
 	u16 i, phy_status;
@@ -2203,7 +2382,7 @@
 		goto out;
 
 	index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
-	        M88E1000_PSSR_CABLE_LENGTH_SHIFT;
+		M88E1000_PSSR_CABLE_LENGTH_SHIFT;
 	if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
 		ret_val = -E1000_ERR_PHY;
 		goto out;
@@ -2250,14 +2429,14 @@
 		if (ret_val)
 			goto out;
 
-		is_cm = !(phy_data & I347AT4_PCDC_CABLE_LENGTH_UNIT);
+		is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
 
 		/* Populate the phy structure with cable length in meters */
 		phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
 		phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
 		phy->cable_length = phy_data / (is_cm ? 100 : 1);
 
-		/* Reset the page selec	to its original value */
+		/* Reset the page select to its original value */
 		ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
 					     default_page);
 		if (ret_val)
@@ -2327,10 +2506,10 @@
 	u16 cur_agc_index, max_agc_index = 0;
 	u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
 	static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
-	       IGP02E1000_PHY_AGC_A,
-	       IGP02E1000_PHY_AGC_B,
-	       IGP02E1000_PHY_AGC_C,
-	       IGP02E1000_PHY_AGC_D
+		IGP02E1000_PHY_AGC_A,
+		IGP02E1000_PHY_AGC_B,
+		IGP02E1000_PHY_AGC_C,
+		IGP02E1000_PHY_AGC_D
 	};
 
 	DEBUGFUNC("e1000_get_cable_length_igp_2");
@@ -2348,7 +2527,7 @@
 		 * approximate cable length.
 		 */
 		cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
-		                IGP02E1000_AGC_LENGTH_MASK;
+				IGP02E1000_AGC_LENGTH_MASK;
 
 		/* Array index bound check. */
 		if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
@@ -2369,12 +2548,12 @@
 	}
 
 	agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
-	              e1000_igp_2_cable_length_table[max_agc_index]);
+		      e1000_igp_2_cable_length_table[max_agc_index]);
 	agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
 
 	/* Calculate cable length with the error range of +/- 10 meters. */
 	phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
-	                         (agc_value - IGP02E1000_AGC_RANGE) : 0;
+				 (agc_value - IGP02E1000_AGC_RANGE) : 0;
 	phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
 
 	phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
@@ -2423,7 +2602,7 @@
 		goto out;
 
 	phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
-	                           ? TRUE : FALSE;
+				   ? TRUE : FALSE;
 
 	ret_val = e1000_check_polarity_m88(hw);
 	if (ret_val)
@@ -2445,12 +2624,12 @@
 			goto out;
 
 		phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
-		                ? e1000_1000t_rx_status_ok
-		                : e1000_1000t_rx_status_not_ok;
+				? e1000_1000t_rx_status_ok
+				: e1000_1000t_rx_status_not_ok;
 
 		phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
-		                 ? e1000_1000t_rx_status_ok
-		                 : e1000_1000t_rx_status_not_ok;
+				 ? e1000_1000t_rx_status_ok
+				 : e1000_1000t_rx_status_not_ok;
 	} else {
 		/* Set values to "undefined" */
 		phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
@@ -2513,12 +2692,12 @@
 			goto out;
 
 		phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
-		                ? e1000_1000t_rx_status_ok
-		                : e1000_1000t_rx_status_not_ok;
+				? e1000_1000t_rx_status_ok
+				: e1000_1000t_rx_status_not_ok;
 
 		phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
-		                 ? e1000_1000t_rx_status_ok
-		                 : e1000_1000t_rx_status_not_ok;
+				 ? e1000_1000t_rx_status_ok
+				 : e1000_1000t_rx_status_not_ok;
 	} else {
 		phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
 		phy->local_rx = e1000_1000t_rx_status_undefined;
@@ -2558,7 +2737,7 @@
 	if (ret_val)
 		goto out;
 	phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
-	                           ? FALSE : TRUE;
+				   ? FALSE : TRUE;
 
 	if (phy->polarity_correction) {
 		ret_val = e1000_check_polarity_ife(hw);
@@ -2567,8 +2746,8 @@
 	} else {
 		/* Polarity is forced */
 		phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
-		                      ? e1000_rev_polarity_reversed
-		                      : e1000_rev_polarity_normal;
+				      ? e1000_rev_polarity_reversed
+				      : e1000_rev_polarity_normal;
 	}
 
 	ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
@@ -2903,7 +3082,7 @@
 	/* Page 800 works differently than the rest so it has its own func */
 	if (page == BM_WUC_PAGE) {
 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
-		                                         FALSE);
+							 FALSE, FALSE);
 		goto out;
 	}
 
@@ -2927,13 +3106,13 @@
 
 		/* Page is shifted left, PHY expects (page x 32) */
 		ret_val = e1000_write_phy_reg_mdic(hw, page_select,
-		                                   (page << page_shift));
+						   (page << page_shift));
 		if (ret_val)
 			goto out;
 	}
 
 	ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
-	                                   data);
+					   data);
 
 out:
 	hw->phy.ops.release(hw);
@@ -2964,7 +3143,7 @@
 	/* Page 800 works differently than the rest so it has its own func */
 	if (page == BM_WUC_PAGE) {
 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
-		                                         TRUE);
+							 TRUE, FALSE);
 		goto out;
 	}
 
@@ -2988,13 +3167,13 @@
 
 		/* Page is shifted left, PHY expects (page x 32) */
 		ret_val = e1000_write_phy_reg_mdic(hw, page_select,
-		                                   (page << page_shift));
+						   (page << page_shift));
 		if (ret_val)
 			goto out;
 	}
 
 	ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
-	                                  data);
+					  data);
 out:
 	hw->phy.ops.release(hw);
 	return ret_val;
@@ -3015,7 +3194,7 @@
 	s32 ret_val;
 	u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
 
-	DEBUGFUNC("e1000_write_phy_reg_bm2");
+	DEBUGFUNC("e1000_read_phy_reg_bm2");
 
 	ret_val = hw->phy.ops.acquire(hw);
 	if (ret_val)
@@ -3024,7 +3203,7 @@
 	/* Page 800 works differently than the rest so it has its own func */
 	if (page == BM_WUC_PAGE) {
 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
-		                                         TRUE);
+							 TRUE, FALSE);
 		goto out;
 	}
 
@@ -3034,14 +3213,14 @@
 
 		/* Page is shifted left, PHY expects (page x 32) */
 		ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
-		                                   page);
+						   page);
 
 		if (ret_val)
 			goto out;
 	}
 
 	ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
-	                                  data);
+					  data);
 out:
 	hw->phy.ops.release(hw);
 	return ret_val;
@@ -3070,7 +3249,7 @@
 	/* Page 800 works differently than the rest so it has its own func */
 	if (page == BM_WUC_PAGE) {
 		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
-		                                         FALSE);
+							 FALSE, FALSE);
 		goto out;
 	}
 
@@ -3079,14 +3258,14 @@
 	if (offset > MAX_PHY_MULTI_PAGE_REG) {
 		/* Page is shifted left, PHY expects (page x 32) */
 		ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
-		                                   page);
+						   page);
 
 		if (ret_val)
 			goto out;
 	}
 
 	ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
-	                                   data);
+					   data);
 
 out:
 	hw->phy.ops.release(hw);
@@ -3094,26 +3273,128 @@
 }
 
 /**
- *  e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register
+ *  e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
+ *  @hw: pointer to the HW structure
+ *  @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
+ *
+ *  Assumes semaphore already acquired and phy_reg points to a valid memory
+ *  address to store contents of the BM_WUC_ENABLE_REG register.
+ **/
+s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
+{
+	s32 ret_val;
+	u16 temp;
+
+	DEBUGFUNC("e1000_enable_phy_wakeup_reg_access_bm");
+
+	if (!phy_reg) {
+		ret_val = -E1000_ERR_PARAM;
+		goto out;
+	}
+
+	/* All page select, port ctrl and wakeup registers use phy address 1 */
+	hw->phy.addr = 1;
+
+	/* Select Port Control Registers page */
+	ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
+	if (ret_val) {
+		DEBUGOUT("Could not set Port Control page\n");
+		goto out;
+	}
+
+	ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
+	if (ret_val) {
+		DEBUGOUT2("Could not read PHY register %d.%d\n",
+			  BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
+		goto out;
+	}
+
+	/*
+	 * Enable both PHY wakeup mode and Wakeup register page writes.
+	 * Prevent a power state change by disabling ME and Host PHY wakeup.
+	 */
+	temp = *phy_reg;
+	temp |= BM_WUC_ENABLE_BIT;
+	temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
+
+	ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
+	if (ret_val) {
+		DEBUGOUT2("Could not write PHY register %d.%d\n",
+			  BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
+		goto out;
+	}
+
+	/* Select Host Wakeup Registers page */
+	ret_val = e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
+
+	/* caller now able to write registers on the Wakeup registers page */
+out:
+	return ret_val;
+}
+
+/**
+ *  e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
+ *  @hw: pointer to the HW structure
+ *  @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
+ *
+ *  Restore BM_WUC_ENABLE_REG to its original value.
+ *
+ *  Assumes semaphore already acquired and *phy_reg is the contents of the
+ *  BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
+ *  caller.
+ **/
+s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
+{
+	s32 ret_val = E1000_SUCCESS;
+
+	DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm");
+
+	if (!phy_reg)
+		return -E1000_ERR_PARAM;
+
+	/* Select Port Control Registers page */
+	ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
+	if (ret_val) {
+		DEBUGOUT("Could not set Port Control page\n");
+		goto out;
+	}
+
+	/* Restore 769.17 to its original value */
+	ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
+	if (ret_val)
+		DEBUGOUT2("Could not restore PHY register %d.%d\n",
+			  BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
+out:
+	return ret_val;
+}
+
+/**
+ *  e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
  *  @hw: pointer to the HW structure
  *  @offset: register offset to be read or written
  *  @data: pointer to the data to read or write
  *  @read: determines if operation is read or write
+ *  @page_set: BM_WUC_PAGE already set and access enabled
  *
- *  Acquires semaphore, if necessary, then reads the PHY register at offset
- *  and storing the retrieved information in data.  Release any acquired
- *  semaphores before exiting. Note that procedure to read the wakeup
- *  registers are different. It works as such:
- *  1) Set page 769, register 17, bit 2 = 1
+ *  Read the PHY register at offset and store the retrieved information in
+ *  data, or write data to PHY register at offset.  Note the procedure to
+ *  access the PHY wakeup registers is different than reading the other PHY
+ *  registers. It works as such:
+ *  1) Set 769.17.2 (page 769, register 17, bit 2) = 1
  *  2) Set page to 800 for host (801 if we were manageability)
  *  3) Write the address using the address opcode (0x11)
  *  4) Read or write the data using the data opcode (0x12)
- *  5) Restore 769_17.2 to its original value
+ *  5) Restore 769.17.2 to its original value
  *
- *  Assumes semaphore already acquired.
+ *  Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
+ *  step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
+ *
+ *  Assumes semaphore is already acquired.  When page_set==TRUE, assumes
+ *  the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
+ *  is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
  **/
 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
-                                          u16 *data, bool read)
+					  u16 *data, bool read, bool page_set)
 {
 	s32 ret_val;
 	u16 reg = BM_PHY_REG_NUM(offset);
@@ -3121,79 +3402,47 @@
 
 	DEBUGFUNC("e1000_access_phy_wakeup_reg_bm");
 
-	/* Gig must be disabled for MDIO accesses to page 800 */
+	/* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
 	if ((hw->mac.type == e1000_pchlan) &&
 	   (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
-		DEBUGOUT("Attempting to access page 800 while gig enabled.\n");
-
-	/* All operations in this function are phy address 1 */
-	hw->phy.addr = 1;
-
-	/* Set page 769 */
-	e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
-	                         (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
-
-	ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg);
+		DEBUGOUT1("Attempting to access page %d while gig enabled.\n",
+			  page);
+
+	if (!page_set) {
+		/* Enable access to PHY wakeup registers */
+		ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
+		if (ret_val) {
+			DEBUGOUT("Could not enable PHY wakeup reg access\n");
+			goto out;
+		}
+	}
+
+	DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg);
+
+	/* Write the Wakeup register page offset value using opcode 0x11 */
+	ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
 	if (ret_val) {
-		DEBUGOUT("Could not read PHY page 769\n");
+		DEBUGOUT1("Could not write address opcode to page %d\n", page);
 		goto out;
 	}
 
-	/* First clear bit 4 to avoid a power state change */
-	phy_reg &= ~(BM_WUC_HOST_WU_BIT);
-	ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
+	if (read) {
+		/* Read the Wakeup register page value using opcode 0x12 */
+		ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
+						  data);
+	} else {
+		/* Write the Wakeup register page value using opcode 0x12 */
+		ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
+						   *data);
+	}
+
 	if (ret_val) {
-		DEBUGOUT("Could not clear PHY page 769 bit 4\n");
+		DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg);
 		goto out;
 	}
 
-	/* Write bit 2 = 1, and clear bit 4 to 769_17 */
-	ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG,
-	                                   phy_reg | BM_WUC_ENABLE_BIT);
-	if (ret_val) {
-		DEBUGOUT("Could not write PHY page 769 bit 2\n");
-		goto out;
-	}
-
-	/* Select page 800 */
-	ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
-	                                   (BM_WUC_PAGE << IGP_PAGE_SHIFT));
-
-	/* Write the page 800 offset value using opcode 0x11 */
-	ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
-	if (ret_val) {
-		DEBUGOUT("Could not write address opcode to page 800\n");
-		goto out;
-	}
-
-	if (read) {
-	        /* Read the page 800 value using opcode 0x12 */
-		ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
-		                                  data);
-	} else {
-	        /* Write the page 800 value using opcode 0x12 */
-		ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
-		                                   *data);
-	}
-
-	if (ret_val) {
-		DEBUGOUT("Could not access data value from page 800\n");
-		goto out;
-	}
-
-	/*
-	 * Restore 769_17.2 to its original value
-	 * Set page 769
-	 */
-	e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
-	                         (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
-
-	/* Clear 769_17.2 */
-	ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
-	if (ret_val) {
-		DEBUGOUT("Could not clear PHY page 769 bit 2\n");
-		goto out;
-	}
+	if (!page_set)
+		ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
 
 out:
 	return ret_val;
@@ -3248,11 +3497,12 @@
  *  semaphore before exiting.
  **/
 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
-                                   bool locked)
+				   bool locked, bool page_set)
 {
 	s32 ret_val;
 	u16 page = BM_PHY_REG_PAGE(offset);
 	u16 reg = BM_PHY_REG_NUM(offset);
+	u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
 
 	DEBUGFUNC("__e1000_read_phy_reg_hv");
 
@@ -3264,39 +3514,38 @@
 
 	/* Page 800 works differently than the rest so it has its own func */
 	if (page == BM_WUC_PAGE) {
-		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
-		                                         data, TRUE);
+		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
+							 TRUE, page_set);
 		goto out;
 	}
 
 	if (page > 0 && page < HV_INTC_FC_PAGE_START) {
 		ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
-		                                         data, TRUE);
+							 data, TRUE);
 		goto out;
 	}
 
-	hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
-
-	if (page == HV_INTC_FC_PAGE_START)
-		page = 0;
-
-	if (reg > MAX_PHY_MULTI_PAGE_REG) {
-		u32 phy_addr = hw->phy.addr;
-
-		hw->phy.addr = 1;
-
-		/* Page is shifted left, PHY expects (page x 32) */
-		ret_val = e1000_write_phy_reg_mdic(hw,
-					     IGP01E1000_PHY_PAGE_SELECT,
-					     (page << IGP_PAGE_SHIFT));
-		hw->phy.addr = phy_addr;
-
-		if (ret_val)
-			goto out;
+	if (!page_set) {
+		if (page == HV_INTC_FC_PAGE_START)
+			page = 0;
+
+		if (reg > MAX_PHY_MULTI_PAGE_REG) {
+			/* Page is shifted left, PHY expects (page x 32) */
+			ret_val = e1000_set_page_igp(hw,
+						     (page << IGP_PAGE_SHIFT));
+
+			hw->phy.addr = phy_addr;
+
+			if (ret_val)
+				goto out;
+		}
 	}
 
+	DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
+		  page << IGP_PAGE_SHIFT, reg);
+
 	ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
-	                                  data);
+					  data);
 out:
 	if (!locked)
 		hw->phy.ops.release(hw);
@@ -3316,7 +3565,7 @@
  **/
 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
 {
-	return __e1000_read_phy_reg_hv(hw, offset, data, FALSE);
+	return __e1000_read_phy_reg_hv(hw, offset, data, FALSE, FALSE);
 }
 
 /**
@@ -3330,7 +3579,21 @@
  **/
 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
 {
-	return __e1000_read_phy_reg_hv(hw, offset, data, TRUE);
+	return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, FALSE);
+}
+
+/**
+ *  e1000_read_phy_reg_page_hv - Read HV PHY register
+ *  @hw: pointer to the HW structure
+ *  @offset: register offset to write to
+ *  @data: data to write at register offset
+ *
+ *  Reads the PHY register at offset and stores the retrieved information
+ *  in data.  Assumes semaphore already acquired and page already set.
+ **/
+s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
+{
+	return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, true);
 }
 
 /**
@@ -3344,11 +3607,12 @@
  *  at the offset.  Release any acquired semaphores before exiting.
  **/
 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
-                                    bool locked)
+				    bool locked, bool page_set)
 {
 	s32 ret_val;
 	u16 page = BM_PHY_REG_PAGE(offset);
 	u16 reg = BM_PHY_REG_NUM(offset);
+	u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
 
 	DEBUGFUNC("__e1000_write_phy_reg_hv");
 
@@ -3360,55 +3624,55 @@
 
 	/* Page 800 works differently than the rest so it has its own func */
 	if (page == BM_WUC_PAGE) {
-		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
-		                                         &data, FALSE);
+		ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
+							 FALSE, page_set);
 		goto out;
 	}
 
 	if (page > 0 && page < HV_INTC_FC_PAGE_START) {
 		ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
-		                                         &data, FALSE);
+							 &data, FALSE);
 		goto out;
 	}
 
-	hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
-
-	if (page == HV_INTC_FC_PAGE_START)
-		page = 0;
-
-	/*
-	 * Workaround MDIO accesses being disabled after entering IEEE Power
-	 * Down (whenever bit 11 of the PHY Control register is set)
-	 */
-	if ((hw->phy.type == e1000_phy_82578) &&
-	    (hw->phy.revision >= 1) &&
-	    (hw->phy.addr == 2) &&
-	    ((MAX_PHY_REG_ADDRESS & reg) == 0) &&
-	    (data & (1 << 11))) {
-		u16 data2 = 0x7EFF;
-		ret_val = e1000_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3,
-		                                         &data2, FALSE);
-		if (ret_val)
-			goto out;
+	if (!page_set) {
+		if (page == HV_INTC_FC_PAGE_START)
+			page = 0;
+
+		/*
+		 * Workaround MDIO accesses being disabled after entering IEEE
+		 * Power Down (when bit 11 of the PHY Control register is set)
+		 */
+		if ((hw->phy.type == e1000_phy_82578) &&
+		    (hw->phy.revision >= 1) &&
+		    (hw->phy.addr == 2) &&
+		    ((MAX_PHY_REG_ADDRESS & reg) == 0) &&
+		    (data & (1 << 11))) {
+			u16 data2 = 0x7EFF;
+			ret_val = e1000_access_phy_debug_regs_hv(hw,
+								 (1 << 6) | 0x3,
+								 &data2, FALSE);
+			if (ret_val)
+				goto out;
+		}
+
+		if (reg > MAX_PHY_MULTI_PAGE_REG) {
+			/* Page is shifted left, PHY expects (page x 32) */
+			ret_val = e1000_set_page_igp(hw,
+						     (page << IGP_PAGE_SHIFT));
+
+			hw->phy.addr = phy_addr;
+
+			if (ret_val)
+				goto out;
+		}
 	}
 
-	if (reg > MAX_PHY_MULTI_PAGE_REG) {
-		u32 phy_addr = hw->phy.addr;
-
-		hw->phy.addr = 1;
-
-		/* Page is shifted left, PHY expects (page x 32) */
-		ret_val = e1000_write_phy_reg_mdic(hw,
-					     IGP01E1000_PHY_PAGE_SELECT,
-					     (page << IGP_PAGE_SHIFT));
-		hw->phy.addr = phy_addr;
-
-		if (ret_val)
-			goto out;
-	}
+	DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
+		  page << IGP_PAGE_SHIFT, reg);
 
 	ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
-	                                  data);
+					   data);
 
 out:
 	if (!locked)
@@ -3428,7 +3692,7 @@
  **/
 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
 {
-	return __e1000_write_phy_reg_hv(hw, offset, data, FALSE);
+	return __e1000_write_phy_reg_hv(hw, offset, data, FALSE, FALSE);
 }
 
 /**
@@ -3442,7 +3706,21 @@
  **/
 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
 {
-	return __e1000_write_phy_reg_hv(hw, offset, data, TRUE);
+	return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, FALSE);
+}
+
+/**
+ *  e1000_write_phy_reg_page_hv - Write HV PHY register
+ *  @hw: pointer to the HW structure
+ *  @offset: register offset to write to
+ *  @data: data to write at register offset
+ *
+ *  Writes the data to PHY register at the offset.  Assumes semaphore
+ *  already acquired and page already set.
+ **/
+s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
+{
+	return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, true);
 }
 
 /**
@@ -3464,14 +3742,15 @@
  *  @hw: pointer to the HW structure
  *  @offset: register offset to be read or written
  *  @data: pointer to the data to be read or written
- *  @read: determines if operation is read or written
+ *  @read: determines if operation is read or write
  *
  *  Reads the PHY register at offset and stores the retreived information
  *  in data.  Assumes semaphore already acquired.  Note that the procedure
- *  to read these regs uses the address port and data port to read/write.
+ *  to access these regs uses the address port and data port to read/write.
+ *  These accesses done with PHY address 2 and without using pages.
  **/
 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
-                                          u16 *data, bool read)
+					  u16 *data, bool read)
 {
 	s32 ret_val;
 	u32 addr_reg = 0;
@@ -3481,7 +3760,7 @@
 
 	/* This takes care of the difference with desktop vs mobile phy */
 	addr_reg = (hw->phy.type == e1000_phy_82578) ?
-	           I82578_ADDR_REG : I82577_ADDR_REG;
+		   I82578_ADDR_REG : I82577_ADDR_REG;
 	data_reg = addr_reg + 1;
 
 	/* All operations in this function are phy address 2 */
@@ -3490,7 +3769,7 @@
 	/* masking with 0x3F to remove the page from offset */
 	ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
 	if (ret_val) {
-		DEBUGOUT("Could not write PHY the HV address register\n");
+		DEBUGOUT("Could not write the Address Offset port register\n");
 		goto out;
 	}
 
@@ -3501,7 +3780,7 @@
 		ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data);
 
 	if (ret_val) {
-		DEBUGOUT("Could not read data value from HV data register\n");
+		DEBUGOUT("Could not access the Data port register\n");
 		goto out;
 	}
 
@@ -3540,26 +3819,24 @@
 	if (ret_val)
 		goto out;
 
-	data &= BM_CS_STATUS_LINK_UP |
-	        BM_CS_STATUS_RESOLVED |
-	        BM_CS_STATUS_SPEED_MASK;
-
-	if (data != (BM_CS_STATUS_LINK_UP |
-	             BM_CS_STATUS_RESOLVED |
-	             BM_CS_STATUS_SPEED_1000))
+	data &= BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
+		BM_CS_STATUS_SPEED_MASK;
+
+	if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
+		     BM_CS_STATUS_SPEED_1000))
 		goto out;
 
 	msec_delay(200);
 
 	/* flush the packets in the fifo buffer */
 	ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
-	                                HV_MUX_DATA_CTRL_GEN_TO_MAC |
-	                                HV_MUX_DATA_CTRL_FORCE_SPEED);
+					HV_MUX_DATA_CTRL_GEN_TO_MAC |
+					HV_MUX_DATA_CTRL_FORCE_SPEED);
 	if (ret_val)
 		goto out;
 
 	ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
-	                                HV_MUX_DATA_CTRL_GEN_TO_MAC);
+					HV_MUX_DATA_CTRL_GEN_TO_MAC);
 
 out:
 	return ret_val;
@@ -3585,8 +3862,8 @@
 
 	if (!ret_val)
 		phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
-		                      ? e1000_rev_polarity_reversed
-		                      : e1000_rev_polarity_normal;
+				      ? e1000_rev_polarity_reversed
+				      : e1000_rev_polarity_normal;
 
 	return ret_val;
 }
@@ -3621,10 +3898,8 @@
 	if (phy->autoneg_wait_to_complete) {
 		DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
 
-		ret_val = e1000_phy_has_link_generic(hw,
-		                                     PHY_FORCE_LIMIT,
-		                                     100000,
-		                                     &link);
+		ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
+						     100000, &link);
 		if (ret_val)
 			goto out;
 
@@ -3632,10 +3907,8 @@
 			DEBUGOUT("Link taking longer than expected.\n");
 
 		/* Try once more */
-		ret_val = e1000_phy_has_link_generic(hw,
-		                                     PHY_FORCE_LIMIT,
-		                                     100000,
-		                                     &link);
+		ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
+						     100000, &link);
 		if (ret_val)
 			goto out;
 	}
@@ -3695,12 +3968,12 @@
 			goto out;
 
 		phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
-		                ? e1000_1000t_rx_status_ok
-		                : e1000_1000t_rx_status_not_ok;
+				? e1000_1000t_rx_status_ok
+				: e1000_1000t_rx_status_not_ok;
 
 		phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
-		                 ? e1000_1000t_rx_status_ok
-		                 : e1000_1000t_rx_status_not_ok;
+				 ? e1000_1000t_rx_status_ok
+				 : e1000_1000t_rx_status_not_ok;
 	} else {
 		phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
 		phy->local_rx = e1000_1000t_rx_status_undefined;
@@ -3731,7 +4004,7 @@
 		goto out;
 
 	length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
-	         I82577_DSTATUS_CABLE_LENGTH_SHIFT;
+		 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
 
 	if (length == E1000_CABLE_LENGTH_UNDEFINED)
 		ret_val = -E1000_ERR_PHY;
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/e1000/e1000_phy.h
--- a/head/sys/dev/e1000/e1000_phy.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/e1000/e1000_phy.h	Thu Dec 15 12:59:38 2011 +0200
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD: head/sys/dev/e1000/e1000_phy.h 228386 2011-12-10 06:55:02Z jfv $*/
 
 #ifndef _E1000_PHY_H_
 #define _E1000_PHY_H_
@@ -40,6 +40,7 @@
 void e1000_null_phy_generic(struct e1000_hw *hw);
 s32  e1000_null_lplu_state(struct e1000_hw *hw, bool active);
 s32  e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data);
+s32  e1000_null_set_page(struct e1000_hw *hw, u16 data);
 s32  e1000_check_downshift_generic(struct e1000_hw *hw);
 s32  e1000_check_polarity_m88(struct e1000_hw *hw);
 s32  e1000_check_polarity_igp(struct e1000_hw *hw);
@@ -67,6 +68,7 @@
 s32  e1000_phy_reset_dsp_generic(struct e1000_hw *hw);
 s32  e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data);
 s32  e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data);
+s32  e1000_set_page_igp(struct e1000_hw *hw, u16 page);
 s32  e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
 s32  e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data);
 s32  e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
@@ -80,12 +82,14 @@
 s32  e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
 s32  e1000_phy_reset_dsp(struct e1000_hw *hw);
 s32  e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
-                                u32 usec_interval, bool *success);
+				u32 usec_interval, bool *success);
 s32  e1000_phy_init_script_igp3(struct e1000_hw *hw);
 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id);
 s32  e1000_determine_phy_address(struct e1000_hw *hw);
 s32  e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
 s32  e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
+s32  e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);
+s32  e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);
 s32  e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
 s32  e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
 void e1000_power_up_phy_copper(struct e1000_hw *hw);
@@ -94,10 +98,14 @@
 s32  e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
 s32  e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
 s32  e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
+s32  e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data);
+s32  e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data);
 s32  e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
 s32  e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data);
+s32  e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data);
 s32  e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
 s32  e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data);
+s32  e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data);
 s32  e1000_link_stall_workaround_hv(struct e1000_hw *hw);
 s32  e1000_copper_link_setup_82577(struct e1000_hw *hw);
 s32  e1000_check_polarity_82577(struct e1000_hw *hw);
@@ -105,34 +113,34 @@
 s32  e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
 s32  e1000_get_cable_length_82577(struct e1000_hw *hw);
 
-#define E1000_MAX_PHY_ADDR                4
+#define E1000_MAX_PHY_ADDR		8
 
 /* IGP01E1000 Specific Registers */
-#define IGP01E1000_PHY_PORT_CONFIG        0x10 /* Port Config */
-#define IGP01E1000_PHY_PORT_STATUS        0x11 /* Status */
-#define IGP01E1000_PHY_PORT_CTRL          0x12 /* Control */
-#define IGP01E1000_PHY_LINK_HEALTH        0x13 /* PHY Link Health */
-#define IGP01E1000_GMII_FIFO              0x14 /* GMII FIFO */
-#define IGP01E1000_PHY_CHANNEL_QUALITY    0x15 /* PHY Channel Quality */
-#define IGP02E1000_PHY_POWER_MGMT         0x19 /* Power Management */
-#define IGP01E1000_PHY_PAGE_SELECT        0x1F /* Page Select */
-#define BM_PHY_PAGE_SELECT                22   /* Page Select for BM */
-#define IGP_PAGE_SHIFT                    5
-#define PHY_REG_MASK                      0x1F
+#define IGP01E1000_PHY_PORT_CONFIG	0x10 /* Port Config */
+#define IGP01E1000_PHY_PORT_STATUS	0x11 /* Status */
+#define IGP01E1000_PHY_PORT_CTRL	0x12 /* Control */
+#define IGP01E1000_PHY_LINK_HEALTH	0x13 /* PHY Link Health */
+#define IGP01E1000_GMII_FIFO		0x14 /* GMII FIFO */
+#define IGP01E1000_PHY_CHANNEL_QUALITY	0x15 /* PHY Channel Quality */
+#define IGP02E1000_PHY_POWER_MGMT	0x19 /* Power Management */
+#define IGP01E1000_PHY_PAGE_SELECT	0x1F /* Page Select */
+#define BM_PHY_PAGE_SELECT		22   /* Page Select for BM */
+#define IGP_PAGE_SHIFT			5
+#define PHY_REG_MASK			0x1F
 
 /* BM/HV Specific Registers */
-#define BM_PORT_CTRL_PAGE                 769
-#define BM_PORT_GEN_CFG_REG               PHY_REG(BM_PORT_CTRL_PAGE, 17)
-#define BM_PCIE_PAGE                      770
-#define BM_WUC_PAGE                       800
-#define BM_WUC_ADDRESS_OPCODE             0x11
-#define BM_WUC_DATA_OPCODE                0x12
-#define BM_WUC_ENABLE_PAGE                BM_PORT_CTRL_PAGE
-#define BM_WUC_ENABLE_REG                 17
-#define BM_WUC_ENABLE_BIT                 (1 << 2)
-#define BM_WUC_HOST_WU_BIT                (1 << 4)
+#define BM_PORT_CTRL_PAGE		769
+#define BM_PCIE_PAGE			770
+#define BM_WUC_PAGE			800
+#define BM_WUC_ADDRESS_OPCODE		0x11
+#define BM_WUC_DATA_OPCODE		0x12
+#define BM_WUC_ENABLE_PAGE		BM_PORT_CTRL_PAGE
+#define BM_WUC_ENABLE_REG		17
+#define BM_WUC_ENABLE_BIT		(1 << 2)
+#define BM_WUC_HOST_WU_BIT		(1 << 4)
+#define BM_WUC_ME_WU_BIT		(1 << 5)
 
-#define PHY_UPPER_SHIFT                   21
+#define PHY_UPPER_SHIFT			21
 #define BM_PHY_REG(page, reg) \
 	(((reg) & MAX_PHY_REG_ADDRESS) |\
 	 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
@@ -144,132 +152,156 @@
 	 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
 		~MAX_PHY_REG_ADDRESS)))
 
-#define HV_INTC_FC_PAGE_START             768
-#define I82578_ADDR_REG                   29
-#define I82577_ADDR_REG                   16
-#define I82577_CFG_REG                    22
-#define I82577_CFG_ASSERT_CRS_ON_TX       (1 << 15)
-#define I82577_CFG_ENABLE_DOWNSHIFT       (3 << 10) /* auto downshift 100/10 */
-#define I82577_CTRL_REG                   23
+#define HV_INTC_FC_PAGE_START		768
+#define I82578_ADDR_REG			29
+#define I82577_ADDR_REG			16
+#define I82577_CFG_REG			22
+#define I82577_CFG_ASSERT_CRS_ON_TX	(1 << 15)
+#define I82577_CFG_ENABLE_DOWNSHIFT	(3 << 10) /* auto downshift 100/10 */
+#define I82577_CTRL_REG			23
 
 /* 82577 specific PHY registers */
-#define I82577_PHY_CTRL_2            18
-#define I82577_PHY_LBK_CTRL          19
-#define I82577_PHY_STATUS_2          26
-#define I82577_PHY_DIAG_STATUS       31
+#define I82577_PHY_CTRL_2		18
+#define I82577_PHY_LBK_CTRL		19
+#define I82577_PHY_STATUS_2		26
+#define I82577_PHY_DIAG_STATUS		31
 
 /* I82577 PHY Status 2 */
-#define I82577_PHY_STATUS2_REV_POLARITY   0x0400
-#define I82577_PHY_STATUS2_MDIX           0x0800
-#define I82577_PHY_STATUS2_SPEED_MASK     0x0300
-#define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
-#define I82577_PHY_STATUS2_SPEED_100MBPS  0x0100
+#define I82577_PHY_STATUS2_REV_POLARITY		0x0400
+#define I82577_PHY_STATUS2_MDIX			0x0800
+#define I82577_PHY_STATUS2_SPEED_MASK		0x0300
+#define I82577_PHY_STATUS2_SPEED_1000MBPS	0x0200
+#define I82577_PHY_STATUS2_SPEED_100MBPS	0x0100
 
 /* I82577 PHY Control 2 */
-#define I82577_PHY_CTRL2_AUTO_MDIX        0x0400
-#define I82577_PHY_CTRL2_FORCE_MDI_MDIX   0x0200
+#define I82577_PHY_CTRL2_AUTO_MDIX		0x0400
+#define I82577_PHY_CTRL2_FORCE_MDI_MDIX		0x0200
 
 /* I82577 PHY Diagnostics Status */
-#define I82577_DSTATUS_CABLE_LENGTH       0x03FC
-#define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
+#define I82577_DSTATUS_CABLE_LENGTH		0x03FC
+#define I82577_DSTATUS_CABLE_LENGTH_SHIFT	2
 
 /* 82580 PHY Power Management */
-#define E1000_82580_PHY_POWER_MGMT        0xE14
-#define E1000_82580_PM_SPD                0x0001 /* Smart Power Down */
-#define E1000_82580_PM_D0_LPLU            0x0002 /* For D0a states */
-#define E1000_82580_PM_D3_LPLU            0x0004 /* For all other states */
+#define E1000_82580_PHY_POWER_MGMT	0xE14
+#define E1000_82580_PM_SPD		0x0001 /* Smart Power Down */
+#define E1000_82580_PM_D0_LPLU		0x0002 /* For D0a states */
+#define E1000_82580_PM_D3_LPLU		0x0004 /* For all other states */
 
 /* BM PHY Copper Specific Control 1 */
-#define BM_CS_CTRL1                       16
-#define BM_CS_CTRL1_ENERGY_DETECT         0x0300 /* Enable Energy Detect */
+#define BM_CS_CTRL1			16
+#define BM_CS_CTRL1_ENERGY_DETECT	0x0300 /* Enable Energy Detect */
 
 /* BM PHY Copper Specific Status */
-#define BM_CS_STATUS                      17
-#define BM_CS_STATUS_ENERGY_DETECT        0x0010 /* Energy Detect Status */
-#define BM_CS_STATUS_LINK_UP              0x0400
-#define BM_CS_STATUS_RESOLVED             0x0800
-#define BM_CS_STATUS_SPEED_MASK           0xC000
-#define BM_CS_STATUS_SPEED_1000           0x8000
+#define BM_CS_STATUS			17
+#define BM_CS_STATUS_ENERGY_DETECT	0x0010 /* Energy Detect Status */
+#define BM_CS_STATUS_LINK_UP		0x0400
+#define BM_CS_STATUS_RESOLVED		0x0800
+#define BM_CS_STATUS_SPEED_MASK		0xC000
+#define BM_CS_STATUS_SPEED_1000		0x8000
 
 /* 82577 Mobile Phy Status Register */
-#define HV_M_STATUS                       26
-#define HV_M_STATUS_AUTONEG_COMPLETE      0x1000
-#define HV_M_STATUS_SPEED_MASK            0x0300
-#define HV_M_STATUS_SPEED_1000            0x0200
-#define HV_M_STATUS_LINK_UP               0x0040
+#define HV_M_STATUS			26
+#define HV_M_STATUS_AUTONEG_COMPLETE	0x1000
+#define HV_M_STATUS_SPEED_MASK		0x0300
+#define HV_M_STATUS_SPEED_1000		0x0200
+#define HV_M_STATUS_LINK_UP		0x0040
 
-#define IGP01E1000_PHY_PCS_INIT_REG       0x00B4
-#define IGP01E1000_PHY_POLARITY_MASK      0x0078
+#define IGP01E1000_PHY_PCS_INIT_REG	0x00B4
+#define IGP01E1000_PHY_POLARITY_MASK	0x0078
 
-#define IGP01E1000_PSCR_AUTO_MDIX         0x1000
-#define IGP01E1000_PSCR_FORCE_MDI_MDIX    0x2000 /* 0=MDI, 1=MDIX */
+#define IGP01E1000_PSCR_AUTO_MDIX	0x1000
+#define IGP01E1000_PSCR_FORCE_MDI_MDIX	0x2000 /* 0=MDI, 1=MDIX */
 
-#define IGP01E1000_PSCFR_SMART_SPEED      0x0080
+#define IGP01E1000_PSCFR_SMART_SPEED	0x0080
 
 /* Enable flexible speed on link-up */
-#define IGP01E1000_GMII_FLEX_SPD          0x0010
-#define IGP01E1000_GMII_SPD               0x0020 /* Enable SPD */
+#define IGP01E1000_GMII_FLEX_SPD	0x0010
+#define IGP01E1000_GMII_SPD		0x0020 /* Enable SPD */
 
-#define IGP02E1000_PM_SPD                 0x0001 /* Smart Power Down */
-#define IGP02E1000_PM_D0_LPLU             0x0002 /* For D0a states */
-#define IGP02E1000_PM_D3_LPLU             0x0004 /* For all other states */
+#define IGP02E1000_PM_SPD		0x0001 /* Smart Power Down */
+#define IGP02E1000_PM_D0_LPLU		0x0002 /* For D0a states */
+#define IGP02E1000_PM_D3_LPLU		0x0004 /* For all other states */
 
-#define IGP01E1000_PLHR_SS_DOWNGRADE      0x8000
+#define IGP01E1000_PLHR_SS_DOWNGRADE	0x8000
 
-#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
-#define IGP01E1000_PSSR_MDIX              0x0800
-#define IGP01E1000_PSSR_SPEED_MASK        0xC000
-#define IGP01E1000_PSSR_SPEED_1000MBPS    0xC000
+#define IGP01E1000_PSSR_POLARITY_REVERSED	0x0002
+#define IGP01E1000_PSSR_MDIX		0x0800
+#define IGP01E1000_PSSR_SPEED_MASK	0xC000
+#define IGP01E1000_PSSR_SPEED_1000MBPS	0xC000
 
-#define IGP02E1000_PHY_CHANNEL_NUM        4
-#define IGP02E1000_PHY_AGC_A              0x11B1
-#define IGP02E1000_PHY_AGC_B              0x12B1
-#define IGP02E1000_PHY_AGC_C              0x14B1
-#define IGP02E1000_PHY_AGC_D              0x18B1
+#define IGP02E1000_PHY_CHANNEL_NUM	4
+#define IGP02E1000_PHY_AGC_A		0x11B1
+#define IGP02E1000_PHY_AGC_B		0x12B1
+#define IGP02E1000_PHY_AGC_C		0x14B1
+#define IGP02E1000_PHY_AGC_D		0x18B1
 
-#define IGP02E1000_AGC_LENGTH_SHIFT       9   /* Course - 15:13, Fine - 12:9 */
-#define IGP02E1000_AGC_LENGTH_MASK        0x7F
-#define IGP02E1000_AGC_RANGE              15
+#define IGP02E1000_AGC_LENGTH_SHIFT	9   /* Course - 15:13, Fine - 12:9 */
+#define IGP02E1000_AGC_LENGTH_MASK	0x7F
+#define IGP02E1000_AGC_RANGE		15
 
-#define IGP03E1000_PHY_MISC_CTRL          0x1B
-#define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET  0x1000 /* Manually Set Duplex */
+#define IGP03E1000_PHY_MISC_CTRL	0x1B
+#define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET	0x1000 /* Manually Set Duplex */
 
-#define E1000_CABLE_LENGTH_UNDEFINED      0xFF
+#define E1000_CABLE_LENGTH_UNDEFINED	0xFF
 
-#define E1000_KMRNCTRLSTA_OFFSET          0x001F0000
-#define E1000_KMRNCTRLSTA_OFFSET_SHIFT    16
-#define E1000_KMRNCTRLSTA_REN             0x00200000
-#define E1000_KMRNCTRLSTA_CTRL_OFFSET     0x1    /* Kumeran Control */
-#define E1000_KMRNCTRLSTA_DIAG_OFFSET     0x3    /* Kumeran Diagnostic */
-#define E1000_KMRNCTRLSTA_TIMEOUTS        0x4    /* Kumeran Timeouts */
-#define E1000_KMRNCTRLSTA_INBAND_PARAM    0x9    /* Kumeran InBand Parameters */
-#define E1000_KMRNCTRLSTA_IBIST_DISABLE   0x0200 /* Kumeran IBIST Disable */
-#define E1000_KMRNCTRLSTA_DIAG_NELPBK     0x1000 /* Nearend Loopback mode */
-#define E1000_KMRNCTRLSTA_K1_CONFIG        0x7
-#define E1000_KMRNCTRLSTA_K1_ENABLE        0x0002
-#define E1000_KMRNCTRLSTA_HD_CTRL         0x10   /* Kumeran HD Control */
+#define E1000_KMRNCTRLSTA_OFFSET	0x001F0000
+#define E1000_KMRNCTRLSTA_OFFSET_SHIFT	16
+#define E1000_KMRNCTRLSTA_REN		0x00200000
+#define E1000_KMRNCTRLSTA_CTRL_OFFSET	0x1    /* Kumeran Control */
+#define E1000_KMRNCTRLSTA_DIAG_OFFSET	0x3    /* Kumeran Diagnostic */
+#define E1000_KMRNCTRLSTA_TIMEOUTS	0x4    /* Kumeran Timeouts */
+#define E1000_KMRNCTRLSTA_INBAND_PARAM	0x9    /* Kumeran InBand Parameters */
+#define E1000_KMRNCTRLSTA_IBIST_DISABLE	0x0200 /* Kumeran IBIST Disable */
+#define E1000_KMRNCTRLSTA_DIAG_NELPBK	0x1000 /* Nearend Loopback mode */
+#define E1000_KMRNCTRLSTA_K1_CONFIG	0x7
+#define E1000_KMRNCTRLSTA_K1_ENABLE	0x0002
+#define E1000_KMRNCTRLSTA_HD_CTRL	0x10   /* Kumeran HD Control */
 
-#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
-#define IFE_PHY_SPECIAL_CONTROL     0x11 /* 100BaseTx PHY Special Control */
-#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
-#define IFE_PHY_MDIX_CONTROL        0x1C /* MDI/MDI-X Control */
+#define IFE_PHY_EXTENDED_STATUS_CONTROL	0x10
+#define IFE_PHY_SPECIAL_CONTROL		0x11 /* 100BaseTx PHY Special Control */
+#define IFE_PHY_SPECIAL_CONTROL_LED	0x1B /* PHY Special and LED Control */
+#define IFE_PHY_MDIX_CONTROL		0x1C /* MDI/MDI-X Control */
 
 /* IFE PHY Extended Status Control */
-#define IFE_PESC_POLARITY_REVERSED    0x0100
+#define IFE_PESC_POLARITY_REVERSED	0x0100
 
 /* IFE PHY Special Control */
-#define IFE_PSC_AUTO_POLARITY_DISABLE      0x0010
-#define IFE_PSC_FORCE_POLARITY             0x0020
-#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100
+#define IFE_PSC_AUTO_POLARITY_DISABLE	0x0010
+#define IFE_PSC_FORCE_POLARITY		0x0020
+#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN	0x0100
 
 /* IFE PHY Special Control and LED Control */
-#define IFE_PSCL_PROBE_MODE            0x0020
-#define IFE_PSCL_PROBE_LEDS_OFF        0x0006 /* Force LEDs 0 and 2 off */
-#define IFE_PSCL_PROBE_LEDS_ON         0x0007 /* Force LEDs 0 and 2 on */
+#define IFE_PSCL_PROBE_MODE		0x0020
+#define IFE_PSCL_PROBE_LEDS_OFF		0x0006 /* Force LEDs 0 and 2 off */
+#define IFE_PSCL_PROBE_LEDS_ON		0x0007 /* Force LEDs 0 and 2 on */
 
 /* IFE PHY MDIX Control */
-#define IFE_PMC_MDIX_STATUS      0x0020 /* 1=MDI-X, 0=MDI */
-#define IFE_PMC_FORCE_MDIX       0x0040 /* 1=force MDI-X, 0=force MDI */
-#define IFE_PMC_AUTO_MDIX        0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
+#define IFE_PMC_MDIX_STATUS		0x0020 /* 1=MDI-X, 0=MDI */
+#define IFE_PMC_FORCE_MDIX		0x0040 /* 1=force MDI-X, 0=force MDI */
+#define IFE_PMC_AUTO_MDIX		0x0080 /* 1=enable auto, 0=disable */
+
+/* SFP modules ID memory locations */
+#define E1000_SFF_IDENTIFIER_OFFSET	0x00
+#define E1000_SFF_IDENTIFIER_SFF	0x02
+#define E1000_SFF_IDENTIFIER_SFP	0x03
+
+#define E1000_SFF_ETH_FLAGS_OFFSET	0x06
+/* Flags for SFP modules compatible with ETH up to 1Gb */
+struct sfp_e1000_flags {
+	u8 e1000_base_sx:1;
+	u8 e1000_base_lx:1;
+	u8 e1000_base_cx:1;
+	u8 e1000_base_t:1;
+	u8 e100_base_lx:1;
+	u8 e100_base_fx:1;
+	u8 e10_base_bx10:1;
+	u8 e10_base_px:1;
+};
+
+/* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
+#define E1000_SFF_VENDOR_OUI_TYCO	0x00407600
+#define E1000_SFF_VENDOR_OUI_FTL	0x00906500
+#define E1000_SFF_VENDOR_OUI_AVAGO	0x00176A00
+#define E1000_SFF_VENDOR_OUI_INTEL	0x001B2100
 
 #endif
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/e1000/e1000_regs.h
--- a/head/sys/dev/e1000/e1000_regs.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/e1000/e1000_regs.h	Thu Dec 15 12:59:38 2011 +0200
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,109 +30,119 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD: head/sys/dev/e1000/e1000_regs.h 228386 2011-12-10 06:55:02Z jfv $*/
 
 #ifndef _E1000_REGS_H_
 #define _E1000_REGS_H_
 
-#define E1000_CTRL     0x00000  /* Device Control - RW */
-#define E1000_CTRL_DUP 0x00004  /* Device Control Duplicate (Shadow) - RW */
-#define E1000_STATUS   0x00008  /* Device Status - RO */
-#define E1000_EECD     0x00010  /* EEPROM/Flash Control - RW */
-#define E1000_EERD     0x00014  /* EEPROM Read - RW */
-#define E1000_CTRL_EXT 0x00018  /* Extended Device Control - RW */
-#define E1000_FLA      0x0001C  /* Flash Access - RW */
-#define E1000_MDIC     0x00020  /* MDI Control - RW */
-#define E1000_MDICNFG  0x00E04  /* MDI Config - RW */
-#define E1000_REGISTER_SET_SIZE        0x20000 /* CSR Size */
-#define E1000_EEPROM_INIT_CTRL_WORD_2  0x0F /* EEPROM Init Ctrl Word 2 */
-#define E1000_BARCTRL                  0x5BBC /* BAR ctrl reg */
-#define E1000_BARCTRL_FLSIZE           0x0700 /* BAR ctrl Flsize */
-#define E1000_BARCTRL_CSRSIZE          0x2000 /* BAR ctrl CSR size */
-#define E1000_SCTL     0x00024  /* SerDes Control - RW */
-#define E1000_FCAL     0x00028  /* Flow Control Address Low - RW */
-#define E1000_FCAH     0x0002C  /* Flow Control Address High -RW */
-#define E1000_FEXT     0x0002C  /* Future Extended - RW */
-#define E1000_FEXTNVM4 0x00024  /* Future Extended NVM 4 - RW */
-#define E1000_FEXTNVM  0x00028  /* Future Extended NVM - RW */
-#define E1000_FCT      0x00030  /* Flow Control Type - RW */
-#define E1000_CONNSW   0x00034  /* Copper/Fiber switch control - RW */
-#define E1000_VET      0x00038  /* VLAN Ether Type - RW */
-#define E1000_ICR      0x000C0  /* Interrupt Cause Read - R/clr */
-#define E1000_ITR      0x000C4  /* Interrupt Throttling Rate - RW */
-#define E1000_ICS      0x000C8  /* Interrupt Cause Set - WO */
-#define E1000_IMS      0x000D0  /* Interrupt Mask Set - RW */
-#define E1000_IMC      0x000D8  /* Interrupt Mask Clear - WO */
-#define E1000_IAM      0x000E0  /* Interrupt Acknowledge Auto Mask */
-#define E1000_IVAR     0x000E4  /* Interrupt Vector Allocation Register - RW */
-#define E1000_SVCR     0x000F0
-#define E1000_SVT      0x000F4
-#define E1000_RCTL     0x00100  /* Rx Control - RW */
-#define E1000_FCTTV    0x00170  /* Flow Control Transmit Timer Value - RW */
-#define E1000_TXCW     0x00178  /* Tx Configuration Word - RW */
-#define E1000_RXCW     0x00180  /* Rx Configuration Word - RO */
-#define E1000_PBA_ECC  0x01100  /* PBA ECC Register */
-#define E1000_EICR     0x01580  /* Ext. Interrupt Cause Read - R/clr */
-#define E1000_EITR(_n) (0x01680 + (0x4 * (_n)))
-#define E1000_EICS     0x01520  /* Ext. Interrupt Cause Set - W0 */
-#define E1000_EIMS     0x01524  /* Ext. Interrupt Mask Set/Read - RW */
-#define E1000_EIMC     0x01528  /* Ext. Interrupt Mask Clear - WO */
-#define E1000_EIAC     0x0152C  /* Ext. Interrupt Auto Clear - RW */
-#define E1000_EIAM     0x01530  /* Ext. Interrupt Ack Auto Clear Mask - RW */
-#define E1000_GPIE     0x01514  /* General Purpose Interrupt Enable - RW */
-#define E1000_IVAR0    0x01700  /* Interrupt Vector Allocation (array) - RW */
-#define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
-#define E1000_TCTL     0x00400  /* Tx Control - RW */
-#define E1000_TCTL_EXT 0x00404  /* Extended Tx Control - RW */
-#define E1000_TIPG     0x00410  /* Tx Inter-packet gap -RW */
-#define E1000_TBT      0x00448  /* Tx Burst Timer - RW */
-#define E1000_AIT      0x00458  /* Adaptive Interframe Spacing Throttle - RW */
-#define E1000_LEDCTL   0x00E00  /* LED Control - RW */
-#define E1000_EXTCNF_CTRL  0x00F00  /* Extended Configuration Control */
-#define E1000_EXTCNF_SIZE  0x00F08  /* Extended Configuration Size */
-#define E1000_PHY_CTRL     0x00F10  /* PHY Control Register in CSR */
-#define E1000_POEMB        E1000_PHY_CTRL /* PHY OEM Bits */
-#define E1000_PBA      0x01000  /* Packet Buffer Allocation - RW */
-#define E1000_PBS      0x01008  /* Packet Buffer Size */
-#define E1000_EEMNGCTL 0x01010  /* MNG EEprom Control */
-#define E1000_EEARBC   0x01024  /* EEPROM Auto Read Bus Control */
-#define E1000_FLASHT   0x01028  /* FLASH Timer Register */
-#define E1000_EEWR     0x0102C  /* EEPROM Write Register - RW */
-#define E1000_FLSWCTL  0x01030  /* FLASH control register */
-#define E1000_FLSWDATA 0x01034  /* FLASH data register */
-#define E1000_FLSWCNT  0x01038  /* FLASH Access Counter */
-#define E1000_FLOP     0x0103C  /* FLASH Opcode Register */
-#define E1000_I2CCMD   0x01028  /* SFPI2C Command Register - RW */
-#define E1000_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */
-#define E1000_WDSTP    0x01040  /* Watchdog Setup - RW */
-#define E1000_SWDSTS   0x01044  /* SW Device Status - RW */
-#define E1000_FRTIMER  0x01048  /* Free Running Timer - RW */
-#define E1000_TCPTIMER 0x0104C  /* TCP Timer - RW */
-#define E1000_VPDDIAG  0x01060  /* VPD Diagnostic - RO */
-#define E1000_ICR_V2   0x01500  /* Interrupt Cause - new location - RC */
-#define E1000_ICS_V2   0x01504  /* Interrupt Cause Set - new location - WO */
-#define E1000_IMS_V2   0x01508  /* Interrupt Mask Set/Read - new location - RW */
-#define E1000_IMC_V2   0x0150C  /* Interrupt Mask Clear - new location - WO */
-#define E1000_IAM_V2   0x01510  /* Interrupt Ack Auto Mask - new location - RW */
-#define E1000_ERT      0x02008  /* Early Rx Threshold - RW */
-#define E1000_FCRTL    0x02160  /* Flow Control Receive Threshold Low - RW */
-#define E1000_FCRTH    0x02168  /* Flow Control Receive Threshold High - RW */
-#define E1000_PSRCTL   0x02170  /* Packet Split Receive Control - RW */
-#define E1000_RDFPCQ(_n)  (0x02430 + (0x4 * (_n)))
-#define E1000_PBRTH    0x02458  /* PB Rx Arbitration Threshold - RW */
-#define E1000_FCRTV    0x02460  /* Flow Control Refresh Timer Value - RW */
+#define E1000_CTRL	0x00000  /* Device Control - RW */
+#define E1000_CTRL_DUP	0x00004  /* Device Control Duplicate (Shadow) - RW */
+#define E1000_STATUS	0x00008  /* Device Status - RO */
+#define E1000_EECD	0x00010  /* EEPROM/Flash Control - RW */
+#define E1000_EERD	0x00014  /* EEPROM Read - RW */
+#define E1000_CTRL_EXT	0x00018  /* Extended Device Control - RW */
+#define E1000_FLA	0x0001C  /* Flash Access - RW */
+#define E1000_MDIC	0x00020  /* MDI Control - RW */
+#define E1000_MDICNFG	0x00E04  /* MDI Config - RW */
+#define E1000_REGISTER_SET_SIZE		0x20000 /* CSR Size */
+#define E1000_EEPROM_INIT_CTRL_WORD_2	0x0F /* EEPROM Init Ctrl Word 2 */
+#define E1000_EEPROM_PCIE_CTRL_WORD_2	0x28 /* EEPROM PCIe Ctrl Word 2 */
+#define E1000_BARCTRL			0x5BBC /* BAR ctrl reg */
+#define E1000_BARCTRL_FLSIZE		0x0700 /* BAR ctrl Flsize */
+#define E1000_BARCTRL_CSRSIZE		0x2000 /* BAR ctrl CSR size */
+#define E1000_I350_BARCTRL		0x5BFC /* BAR ctrl reg */
+#define E1000_SCTL	0x00024  /* SerDes Control - RW */
+#define E1000_FCAL	0x00028  /* Flow Control Address Low - RW */
+#define E1000_FCAH	0x0002C  /* Flow Control Address High -RW */
+#define E1000_FEXT	0x0002C  /* Future Extended - RW */
+#define E1000_FEXTNVM4	0x00024  /* Future Extended NVM 4 - RW */
+#define E1000_FEXTNVM	0x00028  /* Future Extended NVM - RW */
+#define E1000_FCT	0x00030  /* Flow Control Type - RW */
+#define E1000_CONNSW	0x00034  /* Copper/Fiber switch control - RW */
+#define E1000_VET	0x00038  /* VLAN Ether Type - RW */
+#define E1000_ICR	0x000C0  /* Interrupt Cause Read - R/clr */
+#define E1000_ITR	0x000C4  /* Interrupt Throttling Rate - RW */
+#define E1000_ICS	0x000C8  /* Interrupt Cause Set - WO */
+#define E1000_IMS	0x000D0  /* Interrupt Mask Set - RW */
+#define E1000_IMC	0x000D8  /* Interrupt Mask Clear - WO */
+#define E1000_IAM	0x000E0  /* Interrupt Acknowledge Auto Mask */
+#define E1000_IVAR	0x000E4  /* Interrupt Vector Allocation Register - RW */
+#define E1000_SVCR	0x000F0
+#define E1000_SVT	0x000F4
+#define E1000_RCTL	0x00100  /* Rx Control - RW */
+#define E1000_FCTTV	0x00170  /* Flow Control Transmit Timer Value - RW */
+#define E1000_TXCW	0x00178  /* Tx Configuration Word - RW */
+#define E1000_RXCW	0x00180  /* Rx Configuration Word - RO */
+#define E1000_PBA_ECC	0x01100  /* PBA ECC Register */
+#define E1000_EICR	0x01580  /* Ext. Interrupt Cause Read - R/clr */
+#define E1000_EITR(_n)	(0x01680 + (0x4 * (_n)))
+#define E1000_EICS	0x01520  /* Ext. Interrupt Cause Set - W0 */
+#define E1000_EIMS	0x01524  /* Ext. Interrupt Mask Set/Read - RW */
+#define E1000_EIMC	0x01528  /* Ext. Interrupt Mask Clear - WO */
+#define E1000_EIAC	0x0152C  /* Ext. Interrupt Auto Clear - RW */
+#define E1000_EIAM	0x01530  /* Ext. Interrupt Ack Auto Clear Mask - RW */
+#define E1000_GPIE	0x01514  /* General Purpose Interrupt Enable - RW */
+#define E1000_IVAR0	0x01700  /* Interrupt Vector Allocation (array) - RW */
+#define E1000_IVAR_MISC	0x01740 /* IVAR for "other" causes - RW */
+#define E1000_TCTL	0x00400  /* Tx Control - RW */
+#define E1000_TCTL_EXT	0x00404  /* Extended Tx Control - RW */
+#define E1000_TIPG	0x00410  /* Tx Inter-packet gap -RW */
+#define E1000_TBT	0x00448  /* Tx Burst Timer - RW */
+#define E1000_AIT	0x00458  /* Adaptive Interframe Spacing Throttle - RW */
+#define E1000_LEDCTL	0x00E00  /* LED Control - RW */
+#define E1000_EXTCNF_CTRL	0x00F00  /* Extended Configuration Control */
+#define E1000_EXTCNF_SIZE	0x00F08  /* Extended Configuration Size */
+#define E1000_PHY_CTRL	0x00F10  /* PHY Control Register in CSR */
+#define E1000_POEMB	E1000_PHY_CTRL /* PHY OEM Bits */
+#define E1000_PBA	0x01000  /* Packet Buffer Allocation - RW */
+#define E1000_PBS	0x01008  /* Packet Buffer Size */
+#define E1000_EEMNGCTL	0x01010  /* MNG EEprom Control */
+#define E1000_EEARBC	0x01024  /* EEPROM Auto Read Bus Control */
+#define E1000_FLASHT	0x01028  /* FLASH Timer Register */
+#define E1000_EEWR	0x0102C  /* EEPROM Write Register - RW */
+#define E1000_FLSWCTL	0x01030  /* FLASH control register */
+#define E1000_FLSWDATA	0x01034  /* FLASH data register */
+#define E1000_FLSWCNT	0x01038  /* FLASH Access Counter */
+#define E1000_FLOP	0x0103C  /* FLASH Opcode Register */
+#define E1000_I2CCMD	0x01028  /* SFPI2C Command Register - RW */
+#define E1000_I2CPARAMS	0x0102C /* SFPI2C Parameters Register - RW */
+#define E1000_I2CBB_EN	0x00000100  /* I2C - Bit Bang Enable */
+#define E1000_I2C_CLK_OUT	0x00000200  /* I2C- Clock */
+#define E1000_I2C_DATA_OUT	0x00000400  /* I2C- Data Out */
+#define E1000_I2C_DATA_OE_N	0x00000800  /* I2C- Data Output Enable */
+#define E1000_I2C_DATA_IN	0x00001000  /* I2C- Data In */
+#define E1000_I2C_CLK_OE_N	0x00002000  /* I2C- Clock Output Enable */
+#define E1000_I2C_CLK_IN	0x00004000  /* I2C- Clock In */
+#define E1000_I2C_CLK_STRETCH_DIS	0x00008000 /* I2C- Dis Clk Stretching */
+#define E1000_WDSTP	0x01040  /* Watchdog Setup - RW */
+#define E1000_SWDSTS	0x01044  /* SW Device Status - RW */
+#define E1000_FRTIMER	0x01048  /* Free Running Timer - RW */
+#define E1000_TCPTIMER	0x0104C  /* TCP Timer - RW */
+#define E1000_VPDDIAG	0x01060  /* VPD Diagnostic - RO */
+#define E1000_ICR_V2	0x01500  /* Intr Cause - new location - RC */
+#define E1000_ICS_V2	0x01504  /* Intr Cause Set - new location - WO */
+#define E1000_IMS_V2	0x01508  /* Intr Mask Set/Read - new location - RW */
+#define E1000_IMC_V2	0x0150C  /* Intr Mask Clear - new location - WO */
+#define E1000_IAM_V2	0x01510  /* Intr Ack Auto Mask - new location - RW */
+#define E1000_ERT	0x02008  /* Early Rx Threshold - RW */
+#define E1000_FCRTL	0x02160  /* Flow Control Receive Threshold Low - RW */
+#define E1000_FCRTH	0x02168  /* Flow Control Receive Threshold High - RW */
+#define E1000_PSRCTL	0x02170  /* Packet Split Receive Control - RW */
+#define E1000_RDFPCQ(_n)	(0x02430 + (0x4 * (_n)))
+#define E1000_PBRTH	0x02458  /* PB Rx Arbitration Threshold - RW */
+#define E1000_FCRTV	0x02460  /* Flow Control Refresh Timer Value - RW */
 /* Split and Replication Rx Control - RW */
-#define E1000_RDPUMB   0x025CC  /* DMA Rx Descriptor uC Mailbox - RW */
-#define E1000_RDPUAD   0x025D0  /* DMA Rx Descriptor uC Addr Command - RW */
-#define E1000_RDPUWD   0x025D4  /* DMA Rx Descriptor uC Data Write - RW */
-#define E1000_RDPURD   0x025D8  /* DMA Rx Descriptor uC Data Read - RW */
-#define E1000_RDPUCTL  0x025DC  /* DMA Rx Descriptor uC Control - RW */
-#define E1000_PBDIAG   0x02458  /* Packet Buffer Diagnostic - RW */
-#define E1000_RXPBS    0x02404  /* Rx Packet Buffer Size - RW */
-#define E1000_IRPBS 0x02404 /* Same as RXPBS, renamed for newer adapters - RW */
-#define E1000_PBRWAC   0x024E8 /* Rx packet buffer wrap around counter - RO */
-#define E1000_RDTR     0x02820  /* Rx Delay Timer - RW */
-#define E1000_RADV     0x0282C  /* Rx Interrupt Absolute Delay Timer - RW */
+#define E1000_RDPUMB	0x025CC  /* DMA Rx Descriptor uC Mailbox - RW */
+#define E1000_RDPUAD	0x025D0  /* DMA Rx Descriptor uC Addr Command - RW */
+#define E1000_RDPUWD	0x025D4  /* DMA Rx Descriptor uC Data Write - RW */
+#define E1000_RDPURD	0x025D8  /* DMA Rx Descriptor uC Data Read - RW */
+#define E1000_RDPUCTL	0x025DC  /* DMA Rx Descriptor uC Control - RW */
+#define E1000_PBDIAG	0x02458  /* Packet Buffer Diagnostic - RW */
+#define E1000_RXPBS	0x02404  /* Rx Packet Buffer Size - RW */
+#define E1000_IRPBS	0x02404 /* Same as RXPBS, renamed for newer Si - RW */
+#define E1000_PBRWAC	0x024E8 /* Rx packet buffer wrap around counter - RO */
+#define E1000_RDTR	0x02820  /* Rx Delay Timer - RW */
+#define E1000_RADV	0x0282C  /* Rx Interrupt Absolute Delay Timer - RW */
 /*
  * Convenience macros
  *
@@ -141,442 +151,470 @@
  * Example usage:
  * E1000_RDBAL_REG(current_rx_queue)
  */
-#define E1000_RDBAL(_n)      ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \
-                                         (0x0C000 + ((_n) * 0x40)))
-#define E1000_RDBAH(_n)      ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \
-                                         (0x0C004 + ((_n) * 0x40)))
-#define E1000_RDLEN(_n)      ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \
-                                         (0x0C008 + ((_n) * 0x40)))
-#define E1000_SRRCTL(_n)     ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \
-                                         (0x0C00C + ((_n) * 0x40)))
-#define E1000_RDH(_n)        ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \
-                                         (0x0C010 + ((_n) * 0x40)))
-#define E1000_RXCTL(_n)      ((_n) < 4 ? (0x02814 + ((_n) * 0x100)) : \
-                                         (0x0C014 + ((_n) * 0x40)))
-#define E1000_DCA_RXCTRL(_n) E1000_RXCTL(_n)
-#define E1000_RDT(_n)        ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \
-                                         (0x0C018 + ((_n) * 0x40)))
-#define E1000_RXDCTL(_n)     ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \
-                                         (0x0C028 + ((_n) * 0x40)))
-#define E1000_RQDPC(_n)      ((_n) < 4 ? (0x02830 + ((_n) * 0x100)) : \
-                                         (0x0C030 + ((_n) * 0x40)))
-#define E1000_TDBAL(_n)      ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \
-                                         (0x0E000 + ((_n) * 0x40)))
-#define E1000_TDBAH(_n)      ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \
-                                         (0x0E004 + ((_n) * 0x40)))
-#define E1000_TDLEN(_n)      ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \
-                                         (0x0E008 + ((_n) * 0x40)))
-#define E1000_TDH(_n)        ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \
-                                         (0x0E010 + ((_n) * 0x40)))
-#define E1000_TXCTL(_n)      ((_n) < 4 ? (0x03814 + ((_n) * 0x100)) : \
-                                         (0x0E014 + ((_n) * 0x40)))
+#define E1000_RDBAL(_n)	((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \
+			 (0x0C000 + ((_n) * 0x40)))
+#define E1000_RDBAH(_n)	((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \
+			 (0x0C004 + ((_n) * 0x40)))
+#define E1000_RDLEN(_n)	((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \
+			 (0x0C008 + ((_n) * 0x40)))
+#define E1000_SRRCTL(_n)	((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \
+				 (0x0C00C + ((_n) * 0x40)))
+#define E1000_RDH(_n)	((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \
+			 (0x0C010 + ((_n) * 0x40)))
+#define E1000_RXCTL(_n)	((_n) < 4 ? (0x02814 + ((_n) * 0x100)) : \
+			 (0x0C014 + ((_n) * 0x40)))
+#define E1000_DCA_RXCTRL(_n)	E1000_RXCTL(_n)
+#define E1000_RDT(_n)	((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \
+			 (0x0C018 + ((_n) * 0x40)))
+#define E1000_RXDCTL(_n)	((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \
+				 (0x0C028 + ((_n) * 0x40)))
+#define E1000_RQDPC(_n)	((_n) < 4 ? (0x02830 + ((_n) * 0x100)) : \
+			 (0x0C030 + ((_n) * 0x40)))
+#define E1000_TDBAL(_n)	((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \
+			 (0x0E000 + ((_n) * 0x40)))
+#define E1000_TDBAH(_n)	((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \
+			 (0x0E004 + ((_n) * 0x40)))
+#define E1000_TDLEN(_n)	((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \
+			 (0x0E008 + ((_n) * 0x40)))
+#define E1000_TDH(_n)	((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \
+			 (0x0E010 + ((_n) * 0x40)))
+#define E1000_TXCTL(_n)	((_n) < 4 ? (0x03814 + ((_n) * 0x100)) : \
+			 (0x0E014 + ((_n) * 0x40)))
 #define E1000_DCA_TXCTRL(_n) E1000_TXCTL(_n)
-#define E1000_TDT(_n)        ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \
-                                         (0x0E018 + ((_n) * 0x40)))
-#define E1000_TXDCTL(_n)     ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \
-                                         (0x0E028 + ((_n) * 0x40)))
-#define E1000_TDWBAL(_n)     ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) : \
-                                         (0x0E038 + ((_n) * 0x40)))
-#define E1000_TDWBAH(_n)     ((_n) < 4 ? (0x0383C + ((_n) * 0x100)) : \
-                                         (0x0E03C + ((_n) * 0x40)))
-#define E1000_TARC(_n)                   (0x03840 + ((_n) * 0x100))
-#define E1000_RSRPD    0x02C00  /* Rx Small Packet Detect - RW */
-#define E1000_RAID     0x02C08  /* Receive Ack Interrupt Delay - RW */
-#define E1000_TXDMAC   0x03000  /* Tx DMA Control - RW */
-#define E1000_KABGTXD  0x03004  /* AFE Band Gap Transmit Ref Data */
-#define E1000_PSRTYPE(_i)       (0x05480 + ((_i) * 4))
-#define E1000_RAL(_i)  (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
-                                       (0x054E0 + ((_i - 16) * 8)))
-#define E1000_RAH(_i)  (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
-                                       (0x054E4 + ((_i - 16) * 8)))
-#define E1000_SHRAL(_i)         (0x05438 + ((_i) * 8))
-#define E1000_SHRAH(_i)         (0x0543C + ((_i) * 8))
-#define E1000_IP4AT_REG(_i)     (0x05840 + ((_i) * 8))
-#define E1000_IP6AT_REG(_i)     (0x05880 + ((_i) * 4))
-#define E1000_WUPM_REG(_i)      (0x05A00 + ((_i) * 4))
-#define E1000_FFMT_REG(_i)      (0x09000 + ((_i) * 8))
-#define E1000_FFVT_REG(_i)      (0x09800 + ((_i) * 8))
-#define E1000_FFLT_REG(_i)      (0x05F00 + ((_i) * 8))
-#define E1000_PBSLAC   0x03100  /* Packet Buffer Slave Access Control */
-#define E1000_PBSLAD(_n)  (0x03110 + (0x4 * (_n)))  /* Packet Buffer DWORD (_n) */
-#define E1000_TXPBS    0x03404  /* Tx Packet Buffer Size - RW */
-#define E1000_ITPBS   0x03404   /* Same as TXPBS, renamed for newer adpaters - RW */
-#define E1000_TDFH     0x03410  /* Tx Data FIFO Head - RW */
-#define E1000_TDFT     0x03418  /* Tx Data FIFO Tail - RW */
-#define E1000_TDFHS    0x03420  /* Tx Data FIFO Head Saved - RW */
-#define E1000_TDFTS    0x03428  /* Tx Data FIFO Tail Saved - RW */
-#define E1000_TDFPC    0x03430  /* Tx Data FIFO Packet Count - RW */
-#define E1000_TDPUMB   0x0357C  /* DMA Tx Descriptor uC Mail Box - RW */
-#define E1000_TDPUAD   0x03580  /* DMA Tx Descriptor uC Addr Command - RW */
-#define E1000_TDPUWD   0x03584  /* DMA Tx Descriptor uC Data Write - RW */
-#define E1000_TDPURD   0x03588  /* DMA Tx Descriptor uC Data  Read  - RW */
-#define E1000_TDPUCTL  0x0358C  /* DMA Tx Descriptor uC Control - RW */
-#define E1000_DTXCTL   0x03590  /* DMA Tx Control - RW */
-#define E1000_DTXTCPFLGL 0x0359C /* DMA Tx Control flag low - RW */
-#define E1000_DTXTCPFLGH 0x035A0 /* DMA Tx Control flag high - RW */
-#define E1000_DTXMXSZRQ  0x03540 /* DMA Tx Max Total Allow Size Requests - RW */
-#define E1000_TIDV     0x03820  /* Tx Interrupt Delay Value - RW */
-#define E1000_TADV     0x0382C  /* Tx Interrupt Absolute Delay Val - RW */
-#define E1000_TSPMT    0x03830  /* TCP Segmentation PAD & Min Threshold - RW */
-#define E1000_CRCERRS  0x04000  /* CRC Error Count - R/clr */
-#define E1000_ALGNERRC 0x04004  /* Alignment Error Count - R/clr */
-#define E1000_SYMERRS  0x04008  /* Symbol Error Count - R/clr */
-#define E1000_RXERRC   0x0400C  /* Receive Error Count - R/clr */
-#define E1000_MPC      0x04010  /* Missed Packet Count - R/clr */
-#define E1000_SCC      0x04014  /* Single Collision Count - R/clr */
-#define E1000_ECOL     0x04018  /* Excessive Collision Count - R/clr */
-#define E1000_MCC      0x0401C  /* Multiple Collision Count - R/clr */
-#define E1000_LATECOL  0x04020  /* Late Collision Count - R/clr */
-#define E1000_COLC     0x04028  /* Collision Count - R/clr */
-#define E1000_DC       0x04030  /* Defer Count - R/clr */
-#define E1000_TNCRS    0x04034  /* Tx-No CRS - R/clr */
-#define E1000_SEC      0x04038  /* Sequence Error Count - R/clr */
-#define E1000_CEXTERR  0x0403C  /* Carrier Extension Error Count - R/clr */
-#define E1000_RLEC     0x04040  /* Receive Length Error Count - R/clr */
-#define E1000_XONRXC   0x04048  /* XON Rx Count - R/clr */
-#define E1000_XONTXC   0x0404C  /* XON Tx Count - R/clr */
-#define E1000_XOFFRXC  0x04050  /* XOFF Rx Count - R/clr */
-#define E1000_XOFFTXC  0x04054  /* XOFF Tx Count - R/clr */
-#define E1000_FCRUC    0x04058  /* Flow Control Rx Unsupported Count- R/clr */
-#define E1000_PRC64    0x0405C  /* Packets Rx (64 bytes) - R/clr */
-#define E1000_PRC127   0x04060  /* Packets Rx (65-127 bytes) - R/clr */
-#define E1000_PRC255   0x04064  /* Packets Rx (128-255 bytes) - R/clr */
-#define E1000_PRC511   0x04068  /* Packets Rx (255-511 bytes) - R/clr */
-#define E1000_PRC1023  0x0406C  /* Packets Rx (512-1023 bytes) - R/clr */
-#define E1000_PRC1522  0x04070  /* Packets Rx (1024-1522 bytes) - R/clr */
-#define E1000_GPRC     0x04074  /* Good Packets Rx Count - R/clr */
-#define E1000_BPRC     0x04078  /* Broadcast Packets Rx Count - R/clr */
-#define E1000_MPRC     0x0407C  /* Multicast Packets Rx Count - R/clr */
-#define E1000_GPTC     0x04080  /* Good Packets Tx Count - R/clr */
-#define E1000_GORCL    0x04088  /* Good Octets Rx Count Low - R/clr */
-#define E1000_GORCH    0x0408C  /* Good Octets Rx Count High - R/clr */
-#define E1000_GOTCL    0x04090  /* Good Octets Tx Count Low - R/clr */
-#define E1000_GOTCH    0x04094  /* Good Octets Tx Count High - R/clr */
-#define E1000_RNBC     0x040A0  /* Rx No Buffers Count - R/clr */
-#define E1000_RUC      0x040A4  /* Rx Undersize Count - R/clr */
-#define E1000_RFC      0x040A8  /* Rx Fragment Count - R/clr */
-#define E1000_ROC      0x040AC  /* Rx Oversize Count - R/clr */
-#define E1000_RJC      0x040B0  /* Rx Jabber Count - R/clr */
-#define E1000_MGTPRC   0x040B4  /* Management Packets Rx Count - R/clr */
-#define E1000_MGTPDC   0x040B8  /* Management Packets Dropped Count - R/clr */
-#define E1000_MGTPTC   0x040BC  /* Management Packets Tx Count - R/clr */
-#define E1000_TORL     0x040C0  /* Total Octets Rx Low - R/clr */
-#define E1000_TORH     0x040C4  /* Total Octets Rx High - R/clr */
-#define E1000_TOTL     0x040C8  /* Total Octets Tx Low - R/clr */
-#define E1000_TOTH     0x040CC  /* Total Octets Tx High - R/clr */
-#define E1000_TPR      0x040D0  /* Total Packets Rx - R/clr */
-#define E1000_TPT      0x040D4  /* Total Packets Tx - R/clr */
-#define E1000_PTC64    0x040D8  /* Packets Tx (64 bytes) - R/clr */
-#define E1000_PTC127   0x040DC  /* Packets Tx (65-127 bytes) - R/clr */
-#define E1000_PTC255   0x040E0  /* Packets Tx (128-255 bytes) - R/clr */
-#define E1000_PTC511   0x040E4  /* Packets Tx (256-511 bytes) - R/clr */
-#define E1000_PTC1023  0x040E8  /* Packets Tx (512-1023 bytes) - R/clr */
-#define E1000_PTC1522  0x040EC  /* Packets Tx (1024-1522 Bytes) - R/clr */
-#define E1000_MPTC     0x040F0  /* Multicast Packets Tx Count - R/clr */
-#define E1000_BPTC     0x040F4  /* Broadcast Packets Tx Count - R/clr */
-#define E1000_TSCTC    0x040F8  /* TCP Segmentation Context Tx - R/clr */
-#define E1000_TSCTFC   0x040FC  /* TCP Segmentation Context Tx Fail - R/clr */
-#define E1000_IAC      0x04100  /* Interrupt Assertion Count */
-#define E1000_ICRXPTC  0x04104  /* Interrupt Cause Rx Pkt Timer Expire Count */
-#define E1000_ICRXATC  0x04108  /* Interrupt Cause Rx Abs Timer Expire Count */
-#define E1000_ICTXPTC  0x0410C  /* Interrupt Cause Tx Pkt Timer Expire Count */
-#define E1000_ICTXATC  0x04110  /* Interrupt Cause Tx Abs Timer Expire Count */
-#define E1000_ICTXQEC  0x04118  /* Interrupt Cause Tx Queue Empty Count */
-#define E1000_ICTXQMTC 0x0411C  /* Interrupt Cause Tx Queue Min Thresh Count */
-#define E1000_ICRXDMTC 0x04120  /* Interrupt Cause Rx Desc Min Thresh Count */
-#define E1000_ICRXOC   0x04124  /* Interrupt Cause Receiver Overrun Count */
-#define E1000_CRC_OFFSET 0x05F50  /* CRC Offset register */
+#define E1000_TDT(_n)	((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \
+			 (0x0E018 + ((_n) * 0x40)))
+#define E1000_TXDCTL(_n)	((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \
+				 (0x0E028 + ((_n) * 0x40)))
+#define E1000_TDWBAL(_n)	((_n) < 4 ? (0x03838 + ((_n) * 0x100)) : \
+				 (0x0E038 + ((_n) * 0x40)))
+#define E1000_TDWBAH(_n)	((_n) < 4 ? (0x0383C + ((_n) * 0x100)) : \
+				 (0x0E03C + ((_n) * 0x40)))
+#define E1000_TARC(_n)		(0x03840 + ((_n) * 0x100))
+#define E1000_RSRPD		0x02C00  /* Rx Small Packet Detect - RW */
+#define E1000_RAID		0x02C08  /* Receive Ack Interrupt Delay - RW */
+#define E1000_TXDMAC		0x03000  /* Tx DMA Control - RW */
+#define E1000_KABGTXD		0x03004  /* AFE Band Gap Transmit Ref Data */
+#define E1000_PSRTYPE(_i)	(0x05480 + ((_i) * 4))
+#define E1000_RAL(_i)		(((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
+				 (0x054E0 + ((_i - 16) * 8)))
+#define E1000_RAH(_i)		(((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
+				 (0x054E4 + ((_i - 16) * 8)))
+#define E1000_SHRAL(_i)		(0x05438 + ((_i) * 8))
+#define E1000_SHRAH(_i)		(0x0543C + ((_i) * 8))
+#define E1000_IP4AT_REG(_i)	(0x05840 + ((_i) * 8))
+#define E1000_IP6AT_REG(_i)	(0x05880 + ((_i) * 4))
+#define E1000_WUPM_REG(_i)	(0x05A00 + ((_i) * 4))
+#define E1000_FFMT_REG(_i)	(0x09000 + ((_i) * 8))
+#define E1000_FFVT_REG(_i)	(0x09800 + ((_i) * 8))
+#define E1000_FFLT_REG(_i)	(0x05F00 + ((_i) * 8))
+#define E1000_PBSLAC		0x03100  /* Pkt Buffer Slave Access Control */
+#define E1000_PBSLAD(_n)	(0x03110 + (0x4 * (_n)))  /* Pkt Buffer DWORD */
+#define E1000_TXPBS		0x03404  /* Tx Packet Buffer Size - RW */
+/* Same as TXPBS, renamed for newer Si - RW */
+#define E1000_ITPBS		0x03404
+#define E1000_TDFH		0x03410  /* Tx Data FIFO Head - RW */
+#define E1000_TDFT		0x03418  /* Tx Data FIFO Tail - RW */
+#define E1000_TDFHS		0x03420  /* Tx Data FIFO Head Saved - RW */
+#define E1000_TDFTS		0x03428  /* Tx Data FIFO Tail Saved - RW */
+#define E1000_TDFPC		0x03430  /* Tx Data FIFO Packet Count - RW */
+#define E1000_TDPUMB		0x0357C  /* DMA Tx Desc uC Mail Box - RW */
+#define E1000_TDPUAD		0x03580  /* DMA Tx Desc uC Addr Command - RW */
+#define E1000_TDPUWD		0x03584  /* DMA Tx Desc uC Data Write - RW */
+#define E1000_TDPURD		0x03588  /* DMA Tx Desc uC Data  Read  - RW */
+#define E1000_TDPUCTL		0x0358C  /* DMA Tx Desc uC Control - RW */
+#define E1000_DTXCTL		0x03590  /* DMA Tx Control - RW */
+#define E1000_DTXTCPFLGL	0x0359C /* DMA Tx Control flag low - RW */
+#define E1000_DTXTCPFLGH	0x035A0 /* DMA Tx Control flag high - RW */
+/* DMA Tx Max Total Allow Size Reqs - RW */
+#define E1000_DTXMXSZRQ		0x03540
+#define E1000_TIDV	0x03820  /* Tx Interrupt Delay Value - RW */
+#define E1000_TADV	0x0382C  /* Tx Interrupt Absolute Delay Val - RW */
+#define E1000_TSPMT	0x03830  /* TCP Segmentation PAD & Min Threshold - RW */
+#define E1000_CRCERRS	0x04000  /* CRC Error Count - R/clr */
+#define E1000_ALGNERRC	0x04004  /* Alignment Error Count - R/clr */
+#define E1000_SYMERRS	0x04008  /* Symbol Error Count - R/clr */
+#define E1000_RXERRC	0x0400C  /* Receive Error Count - R/clr */
+#define E1000_MPC	0x04010  /* Missed Packet Count - R/clr */
+#define E1000_SCC	0x04014  /* Single Collision Count - R/clr */
+#define E1000_ECOL	0x04018  /* Excessive Collision Count - R/clr */
+#define E1000_MCC	0x0401C  /* Multiple Collision Count - R/clr */
+#define E1000_LATECOL	0x04020  /* Late Collision Count - R/clr */
+#define E1000_COLC	0x04028  /* Collision Count - R/clr */
+#define E1000_DC	0x04030  /* Defer Count - R/clr */
+#define E1000_TNCRS	0x04034  /* Tx-No CRS - R/clr */
+#define E1000_SEC	0x04038  /* Sequence Error Count - R/clr */
+#define E1000_CEXTERR	0x0403C  /* Carrier Extension Error Count - R/clr */
+#define E1000_RLEC	0x04040  /* Receive Length Error Count - R/clr */
+#define E1000_XONRXC	0x04048  /* XON Rx Count - R/clr */
+#define E1000_XONTXC	0x0404C  /* XON Tx Count - R/clr */
+#define E1000_XOFFRXC	0x04050  /* XOFF Rx Count - R/clr */
+#define E1000_XOFFTXC	0x04054  /* XOFF Tx Count - R/clr */
+#define E1000_FCRUC	0x04058  /* Flow Control Rx Unsupported Count- R/clr */
+#define E1000_PRC64	0x0405C  /* Packets Rx (64 bytes) - R/clr */
+#define E1000_PRC127	0x04060  /* Packets Rx (65-127 bytes) - R/clr */
+#define E1000_PRC255	0x04064  /* Packets Rx (128-255 bytes) - R/clr */
+#define E1000_PRC511	0x04068  /* Packets Rx (255-511 bytes) - R/clr */
+#define E1000_PRC1023	0x0406C  /* Packets Rx (512-1023 bytes) - R/clr */
+#define E1000_PRC1522	0x04070  /* Packets Rx (1024-1522 bytes) - R/clr */
+#define E1000_GPRC	0x04074  /* Good Packets Rx Count - R/clr */
+#define E1000_BPRC	0x04078  /* Broadcast Packets Rx Count - R/clr */
+#define E1000_MPRC	0x0407C  /* Multicast Packets Rx Count - R/clr */
+#define E1000_GPTC	0x04080  /* Good Packets Tx Count - R/clr */
+#define E1000_GORCL	0x04088  /* Good Octets Rx Count Low - R/clr */
+#define E1000_GORCH	0x0408C  /* Good Octets Rx Count High - R/clr */
+#define E1000_GOTCL	0x04090  /* Good Octets Tx Count Low - R/clr */
+#define E1000_GOTCH	0x04094  /* Good Octets Tx Count High - R/clr */
+#define E1000_RNBC	0x040A0  /* Rx No Buffers Count - R/clr */
+#define E1000_RUC	0x040A4  /* Rx Undersize Count - R/clr */
+#define E1000_RFC	0x040A8  /* Rx Fragment Count - R/clr */
+#define E1000_ROC	0x040AC  /* Rx Oversize Count - R/clr */
+#define E1000_RJC	0x040B0  /* Rx Jabber Count - R/clr */
+#define E1000_MGTPRC	0x040B4  /* Management Packets Rx Count - R/clr */
+#define E1000_MGTPDC	0x040B8  /* Management Packets Dropped Count - R/clr */
+#define E1000_MGTPTC	0x040BC  /* Management Packets Tx Count - R/clr */
+#define E1000_TORL	0x040C0  /* Total Octets Rx Low - R/clr */
+#define E1000_TORH	0x040C4  /* Total Octets Rx High - R/clr */
+#define E1000_TOTL	0x040C8  /* Total Octets Tx Low - R/clr */
+#define E1000_TOTH	0x040CC  /* Total Octets Tx High - R/clr */
+#define E1000_TPR	0x040D0  /* Total Packets Rx - R/clr */
+#define E1000_TPT	0x040D4  /* Total Packets Tx - R/clr */
+#define E1000_PTC64	0x040D8  /* Packets Tx (64 bytes) - R/clr */
+#define E1000_PTC127	0x040DC  /* Packets Tx (65-127 bytes) - R/clr */
+#define E1000_PTC255	0x040E0  /* Packets Tx (128-255 bytes) - R/clr */
+#define E1000_PTC511	0x040E4  /* Packets Tx (256-511 bytes) - R/clr */
+#define E1000_PTC1023	0x040E8  /* Packets Tx (512-1023 bytes) - R/clr */
+#define E1000_PTC1522	0x040EC  /* Packets Tx (1024-1522 Bytes) - R/clr */
+#define E1000_MPTC	0x040F0  /* Multicast Packets Tx Count - R/clr */
+#define E1000_BPTC	0x040F4  /* Broadcast Packets Tx Count - R/clr */
+#define E1000_TSCTC	0x040F8  /* TCP Segmentation Context Tx - R/clr */
+#define E1000_TSCTFC	0x040FC  /* TCP Segmentation Context Tx Fail - R/clr */
+#define E1000_IAC	0x04100  /* Interrupt Assertion Count */
+#define E1000_ICRXPTC	0x04104  /* Interrupt Cause Rx Pkt Timer Expire Count */
+#define E1000_ICRXATC	0x04108  /* Interrupt Cause Rx Abs Timer Expire Count */
+#define E1000_ICTXPTC	0x0410C  /* Interrupt Cause Tx Pkt Timer Expire Count */
+#define E1000_ICTXATC	0x04110  /* Interrupt Cause Tx Abs Timer Expire Count */
+#define E1000_ICTXQEC	0x04118  /* Interrupt Cause Tx Queue Empty Count */
+#define E1000_ICTXQMTC	0x0411C  /* Interrupt Cause Tx Queue Min Thresh Count */
+#define E1000_ICRXDMTC	0x04120  /* Interrupt Cause Rx Desc Min Thresh Count */
+#define E1000_ICRXOC	0x04124  /* Interrupt Cause Receiver Overrun Count */
+#define E1000_CRC_OFFSET	0x05F50  /* CRC Offset register */
 
-#define E1000_VFGPRC   0x00F10
-#define E1000_VFGORC   0x00F18
-#define E1000_VFMPRC   0x00F3C
-#define E1000_VFGPTC   0x00F14
-#define E1000_VFGOTC   0x00F34
-#define E1000_VFGOTLBC 0x00F50
-#define E1000_VFGPTLBC 0x00F44
-#define E1000_VFGORLBC 0x00F48
-#define E1000_VFGPRLBC 0x00F40
+#define E1000_VFGPRC	0x00F10
+#define E1000_VFGORC	0x00F18
+#define E1000_VFMPRC	0x00F3C
+#define E1000_VFGPTC	0x00F14
+#define E1000_VFGOTC	0x00F34
+#define E1000_VFGOTLBC	0x00F50
+#define E1000_VFGPTLBC	0x00F44
+#define E1000_VFGORLBC	0x00F48
+#define E1000_VFGPRLBC	0x00F40
 /* Virtualization statistical counters */
-#define E1000_PFVFGPRC(_n)   (0x010010 + (0x100 * (_n)))
-#define E1000_PFVFGPTC(_n)   (0x010014 + (0x100 * (_n)))
-#define E1000_PFVFGORC(_n)   (0x010018 + (0x100 * (_n)))
-#define E1000_PFVFGOTC(_n)   (0x010034 + (0x100 * (_n)))
-#define E1000_PFVFMPRC(_n)   (0x010038 + (0x100 * (_n)))
-#define E1000_PFVFGPRLBC(_n) (0x010040 + (0x100 * (_n)))
-#define E1000_PFVFGPTLBC(_n) (0x010044 + (0x100 * (_n)))
-#define E1000_PFVFGORLBC(_n) (0x010048 + (0x100 * (_n)))
-#define E1000_PFVFGOTLBC(_n) (0x010050 + (0x100 * (_n)))
+#define E1000_PFVFGPRC(_n)	(0x010010 + (0x100 * (_n)))
+#define E1000_PFVFGPTC(_n)	(0x010014 + (0x100 * (_n)))
+#define E1000_PFVFGORC(_n)	(0x010018 + (0x100 * (_n)))
+#define E1000_PFVFGOTC(_n)	(0x010034 + (0x100 * (_n)))
+#define E1000_PFVFMPRC(_n)	(0x010038 + (0x100 * (_n)))
+#define E1000_PFVFGPRLBC(_n)	(0x010040 + (0x100 * (_n)))
+#define E1000_PFVFGPTLBC(_n)	(0x010044 + (0x100 * (_n)))
+#define E1000_PFVFGORLBC(_n)	(0x010048 + (0x100 * (_n)))
+#define E1000_PFVFGOTLBC(_n)	(0x010050 + (0x100 * (_n)))
 
-#define E1000_LSECTXUT        0x04300  /* LinkSec Tx Untagged Packet Count - OutPktsUntagged */
-#define E1000_LSECTXPKTE      0x04304  /* LinkSec Encrypted Tx Packets Count - OutPktsEncrypted */
-#define E1000_LSECTXPKTP      0x04308  /* LinkSec Protected Tx Packet Count - OutPktsProtected */
-#define E1000_LSECTXOCTE      0x0430C  /* LinkSec Encrypted Tx Octets Count - OutOctetsEncrypted */
-#define E1000_LSECTXOCTP      0x04310  /* LinkSec Protected Tx Octets Count - OutOctetsProtected */
-#define E1000_LSECRXUT        0x04314  /* LinkSec Untagged non-Strict Rx Packet Count - InPktsUntagged/InPktsNoTag */
-#define E1000_LSECRXOCTD      0x0431C  /* LinkSec Rx Octets Decrypted Count - InOctetsDecrypted */
-#define E1000_LSECRXOCTV      0x04320  /* LinkSec Rx Octets Validated - InOctetsValidated */
-#define E1000_LSECRXBAD       0x04324  /* LinkSec Rx Bad Tag - InPktsBadTag */
-#define E1000_LSECRXNOSCI     0x04328  /* LinkSec Rx Packet No SCI Count - InPktsNoSci */
-#define E1000_LSECRXUNSCI     0x0432C  /* LinkSec Rx Packet Unknown SCI Count - InPktsUnknownSci */
-#define E1000_LSECRXUNCH      0x04330  /* LinkSec Rx Unchecked Packets Count - InPktsUnchecked */
-#define E1000_LSECRXDELAY     0x04340  /* LinkSec Rx Delayed Packet Count - InPktsDelayed */
-#define E1000_LSECRXLATE      0x04350  /* LinkSec Rx Late Packets Count - InPktsLate */
-#define E1000_LSECRXOK(_n)    (0x04360 + (0x04 * (_n))) /* LinkSec Rx Packet OK Count - InPktsOk */
-#define E1000_LSECRXINV(_n)   (0x04380 + (0x04 * (_n))) /* LinkSec Rx Invalid Count - InPktsInvalid */
-#define E1000_LSECRXNV(_n)    (0x043A0 + (0x04 * (_n))) /* LinkSec Rx Not Valid Count - InPktsNotValid */
-#define E1000_LSECRXUNSA      0x043C0  /* LinkSec Rx Unused SA Count - InPktsUnusedSa */
-#define E1000_LSECRXNUSA      0x043D0  /* LinkSec Rx Not Using SA Count - InPktsNotUsingSa */
-#define E1000_LSECTXCAP       0x0B000  /* LinkSec Tx Capabilities Register - RO */
-#define E1000_LSECRXCAP       0x0B300  /* LinkSec Rx Capabilities Register - RO */
-#define E1000_LSECTXCTRL      0x0B004  /* LinkSec Tx Control - RW */
-#define E1000_LSECRXCTRL      0x0B304  /* LinkSec Rx Control - RW */
-#define E1000_LSECTXSCL       0x0B008  /* LinkSec Tx SCI Low - RW */
-#define E1000_LSECTXSCH       0x0B00C  /* LinkSec Tx SCI High - RW */
-#define E1000_LSECTXSA        0x0B010  /* LinkSec Tx SA0 - RW */
-#define E1000_LSECTXPN0       0x0B018  /* LinkSec Tx SA PN 0 - RW */
-#define E1000_LSECTXPN1       0x0B01C  /* LinkSec Tx SA PN 1 - RW */
-#define E1000_LSECRXSCL       0x0B3D0  /* LinkSec Rx SCI Low - RW */
-#define E1000_LSECRXSCH       0x0B3E0  /* LinkSec Rx SCI High - RW */
-#define E1000_LSECTXKEY0(_n)  (0x0B020 + (0x04 * (_n))) /* LinkSec Tx 128-bit Key 0 - WO */
-#define E1000_LSECTXKEY1(_n)  (0x0B030 + (0x04 * (_n))) /* LinkSec Tx 128-bit Key 1 - WO */
-#define E1000_LSECRXSA(_n)    (0x0B310 + (0x04 * (_n))) /* LinkSec Rx SAs - RW */
-#define E1000_LSECRXPN(_n)    (0x0B330 + (0x04 * (_n))) /* LinkSec Rx SAs - RW */
+/* LinkSec */
+#define E1000_LSECTXUT		0x04300  /* Tx Untagged Pkt Cnt */
+#define E1000_LSECTXPKTE	0x04304  /* Encrypted Tx Pkts Cnt */
+#define E1000_LSECTXPKTP	0x04308  /* Protected Tx Pkt Cnt */
+#define E1000_LSECTXOCTE	0x0430C  /* Encrypted Tx Octets Cnt */
+#define E1000_LSECTXOCTP	0x04310  /* Protected Tx Octets Cnt */
+#define E1000_LSECRXUT		0x04314  /* Untagged non-Strict Rx Pkt Cnt */
+#define E1000_LSECRXOCTD	0x0431C  /* Rx Octets Decrypted Count */
+#define E1000_LSECRXOCTV	0x04320  /* Rx Octets Validated */
+#define E1000_LSECRXBAD		0x04324  /* Rx Bad Tag */
+#define E1000_LSECRXNOSCI	0x04328  /* Rx Packet No SCI Count */
+#define E1000_LSECRXUNSCI	0x0432C  /* Rx Packet Unknown SCI Count */
+#define E1000_LSECRXUNCH	0x04330  /* Rx Unchecked Packets Count */
+#define E1000_LSECRXDELAY	0x04340  /* Rx Delayed Packet Count */
+#define E1000_LSECRXLATE	0x04350  /* Rx Late Packets Count */
+#define E1000_LSECRXOK(_n)	(0x04360 + (0x04 * (_n))) /* Rx Pkt OK Cnt */
+#define E1000_LSECRXINV(_n)	(0x04380 + (0x04 * (_n))) /* Rx Invalid Cnt */
+#define E1000_LSECRXNV(_n)	(0x043A0 + (0x04 * (_n))) /* Rx Not Valid Cnt */
+#define E1000_LSECRXUNSA	0x043C0  /* Rx Unused SA Count */
+#define E1000_LSECRXNUSA	0x043D0  /* Rx Not Using SA Count */
+#define E1000_LSECTXCAP		0x0B000  /* Tx Capabilities Register - RO */
+#define E1000_LSECRXCAP		0x0B300  /* Rx Capabilities Register - RO */
+#define E1000_LSECTXCTRL	0x0B004  /* Tx Control - RW */
+#define E1000_LSECRXCTRL	0x0B304  /* Rx Control - RW */
+#define E1000_LSECTXSCL		0x0B008  /* Tx SCI Low - RW */
+#define E1000_LSECTXSCH		0x0B00C  /* Tx SCI High - RW */
+#define E1000_LSECTXSA		0x0B010  /* Tx SA0 - RW */
+#define E1000_LSECTXPN0		0x0B018  /* Tx SA PN 0 - RW */
+#define E1000_LSECTXPN1		0x0B01C  /* Tx SA PN 1 - RW */
+#define E1000_LSECRXSCL		0x0B3D0  /* Rx SCI Low - RW */
+#define E1000_LSECRXSCH		0x0B3E0  /* Rx SCI High - RW */
+/* LinkSec Tx 128-bit Key 0 - WO */
+#define E1000_LSECTXKEY0(_n)	(0x0B020 + (0x04 * (_n)))
+/* LinkSec Tx 128-bit Key 1 - WO */
+#define E1000_LSECTXKEY1(_n)	(0x0B030 + (0x04 * (_n)))
+#define E1000_LSECRXSA(_n)	(0x0B310 + (0x04 * (_n))) /* Rx SAs - RW */
+#define E1000_LSECRXPN(_n)	(0x0B330 + (0x04 * (_n))) /* Rx SAs - RW */
 /*
  * LinkSec Rx Keys  - where _n is the SA no. and _m the 4 dwords of the 128 bit
  * key - RW.
  */
-#define E1000_LSECRXKEY(_n, _m) (0x0B350 + (0x10 * (_n)) + (0x04 * (_m)))
+#define E1000_LSECRXKEY(_n, _m)	(0x0B350 + (0x10 * (_n)) + (0x04 * (_m)))
 
-#define E1000_SSVPC             0x041A0  /* Switch Security Violation Packet Count */
-#define E1000_IPSCTRL           0xB430   /* IpSec Control Register */
-#define E1000_IPSRXCMD          0x0B408  /* IPSec Rx Command Register - RW */
-#define E1000_IPSRXIDX          0x0B400  /* IPSec Rx Index - RW */
-#define E1000_IPSRXIPADDR(_n)   (0x0B420+ (0x04 * (_n)))  /* IPSec Rx IPv4/v6 Address - RW */
-#define E1000_IPSRXKEY(_n)      (0x0B410 + (0x04 * (_n))) /* IPSec Rx 128-bit Key - RW */
-#define E1000_IPSRXSALT         0x0B404  /* IPSec Rx Salt - RW */
-#define E1000_IPSRXSPI          0x0B40C  /* IPSec Rx SPI - RW */
-#define E1000_IPSTXKEY(_n)      (0x0B460 + (0x04 * (_n))) /* IPSec Tx 128-bit Key - RW */
-#define E1000_IPSTXSALT         0x0B454  /* IPSec Tx Salt - RW */
-#define E1000_IPSTXIDX          0x0B450  /* IPSec Tx SA IDX - RW */
-#define E1000_PCS_CFG0    0x04200  /* PCS Configuration 0 - RW */
-#define E1000_PCS_LCTL    0x04208  /* PCS Link Control - RW */
-#define E1000_PCS_LSTAT   0x0420C  /* PCS Link Status - RO */
-#define E1000_CBTMPC      0x0402C  /* Circuit Breaker Tx Packet Count */
-#define E1000_HTDPMC      0x0403C  /* Host Transmit Discarded Packets */
-#define E1000_CBRDPC      0x04044  /* Circuit Breaker Rx Dropped Count */
-#define E1000_CBRMPC      0x040FC  /* Circuit Breaker Rx Packet Count */
-#define E1000_RPTHC       0x04104  /* Rx Packets To Host */
-#define E1000_HGPTC       0x04118  /* Host Good Packets Tx Count */
-#define E1000_HTCBDPC     0x04124  /* Host Tx Circuit Breaker Dropped Count */
-#define E1000_HGORCL      0x04128  /* Host Good Octets Received Count Low */
-#define E1000_HGORCH      0x0412C  /* Host Good Octets Received Count High */
-#define E1000_HGOTCL      0x04130  /* Host Good Octets Transmit Count Low */
-#define E1000_HGOTCH      0x04134  /* Host Good Octets Transmit Count High */
-#define E1000_LENERRS     0x04138  /* Length Errors Count */
-#define E1000_SCVPC       0x04228  /* SerDes/SGMII Code Violation Pkt Count */
-#define E1000_HRMPC       0x0A018  /* Header Redirection Missed Packet Count */
-#define E1000_PCS_ANADV   0x04218  /* AN advertisement - RW */
-#define E1000_PCS_LPAB    0x0421C  /* Link Partner Ability - RW */
-#define E1000_PCS_NPTX    0x04220  /* AN Next Page Transmit - RW */
-#define E1000_PCS_LPABNP  0x04224  /* Link Partner Ability Next Page - RW */
-#define E1000_1GSTAT_RCV  0x04228  /* 1GSTAT Code Violation Packet Count - RW */
-#define E1000_RXCSUM   0x05000  /* Rx Checksum Control - RW */
-#define E1000_RLPML    0x05004  /* Rx Long Packet Max Length */
-#define E1000_RFCTL    0x05008  /* Receive Filter Control*/
-#define E1000_MTA      0x05200  /* Multicast Table Array - RW Array */
-#define E1000_RA       0x05400  /* Receive Address - RW Array */
-#define E1000_RA2      0x054E0  /* 2nd half of receive address array - RW Array */
-#define E1000_VFTA     0x05600  /* VLAN Filter Table Array - RW Array */
-#define E1000_VT_CTL   0x0581C  /* VMDq Control - RW */
-#define E1000_VFQA0    0x0B000  /* VLAN Filter Queue Array 0 - RW Array */
-#define E1000_VFQA1    0x0B200  /* VLAN Filter Queue Array 1 - RW Array */
-#define E1000_WUC      0x05800  /* Wakeup Control - RW */
-#define E1000_WUFC     0x05808  /* Wakeup Filter Control - RW */
-#define E1000_WUS      0x05810  /* Wakeup Status - RO */
-#define E1000_MANC     0x05820  /* Management Control - RW */
-#define E1000_IPAV     0x05838  /* IP Address Valid - RW */
-#define E1000_IP4AT    0x05840  /* IPv4 Address Table - RW Array */
-#define E1000_IP6AT    0x05880  /* IPv6 Address Table - RW Array */
-#define E1000_WUPL     0x05900  /* Wakeup Packet Length - RW */
-#define E1000_WUPM     0x05A00  /* Wakeup Packet Memory - RO A */
-#define E1000_PBACL    0x05B68  /* MSIx PBA Clear - Read/Write 1's to clear */
-#define E1000_FFLT     0x05F00  /* Flexible Filter Length Table - RW Array */
-#define E1000_HOST_IF  0x08800  /* Host Interface */
-#define E1000_FFMT     0x09000  /* Flexible Filter Mask Table - RW Array */
-#define E1000_FFVT     0x09800  /* Flexible Filter Value Table - RW Array */
-#define E1000_FHFT(_n)  (0x09000 + (_n * 0x100)) /* Flexible Host Filter Table */
-#define E1000_FHFT_EXT(_n) (0x09A00 + (_n * 0x100)) /* Ext Flexible Host Filter Table */
+#define E1000_SSVPC		0x041A0 /* Switch Security Violation Pkt Cnt */
+#define E1000_IPSCTRL		0xB430  /* IpSec Control Register */
+#define E1000_IPSRXCMD		0x0B408 /* IPSec Rx Command Register - RW */
+#define E1000_IPSRXIDX		0x0B400 /* IPSec Rx Index - RW */
+/* IPSec Rx IPv4/v6 Address - RW */
+#define E1000_IPSRXIPADDR(_n)	(0x0B420 + (0x04 * (_n)))
+/* IPSec Rx 128-bit Key - RW */
+#define E1000_IPSRXKEY(_n)	(0x0B410 + (0x04 * (_n)))
+#define E1000_IPSRXSALT		0x0B404  /* IPSec Rx Salt - RW */
+#define E1000_IPSRXSPI		0x0B40C  /* IPSec Rx SPI - RW */
+/* IPSec Tx 128-bit Key - RW */
+#define E1000_IPSTXKEY(_n)	(0x0B460 + (0x04 * (_n)))
+#define E1000_IPSTXSALT		0x0B454  /* IPSec Tx Salt - RW */
+#define E1000_IPSTXIDX		0x0B450  /* IPSec Tx SA IDX - RW */
+#define E1000_PCS_CFG0	0x04200  /* PCS Configuration 0 - RW */
+#define E1000_PCS_LCTL	0x04208  /* PCS Link Control - RW */
+#define E1000_PCS_LSTAT	0x0420C  /* PCS Link Status - RO */
+#define E1000_CBTMPC	0x0402C  /* Circuit Breaker Tx Packet Count */
+#define E1000_HTDPMC	0x0403C  /* Host Transmit Discarded Packets */
+#define E1000_CBRDPC	0x04044  /* Circuit Breaker Rx Dropped Count */
+#define E1000_CBRMPC	0x040FC  /* Circuit Breaker Rx Packet Count */
+#define E1000_RPTHC	0x04104  /* Rx Packets To Host */
+#define E1000_HGPTC	0x04118  /* Host Good Packets Tx Count */
+#define E1000_HTCBDPC	0x04124  /* Host Tx Circuit Breaker Dropped Count */
+#define E1000_HGORCL	0x04128  /* Host Good Octets Received Count Low */
+#define E1000_HGORCH	0x0412C  /* Host Good Octets Received Count High */
+#define E1000_HGOTCL	0x04130  /* Host Good Octets Transmit Count Low */
+#define E1000_HGOTCH	0x04134  /* Host Good Octets Transmit Count High */
+#define E1000_LENERRS	0x04138  /* Length Errors Count */
+#define E1000_SCVPC	0x04228  /* SerDes/SGMII Code Violation Pkt Count */
+#define E1000_HRMPC	0x0A018  /* Header Redirection Missed Packet Count */
+#define E1000_PCS_ANADV	0x04218  /* AN advertisement - RW */
+#define E1000_PCS_LPAB	0x0421C  /* Link Partner Ability - RW */
+#define E1000_PCS_NPTX	0x04220  /* AN Next Page Transmit - RW */
+#define E1000_PCS_LPABNP	0x04224 /* Link Partner Ability Next Pg - RW */
+#define E1000_1GSTAT_RCV	0x04228 /* 1GSTAT Code Violation Pkt Cnt - RW */
+#define E1000_RXCSUM	0x05000  /* Rx Checksum Control - RW */
+#define E1000_RLPML	0x05004  /* Rx Long Packet Max Length */
+#define E1000_RFCTL	0x05008  /* Receive Filter Control*/
+#define E1000_MTA	0x05200  /* Multicast Table Array - RW Array */
+#define E1000_RA	0x05400  /* Receive Address - RW Array */
+#define E1000_RA2	0x054E0  /* 2nd half of Rx address array - RW Array */
+#define E1000_VFTA	0x05600  /* VLAN Filter Table Array - RW Array */
+#define E1000_VT_CTL	0x0581C  /* VMDq Control - RW */
+#define E1000_CIAA	0x05B88  /* Config Indirect Access Address - RW */
+#define E1000_CIAD	0x05B8C  /* Config Indirect Access Data - RW */
+#define E1000_VFQA0	0x0B000  /* VLAN Filter Queue Array 0 - RW Array */
+#define E1000_VFQA1	0x0B200  /* VLAN Filter Queue Array 1 - RW Array */
+#define E1000_WUC	0x05800  /* Wakeup Control - RW */
+#define E1000_WUFC	0x05808  /* Wakeup Filter Control - RW */
+#define E1000_WUS	0x05810  /* Wakeup Status - RO */
+#define E1000_MANC	0x05820  /* Management Control - RW */
+#define E1000_IPAV	0x05838  /* IP Address Valid - RW */
+#define E1000_IP4AT	0x05840  /* IPv4 Address Table - RW Array */
+#define E1000_IP6AT	0x05880  /* IPv6 Address Table - RW Array */
+#define E1000_WUPL	0x05900  /* Wakeup Packet Length - RW */
+#define E1000_WUPM	0x05A00  /* Wakeup Packet Memory - RO A */
+#define E1000_PBACL	0x05B68  /* MSIx PBA Clear - Read/Write 1's to clear */
+#define E1000_FFLT	0x05F00  /* Flexible Filter Length Table - RW Array */
+#define E1000_HOST_IF	0x08800  /* Host Interface */
+#define E1000_FFMT	0x09000  /* Flexible Filter Mask Table - RW Array */
+#define E1000_FFVT	0x09800  /* Flexible Filter Value Table - RW Array */
+/* Flexible Host Filter Table */
+#define E1000_FHFT(_n)	(0x09000 + (_n * 0x100))
+/* Ext Flexible Host Filter Table */
+#define E1000_FHFT_EXT(_n)	(0x09A00 + (_n * 0x100))
 
 
-#define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */
-#define E1000_MDPHYA      0x0003C /* PHY address - RW */
-#define E1000_MANC2H      0x05860 /* Management Control To Host - RW */
-#define E1000_MDEF(_n)    (0x05890 + (4 * (_n))) /* Mngmt Decision Filters */
-#define E1000_SW_FW_SYNC  0x05B5C /* Software-Firmware Synchronization - RW */
-#define E1000_CCMCTL      0x05B48 /* CCM Control Register */
-#define E1000_GIOCTL      0x05B44 /* GIO Analog Control Register */
-#define E1000_SCCTL       0x05B4C /* PCIc PLL Configuration Register */
-#define E1000_GCR         0x05B00 /* PCI-Ex Control */
-#define E1000_GCR2        0x05B64 /* PCI-Ex Control #2 */
-#define E1000_GSCL_1    0x05B10 /* PCI-Ex Statistic Control #1 */
-#define E1000_GSCL_2    0x05B14 /* PCI-Ex Statistic Control #2 */
-#define E1000_GSCL_3    0x05B18 /* PCI-Ex Statistic Control #3 */
-#define E1000_GSCL_4    0x05B1C /* PCI-Ex Statistic Control #4 */
-#define E1000_FACTPS    0x05B30 /* Function Active and Power State to MNG */
-#define E1000_SWSM      0x05B50 /* SW Semaphore */
-#define E1000_FWSM      0x05B54 /* FW Semaphore */
-#define E1000_SWSM2     0x05B58 /* Driver-only SW semaphore (not used by BOOT agents) */
-#define E1000_DCA_ID    0x05B70 /* DCA Requester ID Information - RO */
-#define E1000_DCA_CTRL  0x05B74 /* DCA Control - RW */
-#define E1000_UFUSE     0x05B78 /* UFUSE - RO */
-#define E1000_FFLT_DBG  0x05F04 /* Debug Register */
-#define E1000_HICR      0x08F00 /* Host Interface Control */
-#define E1000_FWSTS     0x08F0C /* FW Status */
+#define E1000_KMRNCTRLSTA	0x00034 /* MAC-PHY interface - RW */
+#define E1000_MDPHYA		0x0003C /* PHY address - RW */
+#define E1000_MANC2H		0x05860 /* Management Control To Host - RW */
+/* Management Decision Filters */
+#define E1000_MDEF(_n)		(0x05890 + (4 * (_n)))
+#define E1000_SW_FW_SYNC	0x05B5C /* SW-FW Synchronization - RW */
+#define E1000_CCMCTL	0x05B48 /* CCM Control Register */
+#define E1000_GIOCTL	0x05B44 /* GIO Analog Control Register */
+#define E1000_SCCTL	0x05B4C /* PCIc PLL Configuration Register */
+#define E1000_GCR	0x05B00 /* PCI-Ex Control */
+#define E1000_GCR2	0x05B64 /* PCI-Ex Control #2 */
+#define E1000_GSCL_1	0x05B10 /* PCI-Ex Statistic Control #1 */
+#define E1000_GSCL_2	0x05B14 /* PCI-Ex Statistic Control #2 */
+#define E1000_GSCL_3	0x05B18 /* PCI-Ex Statistic Control #3 */
+#define E1000_GSCL_4	0x05B1C /* PCI-Ex Statistic Control #4 */
+#define E1000_FACTPS	0x05B30 /* Function Active and Power State to MNG */
+#define E1000_SWSM	0x05B50 /* SW Semaphore */
+#define E1000_FWSM	0x05B54 /* FW Semaphore */
+/* Driver-only SW semaphore (not used by BOOT agents) */
+#define E1000_SWSM2	0x05B58
+#define E1000_DCA_ID	0x05B70 /* DCA Requester ID Information - RO */
+#define E1000_DCA_CTRL	0x05B74 /* DCA Control - RW */
+#define E1000_UFUSE	0x05B78 /* UFUSE - RO */
+#define E1000_FFLT_DBG	0x05F04 /* Debug Register */
+#define E1000_HICR	0x08F00 /* Host Interface Control */
+#define E1000_FWSTS	0x08F0C /* FW Status */
 
 /* RSS registers */
-#define E1000_CPUVEC    0x02C10 /* CPU Vector Register - RW */
-#define E1000_MRQC      0x05818 /* Multiple Receive Control - RW */
-#define E1000_IMIR(_i)      (0x05A80 + ((_i) * 4))  /* Immediate Interrupt */
-#define E1000_IMIREXT(_i)   (0x05AA0 + ((_i) * 4))  /* Immediate Interrupt Ext*/
-#define E1000_IMIRVP    0x05AC0 /* Immediate Interrupt Rx VLAN Priority - RW */
-#define E1000_MSIXBM(_i)    (0x01600 + ((_i) * 4)) /* MSI-X Allocation Register
-                                                    * (_i) - RW */
-#define E1000_MSIXTADD(_i)  (0x0C000 + ((_i) * 0x10)) /* MSI-X Table entry addr
-                                                       * low reg - RW */
-#define E1000_MSIXTUADD(_i) (0x0C004 + ((_i) * 0x10)) /* MSI-X Table entry addr
-                                                       * upper reg - RW */
-#define E1000_MSIXTMSG(_i)  (0x0C008 + ((_i) * 0x10)) /* MSI-X Table entry
-                                                       * message reg - RW */
-#define E1000_MSIXVCTRL(_i) (0x0C00C + ((_i) * 0x10)) /* MSI-X Table entry
-                                                       * vector ctrl reg - RW */
-#define E1000_MSIXPBA    0x0E000 /* MSI-X Pending bit array */
-#define E1000_RETA(_i)  (0x05C00 + ((_i) * 4)) /* Redirection Table - RW */
-#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */
-#define E1000_RSSIM     0x05864 /* RSS Interrupt Mask */
-#define E1000_RSSIR     0x05868 /* RSS Interrupt Request */
+#define E1000_CPUVEC	0x02C10 /* CPU Vector Register - RW */
+#define E1000_MRQC	0x05818 /* Multiple Receive Control - RW */
+#define E1000_IMIR(_i)	(0x05A80 + ((_i) * 4))  /* Immediate Interrupt */
+#define E1000_IMIREXT(_i)	(0x05AA0 + ((_i) * 4)) /* Immediate INTR Ext*/
+#define E1000_IMIRVP		0x05AC0 /* Immediate INT Rx VLAN Priority -RW */
+#define E1000_MSIXBM(_i)	(0x01600 + ((_i) * 4)) /* MSI-X Alloc Reg -RW */
+/* MSI-X Table entry addr low reg - RW */
+#define E1000_MSIXTADD(_i)	(0x0C000 + ((_i) * 0x10))
+/* MSI-X Table entry addr upper reg - RW */
+#define E1000_MSIXTUADD(_i)	(0x0C004 + ((_i) * 0x10))
+/* MSI-X Table entry message reg - RW */
+#define E1000_MSIXTMSG(_i)	(0x0C008 + ((_i) * 0x10))
+/* MSI-X Table entry vector ctrl reg - RW */
+#define E1000_MSIXVCTRL(_i)	(0x0C00C + ((_i) * 0x10))
+#define E1000_MSIXPBA	0x0E000 /* MSI-X Pending bit array */
+#define E1000_RETA(_i)	(0x05C00 + ((_i) * 4)) /* Redirection Table - RW */
+#define E1000_RSSRK(_i)	(0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */
+#define E1000_RSSIM	0x05864 /* RSS Interrupt Mask */
+#define E1000_RSSIR	0x05868 /* RSS Interrupt Request */
 /* VT Registers */
-#define E1000_SWPBS     0x03004 /* Switch Packet Buffer Size - RW */
-#define E1000_MBVFICR   0x00C80 /* Mailbox VF Cause - RWC */
-#define E1000_MBVFIMR   0x00C84 /* Mailbox VF int Mask - RW */
-#define E1000_VFLRE     0x00C88 /* VF Register Events - RWC */
-#define E1000_VFRE      0x00C8C /* VF Receive Enables */
-#define E1000_VFTE      0x00C90 /* VF Transmit Enables */
-#define E1000_QDE       0x02408 /* Queue Drop Enable - RW */
-#define E1000_DTXSWC    0x03500 /* DMA Tx Switch Control - RW */
-#define E1000_WVBR      0x03554 /* VM Wrong Behavior - RWS */
-#define E1000_RPLOLR    0x05AF0 /* Replication Offload - RW */
-#define E1000_UTA       0x0A000 /* Unicast Table Array - RW */
-#define E1000_IOVTCL    0x05BBC /* IOV Control Register */
-#define E1000_VMRCTL    0X05D80 /* Virtual Mirror Rule Control */
-#define E1000_VMRVLAN   0x05D90 /* Virtual Mirror Rule VLAN */
-#define E1000_VMRVM     0x05DA0 /* Virtual Mirror Rule VM */
-#define E1000_MDFB      0x03558 /* Malicious Driver free block */
-#define E1000_LVMMC     0x03548 /* Last VM Misbehavior cause */
-#define E1000_TXSWC     0x05ACC /* Tx Switch Control */
-#define E1000_SCCRL     0x05DB0 /* Storm Control Control */
-#define E1000_BSCTRH    0x05DB8 /* Broadcast Storm Control Threshold */
-#define E1000_MSCTRH    0x05DBC /* Multicast Storm Control Threshold */
+#define E1000_SWPBS	0x03004 /* Switch Packet Buffer Size - RW */
+#define E1000_MBVFICR	0x00C80 /* Mailbox VF Cause - RWC */
+#define E1000_MBVFIMR	0x00C84 /* Mailbox VF int Mask - RW */
+#define E1000_VFLRE	0x00C88 /* VF Register Events - RWC */
+#define E1000_VFRE	0x00C8C /* VF Receive Enables */
+#define E1000_VFTE	0x00C90 /* VF Transmit Enables */
+#define E1000_QDE	0x02408 /* Queue Drop Enable - RW */
+#define E1000_DTXSWC	0x03500 /* DMA Tx Switch Control - RW */
+#define E1000_WVBR	0x03554 /* VM Wrong Behavior - RWS */
+#define E1000_RPLOLR	0x05AF0 /* Replication Offload - RW */
+#define E1000_UTA	0x0A000 /* Unicast Table Array - RW */
+#define E1000_IOVTCL	0x05BBC /* IOV Control Register */
+#define E1000_VMRCTL	0X05D80 /* Virtual Mirror Rule Control */
+#define E1000_VMRVLAN	0x05D90 /* Virtual Mirror Rule VLAN */
+#define E1000_VMRVM	0x05DA0 /* Virtual Mirror Rule VM */
+#define E1000_MDFB	0x03558 /* Malicious Driver free block */
+#define E1000_LVMMC	0x03548 /* Last VM Misbehavior cause */
+#define E1000_TXSWC	0x05ACC /* Tx Switch Control */
+#define E1000_SCCRL	0x05DB0 /* Storm Control Control */
+#define E1000_BSCTRH	0x05DB8 /* Broadcast Storm Control Threshold */
+#define E1000_MSCTRH	0x05DBC /* Multicast Storm Control Threshold */
 /* These act per VF so an array friendly macro is used */
-#define E1000_V2PMAILBOX(_n)   (0x00C40 + (4 * (_n)))
-#define E1000_P2VMAILBOX(_n)   (0x00C00 + (4 * (_n)))
-#define E1000_VMBMEM(_n)       (0x00800 + (64 * (_n)))
-#define E1000_VFVMBMEM(_n)     (0x00800 + (_n))
-#define E1000_VMOLR(_n)        (0x05AD0 + (4 * (_n)))
-#define E1000_VLVF(_n)         (0x05D00 + (4 * (_n))) /* VLAN Virtual Machine
-                                                       * Filter - RW */
-#define E1000_VMVIR(_n)        (0x03700 + (4 * (_n)))
-#define E1000_DVMOLR(_n)       (0x0C038 + (0x40 * (_n))) /* DMA VM offload */
-/* Time Sync */
-#define E1000_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */
-#define E1000_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */
-#define E1000_TSYNCRXCFG 0x05F50 /* Time Sync Rx Configuration - RW */
-#define E1000_RXSTMPL    0x0B624 /* Rx timestamp Low - RO */
-#define E1000_RXSTMPH    0x0B628 /* Rx timestamp High - RO */
-#define E1000_RXSATRL    0x0B62C /* Rx timestamp attribute low - RO */
-#define E1000_RXSATRH    0x0B630 /* Rx timestamp attribute high - RO */
-#define E1000_TXSTMPL    0x0B618 /* Tx timestamp value Low - RO */
-#define E1000_TXSTMPH    0x0B61C /* Tx timestamp value High - RO */
-#define E1000_SYSTIML    0x0B600 /* System time register Low - RO */
-#define E1000_SYSTIMH    0x0B604 /* System time register High - RO */
-#define E1000_TIMINCA    0x0B608 /* Increment attributes register - RW */
-#define E1000_TSAUXC     0x0B640 /* Timesync Auxiliary Control register */
-#define E1000_SYSTIMR    0x0B6F8 /* System time register Residue */
-#define E1000_RXMTRL     0x0B634 /* Time sync Rx EtherType and Msg Type - RW */
-#define E1000_RXUDP      0x0B638 /* Time Sync Rx UDP Port - RW */
+#define E1000_V2PMAILBOX(_n)	(0x00C40 + (4 * (_n)))
+#define E1000_P2VMAILBOX(_n)	(0x00C00 + (4 * (_n)))
+#define E1000_VMBMEM(_n)	(0x00800 + (64 * (_n)))
+#define E1000_VFVMBMEM(_n)	(0x00800 + (_n))
+#define E1000_VMOLR(_n)		(0x05AD0 + (4 * (_n)))
+/* VLAN Virtual Machine Filter - RW */
+#define E1000_VLVF(_n)		(0x05D00 + (4 * (_n)))
+#define E1000_VMVIR(_n)		(0x03700 + (4 * (_n)))
+#define E1000_DVMOLR(_n)	(0x0C038 + (0x40 * (_n))) /* DMA VM offload */
+#define E1000_VTCTRL(_n)	(0x10000 + (0x100 * (_n))) /* VT Control */
+#define E1000_TSYNCRXCTL	0x0B620 /* Rx Time Sync Control register - RW */
+#define E1000_TSYNCTXCTL	0x0B614 /* Tx Time Sync Control register - RW */
+#define E1000_TSYNCRXCFG	0x05F50 /* Time Sync Rx Configuration - RW */
+#define E1000_RXSTMPL	0x0B624 /* Rx timestamp Low - RO */
+#define E1000_RXSTMPH	0x0B628 /* Rx timestamp High - RO */
+#define E1000_RXSATRL	0x0B62C /* Rx timestamp attribute low - RO */
+#define E1000_RXSATRH	0x0B630 /* Rx timestamp attribute high - RO */
+#define E1000_TXSTMPL	0x0B618 /* Tx timestamp value Low - RO */
+#define E1000_TXSTMPH	0x0B61C /* Tx timestamp value High - RO */
+#define E1000_SYSTIML	0x0B600 /* System time register Low - RO */
+#define E1000_SYSTIMH	0x0B604 /* System time register High - RO */
+#define E1000_TIMINCA	0x0B608 /* Increment attributes register - RW */
+#define E1000_TSAUXC	0x0B640 /* Timesync Auxiliary Control register */
+#define E1000_SYSTIMR	0x0B6F8 /* System time register Residue */
+#define E1000_RXMTRL	0x0B634 /* Time sync Rx EtherType and Msg Type - RW */
+#define E1000_RXUDP	0x0B638 /* Time Sync Rx UDP Port - RW */
 
 /* Filtering Registers */
-#define E1000_SAQF(_n)  (0x05980 + (4 * (_n))) /* Source Address Queue Fltr */
-#define E1000_DAQF(_n)  (0x059A0 + (4 * (_n))) /* Dest Address Queue Fltr */
-#define E1000_SPQF(_n)  (0x059C0 + (4 * (_n))) /* Source Port Queue Fltr */
-#define E1000_FTQF(_n)  (0x059E0 + (4 * (_n))) /* 5-tuple Queue Fltr */
-#define E1000_TTQF(_n)  (0x059E0 + (4 * (_n))) /* 2-tuple Queue Fltr */
-#define E1000_SYNQF(_n) (0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */
-#define E1000_ETQF(_n)  (0x05CB0 + (4 * (_n))) /* EType Queue Fltr */
+#define E1000_SAQF(_n)	(0x05980 + (4 * (_n))) /* Source Address Queue Fltr */
+#define E1000_DAQF(_n)	(0x059A0 + (4 * (_n))) /* Dest Address Queue Fltr */
+#define E1000_SPQF(_n)	(0x059C0 + (4 * (_n))) /* Source Port Queue Fltr */
+#define E1000_FTQF(_n)	(0x059E0 + (4 * (_n))) /* 5-tuple Queue Fltr */
+#define E1000_TTQF(_n)	(0x059E0 + (4 * (_n))) /* 2-tuple Queue Fltr */
+#define E1000_SYNQF(_n)	(0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */
+#define E1000_ETQF(_n)	(0x05CB0 + (4 * (_n))) /* EType Queue Fltr */
 
-#define E1000_RTTDCS            0x3600  /* Reedtown Tx Desc plane control and status */
-#define E1000_RTTPCS            0x3474  /* Reedtown Tx Packet Plane control and status */
-#define E1000_RTRPCS            0x2474  /* Rx packet plane control and status */
-#define E1000_RTRUP2TC          0x05AC4 /* Rx User Priority to Traffic Class */
-#define E1000_RTTUP2TC          0x0418  /* Transmit User Priority to Traffic Class */
-#define E1000_RTTDTCRC(_n)      (0x3610 + ((_n) * 4)) /* Tx Desc plane TC Rate-scheduler config */
-#define E1000_RTTPTCRC(_n)      (0x3480 + ((_n) * 4)) /* Tx Packet plane TC Rate-Scheduler Config */
-#define E1000_RTRPTCRC(_n)      (0x2480 + ((_n) * 4)) /* Rx Packet plane TC Rate-Scheduler Config */
-#define E1000_RTTDTCRS(_n)      (0x3630 + ((_n) * 4)) /* Tx Desc Plane TC Rate-Scheduler Status */
-#define E1000_RTTDTCRM(_n)      (0x3650 + ((_n) * 4)) /* Tx Desc Plane TC Rate-Scheduler MMW */
-#define E1000_RTTPTCRS(_n)      (0x34A0 + ((_n) * 4)) /* Tx Packet plane TC Rate-Scheduler Status */
-#define E1000_RTTPTCRM(_n)      (0x34C0 + ((_n) * 4)) /* Tx Packet plane TC Rate-scheduler MMW */
-#define E1000_RTRPTCRS(_n)      (0x24A0 + ((_n) * 4)) /* Rx Packet plane TC Rate-Scheduler Status */
-#define E1000_RTRPTCRM(_n)      (0x24C0 + ((_n) * 4)) /* Rx Packet plane TC Rate-Scheduler MMW */
-#define E1000_RTTDVMRM(_n)      (0x3670 + ((_n) * 4)) /* Tx Desc plane VM Rate-Scheduler MMW*/
-#define E1000_RTTBCNRM(_n)      (0x3690 + ((_n) * 4)) /* Tx BCN Rate-Scheduler MMW */
-#define E1000_RTTDQSEL          0x3604  /* Tx Desc Plane Queue Select */
-#define E1000_RTTDVMRC          0x3608  /* Tx Desc Plane VM Rate-Scheduler Config */
-#define E1000_RTTDVMRS          0x360C  /* Tx Desc Plane VM Rate-Scheduler Status */
-#define E1000_RTTBCNRC          0x36B0  /* Tx BCN Rate-Scheduler Config */
-#define E1000_RTTBCNRS          0x36B4  /* Tx BCN Rate-Scheduler Status */
-#define E1000_RTTBCNCR          0xB200  /* Tx BCN Control Register */
-#define E1000_RTTBCNTG          0x35A4  /* Tx BCN Tagging */
-#define E1000_RTTBCNCP          0xB208  /* Tx BCN Congestion point */
-#define E1000_RTRBCNCR          0xB20C  /* Rx BCN Control Register */
-#define E1000_RTTBCNRD          0x36B8  /* Tx BCN Rate Drift */
-#define E1000_PFCTOP            0x1080  /* Priority Flow Control Type and Opcode */
-#define E1000_RTTBCNIDX         0xB204  /* Tx BCN Congestion Point */
-#define E1000_RTTBCNACH         0x0B214 /* Tx BCN Control High */
-#define E1000_RTTBCNACL         0x0B210 /* Tx BCN Control Low */
+#define E1000_RTTDCS	0x3600 /* Reedtown Tx Desc plane control and status */
+#define E1000_RTTPCS	0x3474 /* Reedtown Tx Packet Plane control and status */
+#define E1000_RTRPCS	0x2474 /* Rx packet plane control and status */
+#define E1000_RTRUP2TC	0x05AC4 /* Rx User Priority to Traffic Class */
+#define E1000_RTTUP2TC	0x0418 /* Transmit User Priority to Traffic Class */
+/* Tx Desc plane TC Rate-scheduler config */
+#define E1000_RTTDTCRC(_n)	(0x3610 + ((_n) * 4))
+/* Tx Packet plane TC Rate-Scheduler Config */
+#define E1000_RTTPTCRC(_n)	(0x3480 + ((_n) * 4))
+/* Rx Packet plane TC Rate-Scheduler Config */
+#define E1000_RTRPTCRC(_n)	(0x2480 + ((_n) * 4))
+/* Tx Desc Plane TC Rate-Scheduler Status */
+#define E1000_RTTDTCRS(_n)	(0x3630 + ((_n) * 4))
+/* Tx Desc Plane TC Rate-Scheduler MMW */
+#define E1000_RTTDTCRM(_n)	(0x3650 + ((_n) * 4))
+/* Tx Packet plane TC Rate-Scheduler Status */
+#define E1000_RTTPTCRS(_n)	(0x34A0 + ((_n) * 4))
+/* Tx Packet plane TC Rate-scheduler MMW */
+#define E1000_RTTPTCRM(_n)	(0x34C0 + ((_n) * 4))
+/* Rx Packet plane TC Rate-Scheduler Status */
+#define E1000_RTRPTCRS(_n)	(0x24A0 + ((_n) * 4))
+/* Rx Packet plane TC Rate-Scheduler MMW */
+#define E1000_RTRPTCRM(_n)	(0x24C0 + ((_n) * 4))
+/* Tx Desc plane VM Rate-Scheduler MMW*/
+#define E1000_RTTDVMRM(_n)	(0x3670 + ((_n) * 4))
+/* Tx BCN Rate-Scheduler MMW */
+#define E1000_RTTBCNRM(_n)	(0x3690 + ((_n) * 4))
+#define E1000_RTTDQSEL	0x3604  /* Tx Desc Plane Queue Select */
+#define E1000_RTTDVMRC	0x3608  /* Tx Desc Plane VM Rate-Scheduler Config */
+#define E1000_RTTDVMRS	0x360C  /* Tx Desc Plane VM Rate-Scheduler Status */
+#define E1000_RTTBCNRC	0x36B0  /* Tx BCN Rate-Scheduler Config */
+#define E1000_RTTBCNRS	0x36B4  /* Tx BCN Rate-Scheduler Status */
+#define E1000_RTTBCNCR	0xB200  /* Tx BCN Control Register */
+#define E1000_RTTBCNTG	0x35A4  /* Tx BCN Tagging */
+#define E1000_RTTBCNCP	0xB208  /* Tx BCN Congestion point */
+#define E1000_RTRBCNCR	0xB20C  /* Rx BCN Control Register */
+#define E1000_RTTBCNRD	0x36B8  /* Tx BCN Rate Drift */
+#define E1000_PFCTOP	0x1080  /* Priority Flow Control Type and Opcode */
+#define E1000_RTTBCNIDX	0xB204  /* Tx BCN Congestion Point */
+#define E1000_RTTBCNACH	0x0B214 /* Tx BCN Control High */
+#define E1000_RTTBCNACL	0x0B210 /* Tx BCN Control Low */
 
 /* DMA Coalescing registers */
-#define E1000_DMACR             0x02508 /* Control Register */
-#define E1000_DMCTXTH           0x03550 /* Transmit Threshold */
-#define E1000_DMCTLX            0x02514 /* Time to Lx Request */
-#define E1000_DMCRTRH           0x05DD0 /* Receive Packet Rate Threshold */
-#define E1000_DMCCNT            0x05DD4 /* Current Rx Count */
-#define E1000_FCRTC             0x02170 /* Flow Control Rx high watermark */
-#define E1000_PCIEMISC          0x05BB8 /* PCIE misc config register */
+#define E1000_DMACR	0x02508 /* Control Register */
+#define E1000_DMCTXTH	0x03550 /* Transmit Threshold */
+#define E1000_DMCTLX	0x02514 /* Time to Lx Request */
+#define E1000_DMCRTRH	0x05DD0 /* Receive Packet Rate Threshold */
+#define E1000_DMCCNT	0x05DD4 /* Current Rx Count */
+#define E1000_FCRTC	0x02170 /* Flow Control Rx high watermark */
+#define E1000_PCIEMISC	0x05BB8 /* PCIE misc config register */
 
 /* PCIe Parity Status Register */
-#define E1000_PCIEERRSTS        0x05BA8
+#define E1000_PCIEERRSTS	0x05BA8
 
-#define E1000_PROXYS            0x5F64 /* Proxying Status */
-#define E1000_PROXYFC           0x5F60 /* Proxying Filter Control */
+#define E1000_LTRMINV	0x5BB0 /* LTR Minimum Value */
+#define E1000_LTRMAXV	0x5BB4 /* LTR Maximum Value */
+#define E1000_DOBFFCTL	0x3F24 /* DMA OBFF Control Register */
+
+#define E1000_PROXYS	0x5F64 /* Proxying Status */
+#define E1000_PROXYFC	0x5F60 /* Proxying Filter Control */
 /* Thermal sensor configuration and status registers */
-#define E1000_THMJT             0x08100 /* Junction Temperature */
-#define E1000_THLOWTC           0x08104 /* Low Threshold Control */
-#define E1000_THMIDTC           0x08108 /* Mid Threshold Control */
-#define E1000_THHIGHTC          0x0810C /* High Threshold Control */
-#define E1000_THSTAT            0x08110 /* Thermal Sensor Status */
+#define E1000_THMJT	0x08100 /* Junction Temperature */
+#define E1000_THLOWTC	0x08104 /* Low Threshold Control */
+#define E1000_THMIDTC	0x08108 /* Mid Threshold Control */
+#define E1000_THHIGHTC	0x0810C /* High Threshold Control */
+#define E1000_THSTAT	0x08110 /* Thermal Sensor Status */
 
 /*Energy Efficient Ethernet "EEE" registers */
-#define E1000_IPCNFG            0x0E38 /* Internal PHY Configuration */
-#define E1000_LTRC              0x01A0 /* Latency Tolerance Reporting Control */
-#define E1000_EEER              0x0E30 /* Energy Efficient Ethernet "EEE"*/
-#define E1000_EEE_SU            0x0E34 /* EEE Setup */
-#define E1000_TLPIC             0x4148 /* EEE Tx LPI Count - TLPIC */
-#define E1000_RLPIC             0x414C /* EEE Rx LPI Count - RLPIC */
+#define E1000_IPCNFG	0x0E38 /* Internal PHY Configuration */
+#define E1000_LTRC	0x01A0 /* Latency Tolerance Reporting Control */
+#define E1000_EEER	0x0E30 /* Energy Efficient Ethernet "EEE"*/
+#define E1000_EEE_SU	0x0E34 /* EEE Setup */
+#define E1000_TLPIC	0x4148 /* EEE Tx LPI Count - TLPIC */
+#define E1000_RLPIC	0x414C /* EEE Rx LPI Count - RLPIC */
 
 /* OS2BMC Registers */
-#define E1000_B2OSPC            0x08FE0 /* BMC2OS packets sent by BMC */
-#define E1000_B2OGPRC           0x04158 /* BMC2OS packets received by host */
-#define E1000_O2BGPTC           0x08FE4 /* OS2BMC packets received by BMC */
-#define E1000_O2BSPC            0x0415C /* OS2BMC packets transmitted by host */
+#define E1000_B2OSPC	0x08FE0 /* BMC2OS packets sent by BMC */
+#define E1000_B2OGPRC	0x04158 /* BMC2OS packets received by host */
+#define E1000_O2BGPTC	0x08FE4 /* OS2BMC packets received by BMC */
+#define E1000_O2BSPC	0x0415C /* OS2BMC packets transmitted by host */
 
 #endif
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/e1000/e1000_vf.c
--- a/head/sys/dev/e1000/e1000_vf.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/e1000/e1000_vf.c	Thu Dec 15 12:59:38 2011 +0200
@@ -1,6 +1,6 @@
 /******************************************************************************
 
-  Copyright (c) 2001-2010, Intel Corporation 
+  Copyright (c) 2001-2011, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
@@ -30,27 +30,27 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD$*/
+/*$FreeBSD: head/sys/dev/e1000/e1000_vf.c 228386 2011-12-10 06:55:02Z jfv $*/
 
 
 #include "e1000_api.h"
 
 
-static s32       e1000_init_phy_params_vf(struct e1000_hw *hw);
-static s32       e1000_init_nvm_params_vf(struct e1000_hw *hw);
-static void      e1000_release_vf(struct e1000_hw *hw);
-static s32       e1000_acquire_vf(struct e1000_hw *hw);
-static s32       e1000_setup_link_vf(struct e1000_hw *hw);
-static s32       e1000_get_bus_info_pcie_vf(struct e1000_hw *hw);
-static s32       e1000_init_mac_params_vf(struct e1000_hw *hw);
-static s32       e1000_check_for_link_vf(struct e1000_hw *hw);
-static s32       e1000_get_link_up_info_vf(struct e1000_hw *hw, u16 *speed,
-                                              u16 *duplex);
-static s32       e1000_init_hw_vf(struct e1000_hw *hw);
-static s32       e1000_reset_hw_vf(struct e1000_hw *hw);
-static void      e1000_update_mc_addr_list_vf(struct e1000_hw *hw, u8 *, u32);
-static void      e1000_rar_set_vf(struct e1000_hw *, u8 *, u32);
-static s32       e1000_read_mac_addr_vf(struct e1000_hw *);
+static s32 e1000_init_phy_params_vf(struct e1000_hw *hw);
+static s32 e1000_init_nvm_params_vf(struct e1000_hw *hw);
+static void e1000_release_vf(struct e1000_hw *hw);
+static s32 e1000_acquire_vf(struct e1000_hw *hw);
+static s32 e1000_setup_link_vf(struct e1000_hw *hw);
+static s32 e1000_get_bus_info_pcie_vf(struct e1000_hw *hw);
+static s32 e1000_init_mac_params_vf(struct e1000_hw *hw);
+static s32 e1000_check_for_link_vf(struct e1000_hw *hw);
+static s32 e1000_get_link_up_info_vf(struct e1000_hw *hw, u16 *speed,
+				     u16 *duplex);
+static s32 e1000_init_hw_vf(struct e1000_hw *hw);
+static s32 e1000_reset_hw_vf(struct e1000_hw *hw);
+static void e1000_update_mc_addr_list_vf(struct e1000_hw *hw, u8 *, u32);
+static void e1000_rar_set_vf(struct e1000_hw *, u8 *, u32);
+static s32 e1000_read_mac_addr_vf(struct e1000_hw *);
 
 /**
  *  e1000_init_phy_params_vf - Inits PHY params
@@ -219,7 +219,7 @@
  *  the status register's data which is often stale and inaccurate.
  **/
 static s32 e1000_get_link_up_info_vf(struct e1000_hw *hw, u16 *speed,
-                                     u16 *duplex)
+				     u16 *duplex)
 {
 	s32 status;
 
@@ -288,7 +288,7 @@
 		ret_val = mbx->ops.read_posted(hw, msgbuf, 3, 0);
 		if (!ret_val) {
 			if (msgbuf[0] == (E1000_VF_RESET |
-						E1000_VT_MSGTYPE_ACK))
+			    E1000_VT_MSGTYPE_ACK))
 				memcpy(hw->mac.perm_addr, addr, 6);
 			else
 				ret_val = -E1000_ERR_MAC_INIT;
@@ -369,11 +369,22 @@
 		bit_shift++;
 
 	hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
-	                          (((u16) mc_addr[5]) << bit_shift)));
+				  (((u16) mc_addr[5]) << bit_shift)));
 
 	return hash_value;
 }
 
+static void e1000_write_msg_read_ack(struct e1000_hw *hw,
+				     u32 *msg, u16 size)
+{
+	struct e1000_mbx_info *mbx = &hw->mbx;
+	u32 retmsg[E1000_VFMAILBOX_SIZE];
+	s32 retval = mbx->ops.write_posted(hw, msg, size, 0);
+
+	if (!retval)
+		mbx->ops.read_posted(hw, retmsg, E1000_VFMAILBOX_SIZE, 0);
+}
+
 /**
  *  e1000_update_mc_addr_list_vf - Update Multicast addresses
  *  @hw: pointer to the HW structure
@@ -384,9 +395,8 @@
  *  The caller must have a packed mc_addr_list of multicast addresses.
  **/
 void e1000_update_mc_addr_list_vf(struct e1000_hw *hw,
-                                  u8 *mc_addr_list, u32 mc_addr_count)
+				  u8 *mc_addr_list, u32 mc_addr_count)
 {
-	struct e1000_mbx_info *mbx = &hw->mbx;
 	u32 msgbuf[E1000_VFMAILBOX_SIZE];
 	u16 *hash_list = (u16 *)&msgbuf[1];
 	u32 hash_value;
@@ -420,7 +430,7 @@
 		mc_addr_list += ETH_ADDR_LEN;
 	}
 
-	mbx->ops.write_posted(hw, msgbuf, E1000_VFMAILBOX_SIZE, 0);
+	e1000_write_msg_read_ack(hw, msgbuf, E1000_VFMAILBOX_SIZE);
 }
 
 /**
@@ -431,7 +441,6 @@
  **/
 void e1000_vfta_set_vf(struct e1000_hw *hw, u16 vid, bool set)
 {
-	struct e1000_mbx_info *mbx = &hw->mbx;
 	u32 msgbuf[2];
 
 	msgbuf[0] = E1000_VF_SET_VLAN;
@@ -440,7 +449,7 @@
 	if (set)
 		msgbuf[0] |= E1000_VF_SET_VLAN_ADD;
 
-	mbx->ops.write_posted(hw, msgbuf, 2, 0);
+	e1000_write_msg_read_ack(hw, msgbuf, 2);
 }
 
 /** e1000_rlpml_set_vf - Set the maximum receive packet length
@@ -449,13 +458,12 @@
  **/
 void e1000_rlpml_set_vf(struct e1000_hw *hw, u16 max_size)
 {
-	struct e1000_mbx_info *mbx = &hw->mbx;
 	u32 msgbuf[2];
 
 	msgbuf[0] = E1000_VF_SET_LPE;
 	msgbuf[1] = max_size;
 
-	mbx->ops.write_posted(hw, msgbuf, 2, 0);
+	e1000_write_msg_read_ack(hw, msgbuf, 2);
 }
 
 /**
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/e1000/if_em.c
--- a/head/sys/dev/e1000/if_em.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/e1000/if_em.c	Thu Dec 15 12:59:38 2011 +0200
@@ -30,11 +30,12 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD: head/sys/dev/e1000/if_em.c 228281 2011-12-05 15:33:13Z luigi $*/
+/*$FreeBSD: head/sys/dev/e1000/if_em.c 228415 2011-12-11 18:46:14Z jfv $*/
 
 #ifdef HAVE_KERNEL_OPTION_HEADERS
 #include "opt_device_polling.h"
 #include "opt_inet.h"
+#include "opt_inet6.h"
 #endif
 
 #include <sys/param.h>
@@ -93,7 +94,7 @@
 /*********************************************************************
  *  Driver version:
  *********************************************************************/
-char em_driver_version[] = "7.2.3";
+char em_driver_version[] = "7.3.2";
 
 /*********************************************************************
  *  PCI Device ID Table
@@ -286,6 +287,7 @@
 
 static void	em_set_sysctl_value(struct adapter *, const char *,
 		    const char *, int *, int);
+static int	em_set_flowcntl(SYSCTL_HANDLER_ARGS);
 
 static __inline void em_rx_discard(struct rx_ring *, int);
 
@@ -382,13 +384,8 @@
 TUNABLE_INT("hw.em.rx_process_limit", &em_rx_process_limit);
 SYSCTL_INT(_hw_em, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN,
     &em_rx_process_limit, 0,
-    "Maximum number of received packets to process at a time, -1 means unlimited");
-
-/* Flow control setting - default to FULL */
-static int em_fc_setting = e1000_fc_full;
-TUNABLE_INT("hw.em.fc_setting", &em_fc_setting);
-SYSCTL_INT(_hw_em, OID_AUTO, fc_setting, CTLFLAG_RDTUN, &em_fc_setting, 0,
-    "Flow control");
+    "Maximum number of received packets to process "
+    "at a time, -1 means unlimited");
 
 /* Energy efficient ethernet - default to OFF */
 static int eee_setting = 0;
@@ -473,6 +470,11 @@
 
 	INIT_DEBUGOUT("em_attach: begin");
 
+	if (resource_disabled("em", device_get_unit(dev))) {
+		device_printf(dev, "Disabled by device hint\n");
+		return (ENXIO);
+	}
+
 	adapter = device_get_softc(dev);
 	adapter->dev = adapter->osdep.dev = dev;
 	hw = &adapter->hw;
@@ -489,6 +491,11 @@
 	    OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 	    em_sysctl_debug_info, "I", "Debug Information");
 
+	SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
+	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
+	    OID_AUTO, "fc", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
+	    em_set_flowcntl, "I", "Flow Control");
+
 	callout_init_mtx(&adapter->timer, &adapter->core_mtx, 0);
 
 	/* Determine hardware and mac info */
@@ -560,11 +567,6 @@
 	    "max number of rx packets to process", &adapter->rx_process_limit,
 	    em_rx_process_limit);
 
-	/* Sysctl for setting the interface flow control */
-	em_set_sysctl_value(adapter, "flow_control",
-	    "configure flow control",
-	    &adapter->fc_setting, em_fc_setting);
-
 	/*
 	 * Validate number of transmit and receive descriptors. It
 	 * must not exceed hardware maximum, and must be multiple
@@ -714,7 +716,8 @@
 		em_get_hw_control(adapter);
 
 	/* Tell the stack that the interface is not active */
-	adapter->ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
+	adapter->ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
+	adapter->ifp->if_drv_flags |= IFF_DRV_OACTIVE;
 
 	adapter->led_dev = led_create(em_led_func, adapter,
 	    device_get_nameunit(dev));
@@ -847,6 +850,8 @@
 	struct ifnet *ifp = adapter->ifp;
 
 	EM_CORE_LOCK(adapter);
+	if (adapter->hw.mac.type == e1000_pch2lan)
+		e1000_resume_workarounds_pchlan(&adapter->hw);
 	em_init_locked(adapter);
 	em_init_manageability(adapter);
 	EM_CORE_UNLOCK(adapter);
@@ -856,17 +861,15 @@
 }
 
 
+#ifdef EM_MULTIQUEUE
 /*********************************************************************
- *  Transmit entry point
+ *  Multiqueue Transmit routines 
  *
- *  em_start is called by the stack to initiate a transmit.
- *  The driver will remain in this routine as long as there are
- *  packets to transmit and transmit resources are available.
- *  In case resources are not available stack is notified and
- *  the packet is requeued.
+ *  em_mq_start is called by the stack to initiate a transmit.
+ *  however, if busy the driver can queue the request rather
+ *  than do an immediate send. It is this that is an advantage
+ *  in this driver, rather than also having multiple tx queues.
  **********************************************************************/
-
-#ifdef EM_MULTIQUEUE
 static int
 em_mq_start_locked(struct ifnet *ifp, struct tx_ring *txr, struct mbuf *m)
 {
@@ -881,10 +884,6 @@
 		return (err);
 	}
 
-        /* Call cleanup if number of TX descriptors low */
-	if (txr->tx_avail <= EM_TX_CLEANUP_THRESHOLD)
-		em_txeof(txr);
-
 	enq = 0;
 	if (m == NULL) {
 		next = drbr_dequeue(ifp, txr->br);
@@ -907,10 +906,6 @@
 		ETHER_BPF_MTAP(ifp, next);
 		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
                         break;
-		if (txr->tx_avail < EM_MAX_SCATTER) {
-			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
-			break;
-		}
 		next = drbr_dequeue(ifp, txr->br);
 	}
 
@@ -919,6 +914,11 @@
                 txr->queue_status = EM_QUEUE_WORKING;
 		txr->watchdog_time = ticks;
 	}
+
+	if (txr->tx_avail < EM_MAX_SCATTER)
+		em_txeof(txr);
+	if (txr->tx_avail < EM_MAX_SCATTER)
+		ifp->if_drv_flags |= IFF_DRV_OACTIVE;
 	return (err);
 }
 
@@ -959,7 +959,6 @@
 	}
 	if_qflush(ifp);
 }
-
 #endif /* EM_MULTIQUEUE */
 
 static void
@@ -995,7 +994,6 @@
 		if (em_xmit(txr, &m_head)) {
 			if (m_head == NULL)
 				break;
-			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
 			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
 			break;
 		}
@@ -1022,6 +1020,12 @@
 		em_start_locked(ifp, txr);
 		EM_TX_UNLOCK(txr);
 	}
+	/*
+	** If we went inactive schedule
+	** a task to clean up.
+	*/
+	if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
+		taskqueue_enqueue(txr->tq, &txr->tx_task);
 	return;
 }
 
@@ -1038,11 +1042,12 @@
 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
 {
 	struct adapter	*adapter = ifp->if_softc;
-	struct ifreq *ifr = (struct ifreq *)data;
-#ifdef INET
-	struct ifaddr *ifa = (struct ifaddr *)data;
+	struct ifreq	*ifr = (struct ifreq *)data;
+#if defined(INET) || defined(INET6)
+	struct ifaddr	*ifa = (struct ifaddr *)data;
 #endif
-	int error = 0;
+	bool		avoid_reset = FALSE;
+	int		error = 0;
 
 	if (adapter->in_detach)
 		return (error);
@@ -1050,23 +1055,26 @@
 	switch (command) {
 	case SIOCSIFADDR:
 #ifdef INET
-		if (ifa->ifa_addr->sa_family == AF_INET) {
-			/*
-			 * XXX
-			 * Since resetting hardware takes a very long time
-			 * and results in link renegotiation we only
-			 * initialize the hardware only when it is absolutely
-			 * required.
-			 */
+		if (ifa->ifa_addr->sa_family == AF_INET)
+			avoid_reset = TRUE;
+#endif
+#ifdef INET6
+		if (ifa->ifa_addr->sa_family == AF_INET6)
+			avoid_reset = TRUE;
+#endif
+		/*
+		** Calling init results in link renegotiation,
+		** so we avoid doing it when possible.
+		*/
+		if (avoid_reset) {
 			ifp->if_flags |= IFF_UP;
-			if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
-				EM_CORE_LOCK(adapter);
-				em_init_locked(adapter);
-				EM_CORE_UNLOCK(adapter);
-			}
-			arp_ifinit(ifp, ifa);
+			if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
+				em_init(adapter);
+#ifdef INET
+			if (!(ifp->if_flags & IFF_NOARP))
+				arp_ifinit(ifp, ifa);
+#endif
 		} else
-#endif
 			error = ether_ioctl(ifp, command, data);
 		break;
 	case SIOCSIFMTU:
@@ -1083,6 +1091,7 @@
 		case e1000_ich10lan:
 		case e1000_pch2lan:
 		case e1000_82574:
+		case e1000_82583:
 		case e1000_80003es2lan:	/* 9K Jumbo Frame size */
 			max_frame_size = 9234;
 			break;
@@ -1090,7 +1099,6 @@
 			max_frame_size = 4096;
 			break;
 			/* Adapters that do not support jumbo frames */
-		case e1000_82583:
 		case e1000_ich8lan:
 			max_frame_size = ETHER_MAX_LEN;
 			break;
@@ -1145,11 +1153,6 @@
 		}
 		break;
 	case SIOCSIFMEDIA:
-		/*
-		** As the speed/duplex settings are being
-		** changed, we need to reset the PHY.
-		*/
-		adapter->hw.phy.reset_disable = FALSE;
 		/* Check SOL/IDER usage */
 		EM_CORE_LOCK(adapter);
 		if (e1000_check_reset_block(&adapter->hw)) {
@@ -1208,6 +1211,10 @@
 			ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
 			reinit = 1;
 		}
+		if (mask & IFCAP_VLAN_HWTSO) {
+			ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
+			reinit = 1;
+		}
 		if ((mask & IFCAP_WOL) &&
 		    (ifp->if_capabilities & IFCAP_WOL) != 0) {
 			if (mask & IFCAP_WOL_MCAST)
@@ -1246,7 +1253,6 @@
 {
 	struct ifnet	*ifp = adapter->ifp;
 	device_t	dev = adapter->dev;
-	u32		pba;
 
 	INIT_DEBUGOUT("em_init: begin");
 
@@ -1255,46 +1261,6 @@
 	em_disable_intr(adapter);
 	callout_stop(&adapter->timer);
 
-	/*
-	 * Packet Buffer Allocation (PBA)
-	 * Writing PBA sets the receive portion of the buffer
-	 * the remainder is used for the transmit buffer.
-	 */
-	switch (adapter->hw.mac.type) {
-	/* Total Packet Buffer on these is 48K */
-	case e1000_82571:
-	case e1000_82572:
-	case e1000_80003es2lan:
-			pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
-		break;
-	case e1000_82573: /* 82573: Total Packet Buffer is 32K */
-			pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
-		break;
-	case e1000_82574:
-	case e1000_82583:
-			pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
-		break;
-	case e1000_ich8lan:
-		pba = E1000_PBA_8K;
-		break;
-	case e1000_ich9lan:
-	case e1000_ich10lan:
-		pba = E1000_PBA_10K;
-		break;
-	case e1000_pchlan:
-	case e1000_pch2lan:
-		pba = E1000_PBA_26K;
-		break;
-	default:
-		if (adapter->max_frame_size > 8192)
-			pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
-		else
-			pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
-	}
-
-	INIT_DEBUGOUT1("em_init: pba=%dK",pba);
-	E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba);
-	
 	/* Get the latest mac address, User can use a LAA */
         bcopy(IF_LLADDR(adapter->ifp), adapter->hw.mac.addr,
               ETHER_ADDR_LEN);
@@ -1373,6 +1339,7 @@
 	/* Don't lose promiscuous settings */
 	em_set_promisc(adapter);
 
+	/* Set the interface as ACTIVE */
 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 
@@ -1403,9 +1370,6 @@
 	/* AMT based hardware can now take control from firmware */
 	if (adapter->has_manage && adapter->has_amt)
 		em_get_hw_control(adapter);
-
-	/* Don't reset the phy next time init gets called */
-	adapter->hw.phy.reset_disable = TRUE;
 }
 
 static void
@@ -1995,6 +1959,14 @@
 		em_transmit_checksum_setup(txr, m_head,
 		    ip_off, ip, &txd_upper, &txd_lower);
 
+	if (m_head->m_flags & M_VLANTAG) {
+		/* Set the vlan id. */
+		txd_upper |=
+		    (htole16(m_head->m_pkthdr.ether_vtag) << 16);
+                /* Tell hardware to add tag */
+                txd_lower |= htole32(E1000_TXD_CMD_VLE);
+        }
+
 	i = txr->next_avail_desc;
 
 	/* Set up our transmit descriptors */
@@ -2052,15 +2024,13 @@
 	if (tso_desc) /* TSO used an extra for sentinel */
 		txr->tx_avail -= txd_used;
 
-	if (m_head->m_flags & M_VLANTAG) {
-		/* Set the vlan id. */
-		ctxd->upper.fields.special =
-		    htole16(m_head->m_pkthdr.ether_vtag);
-                /* Tell hardware to add tag */
-                ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
-        }
-
         tx_buffer->m_head = m_head;
+	/*
+	** Here we swap the map so the last descriptor,
+	** which gets the completion interrupt has the
+	** real map, and the first descriptor gets the
+	** unused map from this descriptor.
+	*/
 	tx_buffer_mapped->map = tx_buffer->map;
 	tx_buffer->map = map;
         bus_dmamap_sync(txr->txtag, map, BUS_DMASYNC_PREWRITE);
@@ -2230,22 +2200,21 @@
 	else
 		trigger = E1000_ICS_RXDMT0;
 
-	/* 
-	** Don't do TX watchdog check if we've been paused
-	*/
-	if (adapter->pause_frames) {
-		adapter->pause_frames = 0;
-		goto out;
-	}
 	/*
 	** Check on the state of the TX queue(s), this 
 	** can be done without the lock because its RO
 	** and the HUNG state will be static if set.
 	*/
-	for (int i = 0; i < adapter->num_queues; i++, txr++)
-		if (txr->queue_status == EM_QUEUE_HUNG)
+	for (int i = 0; i < adapter->num_queues; i++, txr++) {
+		if ((txr->queue_status == EM_QUEUE_HUNG) &&
+		    (adapter->pause_frames == 0))
 			goto hung;
-out:
+		/* Schedule a TX tasklet if needed */
+		if (txr->tx_avail <= EM_MAX_SCATTER)
+			taskqueue_enqueue(txr->tq, &txr->tx_task);
+	}
+	
+	adapter->pause_frames = 0;
 	callout_reset(&adapter->timer, hz, em_local_timer, adapter);
 #ifndef DEVICE_POLLING
 	/* Trigger an RX interrupt to guarantee mbuf refresh */
@@ -2264,6 +2233,7 @@
 	    txr->me, txr->tx_avail, txr->next_to_clean);
 	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
 	adapter->watchdog_events++;
+	adapter->pause_frames = 0;
 	em_init_locked(adapter);
 }
 
@@ -2362,7 +2332,8 @@
 	callout_stop(&adapter->timer);
 
 	/* Tell the stack that the interface is no longer active */
-	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
+	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
+	ifp->if_drv_flags |= IFF_DRV_OACTIVE;
 
         /* Unarm watchdog timer. */
 	for (int i = 0; i < adapter->num_queues; i++, txr++) {
@@ -2458,6 +2429,7 @@
 em_allocate_legacy(struct adapter *adapter)
 {
 	device_t dev = adapter->dev;
+	struct tx_ring	*txr = adapter->tx_rings;
 	int error, rid = 0;
 
 	/* Manually turn off all interrupts */
@@ -2479,11 +2451,17 @@
 	 * deferred processing contexts.
 	 */
 	TASK_INIT(&adapter->que_task, 0, em_handle_que, adapter);
-	TASK_INIT(&adapter->link_task, 0, em_handle_link, adapter);
 	adapter->tq = taskqueue_create_fast("em_taskq", M_NOWAIT,
 	    taskqueue_thread_enqueue, &adapter->tq);
-	taskqueue_start_threads(&adapter->tq, 1, PI_NET, "%s taskq",
+	taskqueue_start_threads(&adapter->tq, 1, PI_NET, "%s que",
 	    device_get_nameunit(adapter->dev));
+	/* Use a TX only tasklet for local timer */
+	TASK_INIT(&txr->tx_task, 0, em_handle_tx, txr);
+	txr->tq = taskqueue_create_fast("em_txq", M_NOWAIT,
+	    taskqueue_thread_enqueue, &txr->tq);
+	taskqueue_start_threads(&txr->tq, 1, PI_NET, "%s txq",
+	    device_get_nameunit(adapter->dev));
+	TASK_INIT(&adapter->link_task, 0, em_handle_link, adapter);
 	if ((error = bus_setup_intr(dev, adapter->res, INTR_TYPE_NET,
 	    em_irq_fast, NULL, adapter, &adapter->tag)) != 0) {
 		device_printf(dev, "Failed to register fast interrupt "
@@ -2500,7 +2478,8 @@
  *
  *  Setup the MSIX Interrupt handlers
  *   This is not really Multiqueue, rather
- *   its just multiple interrupt vectors.
+ *   its just seperate interrupt vectors
+ *   for TX, RX, and Link.
  *
  **********************************************************************/
 int
@@ -2692,7 +2671,6 @@
 	device_t dev = adapter->dev;
 	int val = 0;
 
-
 	/*
 	** Setup MSI/X for Hartwell: tests have shown
 	** use of two queues to be unstable, and to
@@ -2712,16 +2690,18 @@
 			goto msi;
        		}
 		val = pci_msix_count(dev); 
-		if (val < 3) {
+		/* We only need 3 vectors */
+		if (val > 3)
+			val = 3;
+		if ((val != 3) && (val != 5)) {
 			bus_release_resource(dev, SYS_RES_MEMORY,
 			    PCIR_BAR(EM_MSIX_BAR), adapter->msix_mem);
 			adapter->msix_mem = NULL;
                		device_printf(adapter->dev,
-			    "MSIX: insufficient vectors, using MSI\n");
+			    "MSIX: incorrect vectors, using MSI\n");
 			goto msi;
 		}
-		val = 3;
-		adapter->num_queues = 1;
+
 		if (pci_alloc_msix(dev, &val) == 0) {
 			device_printf(adapter->dev,
 			    "Using MSIX interrupts "
@@ -2756,6 +2736,7 @@
 	struct ifnet	*ifp = adapter->ifp;
 	struct e1000_hw	*hw = &adapter->hw;
 	u16		rx_buffer_size;
+	u32		pba;
 
 	INIT_DEBUGOUT("em_reset: begin");
 
@@ -2771,6 +2752,48 @@
 	}
 
 	/*
+	 * Packet Buffer Allocation (PBA)
+	 * Writing PBA sets the receive portion of the buffer
+	 * the remainder is used for the transmit buffer.
+	 */
+	switch (hw->mac.type) {
+	/* Total Packet Buffer on these is 48K */
+	case e1000_82571:
+	case e1000_82572:
+	case e1000_80003es2lan:
+			pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
+		break;
+	case e1000_82573: /* 82573: Total Packet Buffer is 32K */
+			pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
+		break;
+	case e1000_82574:
+	case e1000_82583:
+			pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
+		break;
+	case e1000_ich8lan:
+		pba = E1000_PBA_8K;
+		break;
+	case e1000_ich9lan:
+	case e1000_ich10lan:
+		/* Boost Receive side for jumbo frames */
+		if (adapter->max_frame_size > 4096)
+			pba = E1000_PBA_14K;
+		else
+			pba = E1000_PBA_10K;
+		break;
+	case e1000_pchlan:
+	case e1000_pch2lan:
+		pba = E1000_PBA_26K;
+		break;
+	default:
+		if (adapter->max_frame_size > 8192)
+			pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
+		else
+			pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
+	}
+	E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba);
+
+	/*
 	 * These parameters control the automatic generation (Tx) and
 	 * response (Rx) to Ethernet PAUSE frames.
 	 * - High water mark should allow for at least two frames to be
@@ -2785,11 +2808,15 @@
 	 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
 	 */
 	rx_buffer_size = ((E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10 );
-
 	hw->fc.high_water = rx_buffer_size -
 	    roundup2(adapter->max_frame_size, 1024);
 	hw->fc.low_water = hw->fc.high_water - 1500;
 
+	if (adapter->fc) /* locally set flow control value? */
+		hw->fc.requested_mode = adapter->fc;
+	else
+		hw->fc.requested_mode = e1000_fc_full;
+
 	if (hw->mac.type == e1000_80003es2lan)
 		hw->fc.pause_time = 0xFFFF;
 	else
@@ -2797,15 +2824,22 @@
 
 	hw->fc.send_xon = TRUE;
 
-        /* Set Flow control, use the tunable location if sane */
-	hw->fc.requested_mode = adapter->fc_setting;
-
-	/* Workaround: no TX flow ctrl for PCH */
-	if (hw->mac.type == e1000_pchlan)
+	/* Device specific overrides/settings */
+	switch (hw->mac.type) {
+	case e1000_pchlan:
+		/* Workaround: no TX flow ctrl for PCH */
                 hw->fc.requested_mode = e1000_fc_rx_pause;
-
-	/* Override - settings for PCH2LAN, ya its magic :) */
-	if (hw->mac.type == e1000_pch2lan) {
+		hw->fc.pause_time = 0xFFFF; /* override */
+		if (ifp->if_mtu > ETHERMTU) {
+			hw->fc.high_water = 0x3500;
+			hw->fc.low_water = 0x1500;
+		} else {
+			hw->fc.high_water = 0x5000;
+			hw->fc.low_water = 0x3000;
+		}
+		hw->fc.refresh_time = 0x1000;
+		break;
+	case e1000_pch2lan:
 		hw->fc.high_water = 0x5C20;
 		hw->fc.low_water = 0x5048;
 		hw->fc.pause_time = 0x0650;
@@ -2815,13 +2849,26 @@
 			E1000_WRITE_REG(hw, E1000_PBA, 12);
 		else
 			E1000_WRITE_REG(hw, E1000_PBA, 26);
+		break;
+        case e1000_ich9lan:
+        case e1000_ich10lan:
+		if (ifp->if_mtu > ETHERMTU) {
+			hw->fc.high_water = 0x2800;
+			hw->fc.low_water = hw->fc.high_water - 8;
+			break;
+		} 
+		/* else fall thru */
+	default:
+		if (hw->mac.type == e1000_80003es2lan)
+			hw->fc.pause_time = 0xFFFF;
+		break;
 	}
 
 	/* Issue a global reset */
 	e1000_reset_hw(hw);
 	E1000_WRITE_REG(hw, E1000_WUC, 0);
 	em_disable_aspm(adapter);
-
+	/* and a re-init */
 	if (e1000_init_hw(hw) < 0) {
 		device_printf(dev, "Hardware Initialization Failed\n");
 		return;
@@ -2866,28 +2913,25 @@
 	ifp->if_capabilities = ifp->if_capenable = 0;
 
 #ifdef EM_MULTIQUEUE
-	/* Multiqueue tx functions */
+	/* Multiqueue stack interface */
 	ifp->if_transmit = em_mq_start;
 	ifp->if_qflush = em_qflush;
 #endif	
 
 	ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM;
-	ifp->if_capenable |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM;
-
-	/* Enable TSO by default, can disable with ifconfig */
 	ifp->if_capabilities |= IFCAP_TSO4;
-	ifp->if_capenable |= IFCAP_TSO4;
-
 	/*
 	 * Tell the upper layer(s) we
 	 * support full VLAN capability
 	 */
 	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
-	ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
-	ifp->if_capenable |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
+	ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING
+			     |  IFCAP_VLAN_HWTSO
+			     |  IFCAP_VLAN_MTU;
+	ifp->if_capenable = ifp->if_capabilities;
 
 	/*
-	** Dont turn this on by default, if vlans are
+	** Don't turn this on by default, if vlans are
 	** created on another pseudo device (eg. lagg)
 	** then vlan events are not passed thru, breaking
 	** operation, but with HW FILTER off it works. If
@@ -3339,11 +3383,6 @@
 
 	/* Set the default values for the Tx Inter Packet Gap timer */
 	switch (adapter->hw.mac.type) {
-	case e1000_82542:
-		tipg = DEFAULT_82542_TIPG_IPGT;
-		tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
-		tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
-		break;
 	case e1000_80003es2lan:
 		tipg = DEFAULT_82543_TIPG_IPGR1;
 		tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
@@ -3813,9 +3852,12 @@
         /*
          * If we have a minimum free, clear IFF_DRV_OACTIVE
          * to tell the stack that it is OK to send packets.
+	 * Notice that all writes of OACTIVE happen under the
+	 * TX lock which, with a single queue, guarantees 
+	 * sanity.
          */
-        if (txr->tx_avail > EM_MAX_SCATTER)
-                ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+        if (txr->tx_avail >= EM_MAX_SCATTER)
+		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 
 	/* Disable watchdog if all clean */
 	if (txr->tx_avail == adapter->num_tx_desc) {
@@ -3978,26 +4020,31 @@
 	struct	adapter 	*adapter = rxr->adapter;
 	struct em_buffer	*rxbuf;
 	bus_dma_segment_t	seg[1];
-	int			i, j, nsegs, error = 0;
+	int			rsize, nsegs, error;
 
 
 	/* Clear the ring contents */
 	EM_RX_LOCK(rxr);
-
-	/* Invalidate all descriptors */
-	for (i = 0; i < adapter->num_rx_desc; i++) {
-		struct e1000_rx_desc* cur;
-		cur = &rxr->rx_base[i];
-		cur->status = 0;
+	rsize = roundup2(adapter->num_rx_desc *
+	    sizeof(struct e1000_rx_desc), EM_DBA_ALIGN);
+	bzero((void *)rxr->rx_base, rsize);
+
+	/*
+	** Free current RX buffer structs and their mbufs
+	*/
+	for (int i = 0; i < adapter->num_rx_desc; i++) {
+		rxbuf = &rxr->rx_buffers[i];
+		if (rxbuf->m_head != NULL) {
+			bus_dmamap_sync(rxr->rxtag, rxbuf->map,
+			    BUS_DMASYNC_POSTREAD);
+			bus_dmamap_unload(rxr->rxtag, rxbuf->map);
+			m_freem(rxbuf->m_head);
+		}
 	}
 
 	/* Now replenish the mbufs */
-	i = j = rxr->next_to_refresh;
-	if (++j == adapter->num_rx_desc)
-		j = 0;
-
-	while (j != rxr->next_to_check) {
-		rxbuf = &rxr->rx_buffers[i];
+        for (int j = 0; j != adapter->num_rx_desc; ++j) {
+		rxbuf = &rxr->rx_buffers[j];
 		rxbuf->m_head = m_getjcl(M_DONTWAIT, MT_DATA,
 		    M_PKTHDR, adapter->rx_mbuf_sz);
 		if (rxbuf->m_head == NULL) {
@@ -4021,11 +4068,13 @@
 		    rxbuf->map, BUS_DMASYNC_PREREAD);
 
 		/* Update descriptor */
-		rxr->rx_base[i].buffer_addr = htole64(seg[0].ds_addr);
-		i = j;
-		if (++j == adapter->num_rx_desc)
-			j = 0;
+		rxr->rx_base[j].buffer_addr = htole64(seg[0].ds_addr);
 	}
+	rxr->next_to_check = 0;
+	rxr->next_to_refresh = 0;
+	bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map,
+	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+
 #ifdef DEV_NETMAP
     {
 	/*
@@ -4055,7 +4104,7 @@
 	if (sj < 0)
 		sj += adapter->num_rx_desc;
 
-	for (j = 0; j != adapter->num_rx_desc; j++, sj++) {
+	for (int j = 0; j != adapter->num_rx_desc; j++, sj++) {
 		void *addr;
 		int sz;
 
@@ -4079,9 +4128,6 @@
 #endif /* DEV_NETMAP */
 
 fail:
-	rxr->next_to_refresh = i;
-	bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map,
-	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 	EM_RX_UNLOCK(rxr);
 	return (error);
 }
@@ -4108,10 +4154,9 @@
 	 * the rings that completed, the failing case will have
 	 * cleaned up for itself. 'q' failed, so its the terminus.
 	 */
-	for (int i = 0, n = 0; i < q; ++i) {
+	for (int i = 0; i < q; ++i) {
 		rxr = &adapter->rx_rings[i];
-		n = rxr->next_to_check;
-		while(n != rxr->next_to_refresh) {
+		for (int n = 0; n < adapter->num_rx_desc; n++) {
 			struct em_buffer *rxbuf;
 			rxbuf = &rxr->rx_buffers[n];
 			if (rxbuf->m_head != NULL) {
@@ -4121,8 +4166,6 @@
 				m_freem(rxbuf->m_head);
 				rxbuf->m_head = NULL;
 			}
-			if (++n == adapter->num_rx_desc)
-				n = 0;
 		}
 		rxr->next_to_check = 0;
 		rxr->next_to_refresh = 0;
@@ -4166,8 +4209,7 @@
 	INIT_DEBUGOUT("free_receive_buffers: begin");
 
 	if (rxr->rx_buffers != NULL) {
-		int i = rxr->next_to_check;
-		while(i != rxr->next_to_refresh) {
+		for (int i = 0; i < adapter->num_rx_desc; i++) {
 			rxbuf = &rxr->rx_buffers[i];
 			if (rxbuf->map != NULL) {
 				bus_dmamap_sync(rxr->rxtag, rxbuf->map,
@@ -4179,8 +4221,6 @@
 				m_freem(rxbuf->m_head);
 				rxbuf->m_head = NULL;
 			}
-			if (++i == adapter->num_rx_desc)
-				i = 0;
 		}
 		free(rxr->rx_buffers, M_DEVBUF);
 		rxr->rx_buffers = NULL;
@@ -4221,7 +4261,9 @@
 	 * up the descriptor ring
 	 */
 	rctl = E1000_READ_REG(hw, E1000_RCTL);
-	E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
+	/* Do not disable if ever enabled on this hardware */
+	if ((hw->mac.type != e1000_82574) && (hw->mac.type != e1000_82583))
+		E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
 
 	E1000_WRITE_REG(&adapter->hw, E1000_RADV,
 	    adapter->rx_abs_int_delay.value);
@@ -4235,14 +4277,13 @@
 	** When using MSIX interrupts we need to throttle
 	** using the EITR register (82574 only)
 	*/
-	if (hw->mac.type == e1000_82574)
+	if (hw->mac.type == e1000_82574) {
 		for (int i = 0; i < 4; i++)
 			E1000_WRITE_REG(hw, E1000_EITR_82574(i),
 			    DEFAULT_ITR);
-
-	/* Disable accelerated ackknowledge */
-	if (adapter->hw.mac.type == e1000_82574)
+		/* Disable accelerated acknowledge */
 		E1000_WRITE_REG(hw, E1000_RFCTL, E1000_RFCTL_ACK_DIS);
+	}
 
 	if (ifp->if_capenable & IFCAP_RXCSUM) {
 		rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
@@ -4268,7 +4309,8 @@
 		E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32));
 		E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr);
 		/* Setup the Head and Tail Descriptor Pointers */
-		E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
+		E1000_WRITE_REG(hw, E1000_RDH(i), 0);
+		E1000_WRITE_REG(hw, E1000_RDT(i), adapter->num_rx_desc - 1);
 #ifdef DEV_NETMAP
 		/*
 		 * an init() while a netmap client is active must
@@ -4286,17 +4328,16 @@
 			E1000_WRITE_REG(hw, E1000_RDT(i), t);
 		} else
 #endif /* DEV_NETMAP */
-		E1000_WRITE_REG(hw, E1000_RDT(i), rxr->next_to_refresh);
+		E1000_WRITE_REG(hw, E1000_RDT(i), adapter->num_rx_desc - 1);
 	}
 
-	/* Set early receive threshold on appropriate hw */
+	/* Set PTHRESH for improved jumbo performance */
 	if (((adapter->hw.mac.type == e1000_ich9lan) ||
 	    (adapter->hw.mac.type == e1000_pch2lan) ||
 	    (adapter->hw.mac.type == e1000_ich10lan)) &&
 	    (ifp->if_mtu > ETHERMTU)) {
 		u32 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(0));
 		E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl | 3);
-		E1000_WRITE_REG(hw, E1000_ERT, 0x100 | (1 << 13));
 	}
 		
 	if (adapter->hw.mac.type == e1000_pch2lan) {
@@ -4443,10 +4484,6 @@
 				    E1000_RXD_SPC_VLAN_MASK);
 				sendmp->m_flags |= M_VLANTAG;
 			}
-#ifdef EM_MULTIQUEUE
-			sendmp->m_pkthdr.flowid = rxr->msix;
-			sendmp->m_flags |= M_FLOWID;
-#endif
 #ifndef __NO_STRICT_ALIGNMENT
 skip:
 #endif
@@ -4921,7 +4958,7 @@
 	    (adapter->hw.mac.type == e1000_pchlan) ||
 	    (adapter->hw.mac.type == e1000_ich9lan) ||
 	    (adapter->hw.mac.type == e1000_ich10lan))
-		e1000_disable_gig_wol_ich8lan(&adapter->hw);
+		e1000_suspend_workarounds_ich8lan(&adapter->hw);
 
 	/* Keep the laser running on Fiber adapters */
 	if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
@@ -5518,7 +5555,7 @@
 static int
 em_sysctl_nvm_info(SYSCTL_HANDLER_ARGS)
 {
-	struct adapter *adapter;
+	struct adapter *adapter = (struct adapter *)arg1;
 	int error;
 	int result;
 
@@ -5533,10 +5570,8 @@
 	 * first 32 16-bit words of the EEPROM to
 	 * the screen.
 	 */
-	if (result == 1) {
-		adapter = (struct adapter *)arg1;
+	if (result == 1)
 		em_print_nvm_info(adapter);
-        }
 
 	return (error);
 }
@@ -5626,6 +5661,49 @@
 	    OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, limit, value, description);
 }
 
+
+/*
+** Set flow control using sysctl:
+** Flow control values:
+**      0 - off
+**      1 - rx pause
+**      2 - tx pause
+**      3 - full
+*/
+static int
+em_set_flowcntl(SYSCTL_HANDLER_ARGS)
+{       
+        int		error;
+	static int	input = 3; /* default is full */
+        struct adapter	*adapter = (struct adapter *) arg1;
+                    
+        error = sysctl_handle_int(oidp, &input, 0, req);
+    
+        if ((error) || (req->newptr == NULL))
+                return (error);
+                
+	if (input == adapter->fc) /* no change? */
+		return (error);
+
+        switch (input) {
+                case e1000_fc_rx_pause:
+                case e1000_fc_tx_pause:
+                case e1000_fc_full:
+                case e1000_fc_none:
+                        adapter->hw.fc.requested_mode = input;
+			adapter->fc = input;
+                        break;
+                default:
+			/* Do nothing */
+			return (error);
+        }
+
+        adapter->hw.fc.current_mode = adapter->hw.fc.requested_mode;
+        e1000_force_mac_fc(&adapter->hw);
+        return (error);
+}
+
+
 static int
 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
 {
@@ -5662,10 +5740,11 @@
 		printf("Interface is RUNNING ");
 	else
 		printf("Interface is NOT RUNNING\n");
+
 	if (adapter->ifp->if_drv_flags & IFF_DRV_OACTIVE)
+		printf("and INACTIVE\n");
+	else
 		printf("and ACTIVE\n");
-	else
-		printf("and INACTIVE\n");
 
 	device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
 	    E1000_READ_REG(&adapter->hw, E1000_TDH(0)),
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/e1000/if_em.h
--- a/head/sys/dev/e1000/if_em.h	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/e1000/if_em.h	Thu Dec 15 12:59:38 2011 +0200
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD: head/sys/dev/e1000/if_em.h 220251 2011-04-01 18:48:31Z jfv $*/
+/*$FreeBSD: head/sys/dev/e1000/if_em.h 228387 2011-12-10 07:08:52Z jfv $*/
 
 
 #ifndef _EM_H_DEFINED_
@@ -212,7 +212,8 @@
 #define EM_BAR_MEM_TYPE_64BIT	0x00000004
 #define EM_MSIX_BAR		3	/* On 82575 */
 
-#if !defined(SYSCTL_ADD_UQUAD)
+/* More backward compatibility */
+#if __FreeBSD_version < 900000
 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
 #endif
 
@@ -418,11 +419,11 @@
 	u32		shadow_vfta[EM_VFTA_SIZE];
 
 	/* Info about the interface */
-	u8		link_active;
+	u16		link_active;
+	u16		fc;
 	u16		link_speed;
 	u16		link_duplex;
 	u32		smartspeed;
-	u32		fc_setting;
 
 	struct em_int_delay_info tx_int_delay;
 	struct em_int_delay_info tx_abs_int_delay;
diff -r 2230520c0499 -r 820af1e39cd6 head/sys/dev/e1000/if_igb.c
--- a/head/sys/dev/e1000/if_igb.c	Sun Dec 11 15:53:23 2011 +0200
+++ b/head/sys/dev/e1000/if_igb.c	Thu Dec 15 12:59:38 2011 +0200
@@ -30,7 +30,7 @@
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
-/*$FreeBSD: head/sys/dev/e1000/if_igb.c 228281 2011-12-05 15:33:13Z luigi $*/
+/*$FreeBSD: head/sys/dev/e1000/if_igb.c 228441 2011-12-12 18:27:34Z mdf $*/
 
 
 #ifdef HAVE_KERNEL_OPTION_HEADERS
@@ -100,7 +100,7 @@
 /*********************************************************************
  *  Driver version:
  *********************************************************************/
-char igb_driver_version[] = "version - 2.2.5";
+char igb_driver_version[] = "version - 2.3.1";
 
 
 /*********************************************************************
@@ -171,15 +171,13 @@
 static int	igb_shutdown(device_t);
 static int	igb_suspend(device_t);
 static int	igb_resume(device_t);
+static void	igb_start(struct ifnet *);
+static void	igb_start_locked(struct tx_ring *, struct ifnet *ifp);
 #if __FreeBSD_version >= 800000
 static int	igb_mq_start(struct ifnet *, struct mbuf *);
 static int	igb_mq_start_locked(struct ifnet *,
 		    struct tx_ring *, struct mbuf *);
 static void	igb_qflush(struct ifnet *);
-static void	igb_deferred_mq_start(void *, int);
-#else
-static void	igb_start(struct ifnet *);
-static void	igb_start_locked(struct tx_ring *, struct ifnet *ifp);
 #endif
 static int	igb_ioctl(struct ifnet *, u_long, caddr_t);
 static void	igb_init(void *);
@@ -225,8 +223,9 @@
 
 static bool	igb_rxeof(struct igb_queue *, int, int *);
 static void	igb_rx_checksum(u32, struct mbuf *, u32);
-static int	igb_tx_ctx_setup(struct tx_ring *, struct mbuf *);
-static bool	igb_tso_setup(struct tx_ring *, struct mbuf *, u32 *);
+static bool	igb_tx_ctx_setup(struct tx_ring *, struct mbuf *);
+static bool	igb_tso_setup(struct tx_ring *, struct mbuf *, int,
+		    struct ip *, struct tcphdr *);
 static void	igb_set_promisc(struct adapter *);
 static void	igb_disable_promisc(struct adapter *);
 static void	igb_set_multi(struct adapter *);
@@ -300,17 +299,11 @@
  *  Tunable default values.
  *********************************************************************/
 
-static SYSCTL_NODE(_hw, OID_AUTO, igb, CTLFLAG_RD, 0, "IGB driver parameters");
-
 /* Descriptor defaults */
 static int igb_rxd = IGB_DEFAULT_RXD;
 static int igb_txd = IGB_DEFAULT_TXD;
 TUNABLE_INT("hw.igb.rxd", &igb_rxd);
 TUNABLE_INT("hw.igb.txd", &igb_txd);
-SYSCTL_INT(_hw_igb, OID_AUTO, rxd, CTLFLAG_RDTUN, &igb_rxd, 0,
-    "Number of receive descriptors per queue");
-SYSCTL_INT(_hw_igb, OID_AUTO, txd, CTLFLAG_RDTUN, &igb_txd, 0,
-    "Number of transmit descriptors per queue");
 
 /*
 ** AIM: Adaptive Interrupt Moderation
@@ -320,8 +313,6 @@
 */
 static int igb_enable_aim = TRUE;
 TUNABLE_INT("hw.igb.enable_aim", &igb_enable_aim);
-SYSCTL_INT(_hw_igb, OID_AUTO, enable_aim, CTLFLAG_RW, &igb_enable_aim, 0,
-    "Enable adaptive interrupt moderation");
 
 /*
  * MSIX should be the default for best performance,
@@ -329,16 +320,12 @@
  */         
 static int igb_enable_msix = 1;
 TUNABLE_INT("hw.igb.enable_msix", &igb_enable_msix);
-SYSCTL_INT(_hw_igb, OID_AUTO, enable_msix, CTLFLAG_RDTUN, &igb_enable_msix, 0,
-    "Enable MSI-X interrupts");
 
 /*
 ** Tuneable Interrupt rate
 */
 static int igb_max_interrupt_rate = 8000;
 TUNABLE_INT("hw.igb.max_interrupt_rate", &igb_max_interrupt_rate);
-SYSCTL_INT(_hw_igb, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
-    &igb_max_interrupt_rate, 0, "Maximum interrupts per second");
 
 /*
 ** Header split causes the packet header to
@@ -348,10 +335,8 @@
 ** into the header and thus use no cluster. Its
 ** a very workload dependent type feature.
 */
-static bool igb_header_split = FALSE;
+static int igb_header_split = FALSE;
 TUNABLE_INT("hw.igb.hdr_split", &igb_header_split);
-SYSCTL_INT(_hw_igb, OID_AUTO, header_split, CTLFLAG_RDTUN, &igb_header_split, 0,
-    "Enable receive mbuf header split");
 
 /*
 ** This will autoconfigure based on
@@ -359,19 +344,7 @@
 */
 static int igb_num_queues = 0;
 TUNABLE_INT("hw.igb.num_queues", &igb_num_queues);
-SYSCTL_INT(_hw_igb, OID_AUTO, num_queues, CTLFLAG_RDTUN, &igb_num_queues, 0,
-    "Number of queues to configure, 0 indicates autoconfigure");
-
-/* How many packets rxeof tries to clean at a time */
-static int igb_rx_process_limit = 100;
-TUNABLE_INT("hw.igb.rx_process_limit", &igb_rx_process_limit);
-SYSCTL_INT(_hw_igb, OID_AUTO, rx_process_limit, CTLFLAG_RDTUN,
-    &igb_rx_process_limit, 0,
-    "Maximum number of received packets to process at a time, -1 means unlimited");
-
-#ifdef DEV_NETMAP	/* see ixgbe.c for details */
-#include <dev/netmap/if_igb_netmap.h>
-#endif /* DEV_NETMAP */
+
 /*********************************************************************
  *  Device identification routine
  *
@@ -457,9 +430,10 @@
 	    OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 	    igb_sysctl_nvm_info, "I", "NVM Information");
 
-	igb_set_sysctl_value(adapter, "enable_aim",
-	    "Interrupt Moderation", &adapter->enable_aim,
-	    igb_enable_aim);
+	SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
+	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
+	    OID_AUTO, "enable_aim", CTLTYPE_INT|CTLFLAG_RW,
+	    &igb_enable_aim, 1, "Interrupt Moderation");
 
 	SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
@@ -490,7 +464,7 @@
 	/* Sysctl for limiting the amount of work done in the taskqueue */
 	igb_set_sysctl_value(adapter, "rx_processing_limit",
 	    "max number of rx packets to process",
-	    &adapter->rx_process_limit, igb_rx_process_limit);
+	    &adapter->rx_process_limit, 100);
 
 	/*
 	 * Validate number of transmit and receive descriptors. It
@@ -614,6 +588,50 @@
 		goto err_late;
 	}
 
+	/* Setup OS specific network interface */
+	if (igb_setup_interface(dev, adapter) != 0)
+		goto err_late;
+
+	/* Now get a good starting state */
+	igb_reset(adapter);
+
+	/* Initialize statistics */
+	igb_update_stats_counters(adapter);
+
+	adapter->hw.mac.get_link_status = 1;
+	igb_update_link_status(adapter);
+
+	/* Indicate SOL/IDER usage */
+	if (e1000_check_reset_block(&adapter->hw))
+		device_printf(dev,
+		    "PHY reset is blocked due to SOL/IDER session.\n");
+
+	/* Determine if we have to control management hardware */
+	adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw);
+
+	/*
+	 * Setup Wake-on-Lan
+	 */
+	/* APME bit in EEPROM is mapped to WUC.APME */
+	eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC) & E1000_WUC_APME;
+	if (eeprom_data)
+		adapter->wol = E1000_WUFC_MAG;
+
+	/* Register for VLAN events */
+	adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
+	     igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
+	adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
+	     igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
+
+	igb_add_hw_stats(adapter);
+
+	/* Tell the stack that the interface is not active */
+	adapter->ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
+	adapter->ifp->if_drv_flags |=  IFF_DRV_OACTIVE;
+
+	adapter->led_dev = led_create(igb_led_func, adapter,
+	    device_get_nameunit(dev));
+
 	/* 
 	** Configure Interrupts
 	*/
@@ -624,52 +642,6 @@
 	if (error)
 		goto err_late;
 
-	/* Setup OS specific network interface */
-	if (igb_setup_interface(dev, adapter) != 0)
-		goto err_late;
-
-	/* Now get a good starting state */
-	igb_reset(adapter);
-
-	/* Initialize statistics */
-	igb_update_stats_counters(adapter);
-
-	adapter->hw.mac.get_link_status = 1;
-	igb_update_link_status(adapter);
-
-	/* Indicate SOL/IDER usage */
-	if (e1000_check_reset_block(&adapter->hw))
-		device_printf(dev,
-		    "PHY reset is blocked due to SOL/IDER session.\n");
-
-	/* Determine if we have to control management hardware */
-	adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw);
-
-	/*
-	 * Setup Wake-on-Lan
-	 */
-	/* APME bit in EEPROM is mapped to WUC.APME */
-	eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC) & E1000_WUC_APME;
-	if (eeprom_data)
-		adapter->wol = E1000_WUFC_MAG;
-
-	/* Register for VLAN events */
-	adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
-	     igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
-	adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
-	     igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
-
-	igb_add_hw_stats(adapter);
-
-	/* Tell the stack that the interface is not active */
-	adapter->ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
-
-	adapter->led_dev = led_create(igb_led_func, adapter,
-	    device_get_nameunit(dev));
-
-#ifdef DEV_NETMAP
-	igb_netmap_attach(adapter);
-#endif /* DEV_NETMAP */
 	INIT_DEBUGOUT("igb_attach: end");
 
 	return (0);
@@ -679,10 +651,10 @@
 	igb_free_transmit_structures(adapter);
 	igb_free_receive_structures(adapter);
 	igb_release_hw_control(adapter);
+err_pci:
+	igb_free_pci_resources(adapter);
 	if (adapter->ifp != NULL)
 		if_free(adapter->ifp);
-err_pci:
-	igb_free_pci_resources(adapter);
 	free(adapter->mta, M_DEVBUF);
 	IGB_CORE_LOCK_DESTROY(adapter);
 
@@ -713,8 +685,6 @@
 		return (EBUSY);
 	}
 
-	ether_ifdetach(adapter->ifp);
-
 	if (adapter->led_dev != NULL)
 		led_destroy(adapter->led_dev);
 
@@ -746,11 +716,10 @@
 	if (adapter->vlan_detach != NULL)
 		EVENTHANDLER_DEREGISTER(vlan_unconfig, adapter->vlan_detach);
 
+	ether_ifdetach(adapter->ifp);
+
 	callout_drain(&adapter->timer);
 
-#ifdef DEV_NETMAP
-	netmap_detach(adapter->ifp);
-#endif /* DEV_NETMAP */
 	igb_free_pci_resources(adapter);
 	bus_generic_detach(dev);
 	if_free(ifp);
@@ -808,27 +777,14 @@
 {
 	struct adapter *adapter = device_get_softc(dev);
 	struct ifnet *ifp = adapter->ifp;
-#if __FreeBSD_version >= 800000
-	struct tx_ring *txr = adapter->tx_rings;
-#endif
 
 	IGB_CORE_LOCK(adapter);
 	igb_init_locked(adapter);
 	igb_init_manageability(adapter);
 
 	if ((ifp->if_flags & IFF_UP) &&
-	    (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
-#if __FreeBSD_version < 800000
+	    (ifp->if_drv_flags & IFF_DRV_RUNNING))
 		igb_start(ifp);
-#else
-		for (int i = 0; i < adapter->num_queues; i++, txr++) {
-			IGB_TX_LOCK(txr);
-			if (!drbr_empty(ifp, txr->br))
-				igb_mq_start_locked(ifp, txr, NULL);
-			IGB_TX_UNLOCK(txr);
-		}
-#endif
-	}
 
 	IGB_CORE_UNLOCK(adapter);
 
@@ -836,7 +792,6 @@
 }
 
 
-#if __FreeBSD_version < 800000
 /*********************************************************************
  *  Transmit entry point
  *
@@ -867,7 +822,7 @@
 
 	while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
 		if (txr->tx_avail <= IGB_MAX_SCATTER) {
-			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
+			txr->queue_status |= IGB_QUEUE_DEPLETED;
 			break;
 		}
 		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
@@ -878,10 +833,10 @@
 		 *  NULL on failure.  In that event, we can't requeue.
 		 */
 		if (igb_xmit(txr, &m_head)) {
-			if (m_head == NULL)
-				break;
-			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
-			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
+			if (m_head != NULL)
+				IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
+			if (txr->tx_avail <= IGB_MAX_SCATTER)
+				txr->queue_status |= IGB_QUEUE_DEPLETED;
 			break;
 		}
 
@@ -890,7 +845,7 @@
 
 		/* Set watchdog on */
 		txr->watchdog_time = ticks;
-		txr->queue_status = IGB_QUEUE_WORKING;
+		txr->queue_status |= IGB_QUEUE_WORKING;
 	}
 }
  
@@ -913,7 +868,7 @@
 	return;
 }
 
-#else /* __FreeBSD_version >= 800000 */
+#if __FreeBSD_version >= 800000
 /*
 ** Multiqueue Transmit driver
 **
@@ -924,21 +879,25 @@
 	struct adapter		*adapter = ifp->if_softc;
 	struct igb_queue	*que;
 	struct tx_ring		*txr;
-	int 			i = 0, err = 0;
+	int 			i, err = 0;
+	bool			moveable = TRUE;
 
 	/* Which queue to use */
-	if ((m->m_flags & M_FLOWID) != 0)
+	if ((m->m_flags & M_FLOWID) != 0) {
 		i = m->m_pkthdr.flowid % adapter->num_queues;
+		moveable = FALSE;
+	} else
+		i = curcpu % adapter->num_queues;
 
 	txr = &adapter->tx_rings[i];
 	que = &adapter->queues[i];
-
-	if (IGB_TX_TRYLOCK(txr)) {
+	if (((txr->queue_status & IGB_QUEUE_DEPLETED) == 0) &&
+	    IGB_TX_TRYLOCK(txr)) {
 		err = igb_mq_start_locked(ifp, txr, m);
 		IGB_TX_UNLOCK(txr);
 	} else {
 		err = drbr_enqueue(ifp, txr->br, m);
-		taskqueue_enqueue(que->tq, &txr->txq_task);
+		taskqueue_enqueue(que->tq, &que->que_task);
 	}
 
 	return (err);
@@ -953,8 +912,9 @@
 
 	IGB_TX_LOCK_ASSERT(txr);
 
-	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
-	    IFF_DRV_RUNNING || adapter->link_active == 0) {
+	if (((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) ||
+	    (txr->queue_status == IGB_QUEUE_DEPLETED) ||
+	    adapter->link_active == 0) {
 		if (m != NULL)
 			err = drbr_enqueue(ifp, txr->br, m);
 		return (err);
@@ -982,39 +942,21 @@
 		ETHER_BPF_MTAP(ifp, next);
 		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
 			break;
-		if (txr->tx_avail <= IGB_TX_CLEANUP_THRESHOLD)
-			igb_txeof(txr);
-		if (txr->tx_avail <= IGB_MAX_SCATTER) {
-			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
-			break;
-		}
 		next = drbr_dequeue(ifp, txr->br);
 	}
 	if (enq > 0) {
 		/* Set the watchdog */
-		txr->queue_status = IGB_QUEUE_WORKING;
+		txr->queue_status |= IGB_QUEUE_WORKING;
 		txr->watchdog_time = ticks;
 	}
+	if (txr->tx_avail <= IGB_TX_CLEANUP_THRESHOLD)
+		igb_txeof(txr);
+	if (txr->tx_avail <= IGB_MAX_SCATTER)
+		txr->queue_status |= IGB_QUEUE_DEPLETED;
 	return (err);
 }
 
 /*
- * Called from a taskqueue to drain queued transmit packets.
- */
-static void
-igb_deferred_mq_start(void *arg, int pending)
-{
-	struct tx_ring *txr = arg;
-	struct adapter *adapter = txr->adapter;
-	struct ifnet *ifp = adapter->ifp;
-
-	IGB_TX_LOCK(txr);
-	if (!drbr_empty(ifp, txr->br))
-		igb_mq_start_locked(ifp, txr, NULL);
-	IGB_TX_UNLOCK(txr);
-}
-
-/*
 ** Flush all ring buffers
 */
 static void
@@ -1032,7 +974,7 @@
 	}
 	if_qflush(ifp);
 }
-#endif /* __FreeBSD_version < 800000 */
+#endif /* __FreeBSD_version >= 800000 */
 
 /*********************************************************************
  *  Ioctl entry point
@@ -1138,11 +1080,6 @@
 		}
 		break;
 	case SIOCSIFMEDIA:
-		/*
-		** As the speed/duplex settings are being
-		** changed, we need toreset the PHY.
-		*/
-		adapter->hw.phy.reset_disable = FALSE;
 		/* Check SOL/IDER usage */
 		IGB_CORE_LOCK(adapter);
 		if (e1000_check_reset_block(&adapter->hw)) {
@@ -1333,10 +1270,8 @@
 	}
 
 	/*