[Zrouter-src-freebsd] [rt2860-in-ral] 4 new revisions pushed by bschm... at techwires.net on 2012-03-14 09:48 GMT
rt2860-in-ral at googlecode.com
rt2860-in-ral at googlecode.com
Wed Mar 14 09:49:04 UTC 2012
4 new revisions:
Revision: 1f639e6b63b6
Author: Bernhard Schmidt <bschmidt at techwires.net>
Date: Wed Mar 14 01:48:10 2012
Log: move the rf/chan initialization stuff into reg.h, rename some
regs whi...
http://code.google.com/p/rt2860-in-ral/source/detail?r=1f639e6b63b6
Revision: 0a74d339b273
Author: Bernhard Schmidt <bschmidt at techwires.net>
Date: Wed Mar 14 01:49:59 2012
Log: no need for that
http://code.google.com/p/rt2860-in-ral/source/detail?r=0a74d339b273
Revision: 5d6745ae9c6a
Author: Bernhard Schmidt <bschmidt at techwires.net>
Date: Wed Mar 14 02:27:13 2012
Log: add RT2860_EEPROM_CTL() and friends
http://code.google.com/p/rt2860-in-ral/source/detail?r=5d6745ae9c6a
Revision: 0a72554935b9
Author: Bernhard Schmidt <bschmidt at techwires.net>
Date: Wed Mar 14 02:42:49 2012
Log: rename/move some constants
http://code.google.com/p/rt2860-in-ral/source/detail?r=0a72554935b9
==============================================================================
Revision: 1f639e6b63b6
Author: Bernhard Schmidt <bschmidt at techwires.net>
Date: Wed Mar 14 01:48:10 2012
Log: move the rf/chan initialization stuff into reg.h, rename some
regs while here
http://code.google.com/p/rt2860-in-ral/source/detail?r=1f639e6b63b6
Modified:
/sys/dev/ral/rt2860.c
/sys/dev/ral/rt2860reg.h
=======================================
--- /sys/dev/ral/rt2860.c Tue Mar 13 17:13:21 2012
+++ /sys/dev/ral/rt2860.c Wed Mar 14 01:48:10 2012
@@ -54,347 +54,6 @@
static void rt2872_rf_set_chan(struct rt2860_softc *sc,
struct ieee80211_channel *c);
-/*
- * Static variables
- */
-
-static const struct rt2860_rf_prog
-{
- uint8_t chan;
- uint32_t r1, r2, r3, r4;
-} rt2860_rf_2850[] =
-{
- { 1, 0x98402ecc, 0x984c0786, 0x9816b455, 0x9800510b },
- { 2, 0x98402ecc, 0x984c0786, 0x98168a55, 0x9800519f },
- { 3, 0x98402ecc, 0x984c078a, 0x98168a55, 0x9800518b },
- { 4, 0x98402ecc, 0x984c078a, 0x98168a55, 0x9800519f },
- { 5, 0x98402ecc, 0x984c078e, 0x98168a55, 0x9800518b },
- { 6, 0x98402ecc, 0x984c078e, 0x98168a55, 0x9800519f },
- { 7, 0x98402ecc, 0x984c0792, 0x98168a55, 0x9800518b },
- { 8, 0x98402ecc, 0x984c0792, 0x98168a55, 0x9800519f },
- { 9, 0x98402ecc, 0x984c0796, 0x98168a55, 0x9800518b },
- { 10, 0x98402ecc, 0x984c0796, 0x98168a55, 0x9800519f },
- { 11, 0x98402ecc, 0x984c079a, 0x98168a55, 0x9800518b },
- { 12, 0x98402ecc, 0x984c079a, 0x98168a55, 0x9800519f },
- { 13, 0x98402ecc, 0x984c079e, 0x98168a55, 0x9800518b },
- { 14, 0x98402ecc, 0x984c07a2, 0x98168a55, 0x98005193 },
- { 36, 0x98402ecc, 0x984c099a, 0x98158a55, 0x980ed1a3 },
- { 38, 0x98402ecc, 0x984c099e, 0x98158a55, 0x980ed193 },
- { 40, 0x98402ec8, 0x984c0682, 0x98158a55, 0x980ed183 },
- { 44, 0x98402ec8, 0x984c0682, 0x98158a55, 0x980ed1a3 },
- { 46, 0x98402ec8, 0x984c0686, 0x98158a55, 0x980ed18b },
- { 48, 0x98402ec8, 0x984c0686, 0x98158a55, 0x980ed19b },
- { 52, 0x98402ec8, 0x984c068a, 0x98158a55, 0x980ed193 },
- { 54, 0x98402ec8, 0x984c068a, 0x98158a55, 0x980ed1a3 },
- { 56, 0x98402ec8, 0x984c068e, 0x98158a55, 0x980ed18b },
- { 60, 0x98402ec8, 0x984c0692, 0x98158a55, 0x980ed183 },
- { 62, 0x98402ec8, 0x984c0692, 0x98158a55, 0x980ed193 },
- { 64, 0x98402ec8, 0x984c0692, 0x98158a55, 0x980ed1a3 },
- { 100, 0x98402ec8, 0x984c06b2, 0x98178a55, 0x980ed783 },
- { 102, 0x98402ec8, 0x985c06b2, 0x98578a55, 0x980ed793 },
- { 104, 0x98402ec8, 0x985c06b2, 0x98578a55, 0x980ed1a3 },
- { 108, 0x98402ecc, 0x985c0a32, 0x98578a55, 0x980ed193 },
- { 110, 0x98402ecc, 0x984c0a36, 0x98178a55, 0x980ed183 },
- { 112, 0x98402ecc, 0x984c0a36, 0x98178a55, 0x980ed19b },
- { 116, 0x98402ecc, 0x984c0a3a, 0x98178a55, 0x980ed1a3 },
- { 118, 0x98402ecc, 0x984c0a3e, 0x98178a55, 0x980ed193 },
- { 120, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed183 },
- { 124, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed193 },
- { 126, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed15b },
- { 128, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed1a3 },
- { 132, 0x98402ec4, 0x984c0386, 0x98178a55, 0x980ed18b },
- { 134, 0x98402ec4, 0x984c0386, 0x98178a55, 0x980ed193 },
- { 136, 0x98402ec4, 0x984c0386, 0x98178a55, 0x980ed19b },
- { 140, 0x98402ec4, 0x984c038a, 0x98178a55, 0x980ed183 },
- { 149, 0x98402ec4, 0x984c038a, 0x98178a55, 0x980ed1a7 },
- { 151, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed187 },
- { 153, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed18f },
- { 157, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed19f },
- { 159, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed1a7 },
- { 161, 0x98402ec4, 0x984c0392, 0x98178a55, 0x980ed187 },
- { 165, 0x98402ec4, 0x984c0392, 0x98178a55, 0x980ed197 },
- { 184, 0x95002ccc, 0x9500491e, 0x9509be55, 0x950c0a0b },
- { 188, 0x95002ccc, 0x95004922, 0x9509be55, 0x950c0a13 },
- { 192, 0x95002ccc, 0x95004926, 0x9509be55, 0x950c0a1b },
- { 196, 0x95002ccc, 0x9500492a, 0x9509be55, 0x950c0a23 },
- { 208, 0x95002ccc, 0x9500493a, 0x9509be55, 0x950c0a13 },
- { 212, 0x95002ccc, 0x9500493e, 0x9509be55, 0x950c0a1b },
- { 216, 0x95002ccc, 0x95004982, 0x9509be55, 0x950c0a23 },
-};
-
-static const struct rfprog {
- uint8_t chan;
- uint32_t r1, r2, r3, r4;
-} rt2860_rf2850[] = {
- { 1, 0x100bb3, 0x1301e1, 0x05a014, 0x001402 },
- { 2, 0x100bb3, 0x1301e1, 0x05a014, 0x001407 },
- { 3, 0x100bb3, 0x1301e2, 0x05a014, 0x001402 },
- { 4, 0x100bb3, 0x1301e2, 0x05a014, 0x001407 },
- { 5, 0x100bb3, 0x1301e3, 0x05a014, 0x001402 },
- { 6, 0x100bb3, 0x1301e3, 0x05a014, 0x001407 },
- { 7, 0x100bb3, 0x1301e4, 0x05a014, 0x001402 },
- { 8, 0x100bb3, 0x1301e4, 0x05a014, 0x001407 },
- { 9, 0x100bb3, 0x1301e5, 0x05a014, 0x001402 },
- { 10, 0x100bb3, 0x1301e5, 0x05a014, 0x001407 },
- { 11, 0x100bb3, 0x1301e6, 0x05a014, 0x001402 },
- { 12, 0x100bb3, 0x1301e6, 0x05a014, 0x001407 },
- { 13, 0x100bb3, 0x1301e7, 0x05a014, 0x001402 },
- { 14, 0x100bb3, 0x1301e8, 0x05a014, 0x001404 },
- { 36, 0x100bb3, 0x130266, 0x056014, 0x001408 },
- { 38, 0x100bb3, 0x130267, 0x056014, 0x001404 },
- { 40, 0x100bb2, 0x1301a0, 0x056014, 0x001400 },
- { 44, 0x100bb2, 0x1301a0, 0x056014, 0x001408 },
- { 46, 0x100bb2, 0x1301a1, 0x056014, 0x001402 },
- { 48, 0x100bb2, 0x1301a1, 0x056014, 0x001406 },
- { 52, 0x100bb2, 0x1301a2, 0x056014, 0x001404 },
- { 54, 0x100bb2, 0x1301a2, 0x056014, 0x001408 },
- { 56, 0x100bb2, 0x1301a3, 0x056014, 0x001402 },
- { 60, 0x100bb2, 0x1301a4, 0x056014, 0x001400 },
- { 62, 0x100bb2, 0x1301a4, 0x056014, 0x001404 },
- { 64, 0x100bb2, 0x1301a4, 0x056014, 0x001408 },
- { 100, 0x100bb2, 0x1301ac, 0x05e014, 0x001400 },
- { 102, 0x100bb2, 0x1701ac, 0x15e014, 0x001404 },
- { 104, 0x100bb2, 0x1701ac, 0x15e014, 0x001408 },
- { 108, 0x100bb3, 0x17028c, 0x15e014, 0x001404 },
- { 110, 0x100bb3, 0x13028d, 0x05e014, 0x001400 },
- { 112, 0x100bb3, 0x13028d, 0x05e014, 0x001406 },
- { 116, 0x100bb3, 0x13028e, 0x05e014, 0x001408 },
- { 118, 0x100bb3, 0x13028f, 0x05e014, 0x001404 },
- { 120, 0x100bb1, 0x1300e0, 0x05e014, 0x001400 },
- { 124, 0x100bb1, 0x1300e0, 0x05e014, 0x001404 },
- { 126, 0x100bb1, 0x1300e0, 0x05e014, 0x001406 },
- { 128, 0x100bb1, 0x1300e0, 0x05e014, 0x001408 },
- { 132, 0x100bb1, 0x1300e1, 0x05e014, 0x001402 },
- { 134, 0x100bb1, 0x1300e1, 0x05e014, 0x001404 },
- { 136, 0x100bb1, 0x1300e1, 0x05e014, 0x001406 },
- { 140, 0x100bb1, 0x1300e2, 0x05e014, 0x001400 },
- { 149, 0x100bb1, 0x1300e2, 0x05e014, 0x001409 },
- { 151, 0x100bb1, 0x1300e3, 0x05e014, 0x001401 },
- { 153, 0x100bb1, 0x1300e3, 0x05e014, 0x001403 },
- { 157, 0x100bb1, 0x1300e3, 0x05e014, 0x001407 },
- { 159, 0x100bb1, 0x1300e3, 0x05e014, 0x001409 },
- { 161, 0x100bb1, 0x1300e4, 0x05e014, 0x001401 },
- { 165, 0x100bb1, 0x1300e4, 0x05e014, 0x001405 },
- { 167, 0x100bb1, 0x1300f4, 0x05e014, 0x001407 },
- { 169, 0x100bb1, 0x1300f4, 0x05e014, 0x001409 },
- { 171, 0x100bb1, 0x1300f5, 0x05e014, 0x001401 },
- { 173, 0x100bb1, 0x1300f5, 0x05e014, 0x001403 }
-};
-
-static const struct rt2860_rf_fi3020
-{
- uint8_t channel, n, r, k;
-} rt2860_rf_fi3020[] =
-{
- /* 802.11g */
- {1, 241, 2, 2},
- {2, 241, 2, 7},
- {3, 242, 2, 2},
- {4, 242, 2, 7},
- {5, 243, 2, 2},
- {6, 243, 2, 7},
- {7, 244, 2, 2},
- {8, 244, 2, 7},
- {9, 245, 2, 2},
- {10, 245, 2, 7},
- {11, 246, 2, 2},
- {12, 246, 2, 7},
- {13, 247, 2, 2},
- {14, 248, 2, 4},
-
- /* 802.11 UNI / HyperLan 2 */
- {36, 0x56, 0, 4},
- {38, 0x56, 0, 6},
- {40, 0x56, 0, 8},
- {44, 0x57, 0, 0},
- {46, 0x57, 0, 2},
- {48, 0x57, 0, 4},
- {52, 0x57, 0, 8},
- {54, 0x57, 0, 10},
- {56, 0x58, 0, 0},
- {60, 0x58, 0, 4},
- {62, 0x58, 0, 6},
- {64, 0x58, 0, 8},
-
- /* 802.11 HyperLan 2 */
- {100, 0x5b, 0, 8},
- {102, 0x5b, 0, 10},
- {104, 0x5c, 0, 0},
- {108, 0x5c, 0, 4},
- {110, 0x5c, 0, 6},
- {112, 0x5c, 0, 8},
- {116, 0x5d, 0, 0},
- {118, 0x5d, 0, 2},
- {120, 0x5d, 0, 4},
- {124, 0x5d, 0, 8},
- {126, 0x5d, 0, 10},
- {128, 0x5e, 0, 0},
- {132, 0x5e, 0, 4},
- {134, 0x5e, 0, 6},
- {136, 0x5e, 0, 8},
- {140, 0x5f, 0, 0},
-
- /* 802.11 UNII */
- {149, 0x5f, 0, 9},
- {151, 0x5f, 0, 11},
- {153, 0x60, 0, 1},
- {157, 0x60, 0, 5},
- {159, 0x60, 0, 7},
- {161, 0x60, 0, 9},
- {165, 0x61, 0, 1},
- {167, 0x61, 0, 3},
- {169, 0x61, 0, 5},
- {171, 0x61, 0, 7},
- {173, 0x61, 0, 9},
-};
-
-static const struct {
- uint8_t reg;
- uint8_t val;
-} rt3090_def_rf[] = {
- { 4, 0x40 },
- { 5, 0x03 },
- { 6, 0x02 },
- { 7, 0x70 },
- { 9, 0x0f },
- { 10, 0x41 },
- { 11, 0x21 },
- { 12, 0x7b },
- { 14, 0x90 },
- { 15, 0x58 },
- { 16, 0xb3 },
- { 17, 0x92 },
- { 18, 0x2c },
- { 19, 0x02 },
- { 20, 0xba },
- { 21, 0xdb },
- { 24, 0x16 },
- { 25, 0x01 },
- { 29, 0x1f }
-};
-
-struct {
- uint8_t n, r, k;
-} rt3090_freqs[] = {
- { 0xf1, 2, 2 },
- { 0xf1, 2, 7 },
- { 0xf2, 2, 2 },
- { 0xf2, 2, 7 },
- { 0xf3, 2, 2 },
- { 0xf3, 2, 7 },
- { 0xf4, 2, 2 },
- { 0xf4, 2, 7 },
- { 0xf5, 2, 2 },
- { 0xf5, 2, 7 },
- { 0xf6, 2, 2 },
- { 0xf6, 2, 7 },
- { 0xf7, 2, 2 },
- { 0xf8, 2, 4 },
- { 0x56, 0, 4 },
- { 0x56, 0, 6 },
- { 0x56, 0, 8 },
- { 0x57, 0, 0 },
- { 0x57, 0, 2 },
- { 0x57, 0, 4 },
- { 0x57, 0, 8 },
- { 0x57, 0, 10 },
- { 0x58, 0, 0 },
- { 0x58, 0, 4 },
- { 0x58, 0, 6 },
- { 0x58, 0, 8 },
- { 0x5b, 0, 8 },
- { 0x5b, 0, 10 },
- { 0x5c, 0, 0 },
- { 0x5c, 0, 4 },
- { 0x5c, 0, 6 },
- { 0x5c, 0, 8 },
- { 0x5d, 0, 0 },
- { 0x5d, 0, 2 },
- { 0x5d, 0, 4 },
- { 0x5d, 0, 8 },
- { 0x5d, 0, 10 },
- { 0x5e, 0, 0 },
- { 0x5e, 0, 4 },
- { 0x5e, 0, 6 },
- { 0x5e, 0, 8 },
- { 0x5f, 0, 0 },
- { 0x5f, 0, 9 },
- { 0x5f, 0, 11 },
- { 0x60, 0, 1 },
- { 0x60, 0, 5 },
- { 0x60, 0, 7 },
- { 0x60, 0, 9 },
- { 0x61, 0, 1 },
- { 0x61, 0, 3 },
- { 0x61, 0, 5 },
- { 0x61, 0, 7 },
- { 0x61, 0, 9 }
-};
-
-static const struct {
- uint32_t reg;
- uint32_t val;
-} rt2860_def_mac[] = {
- { RT2860_REG_PBF_BCN_OFFSET0, 0xf8f0e8e0 },
- { RT2860_REG_PBF_BCN_OFFSET1, 0x6f77d0c8 },
- { RT2860_REG_LEGACY_BASIC_RATE, 0x0000013f },
- { RT2860_REG_HT_BASIC_RATE, 0x00008003 },
- { RT2860_REG_SYS_CTRL, 0x00000000 },
- { RT2860_REG_RX_FILTER_CFG, 0x00017f97 },
- { RT2860_REG_BKOFF_SLOT_CFG, 0x00000209 },
- { RT2860_REG_TX_SW_CFG0, 0x00000000 },
- { RT2860_REG_TX_SW_CFG1, 0x00080606 },
- { RT2860_REG_TX_LINK_CFG, 0x00001020 },
- { RT2860_REG_TX_TIMEOUT_CFG, 0x000a2090 },
- { RT2860_REG_MAX_LEN_CFG, (1 << 12) | RT2860_MAX_AGG_SIZE },
- { RT2860_REG_LED_CFG, 0x7f031e46 },
- { RT2860_REG_PBF_MAX_PCNT, 0x1f3fbf9f },
- { RT2860_REG_TX_RTY_CFG, 0x47d01f0f },
- { RT2860_REG_AUTO_RSP_CFG, 0x00000013 },
- { RT2860_REG_TX_CCK_PROT_CFG, 0x05740003 },
- { RT2860_REG_TX_OFDM_PROT_CFG, 0x05740003 },
- { RT2860_REG_TX_GF20_PROT_CFG, 0x01744004 },
- { RT2860_REG_TX_GF40_PROT_CFG, 0x03f44084 },
- { RT2860_REG_TX_MM20_PROT_CFG, 0x01744004 },
- { RT2860_REG_TX_MM40_PROT_CFG, 0x03f54084 },
- { RT2860_REG_TX_TXOP_CTRL_CFG, 0x0000583f },
- { RT2860_REG_TX_RTS_CFG, 0x00092b20 },
- { RT2860_REG_TX_EXP_ACK_TIME, 0x002400ca },
- { RT2860_REG_HCCAPSMP_TXOP_HLDR_ET, 0x00000002 },
- { RT2860_REG_XIFS_TIME_CFG, 0x33a41010 },
- { RT2860_REG_PWR_PIN_CFG, 0x00000003 },
- { RT2860_REG_SCHDMA_WMM_AIFSN_CFG, 0x00002273 },
- { RT2860_REG_SCHDMA_WMM_CWMIN_CFG, 0x00002344 },
- { RT2860_REG_SCHDMA_WMM_CWMAX_CFG, 0x000034aa },
-};
-
-#define RT2860_DEF_MAC_SIZE \
- (sizeof(rt2860_def_mac) / sizeof(rt2860_def_mac[0]))
-
-static const struct {
- uint8_t reg;
- uint8_t val;
-} rt2860_def_bbp[] = {
- { 65, 0x2c },
- { 66, 0x38 },
- { 69, 0x12 },
- { 70, 0x0a },
- { 73, 0x10 },
- { 81, 0x37 },
- { 82, 0x62 },
- { 83, 0x6a },
- { 84, 0x99 },
- { 86, 0x00 },
- { 91, 0x04 },
- { 92, 0x00 },
- { 103, 0x00 },
- { 105, 0x05 },
- { 106, 0x35 },
-};
-
-#define RT2860_DEF_BBP_SIZE \
- (sizeof(rt2860_def_bbp) / sizeof(rt2860_def_bbp[0]))
-
/*
* Static function prototypes
*/
@@ -623,6 +282,40 @@
TUNABLE_INT("hw.ral.debug", &rt2860_debug);
#endif
+static const struct {
+ uint32_t reg;
+ uint32_t val;
+} rt2860_def_mac[] = {
+ RT2860_DEF_MAC
+};
+
+static const struct {
+ uint8_t reg;
+ uint8_t val;
+} rt2860_def_bbp[] = {
+ RT2860_DEF_BBP
+};
+
+static const struct rfprog {
+ uint8_t chan;
+ uint32_t r1, r2, r3, r4;
+} rt2860_rf2850[] = {
+ RT2860_RF2850
+};
+
+struct {
+ uint8_t n, r, k;
+} rt3090_freqs[] = {
+ RT3070_RF3052
+};
+
+static const struct {
+ uint8_t reg;
+ uint8_t val;
+} rt3090_def_rf[] = {
+ RT3070_DEF_RF
+};
+
/*
* rt2860_attach
*/
@@ -1251,6 +944,7 @@
*/
static void rt2860_init_locked(void *priv)
{
+#define nitems(_a) (sizeof((_a)) / sizeof((_a)[0]))
struct rt2860_softc *sc;
struct ifnet *ifp;
struct ieee80211com *ic;
@@ -1284,7 +978,7 @@
sc->flags |= RT2860_SOFTC_FLAGS_UCODE_LOADED;
/* Blink every TX */
- RAL_WRITE(sc, RT2860_REG_LED_CFG,
+ RAL_WRITE(sc, RT2860_LED_CFG,
LED_CFG_LED_POLARITY |
LED_CFG_Y_LED_MODE_ONTX |
LED_CFG_G_LED_MODE_ONTX |
@@ -1294,7 +988,7 @@
LED_CFG_LED_ON_TIME);
}
- RAL_WRITE(sc, RT2860_REG_PWR_PIN_CFG, 0x2);
+ RAL_WRITE(sc, RT2860_PWR_PIN_CFG, 0x2);
/* disable DMA engine */
@@ -1349,11 +1043,11 @@
RAL_WRITE(sc, RT2860_REG_PBF_SYS_CTRL, 0xe1f);
RAL_WRITE(sc, RT2860_REG_PBF_SYS_CTRL, 0xe00);
- RAL_WRITE(sc, RT2860_REG_PWR_PIN_CFG, 0x3);
-
- RAL_WRITE(sc, RT2860_REG_SYS_CTRL,
+ RAL_WRITE(sc, RT2860_PWR_PIN_CFG, 0x3);
+
+ RAL_WRITE(sc, RT2860_MAC_SYS_CTRL,
RT2860_REG_MAC_SRST | RT2860_REG_BBP_HRST);
- RAL_WRITE(sc, RT2860_REG_SYS_CTRL, 0);
+ RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0);
/* init Tx power per rate */
@@ -1365,9 +1059,8 @@
sc->txpow_rate_20mhz[i]);
}
- for (i = 0; i < RT2860_DEF_MAC_SIZE; i++)
- RAL_WRITE(sc, rt2860_def_mac[i].reg,
- rt2860_def_mac[i].val);
+ for (i = 0; i < nitems(rt2860_def_mac); i++)
+ RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val);
/* wait while MAC is busy */
@@ -1593,12 +1286,12 @@
/* set current channel */
rt2860_rf_set_chan(sc, ic->ic_curchan);
- RAL_WRITE(sc, RT2860_REG_SCHDMA_WMM_TXOP0_CFG, 0);
- RAL_WRITE(sc, RT2860_REG_SCHDMA_WMM_TXOP1_CFG,
+ RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG, 0);
+ RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG,
(48 << 16) | 96);
if ((sc->mac_rev & 0xffff) != 0x0101)
- RAL_WRITE(sc, RT2860_REG_TX_TXOP_CTRL_CFG, 0x583f);
+ RAL_WRITE(sc, RT2860_TXOP_CTRL_CFG, 0x583f);
/* clear pending interrupts */
@@ -1641,6 +1334,7 @@
fail:
rt2860_stop_locked(sc);
+#undef nitems
}
/*
@@ -1664,6 +1358,7 @@
*/
static int rt2860_init_bbp(struct rt2860_softc *sc)
{
+#define nitems(_a) (sizeof((_a)) / sizeof((_a)[0]))
int ntries, i;
uint8_t tmp;
@@ -1679,9 +1374,10 @@
return ETIMEDOUT;
}
- for (i = 0; i < RT2860_DEF_BBP_SIZE; i++)
+ for (i = 0; i < nitems(rt2860_def_bbp); i++) {
rt2860_io_bbp_write(sc, rt2860_def_bbp[i].reg,
rt2860_def_bbp[i].val);
+ }
if ((sc->mac_rev & 0xffff) != 0x0101)
rt2860_io_bbp_write(sc, 84, 0x19);
@@ -1692,6 +1388,7 @@
}
return 0;
+#undef nitems
}
/*
@@ -1745,17 +1442,17 @@
/* disable Tx/Rx */
- tmp = RAL_READ(sc, RT2860_REG_SYS_CTRL);
+ tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL);
tmp &= ~(RT2860_REG_RX_ENABLE | RT2860_REG_TX_ENABLE);
- RAL_WRITE(sc, RT2860_REG_SYS_CTRL, tmp);
+ RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp);
/* reset adapter */
- RAL_WRITE(sc, RT2860_REG_SYS_CTRL,
+ RAL_WRITE(sc, RT2860_MAC_SYS_CTRL,
RT2860_REG_MAC_SRST | RT2860_REG_BBP_HRST);
- RAL_WRITE(sc, RT2860_REG_SYS_CTRL, 0);
+ RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0);
}
/*
@@ -3598,14 +3295,14 @@
device_get_nameunit(sc->sc_dev),
(ic->ic_flags & IEEE80211_F_SHPREAMBLE) ? "enabling" : "disabling");
- tmp = RAL_READ(sc, RT2860_REG_AUTO_RSP_CFG);
+ tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG);
tmp &= ~RT2860_REG_CCK_SHORT_ENABLE;
if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
tmp |= RT2860_REG_CCK_SHORT_ENABLE;
- RAL_WRITE(sc, RT2860_REG_AUTO_RSP_CFG, tmp);
+ RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp);
}
/*
@@ -3620,11 +3317,11 @@
ic = ifp->if_l2com;
if (ic->ic_curmode == IEEE80211_MODE_11B)
- RAL_WRITE(sc, RT2860_REG_LEGACY_BASIC_RATE, 0xf);
+ RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0xf);
else if (ic->ic_curmode == IEEE80211_MODE_11A)
- RAL_WRITE(sc, RT2860_REG_LEGACY_BASIC_RATE, 0x150);
+ RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x150);
else
- RAL_WRITE(sc, RT2860_REG_LEGACY_BASIC_RATE, 0x15f);
+ RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, 0x15f);
}
/*
@@ -3653,14 +3350,14 @@
"%s: updating RTS threshold: %d\n",
device_get_nameunit(sc->sc_dev), threshold);
- tmp = RAL_READ(sc, RT2860_REG_TX_RTS_CFG);
+ tmp = RAL_READ(sc, RT2860_TX_RTS_CFG);
tmp &= ~(RT2860_REG_TX_RTS_THRESHOLD_MASK <<
RT2860_REG_TX_RTS_THRESHOLD_SHIFT);
tmp |= ((threshold & RT2860_REG_TX_RTS_THRESHOLD_MASK) <<
RT2860_REG_TX_RTS_THRESHOLD_SHIFT);
- RAL_WRITE(sc, RT2860_REG_TX_RTS_CFG, tmp);
+ RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp);
}
/*
@@ -3775,7 +3472,7 @@
cck_prot |= ((RT2860_REG_PROT_PHYMODE_CCK <<
RT2860_REG_PROT_PHYMODE_SHIFT) |
(3 << RT2860_REG_PROT_MCS_SHIFT));
- RAL_WRITE(sc, RT2860_REG_TX_CCK_PROT_CFG, cck_prot);
+ RAL_WRITE(sc, RT2860_CCK_PROT_CFG, cck_prot);
/* OFDM frame protection */
@@ -3803,7 +3500,7 @@
ofdm_prot |= RT2860_REG_PROT_CTRL_NONE;
}
- RAL_WRITE(sc, RT2860_REG_TX_OFDM_PROT_CFG, ofdm_prot);
+ RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, ofdm_prot);
/* HT frame protection */
@@ -3922,10 +3619,10 @@
break;
}
- RAL_WRITE(sc, RT2860_REG_TX_MM20_PROT_CFG, mm20_prot);
- RAL_WRITE(sc, RT2860_REG_TX_MM40_PROT_CFG, mm40_prot);
- RAL_WRITE(sc, RT2860_REG_TX_GF20_PROT_CFG, gf20_prot);
- RAL_WRITE(sc, RT2860_REG_TX_GF40_PROT_CFG, gf40_prot);
+ RAL_WRITE(sc, RT2860_MM20_PROT_CFG, mm20_prot);
+ RAL_WRITE(sc, RT2860_MM40_PROT_CFG, mm40_prot);
+ RAL_WRITE(sc, RT2860_GF20_PROT_CFG, gf20_prot);
+ RAL_WRITE(sc, RT2860_GF40_PROT_CFG, gf40_prot);
}
/*
@@ -3948,7 +3645,7 @@
((ic->ic_flags & IEEE80211_F_SHSLOT) ||
((vap != NULL) && (vap->iv_flags &
IEEE80211_F_BURST))) ? "enabling" : "disabling");
- tmp = RAL_READ(sc, RT2860_REG_BKOFF_SLOT_CFG);
+ tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG);
tmp &= ~0xff;
@@ -3958,7 +3655,7 @@
else
tmp |= IEEE80211_DUR_SLOT;
- RAL_WRITE(sc, RT2860_REG_BKOFF_SLOT_CFG, tmp);
+ RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp);
}
/*
@@ -3999,22 +3696,22 @@
(wmep[i].wmep_logcwmax << 16) | (wmep[i].wmep_logcwmin << 12) |
(wmep[i].wmep_aifsn << 8) | wmep[i].wmep_txopLimit);
- RAL_WRITE(sc, RT2860_REG_SCHDMA_WMM_AIFSN_CFG,
+ RAL_WRITE(sc, RT2860_WMM_AIFSN_CFG,
(wmep[WME_AC_VO].wmep_aifsn << 12) | (wmep[WME_AC_VI].wmep_aifsn << 8) |
(wmep[WME_AC_BK].wmep_aifsn << 4) | wmep[WME_AC_BE].wmep_aifsn);
- RAL_WRITE(sc, RT2860_REG_SCHDMA_WMM_CWMIN_CFG,
+ RAL_WRITE(sc, RT2860_WMM_CWMIN_CFG,
(wmep[WME_AC_VO].wmep_logcwmin << 12) | (wmep[WME_AC_VI].wmep_logcwmin
<< 8) |
(wmep[WME_AC_BK].wmep_logcwmin << 4) | wmep[WME_AC_BE].wmep_logcwmin);
- RAL_WRITE(sc, RT2860_REG_SCHDMA_WMM_CWMAX_CFG,
+ RAL_WRITE(sc, RT2860_WMM_CWMAX_CFG,
(wmep[WME_AC_VO].wmep_logcwmax << 12) | (wmep[WME_AC_VI].wmep_logcwmax
<< 8) |
(wmep[WME_AC_BK].wmep_logcwmax << 4) | wmep[WME_AC_BE].wmep_logcwmax);
- RAL_WRITE(sc, RT2860_REG_SCHDMA_WMM_TXOP0_CFG,
+ RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG,
(wmep[WME_AC_BK].wmep_txopLimit << 16) | wmep[WME_AC_BE].wmep_txopLimit);
- RAL_WRITE(sc, RT2860_REG_SCHDMA_WMM_TXOP1_CFG,
+ RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG,
(wmep[WME_AC_VO].wmep_txopLimit << 16) | wmep[WME_AC_VI].wmep_txopLimit);
}
@@ -6257,7 +5954,7 @@
/* enable Tx/Rx DMA engine */
- RAL_WRITE(sc, RT2860_REG_SYS_CTRL, RT2860_REG_TX_ENABLE);
+ RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_REG_TX_ENABLE);
for (ntries = 0; ntries < 200; ntries++) {
tmp = RAL_READ(sc, RT2860_REG_SCHDMA_WPDMA_GLO_CFG);
@@ -6306,7 +6003,7 @@
RAL_WRITE(sc, RT2860_REG_RX_FILTER_CFG, tmp);
- RAL_WRITE(sc, RT2860_REG_SYS_CTRL,
+ RAL_WRITE(sc, RT2860_MAC_SYS_CTRL,
RT2860_REG_RX_ENABLE | RT2860_REG_TX_ENABLE);
return 0;
@@ -8939,12 +8636,12 @@
rt2860_io_bbp_write(sc, 31, bbp & ~0x03);
}
- RAL_WRITE(sc, RT2860_REG_TX_SW_CFG1, 0);
+ RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0);
if ((sc->mac_rev & 0x0000ffff) < 0x0211) {
- RAL_WRITE(sc, RT2860_REG_TX_SW_CFG2,
+ RAL_WRITE(sc, RT2860_TX_SW_CFG2,
sc->patch_dac ? 0x2c : 0x0f);
} else
- RAL_WRITE(sc, RT2860_REG_TX_SW_CFG2, 0);
+ RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0);
/* initialize RF registers from ROM */
for (i = 0; i < 10; i++) {
@@ -8963,7 +8660,7 @@
{
struct ifnet *ifp;
struct ieee80211com *ic;
- const struct rt2860_rf_prog *prog;
+ const struct rfprog *prog;
uint32_t r1, r2, r3, r4;
int8_t txpow1, txpow2;
int i, chan;
@@ -8975,7 +8672,7 @@
ifp = sc->sc_ifp;
ic = ifp->if_l2com;
- prog = rt2860_rf_2850;
+ prog = rt2860_rf2850;
/* get central channel position */
@@ -9092,7 +8789,7 @@
{
struct ifnet *ifp;
struct ieee80211com *ic;
- const struct rt2860_rf_prog *prog;
+ const struct rfprog *prog;
uint32_t r1, r2, r3, r4;
uint32_t r6, r7, r12, r13, r23, r24;
int8_t txpow1, txpow2;
@@ -9100,7 +8797,7 @@
ifp = sc->sc_ifp;
ic = ifp->if_l2com;
- prog = rt2860_rf_2850;
+ prog = rt2860_rf2850;
/* get central channel position */
@@ -9133,15 +8830,15 @@
txpow1 = sc->txpow1[i];
txpow2 = sc->txpow2[i];
- for (i = 0; rt2860_rf_fi3020[i].channel != chan; i++);
+ for (i = 0; rt2860_rf2850[i].chan != chan; i++);
/* Programm channel parameters */
- r2 = rt2860_rf_fi3020[i].n;
+ r2 = rt3090_freqs[i].n;
rt2860_io_rf_write(sc, 2 , r2 );
- r3 = rt2860_rf_fi3020[i].k;
+ r3 = rt3090_freqs[i].k;
rt2860_io_rf_write(sc, 3 , r3 );
- r6 = (rt3052_rf_default[6] & 0xFC) | (rt2860_rf_fi3020[i].r & 0x03);
+ r6 = (rt3052_rf_default[6] & 0xFC) | (rt3090_freqs[i].r & 0x03);
rt2860_io_rf_write(sc, 6 , r6 );
/* Set Tx Power */
=======================================
--- /sys/dev/ral/rt2860reg.h Tue Mar 13 14:01:39 2012
+++ /sys/dev/ral/rt2860reg.h Wed Mar 14 01:48:10 2012
@@ -30,11 +30,11 @@
#define RT2860_REG_SCHDMA_WPDMA_GLO_CFG 0x0208
#define RT2860_REG_SCHDMA_WPDMA_RST_IDX 0x020c
#define RT2860_REG_SCHDMA_DELAY_INT_CFG 0x0210
-#define RT2860_REG_SCHDMA_WMM_AIFSN_CFG 0x0214
-#define RT2860_REG_SCHDMA_WMM_CWMIN_CFG 0x0218
-#define RT2860_REG_SCHDMA_WMM_CWMAX_CFG 0x021c
-#define RT2860_REG_SCHDMA_WMM_TXOP0_CFG 0x0220
-#define RT2860_REG_SCHDMA_WMM_TXOP1_CFG 0x0224
+#define RT2860_WMM_AIFSN_CFG 0x0214
+#define RT2860_WMM_CWMIN_CFG 0x0218
+#define RT2860_WMM_CWMAX_CFG 0x021c
+#define RT2860_WMM_TXOP0_CFG 0x0220
+#define RT2860_WMM_TXOP1_CFG 0x0224
#define RT2860_REG_SCHDMA_GPIO_CTRL_CFG 0x0228
#define RT2860_REG_SCHDMA_RX_BASE_PTR 0x0290
#define RT2860_REG_SCHDMA_RX_MAX_CNT 0x0294
@@ -49,7 +49,7 @@
#define RT2860_REG_PBF_SYS_CTRL 0x0400
#define RT2860_REG_PBF_HOST_CMD 0x0404
#define RT2860_REG_PBF_CFG 0x0408
-#define RT2860_REG_PBF_MAX_PCNT 0x040c
+#define RT2860_MAX_PCNT 0x040c
#define RT2860_REG_PBF_BUF_CTRL 0x0410
#define RT2860_REG_PBF_MCU_INT_STA 0x0414
#define RT2860_REG_PBF_MCU_INT_ENA 0x0418
@@ -57,7 +57,7 @@
#define RT2860_REG_PBF_TX1Q_IO 0x0420
#define RT2860_REG_PBF_TX2Q_IO 0x0424
#define RT2860_REG_PBF_RX0Q_IO 0x0428
-#define RT2860_REG_PBF_BCN_OFFSET0 0x042c
+#define RT2860_BCN_OFFSET0 0x042c
#define RT2860_REG_PBF_BCN_OFFSET1 0x0430
#define RT2860_REG_PBF_TXRXQ_STA 0x0434
#define RT2860_REG_PBF_TXRXQ_PCNT 0x0438
@@ -69,7 +69,7 @@
#define RT2872_REG_RF_TEST_CONTROL 0x508
#define RT2860_REG_MAC_CSR0 0x1000
-#define RT2860_REG_SYS_CTRL 0x1004
+#define RT2860_MAC_SYS_CTRL 0x1004
#define RT2860_REG_ADDR_DW0 0x1008
#define RT2860_REG_ADDR_DW1 0x100c
#define RT2860_REG_BSSID_DW0 0x1010
@@ -77,15 +77,15 @@
#define RT2860_REG_MAX_LEN_CFG 0x1018
#define RT2860_REG_BBP_CSR_CFG 0x101c
#define RT2860_REG_RF_CSR_CFG0 0x1020
-#define RT2860_REG_LED_CFG 0x102c
+#define RT2860_LED_CFG 0x102c
#define RT2860_REG_AMPDU_MAX_LEN_20M1S 0x1030
#define RT2860_REG_AMPDU_MAX_LEN_20M2S 0x1034
#define RT2860_REG_AMPDU_MAX_LEN_40M1S 0x1038
#define RT2860_REG_AMPDU_MAX_LEN_40M2S 0x103c
#define RT2860_REG_AMPDU_BA_WINSIZE 0x1040
-#define RT2860_REG_XIFS_TIME_CFG 0x1100
-#define RT2860_REG_BKOFF_SLOT_CFG 0x1104
+#define RT2860_XIFS_TIME_CFG 0x1100
+#define RT2860_BKOFF_SLOT_CFG 0x1104
#define RT2860_REG_NAV_TIME_CFG 0x1108
#define RT2860_REG_CH_TIME_CFG 0x110c
#define RT2860_REG_PBF_LIFE_TIMER 0x1110
@@ -99,7 +99,7 @@
#define RT2860_REG_CH_IDLE_STA 0x1130
#define RT2860_REG_STATUS_CFG 0x1200
-#define RT2860_REG_PWR_PIN_CFG 0x1204
+#define RT2860_PWR_PIN_CFG 0x1204
#define RT2860_REG_AUTO_WAKEUP_CFG 0x1208
#define RT2860_REG_TX_EDCA_AC_CFG(aci) (0x1300 + (aci) * 4)
@@ -107,32 +107,32 @@
#define RT2860_REG_TX_PWR_CFG(ridx) (0x1314 + (ridx) * 4)
#define RT2860_REG_TX_PIN_CFG 0x1328
#define RT2860_REG_TX_BAND_CFG 0x132c
-#define RT2860_REG_TX_SW_CFG0 0x1330
-#define RT2860_REG_TX_SW_CFG1 0x1334
-#define RT2860_REG_TX_SW_CFG2 0x1338
+#define RT2860_TX_SW_CFG0 0x1330
+#define RT2860_TX_SW_CFG1 0x1334
+#define RT2860_TX_SW_CFG2 0x1338
#define RT2860_REG_TX_TXOP_THRES_CFG 0x133c
-#define RT2860_REG_TX_TXOP_CTRL_CFG 0x1340
-#define RT2860_REG_TX_RTS_CFG 0x1344
-#define RT2860_REG_TX_TIMEOUT_CFG 0x1348
-#define RT2860_REG_TX_RTY_CFG 0x134c
-#define RT2860_REG_TX_LINK_CFG 0x1350
+#define RT2860_TXOP_CTRL_CFG 0x1340
+#define RT2860_TX_RTS_CFG 0x1344
+#define RT2860_TX_TIMEOUT_CFG 0x1348
+#define RT2860_TX_RTY_CFG 0x134c
+#define RT2860_TX_LINK_CFG 0x1350
#define RT2860_REG_TX_HT_FBK_CFG0 0x1354
#define RT2860_REG_TX_HT_FBK_CFG1 0x1358
#define RT2860_REG_TX_LG_FBK_CFG0 0x135c
#define RT2860_REG_TX_LG_FBK_CFG1 0x1360
-#define RT2860_REG_TX_CCK_PROT_CFG 0x1364
-#define RT2860_REG_TX_OFDM_PROT_CFG 0x1368
-#define RT2860_REG_TX_MM20_PROT_CFG 0x136c
-#define RT2860_REG_TX_MM40_PROT_CFG 0x1370
-#define RT2860_REG_TX_GF20_PROT_CFG 0x1374
-#define RT2860_REG_TX_GF40_PROT_CFG 0x1378
+#define RT2860_CCK_PROT_CFG 0x1364
+#define RT2860_OFDM_PROT_CFG 0x1368
+#define RT2860_MM20_PROT_CFG 0x136c
+#define RT2860_MM40_PROT_CFG 0x1370
+#define RT2860_GF20_PROT_CFG 0x1374
+#define RT2860_GF40_PROT_CFG 0x1378
#define RT2860_REG_TX_EXP_CTS_TIME 0x137c
-#define RT2860_REG_TX_EXP_ACK_TIME 0x1380
+#define RT2860_EXP_ACK_TIME 0x1380
#define RT2860_REG_RX_FILTER_CFG 0x1400
-#define RT2860_REG_AUTO_RSP_CFG 0x1404
-#define RT2860_REG_LEGACY_BASIC_RATE 0x1408
-#define RT2860_REG_HT_BASIC_RATE 0x140c
+#define RT2860_AUTO_RSP_CFG 0x1404
+#define RT2860_LEGACY_BASIC_RATE 0x1408
+#define RT2860_HT_BASIC_RATE 0x140c
#define RT2860_REG_HT_CTRL_CFG 0x1410
#define RT2860_REG_SIFS_COST_CFG 0x1414
#define RT2860_REG_RX_PARSER_CFG 0x1418
@@ -143,7 +143,7 @@
#define RT2860_REG_HCCAPSMP_TXOP_HLDR_ADDR0 0x1600
#define RT2860_REG_HCCAPSMP_TXOP_HLDR_ADDR1 0x1604
-#define RT2860_REG_HCCAPSMP_TXOP_HLDR_ET 0x1608
+#define RT2860_TXOP_HLDR_ET 0x1608
#define RT2860_REG_HCCAPSMP_QOS_CFPOLL_RA_DW0 0x160c
#define RT2860_REG_HCCAPSMP_QOS_CFPOLL_A1_DW1 0x1610
#define RT2860_REG_HCCAPSMP_QOS_CFPOLL_QC 0x1614
@@ -583,5 +583,258 @@
#define RAL_SET_REGION_4(sc, offset, val, count) \
bus_space_set_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \
(val), (count))
+
+/*
+ * Default values for MAC registers; values taken from the reference
driver.
+ */
+#define RT2860_DEF_MAC \
+ { RT2860_BCN_OFFSET0, 0xf8f0e8e0 }, \
+ { RT2860_LEGACY_BASIC_RATE, 0x0000013f }, \
+ { RT2860_HT_BASIC_RATE, 0x00008003 }, \
+ { RT2860_MAC_SYS_CTRL, 0x00000000 }, \
+ { RT2860_BKOFF_SLOT_CFG, 0x00000209 }, \
+ { RT2860_TX_SW_CFG0, 0x00000000 }, \
+ { RT2860_TX_SW_CFG1, 0x00080606 }, \
+ { RT2860_TX_LINK_CFG, 0x00001020 }, \
+ { RT2860_TX_TIMEOUT_CFG, 0x000a2090 }, \
+ { RT2860_LED_CFG, 0x7f031e46 }, \
+ { RT2860_WMM_AIFSN_CFG, 0x00002273 }, \
+ { RT2860_WMM_CWMIN_CFG, 0x00002344 }, \
+ { RT2860_WMM_CWMAX_CFG, 0x000034aa }, \
+ { RT2860_MAX_PCNT, 0x1f3fbf9f }, \
+ { RT2860_TX_RTY_CFG, 0x47d01f0f }, \
+ { RT2860_AUTO_RSP_CFG, 0x00000013 }, \
+ { RT2860_CCK_PROT_CFG, 0x05740003 }, \
+ { RT2860_OFDM_PROT_CFG, 0x05740003 }, \
+ { RT2860_GF20_PROT_CFG, 0x01744004 }, \
+ { RT2860_GF40_PROT_CFG, 0x03f44084 }, \
+ { RT2860_MM20_PROT_CFG, 0x01744004 }, \
+ { RT2860_MM40_PROT_CFG, 0x03f54084 }, \
+ { RT2860_TXOP_CTRL_CFG, 0x0000583f }, \
+ { RT2860_TXOP_HLDR_ET, 0x00000002 }, \
+ { RT2860_TX_RTS_CFG, 0x00092b20 }, \
+ { RT2860_EXP_ACK_TIME, 0x002400ca }, \
+ { RT2860_XIFS_TIME_CFG, 0x33a41010 }, \
+ { RT2860_PWR_PIN_CFG, 0x00000003 }
+
+/* XXX only a few registers differ from above, try to merge? */
+#define RT2870_DEF_MAC \
+ { RT2860_BCN_OFFSET0, 0xf8f0e8e0 }, \
+ { RT2860_LEGACY_BASIC_RATE, 0x0000013f }, \
+ { RT2860_HT_BASIC_RATE, 0x00008003 }, \
+ { RT2860_MAC_SYS_CTRL, 0x00000000 }, \
+ { RT2860_BKOFF_SLOT_CFG, 0x00000209 }, \
+ { RT2860_TX_SW_CFG0, 0x00000000 }, \
+ { RT2860_TX_SW_CFG1, 0x00080606 }, \
+ { RT2860_TX_LINK_CFG, 0x00001020 }, \
+ { RT2860_TX_TIMEOUT_CFG, 0x000a2090 }, \
+ { RT2860_LED_CFG, 0x7f031e46 }, \
+ { RT2860_WMM_AIFSN_CFG, 0x00002273 }, \
+ { RT2860_WMM_CWMIN_CFG, 0x00002344 }, \
+ { RT2860_WMM_CWMAX_CFG, 0x000034aa }, \
+ { RT2860_MAX_PCNT, 0x1f3fbf9f }, \
+ { RT2860_TX_RTY_CFG, 0x47d01f0f }, \
+ { RT2860_AUTO_RSP_CFG, 0x00000013 }, \
+ { RT2860_CCK_PROT_CFG, 0x05740003 }, \
+ { RT2860_OFDM_PROT_CFG, 0x05740003 }, \
+ { RT2860_PBF_CFG, 0x00f40006 }, \
+ { RT2860_WPDMA_GLO_CFG, 0x00000030 }, \
+ { RT2860_GF20_PROT_CFG, 0x01744004 }, \
+ { RT2860_GF40_PROT_CFG, 0x03f44084 }, \
+ { RT2860_MM20_PROT_CFG, 0x01744004 }, \
+ { RT2860_MM40_PROT_CFG, 0x03f44084 }, \
+ { RT2860_TXOP_CTRL_CFG, 0x0000583f }, \
+ { RT2860_TXOP_HLDR_ET, 0x00000002 }, \
+ { RT2860_TX_RTS_CFG, 0x00092b20 }, \
+ { RT2860_EXP_ACK_TIME, 0x002400ca }, \
+ { RT2860_XIFS_TIME_CFG, 0x33a41010 }, \
+ { RT2860_PWR_PIN_CFG, 0x00000003 }
+
+/*
+ * Default values for BBP registers; values taken from the reference
driver.
+ */
+#define RT2860_DEF_BBP \
+ { 65, 0x2c }, \
+ { 66, 0x38 }, \
+ { 69, 0x12 }, \
+ { 70, 0x0a }, \
+ { 73, 0x10 }, \
+ { 81, 0x37 }, \
+ { 82, 0x62 }, \
+ { 83, 0x6a }, \
+ { 84, 0x99 }, \
+ { 86, 0x00 }, \
+ { 91, 0x04 }, \
+ { 92, 0x00 }, \
+ { 103, 0x00 }, \
+ { 105, 0x05 }, \
+ { 106, 0x35 }
+
+/*
+ * Default settings for RF registers; values derived from the reference
driver.
+ */
+#define RT2860_RF2850 \
+ { 1, 0x100bb3, 0x1301e1, 0x05a014, 0x001402 }, \
+ { 2, 0x100bb3, 0x1301e1, 0x05a014, 0x001407 }, \
+ { 3, 0x100bb3, 0x1301e2, 0x05a014, 0x001402 }, \
+ { 4, 0x100bb3, 0x1301e2, 0x05a014, 0x001407 }, \
+ { 5, 0x100bb3, 0x1301e3, 0x05a014, 0x001402 }, \
+ { 6, 0x100bb3, 0x1301e3, 0x05a014, 0x001407 }, \
+ { 7, 0x100bb3, 0x1301e4, 0x05a014, 0x001402 }, \
+ { 8, 0x100bb3, 0x1301e4, 0x05a014, 0x001407 }, \
+ { 9, 0x100bb3, 0x1301e5, 0x05a014, 0x001402 }, \
+ { 10, 0x100bb3, 0x1301e5, 0x05a014, 0x001407 }, \
+ { 11, 0x100bb3, 0x1301e6, 0x05a014, 0x001402 }, \
+ { 12, 0x100bb3, 0x1301e6, 0x05a014, 0x001407 }, \
+ { 13, 0x100bb3, 0x1301e7, 0x05a014, 0x001402 }, \
+ { 14, 0x100bb3, 0x1301e8, 0x05a014, 0x001404 }, \
+ { 36, 0x100bb3, 0x130266, 0x056014, 0x001408 }, \
+ { 38, 0x100bb3, 0x130267, 0x056014, 0x001404 }, \
+ { 40, 0x100bb2, 0x1301a0, 0x056014, 0x001400 }, \
+ { 44, 0x100bb2, 0x1301a0, 0x056014, 0x001408 }, \
+ { 46, 0x100bb2, 0x1301a1, 0x056014, 0x001402 }, \
+ { 48, 0x100bb2, 0x1301a1, 0x056014, 0x001406 }, \
+ { 52, 0x100bb2, 0x1301a2, 0x056014, 0x001404 }, \
+ { 54, 0x100bb2, 0x1301a2, 0x056014, 0x001408 }, \
+ { 56, 0x100bb2, 0x1301a3, 0x056014, 0x001402 }, \
+ { 60, 0x100bb2, 0x1301a4, 0x056014, 0x001400 }, \
+ { 62, 0x100bb2, 0x1301a4, 0x056014, 0x001404 }, \
+ { 64, 0x100bb2, 0x1301a4, 0x056014, 0x001408 }, \
+ { 100, 0x100bb2, 0x1301ac, 0x05e014, 0x001400 }, \
+ { 102, 0x100bb2, 0x1701ac, 0x15e014, 0x001404 }, \
+ { 104, 0x100bb2, 0x1701ac, 0x15e014, 0x001408 }, \
+ { 108, 0x100bb3, 0x17028c, 0x15e014, 0x001404 }, \
+ { 110, 0x100bb3, 0x13028d, 0x05e014, 0x001400 }, \
+ { 112, 0x100bb3, 0x13028d, 0x05e014, 0x001406 }, \
+ { 116, 0x100bb3, 0x13028e, 0x05e014, 0x001408 }, \
+ { 118, 0x100bb3, 0x13028f, 0x05e014, 0x001404 }, \
+ { 120, 0x100bb1, 0x1300e0, 0x05e014, 0x001400 }, \
+ { 124, 0x100bb1, 0x1300e0, 0x05e014, 0x001404 }, \
+ { 126, 0x100bb1, 0x1300e0, 0x05e014, 0x001406 }, \
+ { 128, 0x100bb1, 0x1300e0, 0x05e014, 0x001408 }, \
+ { 132, 0x100bb1, 0x1300e1, 0x05e014, 0x001402 }, \
+ { 134, 0x100bb1, 0x1300e1, 0x05e014, 0x001404 }, \
+ { 136, 0x100bb1, 0x1300e1, 0x05e014, 0x001406 }, \
+ { 140, 0x100bb1, 0x1300e2, 0x05e014, 0x001400 }, \
+ { 149, 0x100bb1, 0x1300e2, 0x05e014, 0x001409 }, \
+ { 151, 0x100bb1, 0x1300e3, 0x05e014, 0x001401 }, \
+ { 153, 0x100bb1, 0x1300e3, 0x05e014, 0x001403 }, \
+ { 157, 0x100bb1, 0x1300e3, 0x05e014, 0x001407 }, \
+ { 159, 0x100bb1, 0x1300e3, 0x05e014, 0x001409 }, \
+ { 161, 0x100bb1, 0x1300e4, 0x05e014, 0x001401 }, \
+ { 165, 0x100bb1, 0x1300e4, 0x05e014, 0x001405 }, \
+ { 167, 0x100bb1, 0x1300f4, 0x05e014, 0x001407 }, \
+ { 169, 0x100bb1, 0x1300f4, 0x05e014, 0x001409 }, \
+ { 171, 0x100bb1, 0x1300f5, 0x05e014, 0x001401 }, \
+ { 173, 0x100bb1, 0x1300f5, 0x05e014, 0x001403 }
+
+#define RT3070_RF3052 \
+ { 0xf1, 2, 2 }, \
+ { 0xf1, 2, 7 }, \
+ { 0xf2, 2, 2 }, \
+ { 0xf2, 2, 7 }, \
+ { 0xf3, 2, 2 }, \
+ { 0xf3, 2, 7 }, \
+ { 0xf4, 2, 2 }, \
+ { 0xf4, 2, 7 }, \
+ { 0xf5, 2, 2 }, \
+ { 0xf5, 2, 7 }, \
+ { 0xf6, 2, 2 }, \
+ { 0xf6, 2, 7 }, \
+ { 0xf7, 2, 2 }, \
+ { 0xf8, 2, 4 }, \
+ { 0x56, 0, 4 }, \
+ { 0x56, 0, 6 }, \
+ { 0x56, 0, 8 }, \
+ { 0x57, 0, 0 }, \
+ { 0x57, 0, 2 }, \
+ { 0x57, 0, 4 }, \
+ { 0x57, 0, 8 }, \
+ { 0x57, 0, 10 }, \
+ { 0x58, 0, 0 }, \
+ { 0x58, 0, 4 }, \
+ { 0x58, 0, 6 }, \
+ { 0x58, 0, 8 }, \
+ { 0x5b, 0, 8 }, \
+ { 0x5b, 0, 10 }, \
+ { 0x5c, 0, 0 }, \
+ { 0x5c, 0, 4 }, \
+ { 0x5c, 0, 6 }, \
+ { 0x5c, 0, 8 }, \
+ { 0x5d, 0, 0 }, \
+ { 0x5d, 0, 2 }, \
+ { 0x5d, 0, 4 }, \
+ { 0x5d, 0, 8 }, \
+ { 0x5d, 0, 10 }, \
+ { 0x5e, 0, 0 }, \
+ { 0x5e, 0, 4 }, \
+ { 0x5e, 0, 6 }, \
+ { 0x5e, 0, 8 }, \
+ { 0x5f, 0, 0 }, \
+ { 0x5f, 0, 9 }, \
+ { 0x5f, 0, 11 }, \
+ { 0x60, 0, 1 }, \
+ { 0x60, 0, 5 }, \
+ { 0x60, 0, 7 }, \
+ { 0x60, 0, 9 }, \
+ { 0x61, 0, 1 }, \
+ { 0x61, 0, 3 }, \
+ { 0x61, 0, 5 }, \
+ { 0x61, 0, 7 }, \
+ { 0x61, 0, 9 }
+
+#define RT3070_DEF_RF \
+ { 4, 0x40 }, \
+ { 5, 0x03 }, \
+ { 6, 0x02 }, \
+ { 7, 0x70 }, \
+ { 9, 0x0f }, \
+ { 10, 0x41 }, \
+ { 11, 0x21 }, \
+ { 12, 0x7b }, \
+ { 14, 0x90 }, \
+ { 15, 0x58 }, \
+ { 16, 0xb3 }, \
+ { 17, 0x92 }, \
+ { 18, 0x2c }, \
+ { 19, 0x02 }, \
+ { 20, 0xba }, \
+ { 21, 0xdb }, \
+ { 24, 0x16 }, \
+ { 25, 0x01 }, \
+ { 29, 0x1f }
+
+#define RT3572_DEF_RF \
+ { 0, 0x70 }, \
+ { 1, 0x81 }, \
+ { 2, 0xf1 }, \
+ { 3, 0x02 }, \
+ { 4, 0x4c }, \
+ { 5, 0x05 }, \
+ { 6, 0x4a }, \
+ { 7, 0xd8 }, \
+ { 9, 0xc3 }, \
+ { 10, 0xf1 }, \
+ { 11, 0xb9 }, \
+ { 12, 0x70 }, \
+ { 13, 0x65 }, \
+ { 14, 0xa0 }, \
+ { 15, 0x53 }, \
+ { 16, 0x4c }, \
+ { 17, 0x23 }, \
+ { 18, 0xac }, \
+ { 19, 0x93 }, \
+ { 20, 0xb3 }, \
+ { 21, 0xd0 }, \
+ { 22, 0x00 }, \
+ { 23, 0x3c }, \
+ { 24, 0x16 }, \
+ { 25, 0x15 }, \
+ { 26, 0x85 }, \
+ { 27, 0x00 }, \
+ { 28, 0x00 }, \
+ { 29, 0x9b }, \
+ { 30, 0x09 }, \
+ { 31, 0x10 }
#endif /* #ifndef _RT2860_REG_H_ */
==============================================================================
Revision: 0a74d339b273
Author: Bernhard Schmidt <bschmidt at techwires.net>
Date: Wed Mar 14 01:49:59 2012
Log: no need for that
http://code.google.com/p/rt2860-in-ral/source/detail?r=0a74d339b273
Modified:
/sys/dev/ral/rt2860reg.h
/sys/dev/ral/rt2860var.h
=======================================
--- /sys/dev/ral/rt2860reg.h Wed Mar 14 01:48:10 2012
+++ /sys/dev/ral/rt2860reg.h Wed Mar 14 01:49:59 2012
@@ -16,9 +16,6 @@
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
-#ifndef _RT2860_REG_H_
-#define _RT2860_REG_H_
-
#define RT2860_REG_PCI_CFG 0x0000
#define RT2860_REG_EEPROM_CSR 0x0004
#define RT2860_REG_PCI_MCU_CSR 0x0008
@@ -836,5 +833,3 @@
{ 29, 0x9b }, \
{ 30, 0x09 }, \
{ 31, 0x10 }
-
-#endif /* #ifndef _RT2860_REG_H_ */
=======================================
--- /sys/dev/ral/rt2860var.h Tue Mar 13 11:11:15 2012
+++ /sys/dev/ral/rt2860var.h Wed Mar 14 01:49:59 2012
@@ -15,9 +15,6 @@
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
-#ifndef _RT2860VAR_H_
-#define _RT2860VAR_H_
-
#include <sys/param.h>
#include <sys/sysctl.h>
#include <sys/sockio.h>
@@ -765,7 +762,3 @@
void rt2860_suspend(void *);
void rt2860_resume(void *);
void rt2860_intr(void *arg);
-
-
-#endif /* #ifndef _RT2860VAR_H_ */
-
==============================================================================
Revision: 5d6745ae9c6a
Author: Bernhard Schmidt <bschmidt at techwires.net>
Date: Wed Mar 14 02:27:13 2012
Log: add RT2860_EEPROM_CTL() and friends
http://code.google.com/p/rt2860-in-ral/source/detail?r=5d6745ae9c6a
Modified:
/sys/dev/ral/rt2860.c
/sys/dev/ral/rt2860reg.h
/sys/dev/ral/rt2860var.h
=======================================
--- /sys/dev/ral/rt2860.c Wed Mar 14 01:48:10 2012
+++ /sys/dev/ral/rt2860.c Wed Mar 14 02:27:13 2012
@@ -204,8 +204,6 @@
int8_t delta);
void rt2860_io_rf_load_defaults(struct rt2860_softc *sc);
uint16_t rt2860_io_eeprom_read(struct rt2860_softc *sc, uint16_t addr);
-void rt2860_io_eeprom_read_multi(struct rt2860_softc *sc,
- uint16_t addr, void *buf, size_t len);
uint8_t rt2860_io_bbp_read(struct rt2860_softc *sc, uint8_t reg);
void rt2860_io_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t
val);
void rt2860_io_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t
val);
@@ -6863,7 +6861,7 @@
{ \
(val) |= RT2860_REG_EESK; \
\
- RAL_WRITE((sc), RT2860_REG_EEPROM_CSR, (val)); \
+ RAL_WRITE((sc), RT2860_PCI_EECTRL, (val)); \
\
DELAY(1); \
} while (0)
@@ -6876,7 +6874,7 @@
{ \
(val) &= ~RT2860_REG_EESK; \
\
- RAL_WRITE((sc), RT2860_REG_EEPROM_CSR, (val)); \
+ RAL_WRITE((sc), RT2860_PCI_EECTRL, (val)); \
\
DELAY(1); \
} while (0)
@@ -6885,15 +6883,6 @@
((uint16_t) (((crc) << 8) ^ \
rt2860_io_ccitt16[(((crc) >> 8) ^ (byte)) & 255]))
-/*
- * Static function prototypes
- */
-
-static void rt2860_io_eeprom_shiftout_bits(struct rt2860_softc *sc,
- uint16_t val, uint16_t count);
-
-static uint16_t rt2860_io_eeprom_shiftin_bits(struct rt2860_softc *sc);
-
/* #ifdef RT305X_SOC */
static const uint16_t rt3052_eeprom[] =
{
@@ -7055,6 +7044,7 @@
{
uint32_t tmp;
uint16_t val;
+ int n;
addr = (addr >> 1);
@@ -7066,59 +7056,41 @@
return (rt3090_efuse_read_2(sc, addr));
}
- tmp = RAL_READ(sc, RT2860_REG_EEPROM_CSR);
-
- tmp &= ~(RT2860_REG_EEDI | RT2860_REG_EEDO | RT2860_REG_EESK);
- tmp |= RT2860_REG_EECS;
-
- RAL_WRITE(sc, RT2860_REG_EEPROM_CSR, tmp);
-
- if (((sc->mac_rev & 0xffff0000) != 0x30710000) &&
- ((sc->mac_rev & 0xffff0000) != 0x30900000) &&
- ((sc->mac_rev & 0xffff0000) != 0x35720000) &&
- ((sc->mac_rev & 0xffff0000) != 0x33900000)) {
- RT2860_IO_EEPROM_RAISE_CLK(sc, tmp);
- RT2860_IO_EEPROM_LOWER_CLK(sc, tmp);
+ /* clock C once before the first command */
+ RT2860_EEPROM_CTL(sc, 0);
+
+ RT2860_EEPROM_CTL(sc, RT2860_S);
+ RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C);
+ RT2860_EEPROM_CTL(sc, RT2860_S);
+
+ /* write start bit (1) */
+ RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D);
+ RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C);
+
+ /* write READ opcode (10) */
+ RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D);
+ RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C);
+ RT2860_EEPROM_CTL(sc, RT2860_S);
+ RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C);
+
+ /* write address (A5-A0 or A7-A0) */
+ n = ((RAL_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7;
+ for (; n >= 0; n--) {
+ RT2860_EEPROM_CTL(sc, RT2860_S |
+ (((addr >> n) & 1) << RT2860_SHIFT_D));
+ RT2860_EEPROM_CTL(sc, RT2860_S |
+ (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C);
}
- rt2860_io_eeprom_shiftout_bits(sc, RT2860_REG_EEOP_READ, 3);
- rt2860_io_eeprom_shiftout_bits(sc, addr, sc->eeprom_addr_num);
-
- val = rt2860_io_eeprom_shiftin_bits(sc);
-
- tmp = RAL_READ(sc, RT2860_REG_EEPROM_CSR);
-
- tmp &= ~(RT2860_REG_EECS | RT2860_REG_EEDI);
-
- RAL_WRITE(sc, RT2860_REG_EEPROM_CSR, tmp);
-
- RT2860_IO_EEPROM_RAISE_CLK(sc, tmp);
- RT2860_IO_EEPROM_LOWER_CLK(sc, tmp);
+ RT2860_EEPROM_CTL(sc, 0);
+
+ /* clear Chip Select and clock C */
+ RT2860_EEPROM_CTL(sc, RT2860_S);
+ RT2860_EEPROM_CTL(sc, 0);
+ RT2860_EEPROM_CTL(sc, RT2860_C);
return val;
}
-
-/*
- * rt2860_io_eeprom_read_multi
- */
-void rt2860_io_eeprom_read_multi(struct rt2860_softc *sc,
- uint16_t addr, void *buf, size_t len)
-{
- uint16_t *ptr;
- int i;
-
- len += len % sizeof(uint16_t);
- ptr = buf;
-
- i = 0;
-
- do {
- *ptr++ = rt2860_io_eeprom_read(sc, addr + i);
-
- i += sizeof(uint16_t);
- len -= sizeof(uint16_t);
- } while (len > 0);
-}
/*
* rt2860_io_bbp_read
@@ -7489,71 +7461,6 @@
firmware_put(fp, FIRMWARE_UNLOAD);
return error;
}
-
-/*
- * rt2860_io_eeprom_shiftout_bits
- */
-static void rt2860_io_eeprom_shiftout_bits(struct rt2860_softc *sc,
- uint16_t val, uint16_t count)
-{
- uint32_t mask, tmp;
-
- mask = (1 << (count - 1));
-
- tmp = RAL_READ(sc, RT2860_REG_EEPROM_CSR);
-
- tmp &= ~(RT2860_REG_EEDO | RT2860_REG_EEDI);
-
- do {
- tmp &= ~RT2860_REG_EEDI;
-
- if(val & mask)
- tmp |= RT2860_REG_EEDI;
-
- RAL_WRITE(sc, RT2860_REG_EEPROM_CSR, tmp);
-
- RT2860_IO_EEPROM_RAISE_CLK(sc, tmp);
- RT2860_IO_EEPROM_LOWER_CLK(sc, tmp);
-
- mask = (mask >> 1);
- } while (mask);
-
- tmp &= ~RT2860_REG_EEDI;
-
- RAL_WRITE(sc, RT2860_REG_EEPROM_CSR, tmp);
-}
-
-/*
- * rt2860_io_eeprom_shiftin_bits
- */
-static uint16_t rt2860_io_eeprom_shiftin_bits(struct rt2860_softc *sc)
-{
- uint32_t tmp;
- uint16_t val;
- int i;
-
- val = 0;
-
- tmp = RAL_READ(sc, RT2860_REG_EEPROM_CSR);
-
- tmp &= ~(RT2860_REG_EEDO | RT2860_REG_EEDI);
-
- for(i = 0; i < 16; i++) {
- val = (val << 1);
-
- RT2860_IO_EEPROM_RAISE_CLK(sc, tmp);
-
- tmp = RAL_READ(sc, RT2860_REG_EEPROM_CSR);
-
- RT2860_IO_EEPROM_LOWER_CLK(sc, tmp);
-
- tmp &= ~RT2860_REG_EEDI;
- if(tmp & RT2860_REG_EEDO)
- val |= 1;
- }
-
- return val;
-}
/*
* rt2860_led_brightness
@@ -7595,7 +7502,7 @@
/* read EEPROM address number */
- tmp = RAL_READ(sc, RT2860_REG_EEPROM_CSR);
+ tmp = RAL_READ(sc, RT2860_PCI_EECTRL);
if((tmp & 0x30) == 0)
sc->eeprom_addr_num = 6;
@@ -7917,15 +7824,19 @@
/* read Tx power per rate */
- for (i = 0; i < RT2860_SOFTC_TXPOW_RATE_COUNT; i++) {
- rt2860_io_eeprom_read_multi(sc, RT2860_EEPROM_TXPOW_RATE_BASE + i *
sizeof(uint32_t),
- &tmp, sizeof(uint32_t));
-
- sc->txpow_rate_20mhz[i] = tmp;
+ for (i = 0; i < 5; i++) {
+ uint32_t reg;
+
+ tmp = rt2860_io_eeprom_read(sc, RT2860_EEPROM_RPWR + i * 2);
+ reg = tmp;
+ tmp = rt2860_io_eeprom_read(sc, RT2860_EEPROM_RPWR + i * 2 + 1);
+ reg |= (uint32_t)val << 16;
+
+ sc->txpow_rate_20mhz[i] = reg;
sc->txpow_rate_40mhz_2ghz[i] =
- rt2860_read_eeprom_txpow_rate_add_delta(tmp, sc->txpow_rate_delta_2ghz);
+ rt2860_read_eeprom_txpow_rate_add_delta(reg, sc->txpow_rate_delta_2ghz);
sc->txpow_rate_40mhz_5ghz[i] =
- rt2860_read_eeprom_txpow_rate_add_delta(tmp, sc->txpow_rate_delta_5ghz);
+ rt2860_read_eeprom_txpow_rate_add_delta(reg, sc->txpow_rate_delta_5ghz);
RT2860_DPRINTF(sc, RT2860_DEBUG_EEPROM,
"%s: EEPROM Tx power per rate #%d=0x%08x(20MHz), 0x%08x(40MHz/2GHz),
0x%08x(40MHz/5GHz)\n",
@@ -8013,13 +7924,18 @@
sc->tssi_step_5ghz);
/* read default BBP settings */
-
- rt2860_io_eeprom_read_multi(sc, RT2860_EEPROM_BBP_BASE,
- sc->bbp_eeprom, RT2860_SOFTC_BBP_EEPROM_COUNT * 2);
-
+ for (i = 0; i < 8; i++) {
+ val = rt2860_io_eeprom_read(sc, RT2860_EEPROM_BBP_BASE + i);
+ sc->bbp_eeprom[i].val = val & 0xff;
+ sc->bbp_eeprom[i].reg = val >> 8;
+ }
if ((sc->mac_rev & 0xffff0000) >= 0x30710000) {
/* read vendor RF settings */
- rt2860_io_eeprom_read_multi(sc, RT3071_EEPROM_RF_BASE, sc->rf, 10 * 2);
+ for (i = 0; i < 10; i++) {
+ val = rt2860_io_eeprom_read(sc, RT3071_EEPROM_RF_BASE + i);
+ sc->rf[i].val = val & 0xff;
+ sc->rf[i].reg = val >> 8;
+ }
}
/* read powersave level */
@@ -8478,13 +8394,13 @@
uint32_t tmp;
if (aux) {
- tmp = RAL_READ(sc, RT2860_REG_EEPROM_CSR);
- RAL_WRITE(sc, RT2860_REG_EEPROM_CSR, tmp & ~RT2860_REG_EESK);
+ tmp = RAL_READ(sc, RT2860_PCI_EECTRL);
+ RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp & ~RT2860_C);
tmp = RAL_READ(sc, RT2860_REG_SCHDMA_GPIO_CTRL_CFG);
RAL_WRITE(sc, RT2860_REG_SCHDMA_GPIO_CTRL_CFG, (tmp & ~0x0808) | 0x08);
} else {
- tmp = RAL_READ(sc, RT2860_REG_EEPROM_CSR);
- RAL_WRITE(sc, RT2860_REG_EEPROM_CSR, tmp | RT2860_REG_EESK);
+ tmp = RAL_READ(sc, RT2860_PCI_EECTRL);
+ RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp | RT2860_C);
tmp = RAL_READ(sc, RT2860_REG_SCHDMA_GPIO_CTRL_CFG);
RAL_WRITE(sc, RT2860_REG_SCHDMA_GPIO_CTRL_CFG, tmp & ~0x0808);
}
=======================================
--- /sys/dev/ral/rt2860reg.h Wed Mar 14 01:49:59 2012
+++ /sys/dev/ral/rt2860reg.h Wed Mar 14 02:27:13 2012
@@ -17,7 +17,7 @@
*/
#define RT2860_REG_PCI_CFG 0x0000
-#define RT2860_REG_EEPROM_CSR 0x0004
+#define RT2860_PCI_EECTRL 0x0004
#define RT2860_REG_PCI_MCU_CSR 0x0008
#define RT2860_REG_PCI_SYS_CSR 0x000c
#define RT2860_REG_PCIE_JTAG 0x0010
@@ -277,15 +277,52 @@
#define RT2860_REG_RF_R3 2
#define RT2860_REG_RF_R4 3
-/*
- * RT2860_REG_EEPROM_CSR flags
- */
-#define RT2860_REG_EERL (1 << 7)
-#define RT2860_REG_EEDO (1 << 3)
-#define RT2860_REG_EEDI (1 << 2)
-#define RT2860_REG_EECS (1 << 1)
-#define RT2860_REG_EESK (1 << 0)
-#define RT2860_REG_EEOP_READ 0x6
+/* possible flags for register RT2860_PCI_EECTRL */
+#define RT2860_C (1 << 0)
+#define RT2860_S (1 << 1)
+#define RT2860_D (1 << 2)
+#define RT2860_SHIFT_D 2
+#define RT2860_Q (1 << 3)
+#define RT2860_SHIFT_Q 3
+
+#define RT2860_EEPROM_DELAY 1 /* minimum hold time (microsecond) */
+
+#define RT2860_EEPROM_VERSION 0x01
+#define RT2860_EEPROM_MAC01 0x02
+#define RT2860_EEPROM_MAC23 0x03
+#define RT2860_EEPROM_MAC45 0x04
+#define RT2860_EEPROM_PCIE_PSLEVEL 0x11
+#define RT2860_EEPROM_REV 0x12
+#define RT2860_EEPROM_ANTENNA 0x1a
+#define RT2860_EEPROM_CONFIG 0x1b
+#define RT2860_EEPROM_COUNTRY 0x1c
+#define RT2860_EEPROM_FREQ_LEDS 0x1d
+#define RT2860_EEPROM_LED1 0x1e
+#define RT2860_EEPROM_LED2 0x1f
+#define RT2860_EEPROM_LED3 0x20
+#define RT2860_EEPROM_LNA 0x22
+#define RT2860_EEPROM_RSSI1_2GHZ 0x23
+#define RT2860_EEPROM_RSSI2_2GHZ 0x24
+#define RT2860_EEPROM_RSSI1_5GHZ 0x25
+#define RT2860_EEPROM_RSSI2_5GHZ 0x26
+#define RT2860_EEPROM_DELTAPWR 0x28
+#define RT2860_EEPROM_PWR2GHZ_BASE1 0x29
+#define RT2860_EEPROM_PWR2GHZ_BASE2 0x30
+#define RT2860_EEPROM_TSSI1_2GHZ 0x37
+#define RT2860_EEPROM_TSSI2_2GHZ 0x38
+#define RT2860_EEPROM_TSSI3_2GHZ 0x39
+#define RT2860_EEPROM_TSSI4_2GHZ 0x3a
+#define RT2860_EEPROM_TSSI5_2GHZ 0x3b
+#define RT2860_EEPROM_PWR5GHZ_BASE1 0x3c
+#define RT2860_EEPROM_PWR5GHZ_BASE2 0x53
+#define RT2860_EEPROM_TSSI1_5GHZ 0x6a
+#define RT2860_EEPROM_TSSI2_5GHZ 0x6b
+#define RT2860_EEPROM_TSSI3_5GHZ 0x6c
+#define RT2860_EEPROM_TSSI4_5GHZ 0x6d
+#define RT2860_EEPROM_TSSI5_5GHZ 0x6e
+#define RT2860_EEPROM_RPWR 0x6f
+#define RT2860_EEPROM_BBP_BASE 0x78
+#define RT3071_EEPROM_RF_BASE 0x82
/*
* RT2860_REG_SCHDMA_INT_STATUS
@@ -557,8 +594,8 @@
#define RT2860_REG_H2M_CID_MASK 0xff
/*
- * * Control and status registers access macros.
- * */
+ * Control and status registers access macros.
+ */
#define RAL_READ(sc, reg) \
bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
@@ -581,6 +618,15 @@
bus_space_set_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \
(val), (count))
+/*
+ * EEPROM access macro.
+ */
+#define RT2860_EEPROM_CTL(sc, val) do { \
+ RAL_WRITE((sc), RT2860_PCI_EECTRL, (val)); \
+ RAL_BARRIER_READ_WRITE((sc)); \
+ DELAY(RT2860_EEPROM_DELAY); \
+} while (/* CONSTCOND */0)
+
/*
* Default values for MAC registers; values taken from the reference
driver.
*/
=======================================
--- /sys/dev/ral/rt2860var.h Wed Mar 14 01:49:59 2012
+++ /sys/dev/ral/rt2860var.h Wed Mar 14 02:27:13 2012
@@ -650,14 +650,11 @@
#endif
};
-#define RT2860_EEPROM_VERSION 0x0002
#define RT2860_EEPROM_ADDRESS01 0x0004
#define RT2860_EEPROM_ADDRESS23 0x0006
#define RT2860_EEPROM_ADDRESS45 0x0008
#define RT2860_EEPROM_POWERSAVE_LEVEL 0x0022
-#define RT2860_EEPROM_ANTENNA 0x0034
#define RT2860_EEPROM_NIC_CONFIG 0x0036
-#define RT2860_EEPROM_COUNTRY 0x0038
#define RT2860_EEPROM_RF_FREQ_OFF 0x003a
#define RT2860_EEPROM_LED1_OFF 0x003c
#define RT2860_EEPROM_LED2_OFF 0x003e
@@ -675,8 +672,6 @@
#define RT2860_EEPROM_TXPOW2_5GHZ_BASE 0x00a6
#define RT2860_EEPROM_TSSI_5GHZ_BASE 0x00d4
#define RT2860_EEPROM_TXPOW_RATE_BASE 0x00de
-#define RT2860_EEPROM_BBP_BASE 0x00f0
-#define RT3071_EEPROM_RF_BASE 0x0082
#define RT2860_EEPROM_RF_2820 1 /* 2.4GHz 2T3R */
#define RT2860_EEPROM_RF_2850 2 /* 2.4/5GHz 2T3R */
==============================================================================
Revision: 0a72554935b9
Author: Bernhard Schmidt <bschmidt at techwires.net>
Date: Wed Mar 14 02:42:49 2012
Log: rename/move some constants
http://code.google.com/p/rt2860-in-ral/source/detail?r=0a72554935b9
Modified:
/sys/dev/ral/rt2860.c
/sys/dev/ral/rt2860reg.h
/sys/dev/ral/rt2860var.h
=======================================
--- /sys/dev/ral/rt2860.c Wed Mar 14 02:27:13 2012
+++ /sys/dev/ral/rt2860.c Wed Mar 14 02:42:49 2012
@@ -717,9 +717,9 @@
}
/* set supported channels for 5GHz band */
- if (sc->rf_rev == RT2860_EEPROM_RF_2850 ||
- sc->rf_rev == RT2860_EEPROM_RF_2750 ||
- sc->rf_rev == RT2860_EEPROM_RF_3052) {
+ if (sc->rf_rev == RT2860_RF_2850 ||
+ sc->rf_rev == RT2860_RF_2750 ||
+ sc->rf_rev == RT3070_RF_3052) {
for (i = 36; i <= 64; i += 4) {
c = &ic->ic_channels[ic->ic_nchans++];
flags = IEEE80211_CHAN_A;
@@ -821,9 +821,9 @@
}
/* set supported channels for 5GHz band */
- if (sc->rf_rev == RT2860_EEPROM_RF_2850 ||
- sc->rf_rev == RT2860_EEPROM_RF_2750 ||
- sc->rf_rev == RT2860_EEPROM_RF_3052) {
+ if (sc->rf_rev == RT2860_RF_2850 ||
+ sc->rf_rev == RT2860_RF_2750 ||
+ sc->rf_rev == RT3070_RF_3052) {
for (i = 36; i <= 64; i += 4) {
flags = IEEE80211_CHAN_A | IEEE80211_CHAN_HT40;
@@ -1194,9 +1194,9 @@
RAL_WRITE(sc, RT2860_REG_SCHDMA_DELAY_INT_CFG, 0);
/* select Main antenna for 1T1R devices */
- if (sc->rf_rev == RT2860_EEPROM_RF_2020 ||
- sc->rf_rev == RT2860_EEPROM_RF_3020 ||
- sc->rf_rev == RT2860_EEPROM_RF_3320)
+ if (sc->rf_rev == RT3070_RF_2020 ||
+ sc->rf_rev == RT3070_RF_3020 ||
+ sc->rf_rev == RT3070_RF_3320)
rt3090_set_rx_antenna(sc, 0);
/* send LEDs operating mode to microcontroller */
@@ -1268,7 +1268,7 @@
if ((sc->mac_rev & 0xffff0000) >= 0x30710000)
rt3090_rf_setup(sc);
- if (sc->rf_rev == RT2860_EEPROM_RF_3022) {
+ if (sc->rf_rev == RT3070_RF_3022) {
/* calibrate RF */
tmp = rt2860_io_rf_read(sc, 30);
tmp |= 0x80;
@@ -7546,7 +7546,7 @@
if (val == 0xffff) {
device_printf(sc->sc_dev, "invalid EEPROM antenna info\n");
- sc->rf_rev = RT2860_EEPROM_RF_2820;
+ sc->rf_rev = RT2860_RF_2820;
sc->ntxpath = 1;
sc->nrxpath = 2;
} else {
@@ -8033,43 +8033,43 @@
const char *rt2860_rf_name(int rf_rev)
{
switch (rf_rev) {
- case RT2860_EEPROM_RF_2820:
+ case RT2860_RF_2820:
return "RT2820 2.4G 2T3R";
- case RT2860_EEPROM_RF_2850:
+ case RT2860_RF_2850:
return "RT2850 2.4G/5G 2T3R";
- case RT2860_EEPROM_RF_2720:
+ case RT2860_RF_2720:
return "RT2720 2.4G 1T2R";
- case RT2860_EEPROM_RF_2750:
+ case RT2860_RF_2750:
return "RT2750 2.4G/5G 1T2R";
- case RT2860_EEPROM_RF_3020:
+ case RT3070_RF_3020:
return "RT3020 2.4G 1T1R";
- case RT2860_EEPROM_RF_2020:
+ case RT3070_RF_2020:
return "RT2020 2.4G B/G";
- case RT2860_EEPROM_RF_3021:
+ case RT3070_RF_3021:
return "RT3021 2.4G 1T2R";
- case RT2860_EEPROM_RF_3022:
+ case RT3070_RF_3022:
return "RT3022 2.4G 2T2R";
- case RT2860_EEPROM_RF_3052:
+ case RT3070_RF_3052:
return "RT3052 2.4G/5G 2T2R";
- case RT2860_EEPROM_RF_2853:
+ case RT2860_RF_2853:
return "RT2853 2.4G.5G 3T3R";
- case RT2860_EEPROM_RF_3320:
+ case RT3070_RF_3320:
return "RT3320 2.4G 1T1R with PA";
- case RT2860_EEPROM_RF_3322:
+ case RT3070_RF_3322:
return "RT3322 2.4G 2T2R with PA";
- case RT2860_EEPROM_RF_3053:
+ case RT3070_RF_3053:
return "RT3053 2.4G/5G 3T3R";
default:
@@ -8342,7 +8342,7 @@
tmp = RAL_READ(sc, RT3070_OPT_14);
RAL_WRITE(sc, RT3070_OPT_14, tmp | 1);
- if (sc->rf_rev == RT2860_EEPROM_RF_3020)
+ if (sc->rf_rev == RT3070_RF_3020)
rt3090_set_rx_antenna(sc, 0);
bbp = rt2860_io_bbp_read(sc, 138);
=======================================
--- /sys/dev/ral/rt2860reg.h Wed Mar 14 02:27:13 2012
+++ /sys/dev/ral/rt2860reg.h Wed Mar 14 02:42:49 2012
@@ -277,53 +277,6 @@
#define RT2860_REG_RF_R3 2
#define RT2860_REG_RF_R4 3
-/* possible flags for register RT2860_PCI_EECTRL */
-#define RT2860_C (1 << 0)
-#define RT2860_S (1 << 1)
-#define RT2860_D (1 << 2)
-#define RT2860_SHIFT_D 2
-#define RT2860_Q (1 << 3)
-#define RT2860_SHIFT_Q 3
-
-#define RT2860_EEPROM_DELAY 1 /* minimum hold time (microsecond) */
-
-#define RT2860_EEPROM_VERSION 0x01
-#define RT2860_EEPROM_MAC01 0x02
-#define RT2860_EEPROM_MAC23 0x03
-#define RT2860_EEPROM_MAC45 0x04
-#define RT2860_EEPROM_PCIE_PSLEVEL 0x11
-#define RT2860_EEPROM_REV 0x12
-#define RT2860_EEPROM_ANTENNA 0x1a
-#define RT2860_EEPROM_CONFIG 0x1b
-#define RT2860_EEPROM_COUNTRY 0x1c
-#define RT2860_EEPROM_FREQ_LEDS 0x1d
-#define RT2860_EEPROM_LED1 0x1e
-#define RT2860_EEPROM_LED2 0x1f
-#define RT2860_EEPROM_LED3 0x20
-#define RT2860_EEPROM_LNA 0x22
-#define RT2860_EEPROM_RSSI1_2GHZ 0x23
-#define RT2860_EEPROM_RSSI2_2GHZ 0x24
-#define RT2860_EEPROM_RSSI1_5GHZ 0x25
-#define RT2860_EEPROM_RSSI2_5GHZ 0x26
-#define RT2860_EEPROM_DELTAPWR 0x28
-#define RT2860_EEPROM_PWR2GHZ_BASE1 0x29
-#define RT2860_EEPROM_PWR2GHZ_BASE2 0x30
-#define RT2860_EEPROM_TSSI1_2GHZ 0x37
-#define RT2860_EEPROM_TSSI2_2GHZ 0x38
-#define RT2860_EEPROM_TSSI3_2GHZ 0x39
-#define RT2860_EEPROM_TSSI4_2GHZ 0x3a
-#define RT2860_EEPROM_TSSI5_2GHZ 0x3b
-#define RT2860_EEPROM_PWR5GHZ_BASE1 0x3c
-#define RT2860_EEPROM_PWR5GHZ_BASE2 0x53
-#define RT2860_EEPROM_TSSI1_5GHZ 0x6a
-#define RT2860_EEPROM_TSSI2_5GHZ 0x6b
-#define RT2860_EEPROM_TSSI3_5GHZ 0x6c
-#define RT2860_EEPROM_TSSI4_5GHZ 0x6d
-#define RT2860_EEPROM_TSSI5_5GHZ 0x6e
-#define RT2860_EEPROM_RPWR 0x6f
-#define RT2860_EEPROM_BBP_BASE 0x78
-#define RT3071_EEPROM_RF_BASE 0x82
-
/*
* RT2860_REG_SCHDMA_INT_STATUS
* RT2860_REG_SCHDMA_INT_MASK flags
@@ -593,6 +546,79 @@
#define RT2860_REG_H2M_CID3_SHIFT 24
#define RT2860_REG_H2M_CID_MASK 0xff
+/* possible flags for register RT2860_PCI_EECTRL */
+#define RT2860_C (1 << 0)
+#define RT2860_S (1 << 1)
+#define RT2860_D (1 << 2)
+#define RT2860_SHIFT_D 2
+#define RT2860_Q (1 << 3)
+#define RT2860_SHIFT_Q 3
+
+#define RT2860_RF1 0
+#define RT2860_RF2 2
+#define RT2860_RF3 1
+#define RT2860_RF4 3
+
+#define RT2860_RF_2820 1 /* 2T3R */
+#define RT2860_RF_2850 2 /* dual-band 2T3R */
+#define RT2860_RF_2720 3 /* 1T2R */
+#define RT2860_RF_2750 4 /* dual-band 1T2R */
+#define RT3070_RF_3020 5 /* 1T1R */
+#define RT3070_RF_2020 6 /* b/g */
+#define RT3070_RF_3021 7 /* 1T2R */
+#define RT3070_RF_3022 8 /* 2T2R */
+#define RT3070_RF_3052 9 /* dual-band 2T2R */
+#define RT2860_RF_2853 10 /* dual-band 3T3R */
+#define RT3070_RF_3320 11 /* 1T1R */
+#define RT3070_RF_3322 12 /* 2T2R */
+#define RT3070_RF_3053 13 /* dual-band 3T3R */
+
+/* USB commands for RT2870 only */
+#define RT2870_RESET 1
+#define RT2870_WRITE_2 2
+#define RT2870_WRITE_REGION_1 6
+#define RT2870_READ_REGION_1 7
+#define RT2870_EEPROM_READ 9
+
+#define RT2860_EEPROM_DELAY 1 /* minimum hold time (microsecond) */
+
+#define RT2860_EEPROM_VERSION 0x01
+#define RT2860_EEPROM_MAC01 0x02
+#define RT2860_EEPROM_MAC23 0x03
+#define RT2860_EEPROM_MAC45 0x04
+#define RT2860_EEPROM_PCIE_PSLEVEL 0x11
+#define RT2860_EEPROM_REV 0x12
+#define RT2860_EEPROM_ANTENNA 0x1a
+#define RT2860_EEPROM_CONFIG 0x1b
+#define RT2860_EEPROM_COUNTRY 0x1c
+#define RT2860_EEPROM_FREQ_LEDS 0x1d
+#define RT2860_EEPROM_LED1 0x1e
+#define RT2860_EEPROM_LED2 0x1f
+#define RT2860_EEPROM_LED3 0x20
+#define RT2860_EEPROM_LNA 0x22
+#define RT2860_EEPROM_RSSI1_2GHZ 0x23
+#define RT2860_EEPROM_RSSI2_2GHZ 0x24
+#define RT2860_EEPROM_RSSI1_5GHZ 0x25
+#define RT2860_EEPROM_RSSI2_5GHZ 0x26
+#define RT2860_EEPROM_DELTAPWR 0x28
+#define RT2860_EEPROM_PWR2GHZ_BASE1 0x29
+#define RT2860_EEPROM_PWR2GHZ_BASE2 0x30
+#define RT2860_EEPROM_TSSI1_2GHZ 0x37
+#define RT2860_EEPROM_TSSI2_2GHZ 0x38
+#define RT2860_EEPROM_TSSI3_2GHZ 0x39
+#define RT2860_EEPROM_TSSI4_2GHZ 0x3a
+#define RT2860_EEPROM_TSSI5_2GHZ 0x3b
+#define RT2860_EEPROM_PWR5GHZ_BASE1 0x3c
+#define RT2860_EEPROM_PWR5GHZ_BASE2 0x53
+#define RT2860_EEPROM_TSSI1_5GHZ 0x6a
+#define RT2860_EEPROM_TSSI2_5GHZ 0x6b
+#define RT2860_EEPROM_TSSI3_5GHZ 0x6c
+#define RT2860_EEPROM_TSSI4_5GHZ 0x6d
+#define RT2860_EEPROM_TSSI5_5GHZ 0x6e
+#define RT2860_EEPROM_RPWR 0x6f
+#define RT2860_EEPROM_BBP_BASE 0x78
+#define RT3071_EEPROM_RF_BASE 0x82
+
/*
* Control and status registers access macros.
*/
=======================================
--- /sys/dev/ral/rt2860var.h Wed Mar 14 02:27:13 2012
+++ /sys/dev/ral/rt2860var.h Wed Mar 14 02:42:49 2012
@@ -673,37 +673,6 @@
#define RT2860_EEPROM_TSSI_5GHZ_BASE 0x00d4
#define RT2860_EEPROM_TXPOW_RATE_BASE 0x00de
-#define RT2860_EEPROM_RF_2820 1 /* 2.4GHz 2T3R */
-#define RT2860_EEPROM_RF_2850 2 /* 2.4/5GHz 2T3R */
-#define RT2860_EEPROM_RF_2720 3 /* 2.4GHz 1T2R */
-#define RT2860_EEPROM_RF_2750 4 /* 2.4G/5GHz 1T2R */
-#define RT2860_EEPROM_RF_3020 5 /* 2.4G 1T1R */
-#define RT2860_EEPROM_RF_2020 6 /* 2.4G B/G */
-#define RT2860_EEPROM_RF_3021 7 /* 2.4G 1T2R */
-#define RT2860_EEPROM_RF_3022 8 /* 2.4G 2T2R */
-#define RT2860_EEPROM_RF_3052 9 /* 2.4G/5G 2T2R */
-#define RT2860_EEPROM_RF_2853 10 /* 2.4G.5G 3T3R */
-#define RT2860_EEPROM_RF_3320 11 /* 2.4G 1T1R with
- * PA RT3350,
- * RT3370,
- * RT3390
- */
-#define RT2860_EEPROM_RF_3322 12 /* 2.4G 2T2R with
- * PA RT3352,
- * RT3371, RT3372,
- * RT3391, RT3392
- */
-#define RT2860_EEPROM_RF_3053 13 /* 2.4G/5G 3T3R
- * RT3883,RT3563,
- * RT3573,RT3593,
- * RT3662
- */
-#define RT2860_EEPROM_RF_3853 13 /* 2.4G/5G 3T3R
- * RT3883, RT3563,
- * RT3573, RT3593,
- * RT3662
- */
-
/*
* RT2860_EEPROM_NIC_CONFIG flags
*/
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