[Zrouter-src-freebsd] ZRouter.org: push to FreeBSD HEAD tree
zrouter-src-freebsd at zrouter.org
zrouter-src-freebsd at zrouter.org
Wed Jul 25 14:36:33 UTC 2012
details: http://zrouter.org/hg/FreeBSD/head//rev/ff5f67dab441
changeset: 515:ff5f67dab441
user: Aleksandr Rybalko <ray at ddteam.net>
date: Wed Jul 25 17:29:37 2012 +0300
description:
Cleanup
diffstat:
head/sys/mips/rt305x/obio.c | 20 ++--
head/sys/mips/rt305x/rt305x_dotg.c | 8 +-
head/sys/mips/rt305x/rt305x_gpio.c | 26 ++--
head/sys/mips/rt305x/rt305x_machdep.c | 28 ++---
head/sys/mips/rt305x/rt305x_spi.c | 11 +-
head/sys/mips/rt305x/rt305x_sysctl.c | 38 +++---
head/sys/mips/rt305x/rt305xreg.h | 31 +------
head/sys/mips/rt305x/rt5350_ehci.c | 7 +-
head/sys/mips/rt305x/rt5350_usb.c | 4 +-
head/sys/mips/rt305x/rt_swreg.h | 160 ---------------------------------
head/sys/mips/rt305x/uart_bus_rt305x.c | 5 +-
head/sys/mips/rt305x/uart_dev_rt305x.c | 15 +-
12 files changed, 75 insertions(+), 278 deletions(-)
diffs (808 lines):
diff -r 34c1b0310eb0 -r ff5f67dab441 head/sys/mips/rt305x/obio.c
--- a/head/sys/mips/rt305x/obio.c Wed Jul 25 17:28:05 2012 +0300
+++ b/head/sys/mips/rt305x/obio.c Wed Jul 25 17:29:37 2012 +0300
@@ -116,7 +116,7 @@
static int obio_teardown_intr(device_t, device_t, struct resource *,
void *);
-static void
+static void
obio_mask_irq(void *source)
{
int irq;
@@ -129,7 +129,7 @@
rt305x_ic_set(IC_INT_DIS, irqmask);
}
-static void
+static void
obio_unmask_irq(void *source)
{
int irq;
@@ -205,27 +205,27 @@
bus_generic_probe(dev);
- obio_add_res_child(dev, "rt305x_sysctl", 0,
+ obio_add_res_child(dev, "rt305x_sysctl", 0,
SYSCTL_BASE, (SYSCTL_END - SYSCTL_BASE + 1),
IC_SYSCTL);
- obio_add_res_child(dev, "rt305x_ic", 0,
+ obio_add_res_child(dev, "rt305x_ic", 0,
INTCTL_BASE, (INTCTL_END - INTCTL_BASE + 1),
-1);
#ifdef notyet
- obio_add_res_child(dev, "timer",0,
+ obio_add_res_child(dev, "timer",0,
TIMER_BASE, (TIMER_END - TIMER_BASE + 1),
IC_TIMER0);
obio_add_res_child(dev, "rt305x_memc", 0,
MEMCTRL_BASE, (MEMCTRL_END - MEMCTRL_BASE + 1),
-1);
- obio_add_res_child(dev, "pcm", 0,
+ obio_add_res_child(dev, "pcm", 0,
PCM_BASE, (PCM_END - PCM_BASE + 1),
IC_PCM);
#endif
- obio_add_res_child(dev, "uart", 0,
+ obio_add_res_child(dev, "uart", 0,
UART_BASE, (UART_END - UART_BASE + 1),
IC_UART);
- obio_add_res_child(dev, "gpio", 0,
+ obio_add_res_child(dev, "gpio", 0,
PIO_BASE, (PIO_END - PIO_BASE + 1),
IC_PIO);
#ifdef notyet
@@ -241,7 +241,7 @@
obio_add_res_child(dev, "i2s", 0,
I2S_BASE, (I2S_END - I2S_BASE + 1),
IC_I2S);
- obio_add_res_child(dev, "spi", 0,
+ obio_add_res_child(dev, "spi", 0,
SPI_BASE, (SPI_END - SPI_BASE + 1),
-1);
#endif
@@ -492,7 +492,7 @@
}
static void
-obio_add_res_child(device_t bus, const char *dname, int dunit,
+obio_add_res_child(device_t bus, const char *dname, int dunit,
long maddr, int msize, int irq)
{
device_t child;
diff -r 34c1b0310eb0 -r ff5f67dab441 head/sys/mips/rt305x/rt305x_dotg.c
--- a/head/sys/mips/rt305x/rt305x_dotg.c Wed Jul 25 17:28:05 2012 +0300
+++ b/head/sys/mips/rt305x/rt305x_dotg.c Wed Jul 25 17:29:37 2012 +0300
@@ -111,7 +111,7 @@
sc->sc_dci.sc_bsh = rman_get_bushandle(sc->sc_dci.sc_mem_res);
sc->sc_dci.sc_irq_rid = 0;
- sc->sc_dci.sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
+ sc->sc_dci.sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
&sc->sc_dci.sc_irq_rid, RF_SHAREABLE| RF_ACTIVE);
if (!(sc->sc_dci.sc_irq_res)) {
printf("Can`t alloc IRQ\n");
@@ -141,7 +141,7 @@
}
/* Run clock for OTG core */
- rt305x_sysctl_set(SYSCTL_CLKCFG1, rt305x_sysctl_get(SYSCTL_CLKCFG1) |
+ rt305x_sysctl_set(SYSCTL_CLKCFG1, rt305x_sysctl_get(SYSCTL_CLKCFG1) |
SYSCTL_CLKCFG1_OTG_CLK_EN);
rt305x_sysctl_set(SYSCTL_RSTCTRL, SYSCTL_RSTCTRL_OTG);
DELAY(100);
@@ -184,8 +184,8 @@
dotg_uninit(&sc->sc_dci);
/* Stop OTG clock */
- rt305x_sysctl_set(SYSCTL_CLKCFG1,
- rt305x_sysctl_get(SYSCTL_CLKCFG1) &
+ rt305x_sysctl_set(SYSCTL_CLKCFG1,
+ rt305x_sysctl_get(SYSCTL_CLKCFG1) &
~SYSCTL_CLKCFG1_OTG_CLK_EN);
err = bus_teardown_intr(dev, sc->sc_dci.sc_irq_res,
diff -r 34c1b0310eb0 -r ff5f67dab441 head/sys/mips/rt305x/rt305x_gpio.c
--- a/head/sys/mips/rt305x/rt305x_gpio.c Wed Jul 25 17:28:05 2012 +0300
+++ b/head/sys/mips/rt305x/rt305x_gpio.c Wed Jul 25 17:29:37 2012 +0300
@@ -1,7 +1,7 @@
/*-
* Copyright (c) 2010-2011, Aleksandr Rybalko <ray at ddteam.net>
* Copyright (c) 2009, Oleksandr Tymoshenko <gonzo at FreeBSD.org>
- * Copyright (c) 2009, Luiz Otavio O Souza.
+ * Copyright (c) 2009, Luiz Otavio O Souza.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -64,7 +64,7 @@
/*
* Helpers
*/
-static void rt305x_gpio_pin_configure(struct rt305x_gpio_softc *sc,
+static void rt305x_gpio_pin_configure(struct rt305x_gpio_softc *sc,
struct gpio_pin *pin, uint32_t flags);
/*
@@ -92,7 +92,7 @@
static int rt305x_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value);
static int rt305x_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val);
static int rt305x_gpio_pin_toggle(device_t dev, uint32_t pin);
-static int rt305x_gpio_register_irq_handler(device_t dev, device_t bus,
+static int rt305x_gpio_register_irq_handler(device_t dev, device_t bus,
int (*isr)(device_t bus, device_t dev, int pin, int rise));
static int rt305x_gpio_unregister_irq_handler(device_t dev, device_t bus);
@@ -146,7 +146,7 @@
pin->gp_flags |= GPIO_PIN_REPORT;
GPIO_BIT_SET(sc, pin->gp_pin, RENA);
GPIO_BIT_SET(sc, pin->gp_pin, FENA);
- device_printf(sc->dev, "Will report interrupt on pin %d\n",
+ device_printf(sc->dev, "Will report interrupt on pin %d\n",
pin->gp_pin);
}
@@ -324,8 +324,8 @@
return (0);
}
-static int
-rt305x_gpio_register_irq_handler(device_t dev, device_t bus,
+static int
+rt305x_gpio_register_irq_handler(device_t dev, device_t bus,
int (*isr)(device_t bus, device_t dev, int pin, int rise))
{
struct rt305x_gpio_softc *sc = device_get_softc(dev);
@@ -340,7 +340,7 @@
return (0);
}
-static int
+static int
rt305x_gpio_unregister_irq_handler(device_t dev, device_t bus)
{
struct rt305x_gpio_softc *sc = device_get_softc(dev);
@@ -408,7 +408,7 @@
avl &= ~SPI_GPIO_MODE_MASK;
if (!(gmode & SYSCTL_GPIOMODE_I2C_GPIO_MODE))
avl &= ~I2C_GPIO_MODE_MASK;
- if ((gmode & SYSCTL_GPIOMODE_UARTF_SHARE_MODE_GPIO) !=
+ if ((gmode & SYSCTL_GPIOMODE_UARTF_SHARE_MODE_GPIO) !=
SYSCTL_GPIOMODE_UARTF_SHARE_MODE_GPIO)
avl &= ~I2C_GPIO_MODE_MASK;
/* D-Link DAP-1350 Board have
@@ -416,7 +416,7 @@
* UARTF_GPIO_MODE
* SPI_GPIO_MODE
* I2C_GPIO_MODE
- * So we have
+ * So we have
* 00000001 10000000 01111111 11111110
*/
return (avl);
@@ -448,13 +448,13 @@
return(error);
}
- if ((sc->gpio_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
+ if ((sc->gpio_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
&sc->gpio_irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) {
device_printf(dev, "unable to allocate IRQ resource\n");
return (ENXIO);
}
- if ((bus_setup_intr(dev, sc->gpio_irq_res, INTR_TYPE_MISC,
+ if ((bus_setup_intr(dev, sc->gpio_irq_res, INTR_TYPE_MISC,
/* rt305x_gpio_filter, */
rt305x_gpio_intr, NULL, sc, &sc->gpio_ih))) {
device_printf(dev,
@@ -470,7 +470,7 @@
/* TODO */
sc->gpio_npins = NGPIO;
- resource_int_value(device_get_name(dev), device_get_unit(dev),
+ resource_int_value(device_get_name(dev), device_get_unit(dev),
"pins", &sc->gpio_npins);
for (i = 0; i < sc->gpio_npins; i++) {
@@ -584,5 +584,5 @@
};
static devclass_t rt305x_gpio_devclass;
-DRIVER_MODULE(rt305x_gpio, obio, rt305x_gpio_driver,
+DRIVER_MODULE(rt305x_gpio, obio, rt305x_gpio_driver,
rt305x_gpio_devclass, 0, 0);
diff -r 34c1b0310eb0 -r ff5f67dab441 head/sys/mips/rt305x/rt305x_machdep.c
--- a/head/sys/mips/rt305x/rt305x_machdep.c Wed Jul 25 17:28:05 2012 +0300
+++ b/head/sys/mips/rt305x/rt305x_machdep.c Wed Jul 25 17:29:37 2012 +0300
@@ -83,7 +83,6 @@
int rt305x_cpu_clock;
int rt305x_system_clock;
-
#define RT305X_READ4(_reg) (*((uint32_t *)MIPS_PHYS_TO_KSEG1(_reg)))
static void
@@ -129,7 +128,6 @@
printf("entry: mips_init()\n");
-// bootverbose = 1;
realmem = btoc(32 << 20);
for (i = 0; i < 10; i++) {
@@ -294,7 +292,7 @@
case 0x3051:
case 0x3052:
case 0x3350:
- boot_from = (syscfg >> SYSCTL_SYSCFG_BOOT_FROM_SHIFT) & 0x3;
+ boot_from = (syscfg >> SYSCTL_SYSCFG_BOOT_FROM_SHIFT) & 0x3;
switch(syscfg & SYSCTL_SYSCFG_BOOT_FROM_MASK) {
case SYSCTL_SYSCFG_BOOT_FROM_FLASH16:
@@ -347,7 +345,7 @@
id2 = RT305X_READ4(SYSCTL_BASE + 4);
if ((id1 & 0xffff) != ('R' | ('T' << 8))) {
- rt305x_chip_id = 0; /* XXX: found some safe value */
+ rt305x_chip_id = 0; /* XXX: find some safe value */
return;
}
rt305x_chip_id = ((id1 >> 16) & 0xff) - '0';
@@ -364,15 +362,17 @@
}
void
-platform_start(__register_t a0 __unused, __register_t a1 __unused,
+platform_start(__register_t a0 __unused, __register_t a1 __unused,
__register_t a2 __unused, __register_t a3 __unused)
{
+ uint64_t platform_counter_freq;
vm_offset_t kernend;
- uint64_t platform_counter_freq = PLATFORM_COUNTER_FREQ;
- int i;
- int argc = a0;
- char **argv = (char **)MIPS_PHYS_TO_KSEG0(a1);
- char **envp = (char **)MIPS_PHYS_TO_KSEG0(a2);
+ char **argv, **envp;
+ int i, argc;
+
+ argc = a0;
+ argv = (char **)MIPS_PHYS_TO_KSEG0(a1);
+ envp = (char **)MIPS_PHYS_TO_KSEG0(a2);
/* clear the BSS and SBSS segments */
kernend = (vm_offset_t)&end;
@@ -396,9 +396,9 @@
cninit();
printf("RT%x runing with %dMHz clock\n", rt305x_chip_id,
(int)(rt305x_cpu_clock/1000/1000));
- printf("System bus clock - %dMHz\n",
+ printf("System bus clock - %dMHz\n",
(int)(rt305x_system_clock/1000/1000));
- printf("System start from %s flash storage\n",
+ printf("System start from %s flash storage\n",
(rt305x_boot_source == BOOT_SOURCE_NOR) ? "NOR" :
(rt305x_boot_source == BOOT_SOURCE_NAND) ? "NAND" :
(rt305x_boot_source == BOOT_SOURCE_SPI) ? "SPI" : "UNKNOWN");
@@ -411,7 +411,6 @@
printf("\tNone\n");
for (i = 1; i < argc; i++) {
-// char *n = "argv ";
char *arg;
if (i > 99)
@@ -420,9 +419,6 @@
if (argv[i])
{
arg = (char *)(intptr_t)MIPS_PHYS_TO_KSEG0(argv[i]);
- printf("\targv[%d] = %s\n", i, arg);
- //sprintf(n, "argv%d", i);
- //setenv(n, arg);
parse_argv(arg);
}
}
diff -r 34c1b0310eb0 -r ff5f67dab441 head/sys/mips/rt305x/rt305x_spi.c
--- a/head/sys/mips/rt305x/rt305x_spi.c Wed Jul 25 17:28:05 2012 +0300
+++ b/head/sys/mips/rt305x/rt305x_spi.c Wed Jul 25 17:29:37 2012 +0300
@@ -105,7 +105,7 @@
sc->sc_dev = dev;
rid = 0;
- sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
+ sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (!sc->sc_mem_res) {
device_printf(dev, "Could not map memory\n");
@@ -220,11 +220,6 @@
rt305x_spi_chip_activate(sc);
-// KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz,
-// ("TX/RX command sizes should be equal"));
-// KASSERT(cmd->tx_data_sz == cmd->rx_data_sz,
-// ("TX/RX data sizes should be equal"));
-
/*
* Transfer/Receive command
*/
@@ -235,7 +230,7 @@
for (i = 0; i < sz; i++) {
byte = buf[i];
- error = rt305x_spi_txrx(sc, &byte,
+ error = rt305x_spi_txrx(sc, &byte,
write?RT305X_SPI_WRITE:RT305X_SPI_READ);
if (error)
goto rt305x_spi_transfer_fail;
@@ -253,7 +248,7 @@
for (i = 0; i < sz; i++) {
byte = buf[i];
- error = rt305x_spi_txrx(sc, &byte,
+ error = rt305x_spi_txrx(sc, &byte,
write?RT305X_SPI_WRITE:RT305X_SPI_READ);
if (error)
goto rt305x_spi_transfer_fail;
diff -r 34c1b0310eb0 -r ff5f67dab441 head/sys/mips/rt305x/rt305x_sysctl.c
--- a/head/sys/mips/rt305x/rt305x_sysctl.c Wed Jul 25 17:28:05 2012 +0300
+++ b/head/sys/mips/rt305x/rt305x_sysctl.c Wed Jul 25 17:29:37 2012 +0300
@@ -57,16 +57,16 @@
val = rt305x_sysctl_get(r); printf(" " #r "=%#08x\n", val)
val = rt305x_sysctl_get(SYSCTL_CHIPID0_3);
- printf("\tChip ID: \"%c%c%c%c",
- (val >> 0 ) & 0xff,
- (val >> 8 ) & 0xff,
- (val >> 16) & 0xff,
+ printf("\tChip ID: \"%c%c%c%c",
+ (val >> 0 ) & 0xff,
+ (val >> 8 ) & 0xff,
+ (val >> 16) & 0xff,
(val >> 24) & 0xff);
val = rt305x_sysctl_get(SYSCTL_CHIPID4_7);
- printf("%c%c%c%c\"\n",
- (val >> 0 ) & 0xff,
- (val >> 8 ) & 0xff,
- (val >> 16) & 0xff,
+ printf("%c%c%c%c\"\n",
+ (val >> 0 ) & 0xff,
+ (val >> 8 ) & 0xff,
+ (val >> 16) & 0xff,
(val >> 24) & 0xff);
DUMPREG(SYSCTL_SYSCFG);
@@ -75,7 +75,7 @@
if ( val & SYSCTL_SYSCFG_INIC_8MB_SDRAM)
printf("\tBootstrap flag is set\n");
printf("\tGE0 mode %u\n",
- ((val & SYSCTL_SYSCFG_GE0_MODE_MASK) >>
+ ((val & SYSCTL_SYSCFG_GE0_MODE_MASK) >>
SYSCTL_SYSCFG_GE0_MODE_SHIFT));
if ( val & SYSCTL_SYSCFG_BOOT_ADDR_1F00)
printf("\tBoot from 0x1f000000\n");
@@ -86,13 +86,13 @@
if ( val & SYSCTL_SYSCFG_CPU_CLK_SEL_384MHZ)
printf("\tClock is 384MHz\n");
printf("\tBoot from %u\n",
- ((val & SYSCTL_SYSCFG_BOOT_FROM_MASK) >>
+ ((val & SYSCTL_SYSCFG_BOOT_FROM_MASK) >>
SYSCTL_SYSCFG_BOOT_FROM_SHIFT));
printf("\tBootstrap test code %u\n",
- ((val & SYSCTL_SYSCFG_TEST_CODE_MASK) >>
+ ((val & SYSCTL_SYSCFG_TEST_CODE_MASK) >>
SYSCTL_SYSCFG_TEST_CODE_SHIFT));
printf("\tSRAM_CS mode %u\n",
- ((val & SYSCTL_SYSCFG_SRAM_CS_MODE_MASK) >>
+ ((val & SYSCTL_SYSCFG_SRAM_CS_MODE_MASK) >>
SYSCTL_SYSCFG_SRAM_CS_MODE_SHIFT));
printf("\t%umA SDRAM_CLK driving\n",
(val & SYSCTL_SYSCFG_SDRAM_CLK_DRV)?12:8);
@@ -107,20 +107,20 @@
printf("\tUSB OTG clock is enabled\n");
if ( val & SYSCTL_CLKCFG1_I2S_CLK_EN)
printf("\tI2S clock is enabled\n");
- printf("\tI2S clock is %s\n",
+ printf("\tI2S clock is %s\n",
(val & SYSCTL_CLKCFG1_I2S_CLK_SEL_EXT)?
"external":"internal 15.625MHz");
printf("\tI2S clock divider %u\n",
- ((val & SYSCTL_CLKCFG1_I2S_CLK_DIV_MASK) >>
+ ((val & SYSCTL_CLKCFG1_I2S_CLK_DIV_MASK) >>
SYSCTL_CLKCFG1_I2S_CLK_DIV_SHIFT));
if ( val & SYSCTL_CLKCFG1_PCM_CLK_EN)
printf("\tPCM clock is enabled\n");
- printf("\tPCM clock is %s\n",
+ printf("\tPCM clock is %s\n",
(val & SYSCTL_CLKCFG1_PCM_CLK_SEL_EXT)?
"external":"internal 15.625MHz");
printf("\tPCM clock divider %u\n",
- ((val & SYSCTL_CLKCFG1_PCM_CLK_DIV_MASK) >>
+ ((val & SYSCTL_CLKCFG1_PCM_CLK_DIV_MASK) >>
SYSCTL_CLKCFG1_PCM_CLK_DIV_SHIFT));
DUMPREG(SYSCTL_GPIOMODE);
#undef DUMPREG
@@ -163,13 +163,13 @@
}
#ifdef notyet
sc->irq_rid = 0;
- if ((sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
+ if ((sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
&sc->irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) {
device_printf(dev, "unable to allocate IRQ resource\n");
return (ENXIO);
}
- if ((bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC,
+ if ((bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC,
rt305x_sysctl_intr, NULL, sc, &sc->sysctl_ih))) {
device_printf(dev,
"WARNING: unable to register interrupt handler\n");
@@ -183,7 +183,7 @@
*/
/* Check if we need change SYSCTL_GPIOMODE */
gpiomode = rt305x_sysctl_get(SYSCTL_GPIOMODE);
- resource_int_value(device_get_name(dev), device_get_unit(dev),
+ resource_int_value(device_get_name(dev), device_get_unit(dev),
"gpiomode", &gpiomode);
/* if no hint for as, we just return current value */
rt305x_sysctl_set(SYSCTL_GPIOMODE, gpiomode);
diff -r 34c1b0310eb0 -r ff5f67dab441 head/sys/mips/rt305x/rt305xreg.h
--- a/head/sys/mips/rt305x/rt305xreg.h Wed Jul 25 17:28:05 2012 +0300
+++ b/head/sys/mips/rt305x/rt305xreg.h Wed Jul 25 17:29:37 2012 +0300
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2010 Aleksandr Rybalko.
+ * Copyright (c) 2010-2012 Aleksandr Rybalko.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -29,29 +29,6 @@
#ifndef _RT305XREG_H_
#define _RT305XREG_H_
-/* XXX: must move to config */
-#define RT305X 1
-#define RT305XF 1
-#define RT3052F 1
-#define __U_BOOT__ 1
-/* XXX: must move to config */
-
-#ifdef RT3052F
-#define PLATFORM_COUNTER_FREQ (384 * 1000 * 1000)
-#endif
-#ifdef RT3050F
-#define PLATFORM_COUNTER_FREQ (320 * 1000 * 1000)
-#endif
-#ifdef RT5350F
-#define PLATFORM_COUNTER_FREQ (360 * 1000 * 1000)
-#endif
-#ifndef PLATFORM_COUNTER_FREQ
-#error "Chip family not defined"
-#endif
-
-#define SYSTEM_CLOCK (PLATFORM_COUNTER_FREQ/3)
-
-
#define SDRAM_BASE 0x00000000
#define SDRAM_END 0x03FFFFFF
@@ -101,8 +78,6 @@
#define OBIO_MEM_START OBIO_MEM_BASE
#define OBIO_MEM_END FLASH_END
-
-
/* System Control */
#define SYSCTL_CHIPID0_3 0x00 /* 'R''T''3''0' */
#define SYSCTL_CHIPID4_7 0x04 /* '5''2'' '' ' */
@@ -286,7 +261,6 @@
#define IC_INT_MASK 0x000617ff
/* GPIO */
-
#define GPIO23_00_INT 0x00 /* Programmed I/O Int Status */
#define GPIO23_00_EDGE 0x04 /* Programmed I/O Edge Status */
#define GPIO23_00_RENA 0x08 /* Programmed I/O Int on Rising */
@@ -320,9 +294,6 @@
#define GPIO51_40_RESET 0x80
#define GPIO51_40_TOG 0x84
-
-
-
#define GDMA_CHANNEL_REQ0 0
#define GDMA_CHANNEL_REQ1 1 /* (NAND-flash) */
#define GDMA_CHANNEL_REQ2 2 /* (I2S) */
diff -r 34c1b0310eb0 -r ff5f67dab441 head/sys/mips/rt305x/rt5350_ehci.c
--- a/head/sys/mips/rt305x/rt5350_ehci.c Wed Jul 25 17:28:05 2012 +0300
+++ b/head/sys/mips/rt305x/rt5350_ehci.c Wed Jul 25 17:29:37 2012 +0300
@@ -77,9 +77,6 @@
static device_attach_t ehci_siba_attach;
static device_detach_t ehci_siba_detach;
-//#define USB_BRIDGE_INTR_CAUSE 0x210
-//#define USB_BRIDGE_INTR_MASK 0x214
-
static int
ehci_siba_probe(device_t self)
{
@@ -109,7 +106,7 @@
}
rid = 0;
- sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid,
+ sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (!sc->sc_io_res) {
device_printf(self, "Could not map memory\n");
@@ -146,8 +143,6 @@
goto error;
}
-// sc->sc_flags |= EHCI_SCFLG_SETMODE | EHCI_SCFLG_LOSTINTRBUG;
-
err = ehci_init(sc);
if (!err) {
err = device_probe_and_attach(sc->sc_bus.bdev);
diff -r 34c1b0310eb0 -r ff5f67dab441 head/sys/mips/rt305x/rt5350_usb.c
--- a/head/sys/mips/rt305x/rt5350_usb.c Wed Jul 25 17:28:05 2012 +0300
+++ b/head/sys/mips/rt305x/rt5350_usb.c Wed Jul 25 17:29:37 2012 +0300
@@ -129,7 +129,7 @@
rid = 0;
- sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
+ sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
RF_SHAREABLE | RF_ACTIVE);
if (sc->sc_irq == NULL) {
device_printf(dev, "unable to allocate irq\n");
@@ -150,7 +150,7 @@
sc->irq_rman.rm_end = sc->sc_irqn;
sc->irq_rman.rm_type = RMAN_ARRAY;
sc->irq_rman.rm_descr = "rt5350 USB core IRQ";
- /*
+ /*
* rt5350 USB share one IRQ between OHCI and EHCI
*/
if (rman_init(&sc->irq_rman) != 0 ||
diff -r 34c1b0310eb0 -r ff5f67dab441 head/sys/mips/rt305x/rt_swreg.h
--- a/head/sys/mips/rt305x/rt_swreg.h Wed Jul 25 17:28:05 2012 +0300
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,160 +0,0 @@
-/*-
- * Copyright (c) 2010 Aleksandr Rybalko.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $FreeBSD$
- */
-
-#ifndef _RT_SWREG_H_
-#define _RT_SWREG_H_
-
-/* XXX: must move to config */
-#define RT3052F
-
-#define RT_SW_BASE 0x10110000
-
-#define RT_SW_ISR 0x00
-
-#define WATCHDOG1_TMR_EXPIRED (1<<29)
-#define WATCHDOG0_TMR_EXPIRED (1<<28)
-#define HAS_INTRUDER (1<<27)
-#define PORT_ST_CHG (1<<26)
-#define BC_STORM (1<<25)
-#define MUST_DROP_LAN (1<<24)
-#define GLOBAL_QUE_FULL (1<<23)
-#define LAN_QUE_FULL6 (1<<20)
-#define LAN_QUE_FULL5 (1<<19)
-#define LAN_QUE_FULL4 (1<<18)
-#define LAN_QUE_FULL3 (1<<17)
-#define LAN_QUE_FULL2 (1<<16)
-#define LAN_QUE_FULL1 (1<<15)
-#define LAN_QUE_FULL0 (1<<14)
-
-#define RT_SW_IMR 0x04
-
-#define RT_SW_FCT0 0x08
-#define RT_SW_FCT1 0x0c
-#define RT_SW_PFC0 0x10
-#define RT_SW_PFC1 0x14
-#define RT_SW_PFC2 0x18
-#define RT_SW_GQS0 0x1c
-#define RT_SW_GQS1 0x20
-#define RT_SW_ATS 0x24
-#define RT_SW_ATS0 0x28
-#define RT_SW_ATS1 0x2c
-#define RT_SW_ATS2 0x30
-#define RT_SW_WMAD0 0x34
-#define RT_SW_WMAD1 0x38
-#define RT_SW_WMAD2 0x3c
-#define RT_SW_PVIDC0 0x40
-#define RT_SW_PVIDC1 0x44
-#define RT_SW_PVIDC2 0x48
-#define RT_SW_PVIDC3 0x4c
-#define RT_SW_VID0 0x50
-#define RT_SW_VID1 0x54
-#define RT_SW_VID2 0x58
-#define RT_SW_VID3 0x5c
-#define RT_SW_VID4 0x60
-#define RT_SW_VID5 0x64
-#define RT_SW_VID6 0x68
-#define RT_SW_VID7 0x6c
-#define RT_SW_VMSC0 0x70
-#define RT_SW_VMSC1 0x74
-#define RT_SW_VMSC2 0x78
-#define RT_SW_VMSC3 0x7c
-#define RT_SW_POA 0x80
-#define RT_SW_FPA 0x84
-#define RT_SW_PTS 0x88
-#define RT_SW_SOCPC 0x8c
-#define RT_SW_POC0 0x90
-#define RT_SW_POC1 0x94
-#define RT_SW_POC2 0x98
-#define RT_SW_SGC 0x9c
-#define RT_SW_STRT 0xa0
-#define RT_SW_LEDP0 0xa4
-#define RT_SW_LEDP1 0xa8
-#define RT_SW_LEDP2 0xac
-#define RT_SW_LEDP3 0xb0
-#define RT_SW_LEDP4 0xb4
-#define RT_SW_WDTR 0xb8
-#define RT_SW_DES 0xbc
-#define RT_SW_PCR0 0xc0
-#define RT_SW_PCR1 0xc4
-#define RT_SW_FPA 0xc8
-#define RT_SW_FCT2 0xcc
-#define RT_SW_QSS0 0xd0
-
-#define RT_SW_QSS1 0xd4
-#define RT_SW_DEC 0xd8
-#define BRIDGE_IPG_SHIFT 24
-#define DEBUG_SW_PORT_SEL_SHIFT 3
-#define DEBUG_SW_PORT_SEL_MASK 0x00000038
-
-#define RT_SW_MTI 0xdc
-#define SKIP_BLOCKS_SHIFT 7
-#define SKIP_BLOCKS_MASK 0x0000ff80
-#define SW_RAM_TEST_DONE (1<<6)
-#define AT_RAM_TEST_DONE (1<<5)
-#define AT_RAM_TEST_FAIL (1<<4)
-#define LK_RAM_TEST_DONE (1<<3)
-#define LK_RAM_TEST_FAIL (1<<2)
-#define DT_RAM_TEST_DONE (1<<1)
-#define DT_RAM_TEST_FAIL (1<<0)
-
-#define RT_SW_PPC 0xe0
-#define SW2FE_CNT_SHIFT 16
-#define FE2SW_CNT_SHIFT 0
-
-#define RT_SW_SGC2 0xe4
-#define FE2SW_WL_FC_EN (1<<30)
-#define LAN_PMAP_P0_IS_LAN (1<<24)
-#define LAN_PMAP_P1_IS_LAN (1<<25)
-#define LAN_PMAP_P2_IS_LAN (1<<26)
-#define LAN_PMAP_P3_IS_LAN (1<<27)
-#define LAN_PMAP_P4_IS_LAN (1<<28)
-#define LAN_PMAP_P5_IS_LAN (1<<29)
-/* Transmit CPU TPID(810x) port bit map */
-#define TX_CPU_TPID_BIT_MAP_SHIFT 16
-#define TX_CPU_TPID_BIT_MAP_MASK 0x007f0000
-#define ARBITER_LAN_EN (1<<11)
-#define CPU_TPID_EN (1<<10)
-#define P0_DOUBLE_TAG_EN (1<<0)
-#define P1_DOUBLE_TAG_EN (1<<1)
-#define P2_DOUBLE_TAG_EN (1<<2)
-#define P3_DOUBLE_TAG_EN (1<<3)
-#define P4_DOUBLE_TAG_EN (1<<4)
-#define P5_DOUBLE_TAG_EN (1<<5)
-
-#define RT_SW_P0PC 0xe8
-#define RT_SW_P1PC 0xec
-#define RT_SW_P2PC 0xf0
-#define RT_SW_P3PC 0xf4
-#define RT_SW_P4PC 0xf8
-#define RT_SW_P5PC 0xfc
-#define BAD_PCOUNT_SHIFT 16
-#define BAD_PCOUNT_MASK 0xffff0000
-#define GOOD_PCOUNT_SHIFT 0
-#define GOOD_PCOUNT_MASK 0x0000ffff
-
-#endif /* _RT_SWREG_H_ */
diff -r 34c1b0310eb0 -r ff5f67dab441 head/sys/mips/rt305x/uart_bus_rt305x.c
--- a/head/sys/mips/rt305x/uart_bus_rt305x.c Wed Jul 25 17:28:05 2012 +0300
+++ b/head/sys/mips/rt305x/uart_bus_rt305x.c Wed Jul 25 17:29:37 2012 +0300
@@ -85,14 +85,15 @@
sc = device_get_softc(dev);
sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs);
sc->sc_class = &uart_rt305x_uart_class;
+ sc->sc_class->uc_rclk = rt305x_system_clock;
bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas));
sc->sc_sysdev->bas.regshft = 2;
sc->sc_sysdev->bas.bst = mips_bus_space_generic;
- sc->sc_sysdev->bas.bsh =
+ sc->sc_sysdev->bas.bsh =
MIPS_PHYS_TO_KSEG1(device_get_unit(dev)?UARTLITE_BASE:UART_BASE);
sc->sc_bas.regshft = 2;
sc->sc_bas.bst = mips_bus_space_generic;
- sc->sc_bas.bsh =
+ sc->sc_bas.bsh =
MIPS_PHYS_TO_KSEG1(device_get_unit(dev)?UARTLITE_BASE:UART_BASE);
return (uart_bus_probe(dev, 2, rt305x_system_clock, 0, 0));
diff -r 34c1b0310eb0 -r ff5f67dab441 head/sys/mips/rt305x/uart_dev_rt305x.c
--- a/head/sys/mips/rt305x/uart_dev_rt305x.c Wed Jul 25 17:28:05 2012 +0300
+++ b/head/sys/mips/rt305x/uart_dev_rt305x.c Wed Jul 25 17:29:37 2012 +0300
@@ -88,7 +88,7 @@
}
static void
-rt305x_uart_init(struct uart_bas *bas, int baudrate, int databits,
+rt305x_uart_init(struct uart_bas *bas, int baudrate, int databits,
int stopbits, int parity)
{
#ifdef notyet
@@ -217,7 +217,6 @@
sizeof(struct rt305x_uart_softc),
.uc_ops = &uart_rt305x_uart_ops,
.uc_range = 1, /* use hinted range */
- .uc_rclk = SYSTEM_CLOCK
};
#define SIGCHG(c, i, s, d) \
@@ -228,8 +227,8 @@
}
/*
- * Disable TX interrupt. uart should be locked
- */
+ * Disable TX interrupt. uart should be locked
+ */
static __inline void
rt305x_uart_disable_txintr(struct uart_softc *sc)
{
@@ -243,8 +242,8 @@
}
/*
- * Enable TX interrupt. uart should be locked
- */
+ * Enable TX interrupt. uart should be locked
+ */
static __inline void
rt305x_uart_enable_txintr(struct uart_softc *sc)
{
@@ -278,8 +277,8 @@
(void)rt305x_uart_bus_getsig(sc);
/* Enable FIFO */
- uart_setreg(bas, UART_FCR_REG,
- uart_getreg(bas, UART_FCR_REG) |
+ uart_setreg(bas, UART_FCR_REG,
+ uart_getreg(bas, UART_FCR_REG) |
UART_FCR_FIFOEN | UART_FCR_TXTGR_1 | UART_FCR_RXTGR_1);
uart_barrier(bas);
/* Enable interrupts */
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