[Zrouter-src-freebsd] ZRouter.org: push to FreeBSD HEAD tree

zrouter-src-freebsd at zrouter.org zrouter-src-freebsd at zrouter.org
Wed Apr 4 14:02:31 UTC 2012


details:   http://zrouter.org/hg/FreeBSD/head//rev/7aafd0c42486
changeset: 449:7aafd0c42486
user:      Aleksandr Rybalko <ray at ddteam.net>
date:      Wed Apr 04 16:54:19 2012 +0300
description:
Enable RT5350F Ethernet MAC support.

Submitted by:	Alexander A. Mityaev sansan at adm dot ua

diffstat:

 head/sys/dev/rt/if_rt.c    |  302 ++++++++++++++++++++++---------
 head/sys/dev/rt/if_rtreg.h |  424 +++++++++++++++++++++++++-------------------
 head/sys/dev/rt/if_rtvar.h |   26 ++-
 3 files changed, 467 insertions(+), 285 deletions(-)

diffs (1044 lines):

diff -r 701b26f9bc86 -r 7aafd0c42486 head/sys/dev/rt/if_rt.c
--- a/head/sys/dev/rt/if_rt.c	Wed Apr 04 16:52:15 2012 +0300
+++ b/head/sys/dev/rt/if_rt.c	Wed Apr 04 16:54:19 2012 +0300
@@ -1,8 +1,9 @@
 /*-
- * Copyright (c) 2011, Aleksandr Rybalko
- * based on hard work
- * by Alexander Egorenkov <egorenar at gmail.com>
- * and by Damien Bergamini <damien.bergamini at free.fr>
+ * Copyright (c) 2012, Alexander A. Mityaev <sansan at adm.ua>
+ * Copyright (c) 2011-2012, Aleksandr Rybalko <ray at ddteam.net>
+ * Derived from rt2860.c.
+ * Copyright (c) 2009-2010 Alexander Egorenkov <egorenar at gmail.com>
+ * Copyright (c) 2009 Damien Bergamini <damien.bergamini at free.fr>
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -95,6 +96,7 @@
 static void	rt_periodic(void *arg);
 static void	rt_tx_watchdog(void *arg);
 static void	rt_intr(void *arg);
+static void	rt_rt5350_intr(void *arg);
 static void	rt_tx_coherent_intr(struct rt_softc *sc);
 static void	rt_rx_coherent_intr(struct rt_softc *sc);
 static void	rt_rx_delay_intr(struct rt_softc *sc);
@@ -293,6 +295,7 @@
 {
 	struct rt_softc *sc;
 	struct ifnet *ifp;
+	uint32_t tmp;
 	int error, i;
 
 	sc = device_get_softc(dev);
@@ -331,23 +334,63 @@
 		"debug", CTLFLAG_RW, &sc->debug, 0, "rt debug level");
 #endif
 
-	device_printf(dev, "RT305XF Ethernet MAC (rev 0x%08x)\n",
-	    sc->mac_rev);
-
-	/* Reset hardware */
-	RT_WRITE(sc, GE_PORT_BASE + FE_RST_GLO, PSE_RESET);
-
-	RT_WRITE(sc, GDMA1_BASE + GDMA_FWD_CFG,
-	    (
-	    GDM_ICS_EN | /* Enable IP Csum */
-	    GDM_TCS_EN | /* Enable TCP Csum */
-	    GDM_UCS_EN | /* Enable UDP Csum */
-	    GDM_STRPCRC | /* Strip CRC from packet */
-	    GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* Forward UCast to CPU */
-	    GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* Forward BCast to CPU */
-	    GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* Forward MCast to CPU */
-	    GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT   /* Forward Other to CPU */
-	    ));
+	switch(rt305x_chip_id) {
+	case 0x5350:
+    		device_printf(dev, "RT5350F Ethernet MAC\n");
+
+		/* RT5350: No GDMA, PSE, CDMA, PPE */
+		tmp = RT_READ(sc, GE_PORT_BASE + 0x0C00);
+		tmp |= 0x7<<16; /* UDPCS, TCPCS, IPCS=1 */
+		RT_WRITE(sc, GE_PORT_BASE + 0x0C00, tmp);
+
+		/* fill in soc-specific register map */
+		sc->delay_int_cfg = RT5350_PDMA_BASE + RT5350_DELAY_INT_CFG;
+		sc->fe_int_status = RT5350_FE_INT_STATUS;
+		sc->fe_int_enable = RT5350_FE_INT_ENABLE;
+		sc->pdma_glo_cfg = RT5350_PDMA_BASE + RT5350_PDMA_GLO_CFG;
+		sc->pdma_rst_idx = RT5350_PDMA_BASE + RT5350_PDMA_RST_IDX;
+		for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
+			sc->tx_base_ptr[i] = RT5350_PDMA_BASE + RT5350_TX_BASE_PTR(i);
+			sc->tx_max_cnt[i] = RT5350_PDMA_BASE + RT5350_TX_MAX_CNT(i);
+			sc->tx_ctx_idx[i] = RT5350_PDMA_BASE + RT5350_TX_CTX_IDX(i);
+			sc->tx_dtx_idx[i] = RT5350_PDMA_BASE + RT5350_TX_DTX_IDX(i);
+		}
+		sc->rx_base_ptr = RT5350_PDMA_BASE + RT5350_RX_BASE_PTR0;
+		sc->rx_max_cnt = RT5350_PDMA_BASE + RT5350_RX_MAX_CNT0;
+		sc->rx_calc_idx = RT5350_PDMA_BASE + RT5350_RX_CALC_IDX0;
+		sc->rx_drx_idx = RT5350_PDMA_BASE + RT5350_RX_DRX_IDX0;
+
+		break;
+          default:
+		device_printf(dev, "RT305XF Ethernet MAC\n");
+		RT_WRITE(sc, GDMA1_BASE + GDMA_FWD_CFG,
+		    (GDM_ICS_EN | /* Enable IP Csum */
+		    GDM_TCS_EN | /* Enable TCP Csum */
+		    GDM_UCS_EN | /* Enable UDP Csum */
+		    GDM_STRPCRC | /* Strip CRC from packet */
+		    /* CPU forward */
+		    GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* UCast */
+		    GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* BCast */
+		    GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* MCast */
+		    GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT)); /* Other */
+
+		/* fill in soc-specific register map */
+		sc->delay_int_cfg = PDMA_BASE + DELAY_INT_CFG;
+		sc->fe_int_status = GE_PORT_BASE + FE_INT_STATUS;
+		sc->fe_int_enable = GE_PORT_BASE + FE_INT_ENABLE;
+		sc->pdma_glo_cfg = PDMA_BASE + PDMA_GLO_CFG;
+		sc->pdma_rst_idx = PDMA_BASE + PDMA_RST_IDX;
+		for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
+			sc->tx_base_ptr[i] = PDMA_BASE + TX_BASE_PTR(i);
+			sc->tx_max_cnt[i] = PDMA_BASE + TX_MAX_CNT(i);
+			sc->tx_ctx_idx[i] = PDMA_BASE + TX_CTX_IDX(i);
+			sc->tx_dtx_idx[i] = PDMA_BASE + TX_DTX_IDX(i);
+		}
+		sc->rx_base_ptr = PDMA_BASE + RX_BASE_PTR0;
+		sc->rx_max_cnt = PDMA_BASE + RX_MAX_CNT0;
+		sc->rx_calc_idx = PDMA_BASE + RX_CALC_IDX0;
+		sc->rx_drx_idx = PDMA_BASE + RX_DRX_IDX0;
+	}
 
 	/* allocate Tx and Rx rings */
 	for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
@@ -434,7 +477,9 @@
 
 	/* set up interrupt */
 	error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
-	    NULL, rt_intr, sc, &sc->irqh);
+	    NULL,
+	    (rt305x_chip_id == 0x5350) ? rt_rt5350_intr : rt_intr,
+	    sc, &sc->irqh);
 	if (error != 0) {
 		printf("%s: could not set up interrupt\n",
 			device_get_nameunit(dev));
@@ -661,30 +706,28 @@
 
 	RT_SOFTC_ASSERT_LOCKED(sc);
 
-	/* hardware reset */
-	RT_WRITE(sc, GE_PORT_BASE + FE_RST_GLO, PSE_RESET);
-	rt305x_sysctl_set(SYSCTL_RSTCTRL, SYSCTL_RSTCTRL_FRENG);
-
-	/* Fwd to CPU (uni|broad|multi)cast and Unknown */
-	RT_WRITE(sc, GDMA1_BASE + GDMA_FWD_CFG,
-	    (
-	    GDM_ICS_EN | /* Enable IP Csum */
-	    GDM_TCS_EN | /* Enable TCP Csum */
-	    GDM_UCS_EN | /* Enable UDP Csum */
-	    GDM_STRPCRC | /* Strip CRC from packet */
-	    GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* Forward UCast to CPU */
-	    GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* Forward BCast to CPU */
-	    GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* Forward MCast to CPU */
-	    GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT   /* Forward Other to CPU */
-	    ));
+	if (rt305x_chip_id != 0x5350) {
+		/* Fwd to CPU (uni|broad|multi)cast and Unknown */
+		RT_WRITE(sc, GDMA1_BASE + GDMA_FWD_CFG,
+		    (
+		    GDM_ICS_EN | /* Enable IP Csum */
+		    GDM_TCS_EN | /* Enable TCP Csum */
+		    GDM_UCS_EN | /* Enable UDP Csum */
+		    GDM_STRPCRC | /* Strip CRC from packet */
+		    /* CPU Forward */
+		    GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* UCast */
+		    GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* BCast */
+		    GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* MCast */
+		    GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT)); /* Other */
+	}
 
 	/* disable DMA engine */
-	RT_WRITE(sc, PDMA_BASE + PDMA_GLO_CFG, 0);
-	RT_WRITE(sc, PDMA_BASE + PDMA_RST_IDX, 0xffffffff);
+	RT_WRITE(sc, sc->pdma_glo_cfg, 0);
+	RT_WRITE(sc, sc->pdma_rst_idx, 0xffffffff);
 
 	/* wait while DMA engine is busy */
 	for (ntries = 0; ntries < 100; ntries++) {
-		tmp = RT_READ(sc, PDMA_BASE + PDMA_GLO_CFG);
+		tmp = RT_READ(sc, sc->pdma_glo_cfg);
 		if (!(tmp & (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)))
 			break;
 		DELAY(1000);
@@ -702,7 +745,7 @@
 		FE_RST_DTX_IDX1 |
 		FE_RST_DTX_IDX0;
 
-	RT_WRITE(sc, PDMA_BASE + PDMA_RST_IDX, tmp);
+	RT_WRITE(sc, sc->pdma_rst_idx, tmp);
 
 	/* XXX switch set mac address */
 	for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++)
@@ -710,55 +753,65 @@
 
 	for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
 		/* update TX_BASE_PTRx */
-		RT_WRITE(sc, PDMA_BASE + TX_BASE_PTR(i),
+		RT_WRITE(sc, sc->tx_base_ptr[i],
 			sc->tx_ring[i].desc_phys_addr);
-		RT_WRITE(sc, PDMA_BASE + TX_MAX_CNT(i),
+		RT_WRITE(sc, sc->tx_max_cnt[i],
 			RT_SOFTC_TX_RING_DESC_COUNT);
-		RT_WRITE(sc, PDMA_BASE + TX_CTX_IDX(i), 0);
+		RT_WRITE(sc, sc->tx_ctx_idx[i], 0);
 	}
 
 	/* init Rx ring */
 	rt_reset_rx_ring(sc, &sc->rx_ring);
 
 	/* update RX_BASE_PTR0 */
-	RT_WRITE(sc, PDMA_BASE + RX_BASE_PTR0,
+	RT_WRITE(sc, sc->rx_base_ptr,
 		sc->rx_ring.desc_phys_addr);
-	RT_WRITE(sc, PDMA_BASE + RX_MAX_CNT0,
+	RT_WRITE(sc, sc->rx_max_cnt,
 		RT_SOFTC_RX_RING_DATA_COUNT);
-	RT_WRITE(sc, PDMA_BASE + RX_CALC_IDX0,
+	RT_WRITE(sc, sc->rx_calc_idx,
 		RT_SOFTC_RX_RING_DATA_COUNT - 1);
 
 	/* write back DDONE, 16byte burst enable RX/TX DMA */
-	RT_WRITE(sc, PDMA_BASE + PDMA_GLO_CFG,
+	RT_WRITE(sc, sc->pdma_glo_cfg,
 	    FE_TX_WB_DDONE | FE_DMA_BT_SIZE16 | FE_RX_DMA_EN | FE_TX_DMA_EN);
 
 	/* disable interrupts mitigation */
-	RT_WRITE(sc, PDMA_BASE + DELAY_INT_CFG, 0);
+	RT_WRITE(sc, sc->delay_int_cfg, 0);
 
 	/* clear pending interrupts */
-	RT_WRITE(sc, GE_PORT_BASE + FE_INT_STATUS, 0xffffffff);
+	RT_WRITE(sc, sc->fe_int_status, 0xffffffff);
 
 	/* enable interrupts */
-	tmp = 	CNT_PPE_AF |
-		CNT_GDM_AF |
-		PSE_P2_FC |
-		GDM_CRC_DROP |
-		PSE_BUF_DROP |
-		GDM_OTHER_DROP |
-		PSE_P1_FC |
-		PSE_P0_FC |
-		PSE_FQ_EMPTY |
-		INT_TX_COHERENT |
-		INT_RX_COHERENT |
-		INT_TXQ3_DONE |
-		INT_TXQ2_DONE |
-		INT_TXQ1_DONE |
-		INT_TXQ0_DONE |
-		INT_RX_DONE;
+	if (rt305x_chip_id == 0x5350) {
+		tmp = RT5350_INT_TX_COHERENT |
+		    RT5350_INT_RX_COHERENT |
+		    RT5350_INT_TXQ3_DONE |
+		    RT5350_INT_TXQ2_DONE |
+		    RT5350_INT_TXQ1_DONE |
+		    RT5350_INT_TXQ0_DONE |
+		    RT5350_INT_RX_DONE;
+        } else {
+		tmp = CNT_PPE_AF |
+		    CNT_GDM_AF |
+		    PSE_P2_FC |
+		    GDM_CRC_DROP |
+		    PSE_BUF_DROP |
+		    GDM_OTHER_DROP |
+		    PSE_P1_FC |
+		    PSE_P0_FC |
+		    PSE_FQ_EMPTY |
+		    INT_TX_COHERENT |
+		    INT_RX_COHERENT |
+		    INT_TXQ3_DONE |
+		    INT_TXQ2_DONE |
+		    INT_TXQ1_DONE |
+		    INT_TXQ0_DONE |
+		    INT_RX_DONE;
+	}
 
 	sc->intr_enable_mask = tmp;
 
-	RT_WRITE(sc, GE_PORT_BASE + FE_INT_ENABLE, tmp);
+	RT_WRITE(sc, sc->fe_int_enable, tmp);
 
 	if (rt_txrx_enable(sc) != 0)
 		goto fail;
@@ -828,7 +881,10 @@
 	RT_SOFTC_LOCK(sc);
 
 	/* disable interrupts */
-	RT_WRITE(sc, GE_PORT_BASE + FE_INT_ENABLE, 0);
+	RT_WRITE(sc, sc->fe_int_enable, 0);
+
+	if(rt305x_chip_id == 0x5350)
+		return;
 
 	/* reset adapter */
 	RT_WRITE(sc, GE_PORT_BASE + FE_RST_GLO, PSE_RESET);
@@ -990,7 +1046,7 @@
 	ring->data_cur = (ring->data_cur + 1) % RT_SOFTC_TX_RING_DATA_COUNT;
 
 	/* kick Tx */
-	RT_WRITE(sc, PDMA_BASE + TX_CTX_IDX(qid), ring->desc_cur);
+	RT_WRITE(sc, sc->tx_ctx_idx[qid], ring->desc_cur);
 
 	return (0);
 }
@@ -1276,8 +1332,8 @@
 	ifp = sc->ifp;
 
 	/* acknowledge interrupts */
-	status = RT_READ(sc, GE_PORT_BASE + FE_INT_STATUS);
-	RT_WRITE(sc, GE_PORT_BASE + FE_INT_STATUS, status);
+	status = RT_READ(sc, sc->fe_int_status);
+	RT_WRITE(sc, sc->fe_int_status, status);
 
 	RT_DPRINTF(sc, RT_DEBUG_INTR, "interrupt: status=0x%08x\n", status);
 
@@ -1345,6 +1401,62 @@
 		rt_tx_intr(sc, 0);
 }
 
+/*
+ * rt_rt5350_intr - main ISR for Ralink 5350 SoC
+ */
+static void
+rt_rt5350_intr(void *arg)
+{
+	struct rt_softc *sc;
+	struct ifnet *ifp;
+	uint32_t status;
+
+	sc = arg;
+	ifp = sc->ifp;
+
+	/* acknowledge interrupts */
+	status = RT_READ(sc, sc->fe_int_status);
+	RT_WRITE(sc, sc->fe_int_status, status);
+
+	RT_DPRINTF(sc, RT_DEBUG_INTR, "interrupt: status=0x%08x\n", status);
+
+	if (status == 0xffffffff ||	/* device likely went away */
+		status == 0)		/* not for us */
+		return;
+
+	sc->interrupts++;
+
+	if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
+		return;
+
+	if (status & RT5350_INT_TX_COHERENT)
+		rt_tx_coherent_intr(sc);
+
+	if (status & RT5350_INT_RX_COHERENT)
+		rt_rx_coherent_intr(sc);
+
+	if (status & RT5350_RX_DLY_INT)
+		rt_rx_delay_intr(sc);
+
+	if (status & RT5350_TX_DLY_INT)
+		rt_tx_delay_intr(sc);
+
+	if (status & RT5350_INT_RX_DONE)
+		rt_rx_intr(sc);
+
+	if (status & RT5350_INT_TXQ3_DONE)
+		rt_tx_intr(sc, 3);
+
+	if (status & RT5350_INT_TXQ2_DONE)
+		rt_tx_intr(sc, 2);
+
+	if (status & RT5350_INT_TXQ1_DONE)
+		rt_tx_intr(sc, 1);
+
+	if (status & RT5350_INT_TXQ0_DONE)
+		rt_tx_intr(sc, 0);
+}
+
 static void
 rt_tx_coherent_intr(struct rt_softc *sc)
 {
@@ -1356,19 +1468,19 @@
 	sc->tx_coherent_interrupts++;
 
 	/* restart DMA engine */
-	tmp = RT_READ(sc, PDMA_BASE + PDMA_GLO_CFG);
+	tmp = RT_READ(sc, sc->pdma_glo_cfg);
 	tmp &= ~(FE_TX_WB_DDONE | FE_TX_DMA_EN);
-	RT_WRITE(sc, PDMA_BASE + PDMA_GLO_CFG, tmp);
+	RT_WRITE(sc, sc->pdma_glo_cfg, tmp);
 
 	for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++)
 		rt_reset_tx_ring(sc, &sc->tx_ring[i]);
 
 	for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
-		RT_WRITE(sc, PDMA_BASE + TX_BASE_PTR(i),
+		RT_WRITE(sc, sc->tx_base_ptr[i],
 			sc->tx_ring[i].desc_phys_addr);
-		RT_WRITE(sc, PDMA_BASE + TX_MAX_CNT(i),
+		RT_WRITE(sc, sc->tx_max_cnt[i],
 			RT_SOFTC_TX_RING_DESC_COUNT);
-		RT_WRITE(sc, PDMA_BASE + TX_CTX_IDX(i), 0);
+		RT_WRITE(sc, sc->tx_ctx_idx[i], 0);
 	}
 
 	rt_txrx_enable(sc);
@@ -1387,17 +1499,17 @@
 	sc->rx_coherent_interrupts++;
 
 	/* restart DMA engine */
-	tmp = RT_READ(sc, PDMA_BASE + PDMA_GLO_CFG);
+	tmp = RT_READ(sc, sc->pdma_glo_cfg);
 	tmp &= ~(FE_RX_DMA_EN);
-	RT_WRITE(sc, PDMA_BASE + PDMA_GLO_CFG, tmp);
+	RT_WRITE(sc, sc->pdma_glo_cfg, tmp);
 
 	/* init Rx ring */
 	rt_reset_rx_ring(sc, &sc->rx_ring);
-	RT_WRITE(sc, PDMA_BASE + RX_BASE_PTR0,
+	RT_WRITE(sc, sc->rx_base_ptr,
 		sc->rx_ring.desc_phys_addr);
-	RT_WRITE(sc, PDMA_BASE + RX_MAX_CNT0,
+	RT_WRITE(sc, sc->rx_max_cnt,
 		RT_SOFTC_RX_RING_DATA_COUNT);
-	RT_WRITE(sc, PDMA_BASE + RX_CALC_IDX0,
+	RT_WRITE(sc, sc->rx_calc_idx,
 		RT_SOFTC_RX_RING_DATA_COUNT - 1);
 
 	rt_txrx_enable(sc);
@@ -1606,7 +1718,7 @@
 	nframes = 0;
 
 	while (limit != 0) {
-		index = RT_READ(sc, PDMA_BASE + RX_DRX_IDX0);
+		index = RT_READ(sc, sc->rx_drx_idx);
 		if (ring->cur == index)
 			break;
 
@@ -1732,10 +1844,10 @@
 	}
 
 	if (ring->cur == 0)
-		RT_WRITE(sc, PDMA_BASE + RX_CALC_IDX0,
+		RT_WRITE(sc, sc->rx_calc_idx,
 			RT_SOFTC_RX_RING_DATA_COUNT - 1);
 	else
-		RT_WRITE(sc, PDMA_BASE + RX_CALC_IDX0,
+		RT_WRITE(sc, sc->rx_calc_idx,
 			ring->cur - 1);
 
 	RT_DPRINTF(sc, RT_DEBUG_RX, "Rx eof: nframes=%d\n", nframes);
@@ -1764,7 +1876,7 @@
 	nframes = 0;
 
 	for (;;) {
-		index = RT_READ(sc, PDMA_BASE + TX_DTX_IDX(ring->qid));
+		index = RT_READ(sc, sc->tx_dtx_idx[ring->qid]);
 		if (ring->desc_next == index)
 			break;
 
@@ -1839,10 +1951,12 @@
 	int ntries;
 #endif
 
-	tmp = RT_READ(sc, PSE_BASE + CDMA_OQ_STA);
-
-	RT_DPRINTF(sc, RT_DEBUG_WATCHDOG, "watchdog: PSE_IQ_STA=0x%08x\n",
-	    tmp);
+	if (rt305x_chip_id != 0x5350) {
+		tmp = RT_READ(sc, PSE_BASE + CDMA_OQ_STA);
+
+		RT_DPRINTF(sc, RT_DEBUG_WATCHDOG, "watchdog: PSE_IQ_STA=0x%08x\n",
+		    tmp);
+	}
 
 	/* XXX: do not reset */
 #ifdef notyet
@@ -1900,7 +2014,7 @@
 
 	sc->intr_disable_mask &= ~intr_mask;
 	tmp = sc->intr_enable_mask & ~sc->intr_disable_mask;
-	RT_WRITE(sc, GE_PORT_BASE + FE_INT_ENABLE, tmp);
+	RT_WRITE(sc, sc->fe_int_enable, tmp);
 }
 
 static void
@@ -1910,7 +2024,7 @@
 
 	sc->intr_disable_mask |= intr_mask;
 	tmp = sc->intr_enable_mask & ~sc->intr_disable_mask;
-	RT_WRITE(sc, GE_PORT_BASE + FE_INT_ENABLE, tmp);
+	RT_WRITE(sc, sc->fe_int_enable, tmp);
 }
 
 /*
@@ -1927,7 +2041,7 @@
 
 	/* enable Tx/Rx DMA engine */
 	for (ntries = 0; ntries < 200; ntries++) {
-		tmp = RT_READ(sc, PDMA_BASE + PDMA_GLO_CFG);
+		tmp = RT_READ(sc, sc->pdma_glo_cfg);
 		if (!(tmp & (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)))
 			break;
 
@@ -1942,7 +2056,7 @@
 	DELAY(50);
 
 	tmp |= FE_TX_WB_DDONE |	FE_RX_DMA_EN | FE_TX_DMA_EN;
-	RT_WRITE(sc, PDMA_BASE + PDMA_GLO_CFG, tmp);
+	RT_WRITE(sc, sc->pdma_glo_cfg, tmp);
 
 	/* XXX set Rx filter */
 	return (0);
diff -r 701b26f9bc86 -r 7aafd0c42486 head/sys/dev/rt/if_rtreg.h
--- a/head/sys/dev/rt/if_rtreg.h	Wed Apr 04 16:52:15 2012 +0300
+++ b/head/sys/dev/rt/if_rtreg.h	Wed Apr 04 16:54:19 2012 +0300
@@ -1,16 +1,17 @@
 /*-
- * Copyright (c) 2009, Aleksandr Rybalko
+ * Copyright (c) 2012, Alexander A. Mityaev <sansan at adm.ua>
+ * Copyright (c) 2009-2012, Aleksandr Rybalko <ray at ddteam.net>
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
- *    notice unmodified, this list of conditions, and the following
- *    disclaimer.
+ *	notice unmodified, this list of conditions, and the following
+ *	disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
+ *	notice, this list of conditions and the following disclaimer in the
+ *	documentation and/or other materials provided with the distribution.
  *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
@@ -30,116 +31,134 @@
 #ifndef _IF_RTREG_H_
 #define	_IF_RTREG_H_
 
-#define	RT_READ(sc, reg)				\
+#define	RT_READ(sc, reg)						\
 	bus_space_read_4((sc)->bst, (sc)->bsh, reg)
 
-#define	RT_WRITE(sc, reg, val)				\
+#define	RT_WRITE(sc, reg, val)						\
 	bus_space_write_4((sc)->bst, (sc)->bsh, reg, val)
 
-#define	GE_PORT_BASE 0x0000
+#define	GE_PORT_BASE		0x0000
+#define	GDMA1_BASE		0x0020
+#define	GDMA2_BASE		0x0060
+#define	CDMA_BASE		0x0080
+#define	PSE_BASE		0x0040
+#define	PDMA_BASE		0x0100
+#define	RT5350_PDMA_BASE	0x0800
+#define	PPE_BASE		0x0200
+#define	CNTR_BASE		0x0400
+#define	POLICYTABLE_BASE	0x1000
 
 #define	MDIO_ACCESS	0x00
-#define	    MDIO_CMD_ONGO	(1<<31)
-#define	    MDIO_CMD_WR		(1<<30)
-#define	    MDIO_PHY_ADDR_MASK	0x1f000000
-#define	    MDIO_PHY_ADDR_SHIFT	24
-#define	    MDIO_PHYREG_ADDR_MASK 0x001f0000
-#define	    MDIO_PHYREG_ADDR_SHIFT 16
-#define	    MDIO_PHY_DATA_MASK	0x0000ffff
-#define	    MDIO_PHY_DATA_SHIFT	0
+#define		MDIO_CMD_ONGO		(1<<31)
+#define		MDIO_CMD_WR		(1<<30)
+#define		MDIO_PHY_ADDR_MASK	0x1f000000
+#define		MDIO_PHY_ADDR_SHIFT	24
+#define		MDIO_PHYREG_ADDR_MASK	0x001f0000
+#define		MDIO_PHYREG_ADDR_SHIFT	16
+#define		MDIO_PHY_DATA_MASK	0x0000ffff
+#define		MDIO_PHY_DATA_SHIFT	0
 
 #define	FE_GLO_CFG	0x08 /*Frame Engine Global Configuration */
-#define	    EXT_VLAN_TYPE_MASK	0xffff0000
-#define	    EXT_VLAN_TYPE_SHIFT	16
-#define	    EXT_VLAN_TYPE_DFLT	0x81000000
-#define	    US_CYC_CNT_MASK	0x0000ff00
-#define	    US_CYC_CNT_SHIFT	8
-#define	    US_CYC_CNT_DFLT	(132<<8) /* sys clocks per 1uS */
-#define	    L2_SPACE		(8<<4) /* L2 space. Unit is 8 bytes */
+#define	EXT_VLAN_TYPE_MASK	0xffff0000
+#define	EXT_VLAN_TYPE_SHIFT	16
+#define	EXT_VLAN_TYPE_DFLT	0x81000000
+#define	US_CYC_CNT_MASK		0x0000ff00
+#define	US_CYC_CNT_SHIFT	8
+#define	US_CYC_CNT_DFLT		(132<<8) /* sys clocks per 1uS */
+#define	L2_SPACE		(8<<4) /* L2 space. Unit is 8 bytes */
 
 #define	FE_RST_GLO	0x0C /*Frame Engine Global Reset*/
-#define	    FC_DROP_CNT_MASK	0xffff0000 /*Flow cntrl drop count */
-#define	    FC_DROP_CNT_SHIFT	16
-#define	    PSE_RESET		(1<<0)
+#define	FC_DROP_CNT_MASK	0xffff0000 /*Flow cntrl drop count */
+#define	FC_DROP_CNT_SHIFT	16
+#define	PSE_RESET		(1<<0)
 
 #define	FE_INT_STATUS	0x10
-#define	    CNT_PPE_AF		(1<<31)
-#define	    CNT_GDM_AF		(1<<29)
-#define	    PSE_P2_FC		(1<<26)
-#define	    GDM_CRC_DROP	(1<<25)
-#define	    PSE_BUF_DROP	(1<<24)
-#define	    GDM_OTHER_DROP	(1<<23)
-#define	    PSE_P1_FC		(1<<22)
-#define	    PSE_P0_FC		(1<<21)
-#define	    PSE_FQ_EMPTY	(1<<20)
-#define	    INT_TX_COHERENT	(1<<17)
-#define	    INT_RX_COHERENT	(1<<16)
-#define	    INT_TXQ3_DONE	(1<<11)
-#define	    INT_TXQ2_DONE	(1<<10)
-#define	    INT_TXQ1_DONE	(1<<9)
-#define	    INT_TXQ0_DONE	(1<<8)
-#define	    INT_RX_DONE		(1<<2)
-#define	    TX_DLY_INT		(1<<1) /* TXQ[0|1]_DONE with delay */
-#define	    RX_DLY_INT		(1<<0) /* RX_DONE with delay */
 #define	FE_INT_ENABLE	0x14
+#define		CNT_PPE_AF	(1<<31)
+#define		CNT_GDM_AF	(1<<29)
+#define		PSE_P2_FC	(1<<26)
+#define		GDM_CRC_DROP	(1<<25)
+#define		PSE_BUF_DROP	(1<<24)
+#define		GDM_OTHER_DROP	(1<<23)
+#define		PSE_P1_FC	(1<<22)
+#define		PSE_P0_FC	(1<<21)
+#define		PSE_FQ_EMPTY	(1<<20)
+#define		INT_TX_COHERENT	(1<<17)
+#define		INT_RX_COHERENT	(1<<16)
+#define		INT_TXQ3_DONE	(1<<11)
+#define		INT_TXQ2_DONE	(1<<10)
+#define		INT_TXQ1_DONE	(1<<9)
+#define		INT_TXQ0_DONE	(1<<8)
+#define		INT_RX_DONE	(1<<2)
+#define		TX_DLY_INT	(1<<1) /* TXQ[0|1]_DONE with delay */
+#define		RX_DLY_INT	(1<<0) /* RX_DONE with delay */
+#define	RT5350_FE_INT_STATUS	(RT5350_PDMA_BASE + 0x220)
+#define	RT5350_FE_INT_ENABLE	(RT5350_PDMA_BASE + 0x228)
+#define		RT5350_INT_RX_COHERENT	(1<<31)
+#define		RT5350_RX_DLY_INT	(1<<30)
+#define		RT5350_INT_TX_COHERENT	(1<<29)
+#define		RT5350_TX_DLY_INT	(1<<28)
+#define		RT5350_INT_RX_DONE1	(1<<17)
+#define		RT5350_INT_RX_DONE	(1<<16)
+#define		RT5350_INT_TXQ3_DONE	(1<<3)
+#define		RT5350_INT_TXQ2_DONE	(1<<2)
+#define		RT5350_INT_TXQ1_DONE	(1<<1)
+#define		RT5350_INT_TXQ0_DONE	(1<<0)
+
 #define	MDIO_CFG2	0x18
 #define	FOE_TS_T	0x1c
-#define	    PSE_FQ_PCNT_MASK	0xff000000
-#define	    PSE_FQ_PCNT_SHIFT	24
-#define	    FOE_TS_TIMESTAMP_MASK 0x0000ffff
-#define	    FOE_TS_TIMESTAMP_SHIFT 0
-
-#define	GDMA1_BASE 0x0020
-#define	GDMA2_BASE 0x0060
-#define	CDMA_BASE  0x0080
+#define		PSE_FQ_PCNT_MASK	0xff000000
+#define		PSE_FQ_PCNT_SHIFT	24
+#define		FOE_TS_TIMESTAMP_MASK	0x0000ffff
+#define		FOE_TS_TIMESTAMP_SHIFT	0
 
 #define	GDMA_FWD_CFG	0x00	/* Only GDMA */
-#define	    GDM_DROP_256B	(1<<23)
-#define	    GDM_ICS_EN		(1<<22)
-#define	    GDM_TCS_EN		(1<<21)
-#define	    GDM_UCS_EN		(1<<20)
-#define	    GDM_DISPAD		(1<<18)
-#define	    GDM_DISCRC		(1<<17)
-#define	    GDM_STRPCRC		(1<<16)
-#define	    GDM_UFRC_P_SHIFT	12
-#define	    GDM_BFRC_P_SHIFT	8
-#define	    GDM_MFRC_P_SHIFT	4
-#define	    GDM_OFRC_P_SHIFT	0
-#define	    GDM_XFRC_P_MASK	0x07
-#define	    GDM_DST_PORT_CPU	0
-#define	    GDM_DST_PORT_GDMA1	1
-#define	    GDM_DST_PORT_GDMA2	2
-#define	    GDM_DST_PORT_PPE	6
-#define	    GDM_DST_PORT_DISCARD 7
+#define		GDM_DROP_256B		(1<<23)
+#define		GDM_ICS_EN		(1<<22)
+#define		GDM_TCS_EN		(1<<21)
+#define		GDM_UCS_EN		(1<<20)
+#define		GDM_DISPAD		(1<<18)
+#define		GDM_DISCRC		(1<<17)
+#define		GDM_STRPCRC		(1<<16)
+#define		GDM_UFRC_P_SHIFT	12
+#define		GDM_BFRC_P_SHIFT	8
+#define		GDM_MFRC_P_SHIFT	4
+#define		GDM_OFRC_P_SHIFT	0
+#define		GDM_XFRC_P_MASK		0x07
+#define		GDM_DST_PORT_CPU	0
+#define		GDM_DST_PORT_GDMA1	1
+#define		GDM_DST_PORT_GDMA2	2
+#define		GDM_DST_PORT_PPE	6
+#define		GDM_DST_PORT_DISCARD	7
 
 #define	CDMA_CSG_CFG	0x00	/* Only CDMA */
-#define	    INS_VLAN_TAG	(0x8100<<16)
-#define	    ICS_GEN_EN		(1<<2)
-#define	    TCS_GEN_EN		(1<<1)
-#define	    UCS_GEN_EN		(1<<0)
+#define		INS_VLAN_TAG	(0x8100<<16)
+#define		ICS_GEN_EN	(1<<2)
+#define		TCS_GEN_EN	(1<<1)
+#define		UCS_GEN_EN	(1<<0)
 
 #define	GDMA_SCH_CFG	0x04
-#define	    GDM1_SCH_MOD_MASK	0x03000000
-#define	    GDM1_SCH_MOD_SHIFT	24
-#define	    GDM1_SCH_MOD_WRR	0
-#define	    GDM1_SCH_MOD_STRICT	1
-#define	    GDM1_SCH_MOD_MIXED	2
-#define	    GDM1_WT_1		0
-#define	    GDM1_WT_2		1
-#define	    GDM1_WT_4		2
-#define	    GDM1_WT_8		3
-#define	    GDM1_WT_16		4
-#define	    GDM1_WT_Q3_SHIFT	12
-#define	    GDM1_WT_Q2_SHIFT	8
-#define	    GDM1_WT_Q1_SHIFT	4
-#define	    GDM1_WT_Q0_SHIFT	0
+#define		GDM1_SCH_MOD_MASK	0x03000000
+#define		GDM1_SCH_MOD_SHIFT	24
+#define		GDM1_SCH_MOD_WRR	0
+#define		GDM1_SCH_MOD_STRICT	1
+#define		GDM1_SCH_MOD_MIXED	2
+#define		GDM1_WT_1		0
+#define		GDM1_WT_2		1
+#define		GDM1_WT_4		2
+#define		GDM1_WT_8		3
+#define		GDM1_WT_16		4
+#define		GDM1_WT_Q3_SHIFT	12
+#define		GDM1_WT_Q2_SHIFT	8
+#define		GDM1_WT_Q1_SHIFT	4
+#define		GDM1_WT_Q0_SHIFT	0
 
 #define	GDMA_SHPR_CFG	0x08
-#define	    GDM1_SHPR_EN	(1<<24)
-#define	    GDM1_BK_SIZE_MASK	0x00ff0000 /* Bucket size 1kB units */
-#define	    GDM1_BK_SIZE_SHIFT	16
-#define	    GDM1_TK_RATE_MASK	0x00003fff /* Shaper token rate 8B/ms units */
-#define	    GDM1_TK_RATE_SHIFT	0
+#define	GDM1_SHPR_EN	(1<<24)
+#define		GDM1_BK_SIZE_MASK	0x00ff0000 /* Bucket size 1kB units */
+#define		GDM1_BK_SIZE_SHIFT	16
+#define		GDM1_TK_RATE_MASK	0x00003fff /* Shaper token rate 8B/ms units */
+#define		GDM1_TK_RATE_SHIFT	0
 
 #define	GDMA_MAC_ADRL	 0x0C
 #define	GDMA_MAC_ADRH	 0x10
@@ -161,111 +180,146 @@
 #define	VLAN_ID_1213		0x40
 #define	VLAN_ID_1415		0x44
 
-#define	PSE_BASE	    0x0040
-#define	PSE_FQFC_CFG        0x00
-#define	    FQ_MAX_PCNT_MASK	0xff000000
-#define	    FQ_MAX_PCNT_SHIFT	24
-#define	    FQ_FC_RLS_MASK	0x00ff0000
-#define	    FQ_FC_RLS_SHIFT	16
-#define	    FQ_FC_ASRT_MASK	0x0000ff00
-#define	    FQ_FC_ASRT_SHIFT	8
-#define	    FQ_FC_DROP_MASK	0x000000ff
-#define	    FQ_FC_DROP_SHIFT	0
+#define	PSE_FQFC_CFG	0x00
+#define		FQ_MAX_PCNT_MASK	0xff000000
+#define		FQ_MAX_PCNT_SHIFT	24
+#define		FQ_FC_RLS_MASK		0x00ff0000
+#define		FQ_FC_RLS_SHIFT		16
+#define		FQ_FC_ASRT_MASK		0x0000ff00
+#define		FQ_FC_ASRT_SHIFT	8
+#define		FQ_FC_DROP_MASK		0x000000ff
+#define		FQ_FC_DROP_SHIFT	0
 
-#define	CDMA_FC_CFG         0x04
-#define	GDMA1_FC_CFG        0x08
-#define	GDMA2_FC_CFG        0x0C
-#define	    P_SHARING		(1<<28)
-#define	    P_HQ_DEF_MASK	0x0f000000
-#define	    P_HQ_DEF_SHIFT	24
-#define	    P_HQ_RESV_MASK	0x00ff0000
-#define	    P_HQ_RESV_SHIFT	16
-#define	    P_LQ_RESV_MASK	0x0000ff00
-#define	    P_LQ_RESV_SHIFT	8
-#define	    P_IQ_ASRT_MASK	0x000000ff
-#define	    P_IQ_ASRT_SHIFT	0
+#define	CDMA_FC_CFG	0x04
+#define	GDMA1_FC_CFG	0x08
+#define	GDMA2_FC_CFG	0x0C
+#define		P_SHARING		(1<<28)
+#define		P_HQ_DEF_MASK		0x0f000000
+#define		P_HQ_DEF_SHIFT		24
+#define		P_HQ_RESV_MASK		0x00ff0000
+#define		P_HQ_RESV_SHIFT		16
+#define		P_LQ_RESV_MASK		0x0000ff00
+#define		P_LQ_RESV_SHIFT		8
+#define		P_IQ_ASRT_MASK		0x000000ff
+#define		P_IQ_ASRT_SHIFT		0
 
-#define	CDMA_OQ_STA         0x10
-#define	GDMA1_OQ_STA        0x14
-#define	GDMA2_OQ_STA        0x18
-#define	    P_OQ3_PCNT_MASK	0xff000000
-#define	    P_OQ3_PCNT_SHIFT	24
-#define	    P_OQ2_PCNT_MASK	0x00ff0000
-#define	    P_OQ2_PCNT_SHIFT	16
-#define	    P_OQ1_PCNT_MASK	0x0000ff00
-#define	    P_OQ1_PCNT_SHIFT	8
-#define	    P_OQ0_PCNT_MASK	0x000000ff
-#define	    P_OQ0_PCNT_SHIFT	0
+#define	CDMA_OQ_STA	0x10
+#define	GDMA1_OQ_STA	0x14
+#define	GDMA2_OQ_STA	0x18
+#define		P_OQ3_PCNT_MASK		0xff000000
+#define		P_OQ3_PCNT_SHIFT	24
+#define		P_OQ2_PCNT_MASK		0x00ff0000
+#define		P_OQ2_PCNT_SHIFT	16
+#define		P_OQ1_PCNT_MASK		0x0000ff00
+#define		P_OQ1_PCNT_SHIFT	8
+#define		P_OQ0_PCNT_MASK		0x000000ff
+#define		P_OQ0_PCNT_SHIFT	0
 
-#define	PSE_IQ_STA          0x1C
-#define	    P6_OQ0_PCNT_MASK	0xff000000
-#define	    P6_OQ0_PCNT_SHIFT	24
-#define	    P2_IQ_PCNT_MASK	0x00ff0000
-#define	    P2_IQ_PCNT_SHIFT	16
-#define	    P1_IQ_PCNT_MASK	0x0000ff00
-#define	    P1_IQ_PCNT_SHIFT	8
-#define	    P0_IQ_PCNT_MASK	0x000000ff
-#define	    P0_IQ_PCNT_SHIFT	0
+#define	PSE_IQ_STA	0x1C
+#define		P6_OQ0_PCNT_MASK	0xff000000
+#define		P6_OQ0_PCNT_SHIFT	24
+#define		P2_IQ_PCNT_MASK		0x00ff0000
+#define		P2_IQ_PCNT_SHIFT	16
+#define		P1_IQ_PCNT_MASK		0x0000ff00
+#define		P1_IQ_PCNT_SHIFT	8
+#define		P0_IQ_PCNT_MASK		0x000000ff
+#define		P0_IQ_PCNT_SHIFT	0
 
-#define	PDMA_BASE 0x0100
-#define	PDMA_GLO_CFG	    0x00
-#define	    FE_TX_WB_DDONE	(1<<6)
-#define	    FE_DMA_BT_SIZE4	(0<<4)
-#define	    FE_DMA_BT_SIZE8	(1<<4)
-#define	    FE_DMA_BT_SIZE16	(2<<4)
-#define	    FE_RX_DMA_BUSY	(1<<3)
-#define	    FE_RX_DMA_EN	(1<<2)
-#define	    FE_TX_DMA_BUSY	(1<<1)
-#define	    FE_TX_DMA_EN	(1<<0)
-#define	PDMA_RST_IDX        0x04
-#define	    FE_RST_DRX_IDX0	(1<<16)
-#define	    FE_RST_DTX_IDX3	(1<<3)
-#define	    FE_RST_DTX_IDX2	(1<<2)
-#define	    FE_RST_DTX_IDX1	(1<<1)
-#define	    FE_RST_DTX_IDX0	(1<<0)
+#define	PDMA_GLO_CFG	0x00
+#define	RT5350_PDMA_GLO_CFG 0x204
+#define		FE_TX_WB_DDONE		(1<<6)
+#define		FE_DMA_BT_SIZE4		(0<<4)
+#define		FE_DMA_BT_SIZE8		(1<<4)
+#define		FE_DMA_BT_SIZE16	(2<<4)
+#define		FE_RX_DMA_BUSY		(1<<3)
+#define		FE_RX_DMA_EN		(1<<2)
+#define		FE_TX_DMA_BUSY		(1<<1)
+#define		FE_TX_DMA_EN		(1<<0)
 
-#define	PDMA_SCH_CFG        0x08
-#define	DELAY_INT_CFG       0x0C
-#define	    TXDLY_INT_EN 	(1<<31)
-#define	    TXMAX_PINT_SHIFT	24
-#define	    TXMAX_PTIME_SHIFT	16
-#define	    RXDLY_INT_EN	(1<<15)
-#define	    RXMAX_PINT_SHIFT	8
-#define	    RXMAX_PTIME_SHIFT	0
+#define	PDMA_RST_IDX	0x04
+#define	RT5350_PDMA_RST_IDX 0x208
+#define		FE_RST_DRX_IDX0		(1<<16)
+#define		FE_RST_DTX_IDX3		(1<<3)
+#define		FE_RST_DTX_IDX2		(1<<2)
+#define		FE_RST_DTX_IDX1		(1<<1)
+#define		FE_RST_DTX_IDX0		(1<<0)
 
-#define	TX_BASE_PTR0        0x10
-#define	TX_MAX_CNT0         0x14
-#define	TX_CTX_IDX0         0x18
-#define	TX_DTX_IDX0         0x1C
+#define	PDMA_SCH_CFG		0x08
+#define	RT5350_PDMA_SCH_CFG	0x280
+#define	DELAY_INT_CFG		0x0C
+#define	RT5350_DELAY_INT_CFG	0x20C
+#define		TXDLY_INT_EN 		(1<<31)
+#define		TXMAX_PINT_SHIFT	24
+#define		TXMAX_PTIME_SHIFT	16
+#define		RXDLY_INT_EN		(1<<15)
+#define		RXMAX_PINT_SHIFT	8
+#define		RXMAX_PTIME_SHIFT	0
 
-#define	TX_BASE_PTR1        0x20
-#define	TX_MAX_CNT1         0x24
-#define	TX_CTX_IDX1         0x28
-#define	TX_DTX_IDX1         0x2C
+#define	TX_BASE_PTR0	0x10
+#define	TX_MAX_CNT0	0x14
+#define	TX_CTX_IDX0	0x18
+#define	TX_DTX_IDX0	0x1C
 
-#define	RX_BASE_PTR0        0x30
-#define	RX_MAX_CNT0         0x34
-#define	RX_CALC_IDX0        0x38
-#define	RX_DRX_IDX0         0x3C
+#define	TX_BASE_PTR1	0x20
+#define	TX_MAX_CNT1	0x24
+#define	TX_CTX_IDX1	0x28
+#define	TX_DTX_IDX1	0x2C
 
-#define	TX_BASE_PTR2        0x40
-#define	TX_MAX_CNT2         0x44
-#define	TX_CTX_IDX2         0x48
-#define	TX_DTX_IDX2         0x4C
+#define	RX_BASE_PTR0	0x30
+#define	RX_MAX_CNT0	0x34
+#define	RX_CALC_IDX0	0x38
+#define	RX_DRX_IDX0	0x3C
 
-#define	TX_BASE_PTR3        0x50
-#define	TX_MAX_CNT3         0x54
-#define	TX_CTX_IDX3         0x58
-#define	TX_DTX_IDX3         0x5C
+#define	TX_BASE_PTR2	0x40
+#define	TX_MAX_CNT2	0x44
+#define	TX_CTX_IDX2	0x48
+#define	TX_DTX_IDX2	0x4C
 
-#define	TX_BASE_PTR(qid)		(((qid>1)?(0x20):(0x10)) + (qid) * 16)
-#define	TX_MAX_CNT(qid)			(((qid>1)?(0x24):(0x14)) + (qid) * 16)
-#define	TX_CTX_IDX(qid)			(((qid>1)?(0x28):(0x18)) + (qid) * 16)
-#define	TX_DTX_IDX(qid)			(((qid>1)?(0x2c):(0x1c)) + (qid) * 16)
+#define	TX_BASE_PTR3	0x50
+#define	TX_MAX_CNT3	0x54
+#define	TX_CTX_IDX3	0x58
+#define	TX_DTX_IDX3	0x5C
 
-#define	PPE_BASE 0x0200
+#define	TX_BASE_PTR(qid)	(((qid > 1) ? (0x20) : (0x10)) + (qid) * 16)
+#define	TX_MAX_CNT(qid)		(((qid > 1) ? (0x24) : (0x14)) + (qid) * 16)
+#define	TX_CTX_IDX(qid)		(((qid > 1) ? (0x28) : (0x18)) + (qid) * 16)
+#define	TX_DTX_IDX(qid)		(((qid > 1) ? (0x2c) : (0x1c)) + (qid) * 16)
 
-#define	CNTR_BASE 0x0400
+#define	RT5350_TX_BASE_PTR0        0x000
+#define	RT5350_TX_MAX_CNT0         0x004
+#define	RT5350_TX_CTX_IDX0         0x008
+#define	RT5350_TX_DTX_IDX0         0x00C
+
+#define	RT5350_TX_BASE_PTR1        0x010
+#define	RT5350_TX_MAX_CNT1         0x014
+#define	RT5350_TX_CTX_IDX1         0x018
+#define	RT5350_TX_DTX_IDX1         0x01C
+
+#define	RT5350_TX_BASE_PTR2        0x020
+#define	RT5350_TX_MAX_CNT2         0x024
+#define	RT5350_TX_CTX_IDX2         0x028
+#define	RT5350_TX_DTX_IDX2         0x02C
+
+#define	RT5350_TX_BASE_PTR3        0x030
+#define	RT5350_TX_MAX_CNT3         0x034
+#define	RT5350_TX_CTX_IDX3         0x038
+#define	RT5350_TX_DTX_IDX3         0x03C
+
+#define	RT5350_RX_BASE_PTR0        0x100
+#define	RT5350_RX_MAX_CNT0         0x104
+#define	RT5350_RX_CALC_IDX0        0x108
+#define	RT5350_RX_DRX_IDX0         0x10C
+
+#define	RT5350_RX_BASE_PTR1        0x110
+#define	RT5350_RX_MAX_CNT1         0x114
+#define	RT5350_RX_CALC_IDX1        0x118
+#define	RT5350_RX_DRX_IDX1         0x11C
+
+#define	RT5350_TX_BASE_PTR(qid)		((qid) * 0x10 + 0x000)
+#define	RT5350_TX_MAX_CNT(qid)		((qid) * 0x10 + 0x004)
+#define	RT5350_TX_CTX_IDX(qid)		((qid) * 0x10 + 0x008)
+#define	RT5350_TX_DTX_IDX(qid)		((qid) * 0x10 + 0x00C)
+
 #define	PPE_AC_BCNT0		0x000
 #define	PPE_AC_PCNT0		0x004
 #define	PPE_AC_BCNT63		0x1F8
@@ -284,6 +338,4 @@
 #define	GDMA_RX_LONG_ERCNT0	0x334
 #define	GDMA_RX_CSUM_ERCNT0	0x338
 
-#define	POLICYTABLE_BASE 	0x1000
-
 #endif /* _IF_RTREG_H_ */
diff -r 701b26f9bc86 -r 7aafd0c42486 head/sys/dev/rt/if_rtvar.h
--- a/head/sys/dev/rt/if_rtvar.h	Wed Apr 04 16:52:15 2012 +0300
+++ b/head/sys/dev/rt/if_rtvar.h	Wed Apr 04 16:54:19 2012 +0300
@@ -1,5 +1,6 @@
 /*-
- * Copyright (c) 2010-2011 Aleksandr Rybalko <ray at ddteam.net>
+ * Copyright (c) 2012, Alexander A. Mityaev <sansan at adm.ua>
+ * Copyright (c) 2010-2012, Aleksandr Rybalko <ray at ddteam.net>
  * Copyright (c) 2009-2010 Alexander Egorenkov <egorenar at gmail.com>
  * Copyright (c) 2009 Damien Bergamini <damien.bergamini at free.fr>
  *
@@ -252,6 +253,21 @@
 	unsigned long	 tx_skip;
 	unsigned long	 tx_collision;
 
+	/* H/W depended registers */
+	uint32_t	delay_int_cfg;
+	uint32_t	fe_int_status;
+	uint32_t	fe_int_enable;
+	uint32_t	pdma_glo_cfg;
+	uint32_t	pdma_rst_idx;
+	uint32_t	tx_base_ptr[RT_SOFTC_TX_RING_COUNT];
+	uint32_t	tx_max_cnt[RT_SOFTC_TX_RING_COUNT];
+	uint32_t	tx_ctx_idx[RT_SOFTC_TX_RING_COUNT];
+	uint32_t	tx_dtx_idx[RT_SOFTC_TX_RING_COUNT];
+	uint32_t	rx_base_ptr;
+	uint32_t	rx_max_cnt;
+	uint32_t	rx_calc_idx;
+	uint32_t	rx_drx_idx;
+
 	int		 phy_addr;
 
 #ifdef IF_RT_DEBUG
@@ -272,11 +288,11 @@
 	RT_DEBUG_ANY = 0xffffffff
 };
 
-#define	RT_DPRINTF(sc, m, fmt, ...)		\
-	do { if ((sc)->debug & (m)) 		\
-	    device_printf(sc->dev, fmt, __VA_ARGS__); } while (0)
+#define	RT_DPRINTF(sc, m, ...)						\
+	do { if ((sc)->debug & (m)) 					\
+	    device_printf(sc->dev, __VA_ARGS__); } while (0)
 #else
-#define	RT_DPRINTF(sc, m, fmt, ...)
+#define	RT_DPRINTF(sc, m, ...)
 #endif /* #ifdef IF_RT_DEBUG */
 
 #endif /* #ifndef _IF_RTVAR_H_ */


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