[Zrouter-src-freebsd] ZRouter.org: push to FreeBSD HEAD tree

zrouter-src-freebsd at zrouter.org zrouter-src-freebsd at zrouter.org
Sat Dec 31 19:10:10 UTC 2011


details:   http://zrouter.org/hg/FreeBSD/head//rev/0fb69cff9fee
changeset: 255:0fb69cff9fee
user:      ray at terran.dlink.ua
date:      Sat Dec 31 21:09:18 2011 +0200
description:
Remove tails of phymask ability.
Whitespace cleanup.
Make ring buffer alocation at arge_attach.
XXX: still have style(9) bugs.

diffstat:

 head/sys/mips/atheros/if_arge.c |  345 ++++++++++-----------------------------
 1 files changed, 89 insertions(+), 256 deletions(-)

diffs (750 lines):

diff -r b9a3c2613f46 -r 0fb69cff9fee head/sys/mips/atheros/if_arge.c
--- a/head/sys/mips/atheros/if_arge.c	Sat Dec 31 21:06:22 2011 +0200
+++ b/head/sys/mips/atheros/if_arge.c	Sat Dec 31 21:09:18 2011 +0200
@@ -103,6 +103,7 @@
 
 static int arge_attach(device_t);
 static int arge_detach(device_t);
+static void arge_flush_ddr(struct arge_softc *);
 static int arge_ifmedia_upd(struct ifnet *);
 static void arge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 static int arge_ioctl(struct ifnet *, u_long, caddr_t);
@@ -168,7 +169,7 @@
 DRIVER_MODULE(miibus, arge, miibus_driver, miibus_devclass, 0, 0);
 
 /*
- * RedBoot passes MAC address to entry point as environment 
+ * RedBoot passes MAC address to entry point as environment
  * variable. platfrom_start parses it and stores in this variable
  */
 extern uint32_t ar711_base_mac[ETHER_ADDR_LEN];
@@ -178,7 +179,7 @@
 MTX_SYSINIT(miibus_mtx, &miibus_mtx, "arge mii lock", MTX_DEF);
 
 /*
- * Flushes all 
+ * Flushes all
  */
 static void
 arge_flush_ddr(struct arge_softc *sc)
@@ -187,7 +188,7 @@
 	ar71xx_device_flush_ddr_ge(sc->arge_mac_unit);
 }
 
-static int 
+static int
 arge_probe(device_t dev)
 {
 
@@ -228,10 +229,6 @@
 	SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_cnt",
 	    CTLFLAG_RW, &sc->arge_cdata.arge_tx_cnt, 0, "");
 #endif
-	SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "media",
-	    CTLFLAG_RW, &sc->arge_media_speed, 0, "Force link speed");  /* 0 - not used */
-	SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "duplex",
-	    CTLFLAG_RW, &sc->arge_media_duplex, 1, "Force link duplex");
 }
 
 struct miibus_ivars {
@@ -244,12 +241,12 @@
 static int
 arge_attach(device_t dev)
 {
-	uint8_t			eaddr[ETHER_ADDR_LEN];
+	uint8_t			eaddr[ETHER_ADDR_LEN], mdio_clock_div;
 	struct ifnet		*ifp;
 	struct arge_softc	*sc;
-	int			error = 0, rid, phymask;
+	int			error = 0, rid;
 	uint32_t		reg, rnd;
-	int			is_base_mac_empty, i, phys_total;
+	int			is_base_mac_empty, i;
 	uint32_t		hint;
 	long			eeprom_mac_addr = 0;
 
@@ -267,7 +264,7 @@
 	 * in CPU address space.
 	 */
 	if (sc->arge_mac_unit == 0 &&
-	    resource_long_value(device_get_name(dev), device_get_unit(dev), 
+	    resource_long_value(device_get_name(dev), device_get_unit(dev),
 	    "eeprommac", &eeprom_mac_addr) == 0) {
 		int i;
 		const char *mac = (const char *) MIPS_PHYS_TO_KSEG1(eeprom_mac_addr);
@@ -277,32 +274,14 @@
 		}
 	}
 
-	KASSERT(((sc->arge_mac_unit == 0) || (sc->arge_mac_unit == 1)), 
+	KASSERT(((sc->arge_mac_unit == 0) || (sc->arge_mac_unit == 1)),
 	    ("if_arge: Only MAC0 and MAC1 supported"));
 
 	/*
-	 *  Get which PHY of 5 available we should use for this unit
-	 */
-	if (resource_int_value(device_get_name(dev), device_get_unit(dev), 
-	    "phymask", &phymask) != 0) {
-		/*
-		 * Use port 4 (WAN) for GE0. For any other port use 
-		 * its PHY the same as its unit number 
-		 */
-		if (sc->arge_mac_unit == 0)
-			phymask = (1 << 4);
-		else
-			/* Use all phys up to 4 */
-			phymask = (1 << 4) - 1;
-
-		device_printf(dev, "No PHY specified, using mask %d\n", phymask);
-	}
-
-	/*
-	 *  Get default media & duplex mode, by default its Base100T 
+	 *  Get default media & duplex mode, by default its Base100T
 	 *  and full duplex
 	 */
-	if (resource_int_value(device_get_name(dev), device_get_unit(dev), 
+	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
 	    "media", &hint) != 0)
 		hint = 0;
 
@@ -311,7 +290,7 @@
 	else
 		sc->arge_media_type = IFM_100_TX;
 
-	if (resource_int_value(device_get_name(dev), device_get_unit(dev), 
+	if (resource_int_value(device_get_name(dev), device_get_unit(dev),
 	    "fduplex", &hint) != 0)
 		hint = 1;
 
@@ -320,8 +299,6 @@
 	else
 		sc->arge_duplex_mode = 0;
 
-	sc->arge_phymask = phymask;
-
 	mtx_init(&sc->arge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
 	    MTX_DEF);
 	callout_init_mtx(&sc->arge_stat_callout, &sc->arge_mtx, 0);
@@ -329,7 +306,7 @@
 
 	/* Map control/status registers. */
 	sc->arge_rid = 0;
-	sc->arge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 
+	sc->arge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 	    &sc->arge_rid, RF_ACTIVE);
 
 	if (sc->arge_res == NULL) {
@@ -340,7 +317,7 @@
 
 	/* Allocate interrupts */
 	rid = 0;
-	sc->arge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 
+	sc->arge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 	    RF_SHAREABLE | RF_ACTIVE);
 
 	if (sc->arge_irq == NULL) {
@@ -388,7 +365,7 @@
 		 * No MAC address configured. Generate the random one.
 		 */
 		if  (bootverbose)
-			device_printf(dev, 
+			device_printf(dev,
 			    "Generating random ethernet address.\n");
 
 		rnd = arc4random();
@@ -409,22 +386,22 @@
 	}
 
 	/* Initialize the MAC block */
-	
+
 	/* Step 1. Soft-reset MAC */
 	ARGE_SET_BITS(sc, AR71XX_MAC_CFG1, MAC_CFG1_SOFT_RESET);
 	DELAY(20);
 
 	/* Step 2. Punt the MAC core from the central reset register */
-	ar71xx_device_stop(sc->arge_mac_unit == 0 ? 
-	    (RST_RESET_GE0_MAC|RST_RESET_GE0_PHY|RST_RESET_GE1_MDIO) : 
+	ar71xx_device_stop(sc->arge_mac_unit == 0 ?
+	    (RST_RESET_GE0_MAC|RST_RESET_GE0_PHY|RST_RESET_GE1_MDIO) :
 	    (RST_RESET_GE1_MAC|RST_RESET_GE1_PHY|RST_RESET_GE1_MDIO));
 	DELAY(100);
 	ar71xx_device_start(sc->arge_mac_unit == 0 ?
-	    (RST_RESET_GE0_MAC|RST_RESET_GE0_PHY|RST_RESET_GE1_MDIO) : 
+	    (RST_RESET_GE0_MAC|RST_RESET_GE0_PHY|RST_RESET_GE1_MDIO) :
 	    (RST_RESET_GE1_MAC|RST_RESET_GE1_PHY|RST_RESET_GE1_MDIO));
 
 	/* Step 3. Reconfigure MAC block */
-	ARGE_WRITE(sc, AR71XX_MAC_CFG1, 
+	ARGE_WRITE(sc, AR71XX_MAC_CFG1,
 		MAC_CFG1_SYNC_RX | MAC_CFG1_RX_ENABLE |
 		MAC_CFG1_SYNC_TX | MAC_CFG1_TX_ENABLE);
 
@@ -434,31 +411,34 @@
 
 	ARGE_WRITE(sc, AR71XX_MAC_MAX_FRAME_LEN, 1536);
 
-#ifdef NO_AR7242
 	/* Reset MII bus */
-	ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_RESET);
+	switch (ar71xx_soc) {
+	case AR71XX_SOC_AR7242:
+		mdio_clock_div = MAC_MII_CFG_CLOCK_DIV_20;
+		break;
+	default:
+		mdio_clock_div = MAC_MII_CFG_CLOCK_DIV_28;
+		break;
+	}
+	ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_RESET | mdio_clock_div);
 	DELAY(100);
-	ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_CLOCK_DIV_28);
+	ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, mdio_clock_div);
 	DELAY(100);
-#else
-	/* Reset MII bus */
-//	ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_RESET | MAC_MII_CFG_CLOCK_DIV_10);
-	ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_RESET | MAC_MII_CFG_CLOCK_DIV_20);
+
+	/* Scan bus */
+	ARGE_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_SCAN_CYCLE);
 	DELAY(100);
-//	ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_CLOCK_DIV_10);
-	ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_CLOCK_DIV_20);
-	DELAY(100);
-#endif
+	ARGE_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_READ);
 
 	/*
 	 * Set all Ethernet address registers to the same initial values
 	 * set all four addresses to 66-88-aa-cc-dd-ee
 	 */
-	ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR1, 
+	ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR1,
 	    (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8)  | eaddr[5]);
 	ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR2, (eaddr[0] << 8) | eaddr[1]);
 
-	ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG0, 
+	ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG0,
 	    FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT);
 
 	switch (ar71xx_soc) {
@@ -468,86 +448,22 @@
 			ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0010ffff);
 			ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x015500aa);
 			ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMATCH, 0x3ffff);
-			ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK, 0x3ffff | ((sc->arge_mac_unit == 1)?(1<<19):0));
+			ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK, 0x3ffff |
+			    ((sc->arge_mac_unit == 1)?(1<<19):0));
 			break;
 		default:
 			ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0fff0000);
 			ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x00001fff);
-			ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMATCH, 
+			ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMATCH,
 			    FIFO_RX_FILTMATCH_DEFAULT);
-			ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK, 
+			ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK,
 			    FIFO_RX_FILTMASK_DEFAULT);
 	}
-#if 0
-	ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0xfff0000);
-	ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x1fff);
 
-//	mgmt_cfg_val = 0x4;
+	printf("%s:%d: call arge_set_pll(sc, media=%08x, duplex=%08x)\n", __func__, __LINE__, sc->arge_media_type, sc->arge_media_duplex);
+	arge_set_pll(sc, sc->arge_media_type, sc->arge_media_duplex);
 
-//	if ((mac->mac_unit == 0))
-//		ar7240_reg_rmw_set(AR71XX_ETH_CFG, AR71XX_ETH_CFG_MII_GE0 | AR71XX_ETH_CFG_MII_GE0_SLAVE);
-
-	ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, 0x4| (1 << 31));
-	ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, 0x4);
-
-	ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG0, 0x1f00);
-
-	ag7240_reg_rmw_set(sc, AR71XX_MAC_FIFO_RX_FILTMATCH, 0x3ffff);
-
-	ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x10ffff);
-	ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0xAAA0555);
-
-	/* 
-	 * Alloow CRC Errors, Pause Frames, Length Error Frames and Multi / Broadcast Frame entry.
-	 */
-	if(mac->mac_unit == 0) {
-		ag7240_reg_rmw_clear(sc, AR71XX_MAC_FIFO_RX_FILTMASK, (1 << 18));
-		ag7240_reg_rmw_clear(sc, AR71XX_MAC_FIFO_RX_FILTMASK, (1 << 19));
-	} else {
-		ag7240_reg_rmw_clear(sc, AR71XX_MAC_FIFO_RX_FILTMASK, (1 << 18));
-
-	}
-	ARGE_WRITE(sc, AR71XX_MAC_FIFO_TX_THRESHOLD, 0x1f00140);
-#endif
-	/* 
-	 * Check if we have single-PHY MAC or multi-PHY
-	 */
-	phys_total = 0;
-	for (i = 0; i < ARGE_NPHY; i++)
-		if (phymask & (1 << i))
-			phys_total ++;
-
-	if (phys_total == 0) {
-		error = EINVAL;
-		goto fail;
-	}
-	device_printf(dev, "attach PHYs\n");
-
-#if 1
-	device_printf(dev, "Set PLL\n");
-	arge_set_pll(sc, sc->arge_media_type, sc->arge_media_duplex);
-	/* Reset MII bus */
-//	ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_RESET | MAC_MII_CFG_CLOCK_DIV_10);
-	ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_RESET | MAC_MII_CFG_CLOCK_DIV_20);
-	DELAY(100);
-//	ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_CLOCK_DIV_10);
-	ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_CLOCK_DIV_20);
-	DELAY(100);
-
-	device_printf(dev, "Do MII setup\n");
-#if 0
-	/* Do MII setup. */
-	error = mii_attach(dev, &sc->arge_miibus, ifp,
-	    arge_ifmedia_upd, arge_ifmedia_sts, BMSR_DEFCAPMASK,
-	    MII_PHY_ANY, MII_OFFSET_ANY, 0);
-	if (error != 0) {
-		device_printf(dev, "attaching PHYs failed\n");
-//		goto fail; /* continue w/o PHY */
-	}
-
-#else
 	/* Attach miibus */
-	device_printf(dev, "Attach miibus\n");
 	struct miibus_ivars *ivars;
 	ivars = malloc(sizeof(*ivars), M_DEVBUF, M_NOWAIT);
 	if (ivars == NULL) {
@@ -565,68 +481,13 @@
 	}
 	device_set_ivars(sc->arge_miibus, ivars);
 
-	device_printf(dev, "Attach switch\n");
-	/* Attach switch */
-	struct mii_attach_args *ma;
-	device_t phy;
-	ma = malloc(sizeof(struct mii_attach_args), M_DEVBUF, M_NOWAIT);
-	ma->mii_id1 = 0;
-	ma->mii_id2 = 0;
-	ma->mii_phyno = 0;
-	if (ma == NULL) {
-		error = ENOMEM;
-		goto fail;
-	}
-	phy = device_add_child(sc->arge_miibus, "switch", -1);
-	if (phy == NULL) {
-		free(ma, M_DEVBUF);
-		error = ENXIO;
-		goto fail;
-	}
-	device_set_ivars(phy, ma);
-
-	device_printf(dev, "bus_generic_attach(miibus)\n");
 	error = bus_generic_attach(dev);
 	if (error != 0) {
 		goto fail;
 	}
 
-#endif
-
-
-
-
-
-
-
-	device_printf(dev, "Set PLL 0x%08x\n", sc->arge_media_type|sc->arge_media_duplex);
-	arge_set_pll(sc, sc->arge_media_type, sc->arge_media_duplex);
-#else
-	if (phys_total == 1) {
-		/* Do MII setup. */
-		error = mii_attach(dev, &sc->arge_miibus, ifp,
-		    arge_ifmedia_upd, arge_ifmedia_sts, BMSR_DEFCAPMASK,
-		    MII_PHY_ANY, MII_OFFSET_ANY, 0);
-		if (error != 0) {
-			device_printf(dev, "attaching PHYs failed\n");
-			goto fail;
-		}
-	}
-	else {
-		ifmedia_init(&sc->arge_ifmedia, 0, 
-		    arge_ifmedia_upd,
-		    arge_ifmedia_sts);
-		ifmedia_add(&sc->arge_ifmedia,
-		    IFM_ETHER | sc->arge_media_type|sc->arge_media_duplex, 0, NULL);
-		ifmedia_set(&sc->arge_ifmedia,
-		    IFM_ETHER | sc->arge_media_type|sc->arge_media_duplex);
-		arge_set_pll(sc, sc->arge_media_type, sc->arge_media_duplex);
-	}
-#endif
-	device_printf(dev, "Call MI attach\n");
 	/* Call MII attach routine. */
 	ether_ifattach(ifp, eaddr);
-	device_printf(dev, "Enable iterrupts\n");
 
 	/* Hook interrupt last to avoid having to lock softc */
 	error = bus_setup_intr(dev, sc->arge_irq, INTR_TYPE_NET | INTR_MPSAFE,
@@ -641,10 +502,9 @@
 	/* setup sysctl variables */
 	arge_attach_sysctl(dev);
 
-#ifndef ALOCATE_RING_IN_INIT
 	/* Init circular RX list. */
 	if (arge_rx_ring_init(sc) != 0) {
-		device_printf(sc->arge_dev,
+		device_printf(dev,
 		    "initialization failed: no memory for rx buffers\n");
 		error = ENOMEM;
 		goto fail;
@@ -652,10 +512,9 @@
 
 	/* Init tx descriptors. */
 	arge_tx_ring_init(sc);
-#endif
 
 fail:
-	if (error) 
+	if (error)
 		arge_detach(dev);
 
 	return (error);
@@ -693,7 +552,7 @@
 		bus_teardown_intr(dev, sc->arge_irq, sc->arge_intrhand);
 
 	if (sc->arge_res)
-		bus_release_resource(dev, SYS_RES_MEMORY, sc->arge_rid, 
+		bus_release_resource(dev, SYS_RES_MEMORY, sc->arge_rid,
 		    sc->arge_res);
 
 	if (ifp)
@@ -742,34 +601,30 @@
 {
 	struct arge_softc * sc = device_get_softc(dev);
 	int i, result;
-	uint32_t addr = (phy << MAC_MII_PHY_ADDR_SHIFT) 
+	uint32_t addr = (phy << MAC_MII_PHY_ADDR_SHIFT)
 	    | (reg & MAC_MII_REG_MASK);
 
-	if ((sc->arge_phymask  & (1 << phy)) == 0)
-		return (0);
-
 	mtx_lock(&miibus_mtx);
 	ARGE_MII_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE);
 	ARGE_MII_WRITE(sc, AR71XX_MAC_MII_ADDR, addr);
 	ARGE_MII_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_READ);
 
 	i = ARGE_MII_TIMEOUT;
-	while ((ARGE_MII_READ(sc, AR71XX_MAC_MII_INDICATOR) & 
+	while ((ARGE_MII_READ(sc, AR71XX_MAC_MII_INDICATOR) &
 	    MAC_MII_INDICATOR_BUSY) && (i--))
 		DELAY(5);
 
 	if (i < 0) {
 		mtx_unlock(&miibus_mtx);
 		ARGEDEBUG(sc, ARGE_DBG_MII, "%s timedout\n", __func__);
-		/* XXX: return ERRNO istead? */
-		return (-1);
+		return (-EIO);
 	}
 
 	result = ARGE_MII_READ(sc, AR71XX_MAC_MII_STATUS) & MAC_MII_STATUS_MASK;
 	ARGE_MII_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE);
 	mtx_unlock(&miibus_mtx);
 
-	ARGEDEBUG(sc, ARGE_DBG_MII, "%s: phy=%d, reg=%02x, value[%08x]=%04x\n", __func__, 
+	ARGEDEBUG(sc, ARGE_DBG_MII, "%s: phy=%d, reg=%02x, value[%08x]=%04x\n", __func__,
 		 phy, reg, addr, result);
 
 	return (result);
@@ -780,14 +635,10 @@
 {
 	struct arge_softc * sc = device_get_softc(dev);
 	int i;
-	uint32_t addr = 
+	uint32_t addr =
 	    (phy << MAC_MII_PHY_ADDR_SHIFT) | (reg & MAC_MII_REG_MASK);
 
-
-	if ((sc->arge_phymask  & (1 << phy)) == 0)
-		return (-1);
-
-	ARGEDEBUG(sc, ARGE_DBG_MII, "%s: phy=%d, reg=%02x, value=%04x\n", __func__, 
+	ARGEDEBUG(sc, ARGE_DBG_MII, "%s: phy=%d, reg=%02x, value=%04x\n", __func__,
 	    phy, reg, data);
 
 	mtx_lock(&miibus_mtx);
@@ -795,7 +646,7 @@
 	ARGE_MII_WRITE(sc, AR71XX_MAC_MII_CONTROL, data);
 
 	i = ARGE_MII_TIMEOUT;
-	while ((ARGE_MII_READ(sc, AR71XX_MAC_MII_INDICATOR) & 
+	while ((ARGE_MII_READ(sc, AR71XX_MAC_MII_INDICATOR) &
 	    MAC_MII_INDICATOR_BUSY) && (i--))
 		DELAY(5);
 
@@ -803,8 +654,7 @@
 
 	if (i < 0) {
 		ARGEDEBUG(sc, ARGE_DBG_MII, "%s timedout\n", __func__);
-		/* XXX: return ERRNO istead? */
-		return (-1);
+		return (-EIO);
 	}
 
 	return (0);
@@ -843,6 +693,7 @@
 		else
 			sc->arge_media_type = IFM_100_TX;
 
+		printf("%s:%d: call arge_set_pll(sc, media=%08x, duplex=%08x)\n", __func__, __LINE__, sc->arge_media_type, sc->arge_media_duplex);
 		arge_set_pll(sc, sc->arge_media_type, sc->arge_media_duplex);
 		ARGE_UNLOCK(sc);
 		return;
@@ -851,7 +702,9 @@
 	if (mii->mii_media_status & IFM_ACTIVE) {
 		if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
 			sc->arge_link_status = 1;
-			arge_set_pll(sc, mii->mii_media_active, 1);
+			printf("%s:%d: call arge_set_pll(sc, media=%08x, duplex=%08x)\n", __func__, __LINE__, IFM_SUBTYPE(mii->mii_media_active), (mii->mii_media_active & IFM_GMASK));
+			arge_set_pll(sc, IFM_SUBTYPE(mii->mii_media_active),
+			    (mii->mii_media_active & IFM_GMASK));
 		}
 	} else
 		sc->arge_link_status = 0;
@@ -867,8 +720,8 @@
 	int 			if_speed;
 
 	cfg = ARGE_READ(sc, AR71XX_MAC_CFG2);
-	cfg &= ~(MAC_CFG2_IFACE_MODE_1000 
-	    | MAC_CFG2_IFACE_MODE_10_100 
+	cfg &= ~(MAC_CFG2_IFACE_MODE_1000
+	    | MAC_CFG2_IFACE_MODE_10_100
 	    | MAC_CFG2_FULL_DUPLEX);
 
 	if (duplex == IFM_FDX)
@@ -876,7 +729,7 @@
 
 	ifcontrol = ARGE_READ(sc, AR71XX_MAC_IFCONTROL);
 	ifcontrol &= ~MAC_IFCONTROL_SPEED;
-	rx_filtmask = 
+	rx_filtmask =
 	    ARGE_READ(sc, AR71XX_MAC_FIFO_RX_FILTMASK);
 	rx_filtmask &= ~FIFO_RX_MASK_BYTE_MODE;
 
@@ -918,7 +771,7 @@
 
 	ARGE_WRITE(sc, AR71XX_MAC_CFG2, cfg);
 	ARGE_WRITE(sc, AR71XX_MAC_IFCONTROL, ifcontrol);
-	ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK, 
+	ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK,
 	    rx_filtmask);
 	ARGE_WRITE(sc, AR71XX_MAC_FIFO_TX_THRESHOLD, fifo_tx);
 
@@ -940,18 +793,18 @@
 	while(ARGE_READ(sc, AR71XX_DMA_RX_STATUS) & DMA_RX_STATUS_PKT_RECVD)
 		ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_PKT_RECVD);
 
-	/* 
+	/*
 	 * Clear all possible TX interrupts
 	 */
 	while(ARGE_READ(sc, AR71XX_DMA_TX_STATUS) & DMA_TX_STATUS_PKT_SENT)
 		ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_PKT_SENT);
 
-	/* 
+	/*
 	 * Now Rx/Tx errors
 	 */
-	ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, 
+	ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS,
 	    DMA_RX_STATUS_BUS_ERROR | DMA_RX_STATUS_OVERFLOW);
-	ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, 
+	ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS,
 	    DMA_TX_STATUS_BUS_ERROR | DMA_TX_STATUS_UNDERRUN);
 }
 
@@ -976,32 +829,11 @@
 	ARGE_LOCK_ASSERT(sc);
 
 	arge_stop(sc);
-#ifdef ALOCATE_RING_IN_INIT
-	/* Init circular RX list. */
-	if (arge_rx_ring_init(sc) != 0) {
-		device_printf(sc->arge_dev,
-		    "initialization failed: no memory for rx buffers\n");
-		arge_stop(sc);
-		return;
-	}
-
-	/* Init tx descriptors. */
-	arge_tx_ring_init(sc);
-#endif
 	arge_reset_dma(sc);
 
-
-	if (sc->arge_miibus) {
-		sc->arge_link_status = 0;
-		mii = device_get_softc(sc->arge_miibus);
-		mii_mediachg(mii);
-	}
-	else {
-		/*
-		 * Sun always shines over multiPHY interface
-		 */
-		sc->arge_link_status = 1;
-	}
+	sc->arge_link_status = 0;
+	mii = device_get_softc(sc->arge_miibus);
+	mii_mediachg(mii);
 
 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
@@ -1074,7 +906,7 @@
 
 	prod = sc->arge_cdata.arge_tx_prod;
 	txd = &sc->arge_cdata.arge_txdesc[prod];
-	error = bus_dmamap_load_mbuf_sg(sc->arge_cdata.arge_tx_tag, 
+	error = bus_dmamap_load_mbuf_sg(sc->arge_cdata.arge_tx_tag,
 	    txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
 
 	if (error == EFBIG) {
@@ -1098,7 +930,7 @@
 	bus_dmamap_sync(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap,
 	    BUS_DMASYNC_PREWRITE);
 
-	/* 
+	/*
 	 * Make a list of descriptors for this packet. DMA controller will
 	 * walk through it while arge_link is not zero.
 	 */
@@ -1112,7 +944,7 @@
 			panic("TX packet address unaligned\n");
 
 		desc->packet_addr = txsegs[i].ds_addr;
-		
+
 		/* link with previous descriptor */
 		if (prev_desc)
 			prev_desc->packet_ctrl |= ARGE_DESC_MORE;
@@ -1248,7 +1080,7 @@
 				    & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
 					/* XXX: handle promisc & multi flags */
 				}
-					
+
 			} else {
 				if (!sc->arge_detach)
 					arge_init_locked(sc);
@@ -1272,7 +1104,7 @@
 			mii = device_get_softc(sc->arge_miibus);
 			error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
 		}
-		else 
+		else
 			error = ifmedia_ioctl(ifp, ifr, &sc->arge_ifmedia, command);
 		break;
 	case SIOCSIFCAP:
@@ -1857,7 +1689,7 @@
 	    sc->arge_cdata.arge_rx_ring_map,
 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 
-	for (prog = 0; prog < ARGE_RX_RING_COUNT; 
+	for (prog = 0; prog < ARGE_RX_RING_COUNT;
 	    ARGE_INC(cons, ARGE_RX_RING_COUNT)) {
 		cur_rx = &sc->arge_rdata.arge_rx_ring[cons];
 		rxd = &sc->arge_cdata.arge_rxdesc[cons];
@@ -1894,7 +1726,7 @@
 		i = sc->arge_cdata.arge_rx_cons;
 		for (; prog > 0 ; prog--) {
 			if (arge_newbuf(sc, i) != 0) {
-				device_printf(sc->arge_dev, 
+				device_printf(sc->arge_dev,
 				    "Failed to allocate buffer\n");
 				break;
 			}
@@ -1923,7 +1755,7 @@
 	ARGEDEBUG(sc, ARGE_DBG_INTR, "int mask(filter) = %b\n", ints,
 	    "\20\10RX_BUS_ERROR\7RX_OVERFLOW\5RX_PKT_RCVD"
 	    "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
-	ARGEDEBUG(sc, ARGE_DBG_INTR, "status(filter) = %b\n", status, 
+	ARGEDEBUG(sc, ARGE_DBG_INTR, "status(filter) = %b\n", status,
 	    "\20\10RX_BUS_ERROR\7RX_OVERFLOW\5RX_PKT_RCVD"
 	    "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
 
@@ -1931,7 +1763,7 @@
 		sc->arge_intr_status |= status;
 		ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
 		return (FILTER_SCHEDULE_THREAD);
-	} 
+	}
 
 	sc->arge_intr_status = 0;
 	return (FILTER_STRAY);
@@ -1947,12 +1779,12 @@
 	status = ARGE_READ(sc, AR71XX_DMA_INTR_STATUS);
 	status |= sc->arge_intr_status;
 
-	ARGEDEBUG(sc, ARGE_DBG_INTR, "int status(intr) = %b\n", status, 
+	ARGEDEBUG(sc, ARGE_DBG_INTR, "int status(intr) = %b\n", status,
 	    "\20\10\7RX_OVERFLOW\5RX_PKT_RCVD"
 	    "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
 
-	/* 
-	 * Is it our interrupt at all? 
+	/*
+	 * Is it our interrupt at all?
 	 */
 	if (status == 0)
 		return;
@@ -1974,9 +1806,9 @@
 	if (status & DMA_INTR_RX_PKT_RCVD)
 		arge_rx_locked(sc);
 
-	/* 
-	 * RX overrun disables the receiver. 
-	 * Clear indication and re-enable rx. 
+	/*
+	 * RX overrun disables the receiver.
+	 * Clear indication and re-enable rx.
 	 */
 	if ( status & DMA_INTR_RX_OVERFLOW) {
 		ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_OVERFLOW);
@@ -1986,16 +1818,16 @@
 
 	if (status & DMA_INTR_TX_PKT_SENT)
 		arge_tx_locked(sc);
-	/* 
-	 * Underrun turns off TX. Clear underrun indication. 
-	 * If there's anything left in the ring, reactivate the tx. 
+	/*
+	 * Underrun turns off TX. Clear underrun indication.
+	 * If there's anything left in the ring, reactivate the tx.
 	 */
 	if (status & DMA_INTR_TX_UNDERRUN) {
 		ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_UNDERRUN);
 		sc->stats.tx_underflow++;
 		ARGEDEBUG(sc, ARGE_DBG_TX, "%s: TX underrun; tx_cnt=%d\n", __func__, sc->arge_cdata.arge_tx_cnt);
 		if (sc->arge_cdata.arge_tx_cnt > 0 ) {
-			ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, 
+			ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL,
 			    DMA_TX_CONTROL_EN);
 		}
 	}
@@ -2026,8 +1858,9 @@
 	 */
 	sc->arge_intr_status = 0;
 	ARGE_UNLOCK(sc);
+
 	/*
-	 * re-enable all interrupts 
+	 * re-enable all interrupts
 	 */
 	ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
 }


More information about the Zrouter-src-freebsd mailing list