[Zrouter-src-freebsd] ZRouter.org: push to FreeBSD HEAD tree
zrouter-src-freebsd at zrouter.org
zrouter-src-freebsd at zrouter.org
Sat Dec 3 20:37:18 UTC 2011
details: http://zrouter.org/hg/FreeBSD/head//rev/fd105b7d9d74
changeset: 236:fd105b7d9d74
user: ray at terran.dlink.ua
date: Sat Dec 03 22:37:51 2011 +0200
description:
Switch Framework update
1. Add new methods for reset subsystems (switch/VLANs/ports/etc)
2. Remove bad/good packets count methods, we need something more generic
(some other stuff)
<<still dirty>>
diffstat:
head/sys/dev/switch/ar8x16_switch.c | 137 ++++++-
head/sys/dev/switch/ar8x16_switchreg.h | 62 ++-
head/sys/dev/switch/ar8x16_switchvar.h | 2 +-
head/sys/dev/switch/bcm5325_switch.c | 183 +--------
head/sys/dev/switch/bcm5325_switchreg.h | 27 +-
head/sys/dev/switch/rt305x_switch.c | 155 +++++++-
head/sys/dev/switch/rt305x_switchreg.h | 14 +-
head/sys/dev/switch/rt305x_switchvar.h | 21 +-
head/sys/dev/switch/rtl830x_switch.c | 39 +-
head/sys/dev/switch/rtl830x_switchreg.h | 645 +------------------------------
head/sys/dev/switch/rtl830x_switchvar.h | 2 +-
head/sys/dev/switch/switch.c | 154 +++++++-
head/sys/dev/switch/switch_gpio.c | 33 -
head/sys/dev/switch/switch_if.m | 80 ++-
head/sys/dev/switch/switch_ioctl.h | 14 +-
head/sys/dev/switch/switch_mii.c | 172 ++++----
head/sys/dev/switch/switch_obio.c | 5 +-
head/sys/dev/switch/switchb_if.m | 2 +-
head/sys/dev/switch/switchvar.h | 10 +-
head/sys/dev/switch/template_switch.c | 9 +-
20 files changed, 772 insertions(+), 994 deletions(-)
diffs (2652 lines):
diff -r f8392f3407da -r fd105b7d9d74 head/sys/dev/switch/ar8x16_switch.c
--- a/head/sys/dev/switch/ar8x16_switch.c Fri Dec 02 15:27:25 2011 +0200
+++ b/head/sys/dev/switch/ar8x16_switch.c Sat Dec 03 22:37:51 2011 +0200
@@ -1,3 +1,32 @@
+/*-
+ * Copyright (c) 2011 Luiz Otavio O Souza.
+ * Copyright (c) 2011 Aleksandr Rybalko.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
@@ -21,6 +50,7 @@
static int get_reg(device_t dev, uint32_t reg, uint32_t *value);
static int set_reg(device_t dev, uint32_t reg, uint32_t *value);
+static int reset_subsys(device_t dev, int subsys);
static __uint32_t
ar8x16_reg_read(struct ar8x16_switch_softc *sc, __uint32_t reg)
@@ -62,6 +92,45 @@
}
static int
+miibus_writereg(device_t dev, int phy, int reg, int value)
+{
+ struct ar8x16_switch_softc *sc;
+
+ sc = device_get_softc(dev);
+ WRITE4(sc, AR8X16_REG_MDIO_CTRL,
+ AR8X16_MDIO_CTRL_BUSY |
+ AR8X16_MDIO_CTRL_MASTER_EN |
+ AR8X16_MDIO_CTRL_CMD_READ |
+ (phy << AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT) |
+ (reg << AR8X16_MDIO_CTRL_REG_ADDR_SHIFT) |
+ (value & AR8X16_MDIO_CTRL_DATA_MASK));
+
+ if (WAIT4(sc, AR8X16_REG_MDIO_CTRL, AR8X16_MDIO_CTRL_BUSY, 0, 1000))
+ return (-1);
+
+ return (0);
+}
+
+static int
+miibus_readreg(device_t dev, int phy, int reg)
+{
+ struct ar8x16_switch_softc *sc;
+
+ sc = device_get_softc(dev);
+ WRITE4(sc, AR8X16_REG_MDIO_CTRL,
+ AR8X16_MDIO_CTRL_BUSY |
+ AR8X16_MDIO_CTRL_MASTER_EN |
+ AR8X16_MDIO_CTRL_CMD_READ |
+ (phy << AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT) |
+ (reg << AR8X16_MDIO_CTRL_REG_ADDR_SHIFT));
+
+ if (WAIT4(sc, AR8X16_REG_MDIO_CTRL, AR8X16_MDIO_CTRL_BUSY, 0, 1000))
+ return (0xffff);
+
+ return (READ4(sc, AR8X16_REG_MDIO_CTRL) & 0xffff);
+}
+
+static int
get_reg(device_t dev, uint32_t reg, uint32_t *value)
{
struct ar8x16_switch_softc *sc;
@@ -69,6 +138,8 @@
sc = device_get_softc(dev);
if (reg & 0x80000000)
*value = READ4(sc, reg);
+ else if (reg & 0x40000000)
+ *value = miibus_readreg(dev, ((reg >> 8) & 0xff), (reg & 0xff));
else
*value = MII_SW_READ4(sc, reg);
return (0);
@@ -84,6 +155,9 @@
if (reg & 0x80000000) {
old = READ4(sc, reg);
WRITE4(sc, reg, *value);
+ } else if (reg & 0x40000000) {
+ old = miibus_readreg(dev, ((reg >> 8) & 0xff), (reg & 0xff));
+ *value = miibus_writereg(dev, ((reg >> 8) & 0xff), (reg & 0xff), *value);
} else {
old = MII_SW_READ4(sc, reg);
MII_SW_WRITE4(sc, reg, *value);
@@ -165,6 +239,7 @@
/* ar8x16 use PHYs for access */
if (!res->phys)
return (ENXIO);
+//model SWITCHFW AR8X16 0x0101 Atheros AR8x16 switch family
sc = device_get_softc(dev);
sc->parent = device_get_parent(dev); /* switchX device */
@@ -193,9 +268,12 @@
{
uint32_t mode;
+ WRITE4(sc, AR8X16_REG_MODE, AR8X16_MODE_DIR_615_MY);
+
/* Set the interface type: rgmii, gmii - We only support rgmii atm. */
mode = READ4(sc, AR8X16_REG_MODE);
-
+#if 0
+ /* XXX: set what we need, instead of failing on unsupported */
if (mode == AR8X16_MODE_GMII) {
device_printf(sc->sc_dev, "Unsupported MII mode.\n");
return (ENXIO);
@@ -208,7 +286,7 @@
}
WRITE4(sc, AR8X16_REG_MODE, sc->sc_mii_mode);
}
-
+#endif
/* Standard Atheros magic */
/* XXX, find what magic in those value,
* somewhere I(ray) already seen it, but forget where */
@@ -604,6 +682,45 @@
return (error);
}
+static int
+reset_subsys(device_t dev, int subsys)
+{
+ struct ar8x16_switch_softc *sc = device_get_softc(dev);
+ int port;
+
+ switch (subsys & SWITCH_RESETSUB_MASK) {
+ case SWITCH_RESETSUB_SWITCH:
+ ar8x16_switch_reset(sc);
+ break;
+ case SWITCH_RESETSUB_PORT:
+ if ((subsys & SWITCH_RESETSUB_PORT_MASK) ==
+ SWITCH_RESETSUB_ALLPORTS) {
+ /* Reset all PHYs */
+#ifdef notyet
+ for (port = 0; port < sc->ports; port ++)
+ reset_port(sc, port);
+#endif
+ } else {
+ /* Reset syngle PHY */
+ port = (subsys & SWITCH_RESETSUB_PORT_MASK) >>
+ SWITCH_RESETSUB_PORT_SHIFT;
+#ifdef notyet
+ reset_port(sc, port);
+#endif
+ }
+ break;
+ case SWITCH_RESETSUB_VLANS:
+ if (WAIT4(sc, AR8X16_REG_VLAN_CTRL, AR8X16_VLAN_ACTIVE, 0, 5))
+ return (EBUSY);
+ WRITE4(sc, AR8X16_REG_VLAN_CTRL, AR8X16_VLAN_ACTIVE | AR8X16_VLAN_OP_FLUSH);
+ break;
+ case SWITCH_RESETSUB_QOS:
+ break;
+ }
+
+ return (0);
+}
+
static device_method_t ar8x16_switch_methods[] = {
DEVMETHOD(device_probe, ar8x16_switch_probe),
DEVMETHOD(device_attach, ar8x16_switch_attach),
@@ -613,6 +730,7 @@
DEVMETHOD(switch_get_caps, get_caps),
DEVMETHOD(switch_set_reg, set_reg),
DEVMETHOD(switch_get_reg, get_reg),
+ DEVMETHOD(switch_reset_subsys, reset_subsys),
/* MAC address table */
DEVMETHOD(switch_find_mac, find_mac_addr),
@@ -627,19 +745,10 @@
DEVMETHOD(switch_get_vid, get_vid),
DEVMETHOD(switch_set_vlanports, set_vlan_ports),
DEVMETHOD(switch_get_vlanports, get_vlan_ports),
-// DEVMETHOD(switch_set_vlanutports, set_vlan_untagged_ports),
-// DEVMETHOD(switch_get_vlanutports, get_vlan_untagged_ports),
- /* Port state */
-// DEVMETHOD(switch_get_portlink, get_port_link),
-// DEVMETHOD(switch_get_portspeed, get_port_speed),
-// DEVMETHOD(switch_force_mode, force_port_mode),
-
- /* Statistics */
-// DEVMETHOD(switch_good_in_cnt, stat_good_in_packet_count),
-// DEVMETHOD(switch_good_out_cnt, stat_good_out_packet_count),
-// DEVMETHOD(switch_bad_in_cnt, stat_bad_in_packet_count),
-// DEVMETHOD(switch_bad_out_cnt, stat_bad_out_packet_count),
+ /* ports PHY access */
+ DEVMETHOD(switch_miibus_readreg, miibus_readreg),
+ DEVMETHOD(switch_miibus_writereg, miibus_writereg),
{0, 0},
};
diff -r f8392f3407da -r fd105b7d9d74 head/sys/dev/switch/ar8x16_switchreg.h
--- a/head/sys/dev/switch/ar8x16_switchreg.h Fri Dec 02 15:27:25 2011 +0200
+++ b/head/sys/dev/switch/ar8x16_switchreg.h Sat Dec 03 22:37:51 2011 +0200
@@ -1,3 +1,31 @@
+/*-
+ * Copyright (c) 2011 Aleksandr Rybalko.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
#ifndef __AR8X16_SWITCHREG_H__
#define __AR8X16_SWITCHREG_H__
@@ -8,9 +36,37 @@
#define AR8X16_MASK_CTRL_SOFT_RESET (1 << 31)
#define AR8X16_REG_MODE 0x0008
-#define AR8X16_MODE_RGMII_PORT4_ISO 0x81461bea /* From Ubiquiti RSPRO */
-#define AR8X16_MODE_RGMII_PORT4_SWITCH 0x01261be2 /* Unknown */
-#define AR8X16_MODE_GMII 0x010e5b71 /* AVM Fritz!Box 7390 */
+/* DIR-615 E4 U-Boot */
+#define AR8X16_MODE_DIR_615_UBOOT 0x8d1003e0
+/* Mode enable all PHYs and maybe pass MII1 data to PHY4(WAN) (XXX check it) */
+#define AR8X16_MODE_DIR_615_MY 0x814603ea /* (MMI0 - RGMII, MMI1 - RGMII, !PORTx_ISO) */
+/* From Ubiquiti RSPRO */
+#define AR8X16_MODE_RGMII_PORT4_ISO 0x81461bea
+#define AR8X16_MODE_RGMII_PORT4_SWITCH 0x01261be2
+/* AVM Fritz!Box 7390 */
+#define AR8X16_MODE_GMII 0x010e5b71
+/* from avm_cpmac/linux_ar_reg.h */
+#define AR8X16_MODE_RESERVED 0x000e1b20
+#define AR8X16_MODE_MII0_MAC_GMII (1u << 0)
+#define AR8X16_MODE_MII0_MAC_RGMII (1u << 1)
+#define AR8X16_MODE_MII1_PHY_GMII (1u << 2)
+#define AR8X16_MODE_MII1_PHY_RGMII (1u << 3)
+#define AR8X16_MODE_MII0_MAC_MODE (1u << 4)
+#define AR8X16_MODE_RGMII_RXCLK_DELAY_EN (1u << 6)
+#define AR8X16_MODE_RGMII_TXCLK_DELAY_EN (1u << 7)
+#define AR8X16_MODE_PORT0_ISO (1u << 10)
+#define AR8X16_MODE_PORT1_ISO (1u << 11)
+#define AR8X16_MODE_PORT2_ISO (1u << 12)
+#define AR8X16_MODE_PORT3_ISO (1u << 13)
+#define AR8X16_MODE_MII1_MAC_GMII (1u << 14)
+#define AR8X16_MODE_MII1_PHY_MODE (1u << 15)
+#define AR8X16_MODE_TXDELAY_S0 (1u << 21)
+#define AR8X16_MODE_TXDELAY_S1 (1u << 22)
+#define AR8X16_MODE_RXDELAY_S0 (1u << 23)
+#define AR8X16_MODE_LED_OPEN_EN (1u << 24)
+#define AR8X16_MODE_SPI_EN (1u << 25)
+#define AR8X16_MODE_RXDELAY_S1 (1u << 26)
+#define AR8X16_MODE_POWER_ON_SEL (1u << 31)
#define AR8X16_REG_ISR 0x0010
#define AR8X16_REG_IMR 0x0014
diff -r f8392f3407da -r fd105b7d9d74 head/sys/dev/switch/ar8x16_switchvar.h
--- a/head/sys/dev/switch/ar8x16_switchvar.h Fri Dec 02 15:27:25 2011 +0200
+++ b/head/sys/dev/switch/ar8x16_switchvar.h Sat Dec 03 22:37:51 2011 +0200
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2010 Aleksandr Rybalko.
+ * Copyright (c) 2011 Aleksandr Rybalko.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff -r f8392f3407da -r fd105b7d9d74 head/sys/dev/switch/bcm5325_switch.c
--- a/head/sys/dev/switch/bcm5325_switch.c Fri Dec 02 15:27:25 2011 +0200
+++ b/head/sys/dev/switch/bcm5325_switch.c Sat Dec 03 22:37:51 2011 +0200
@@ -39,10 +39,6 @@
#include <net/if.h>
#include <net/if_media.h>
-//XXX
-#include <dev/mii/mii.h>
-#include <dev/mii/miivar.h>
-
#include <dev/switch/switchvar.h>
#include <dev/switch/bcm5325_switchvar.h>
#include <dev/switch/bcm5325_switchreg.h>
@@ -51,9 +47,6 @@
#include "switch_if.h"
#include "switchb_if.h"
-//XXX
-#include "miibus_if.h"
-
static int bcm5325_switch_probe(device_t dev);
static int bcm5325_switch_attach(device_t dev);
static int bcm5325_switch_detach(device_t dev);
@@ -75,8 +68,10 @@
static int set_vlan_untagged_ports(device_t dev, int idx, uint32_t memb);
static int get_vlan_untagged_ports(device_t dev, int idx, uint32_t *memb);
-static int bcm5325_write(struct bcm5325_switch_softc *sc, uint32_t reg, uint64_t val);
-static int bcm5325_read(struct bcm5325_switch_softc *sc, uint32_t reg, uint64_t *val);
+static int bcm5325_write(struct bcm5325_switch_softc *sc, uint32_t reg,
+ uint64_t val);
+static int bcm5325_read(struct bcm5325_switch_softc *sc, uint32_t reg,
+ uint64_t *val);
#define PSPHY_WRITE(_sc, _reg, _val) \
MII_SW_WRITE4((_sc), ((PSEUDOPHY_ADDR << 8) | (_reg)), (_val))
@@ -85,8 +80,6 @@
#define WRITE4(_sc, _reg, _val) \
MII_SW_WRITE4((_sc), ((PSEUDOPHY_ADDR << 8) | (_reg)), (_val))
-//#define READ4(_sc, _reg)
-// MII_SW_READ4((_sc), ((PSEUDOPHY_ADDR << 8) | (_reg)))
#define WRITE(_sc, _reg, _val) bcm5325_write((_sc), (_reg), (_val))
#define READ(_sc, _reg, _val) bcm5325_read((_sc), (_reg), (_val))
@@ -137,7 +130,7 @@
/* timed out */
if (!i) {
- printf("mii_wreg: timeout");
+ printf("mii_wreg: timeout\n");
return (EBUSY);
}
@@ -189,31 +182,6 @@
return (0);
}
-
-
-//XXX
-static void
-new_mii_statchg(device_t dev)
-{
-}
-
-//XXX
-static int
-new_ifmedia_upd(struct ifnet *ifp)
-{
-
- return (0);
-}
-
-/*
- * Report current media status.
- */
-//XXX
-static void
-new_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
-{
-}
-
static int
bcm5325_switch_probe(device_t dev)
{
@@ -221,8 +189,14 @@
res = device_get_ivars(dev);
+//model SWITCHFW BCM5325 0x0201 Broadcom BCM5325 switch family (5354, 53115, etc)
+
/* XXX: bcm5325 show at leaset 5 PHYs */
+#ifdef notyet
if ((res->phys & 0x1f) != 0x1f)
+#else
+ if (!res->phys)
+#endif
return (ENXIO);
device_set_desc(dev, "BCM5325 family ethernet switch");
@@ -235,7 +209,7 @@
struct bcm5325_switch_softc *sc;
uint64_t reg;
uint64_t reg32;
- int i, error = 0;
+ int i;
sc = device_get_softc(dev);
sc->parent = device_get_parent(dev);
@@ -259,20 +233,17 @@
device_printf(dev, "\t%switch model is BCM%x\n",
((resource_int_value(device_get_name(dev), device_get_unit(dev),
"devid", &sc->devid))?"S":"Hinted s"), sc->devid);
-#if 0
+#ifdef notyet
switch (sc->devid) {
case 0x5365:
sc->mode = 0;
break;
-
case 0x5356:
sc->mode = 0;
break;
-
case 0x53115:
sc->mode = 0;
break;
-
case 0x5325:
case 0x5352:
case 0x5354:
@@ -280,32 +251,7 @@
sc->mode = 0;
break;
}
-/ 0 - 5365, 1 - 5325/5352/5354, 3 - 5356, 4 - 53115 /
- mode, vlans, vvalid, vwreg, vtareg, vtereg, vtireg, ushft,
-{ 4, 256, 32, }
-
-
- val16 = (vid) /* vlan */ | (1 << 12) /* write */ | (1 << 13) /* enable */;
-53115
- val32 = (untag << 9) | member;
- robo_write32(&robo, ROBO_ARLIO_PAGE, ROBO_VTBL_ENTRY_5395, val32);
- robo_write16(&robo, ROBO_ARLIO_PAGE, ROBO_VTBL_INDX_5395, vid);
- robo_write16(&robo, ROBO_ARLIO_PAGE, ROBO_VTBL_ACCESS_5395, (1 << 7) /* start */ | 0 /* write */);
-5356
- val32 = (1 << 24) /* valid */ | (untag << 6) | member | (vid << 12);
- robo_write32(&robo, ROBO_VLAN_PAGE, ROBO_VLAN_WRITE_5350, val32);
- robo_write16(&robo, ROBO_VLAN_PAGE, ROBO_VLAN_TABLE_ACCESS_5350, val16);
-// 5325/5352/5354
- val32 = (1 << 20) /* valid */ | (untag << 6) | member | ((vid >> 4) << 12);
- robo_write32(&robo, ROBO_VLAN_PAGE, ROBO_VLAN_WRITE_5350, val32);
- robo_write16(&robo, ROBO_VLAN_PAGE, ROBO_VLAN_TABLE_ACCESS_5350, val16);
-// 5365
- robo_write16(&robo, ROBO_VLAN_PAGE, ROBO_VLAN_WRITE, (1 << 14) /* valid */ | (untag << 7) | member);
- robo_write16(&robo, ROBO_VLAN_PAGE, ROBO_VLAN_TABLE_ACCESS, val16);
-}
#endif
-
-
sc->caps = malloc(sizeof(struct switch_capability), M_DEVBUF,
M_WAITOK | M_ZERO);
@@ -319,7 +265,8 @@
#define S_C(x) SWITCH_CAPS_ ## x
sc->caps->main = S_C(MAIN_PORT_POWER);
sc->caps->vlan = S_C(VLAN_DOT1Q) |
- ((sc->vlans << S_C(VLAN_MAX_SHIFT_SHIFT)) & S_C(VLAN_MAX_SHIFT_MASK));
+ ((sc->vlans << S_C(VLAN_MAX_SHIFT_SHIFT)) &
+ S_C(VLAN_MAX_SHIFT_MASK));
sc->caps->qos = (2 << S_C(QOS_QUEUES_SHIFT)) & S_C(QOS_QUEUES_MASK);
sc->caps->lacp = 0; /* No LACP caps */
sc->caps->stp = 0; /* No STP caps */
@@ -347,8 +294,6 @@
DUMP(VLAN_DROP_UNTAGGED);
DUMP(VLAN_GLOBAL_CTL4);
DUMP(VLAN_GLOBAL_CTL5);
-// DUMP();
-// DUMP();
#undef DUMP
/* MII port state override (page 0 register 14) */
@@ -370,59 +315,18 @@
}
}
- /* Reset PHYs */
-// for (i = 1; i < 8; i++)
-// WRITE4(sc, PHY_CTL(i), PHY_CTL_RESET);
-
- /* Set to Auto-Negotiation and reset Auto-Negotiation process */
-// for (i = 1; i < 8; i++)
-// WRITE4(sc, PHY_CTL(i), PHY_CTL_ANEG|PHY_CTL_ANEG_RESTART);
-
- /* Insert tag on ingress packet */
-// for (i = 1; i < 8; i++)
-// WRITE4(sc, PHY_CTRL0(i),
-// (READ4(sc, PHY_CTRL0(i)) & 0xfffc) | CTRL0_TAG_I_UTG);
-
-// WRITE4(sc, GCNTRL0,
-// (6 << GCNTRL0_LED_MODE_SHIFT) | /* LED Mode 6: Activity,Speed,Link */
-// GCNTRL0_INGRESS_CHECK_DIS |
-// GCNTRL0_TAG_ONLY_DIS |
-// GCNTRL0_TX_FC |
-// GCNTRL0_RX_FC |
-// GCNTRL0_AGN_EN);
-
+ /*
+ * XXX: Avoid default configuration, bootloader must set it or we
+ * load user defined
+ */
/* set_vid(swdev, Idx, VID) */
set_vid(dev, 0, 1);
-// set_vid(dev, 1, 2);
-// set_vid(dev, 2, 3);
-// set_vid(dev, 3, 4);
-// set_vid(dev, 4, 5);
-// set_vid(dev, 5, 6);
-// set_vid(dev, 6, 7);
-// set_vid(dev, 7, 8);
-// set_vid(dev, 8, 9);
/* All ports are members of VLAN0 (VID1) */
set_vlan_ports(dev, 0, 0x01ff);
/* Other VLANs have no members */
for (i = 1; i < 9; i++)
set_vlan_ports(dev, i, 0x00);
- /* VLAN1 to all ports */
-// for (i = 0; i < 9; i++)
-// set_port_vid_idx(sc, i, 0);
-
- /* Remove isolate flag */
-// for (i = 1; i < 8; i++)
-// WRITE4(sc, PHY_CTL(i), READ4(sc, PHY_CTL(i)) & ~PHY_CTL_ISOLATE);
-
-
- struct ifnet *ifp = if_alloc(1); //0x01 - IFT_OTHER //IFT_ETHER);
- error = mii_attach(dev, &sc->new_mii, ifp, new_ifmedia_upd,
- new_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY,
- 0);
- if (error != 0) {
- device_printf(dev, "attaching PHYs failed\n");
- }
return (0);
}
@@ -480,7 +384,7 @@
} else {
error = READ(sc, reg, &val64);
if (((reg & 0x00ff0000) >> 16) > 4)
- printf("\t%08x = %016llx\n", reg, val64);
+ printf("\t%08x = %016jx\n", reg, val64);
if (error == 0) {
*value = (uint32_t)(val64 & 0xffffffff);
get_set_upper32 =
@@ -541,7 +445,6 @@
{
struct bcm5325_switch_softc *sc;
int idx = -1;
-// uint32_t reg;
sc = device_get_softc(dev);
@@ -552,10 +455,8 @@
mac_table_write(device_t dev, uint64_t mac, int idx, uint32_t port_map,
uint8_t age, int *hash_idx )
{
-// struct bcm5325_switch_softc *sc = device_get_softc(dev);
-// uint32_t reg;
-
+ /* TODO */
return (0);
}
@@ -698,7 +599,6 @@
struct bcm5325_switch_softc *sc;
uint16_t base_vlan_mask;
int error = 0;
- //uint32_t reg;
sc = device_get_softc(dev);
if (idx > (sc->vlans - 1))
@@ -819,38 +719,6 @@
return (0);
}
-static int
-new_mii_readreg(device_t dev, int phy, int reg)
-{
- struct bcm5325_switch_softc *sc = device_get_softc(dev);
- uint64_t val;
- int error = 0;
-
- if ((phy > 0x1f) || (reg > 0x1f))
- return (0xffff);
-
- error = READ(sc, (S2 | PAGE(0x10 + (phy)) | (reg << 1)), &val);
- if (error)
- return (0xffff);
-
- return (val & 0xffff);
-}
-
-static int
-new_mii_writereg(device_t dev, int phy, int reg, int val16)
-{
- struct bcm5325_switch_softc *sc = device_get_softc(dev);
- uint64_t val;
-
- if ((phy > 0x1f) || (reg > 0x1f) || (val16 & 0xffff0000ul))
- return (0);
-
- val = val16;
- WRITE(sc, (S2 | PAGE(0x10 + (phy)) | (reg << 1)), val);
-
- return (val);
-}
-
static device_method_t bcm5325_switch_methods[] = {
DEVMETHOD(device_probe, bcm5325_switch_probe),
DEVMETHOD(device_attach, bcm5325_switch_attach),
@@ -877,11 +745,6 @@
DEVMETHOD(switch_set_vlanutports, set_vlan_untagged_ports),
DEVMETHOD(switch_get_vlanutports, get_vlan_untagged_ports),
- /* MII interface */
- DEVMETHOD(miibus_readreg, new_mii_readreg),
- DEVMETHOD(miibus_writereg, new_mii_writereg),
- DEVMETHOD(miibus_statchg, new_mii_statchg),
-
{0, 0},
};
@@ -895,7 +758,3 @@
DRIVER_MODULE(bcm5325_switch, switch, bcm5325_switch_driver, bcm5325_switch_devclass, 0, 0);
MODULE_VERSION(bcm5325_switch, 1);
MODULE_DEPEND(bcm5325_switch, switch, 1, 1, 1);
-
-DRIVER_MODULE(miibus, bcm5325_switch, miibus_driver, miibus_devclass, 0, 0);
-MODULE_DEPEND(bcm5325_switch, miibus, 1, 1, 1);
-
diff -r f8392f3407da -r fd105b7d9d74 head/sys/dev/switch/bcm5325_switchreg.h
--- a/head/sys/dev/switch/bcm5325_switchreg.h Fri Dec 02 15:27:25 2011 +0200
+++ b/head/sys/dev/switch/bcm5325_switchreg.h Sat Dec 03 22:37:51 2011 +0200
@@ -267,8 +267,13 @@
#define ARL_SEARCH_ADDRESS_VALID 0x8000
#define ARL_SEARCH_ADDRESS_MASK 0x7fff
#define ARL_SEARCH_RESULT (S8 | PAGE(0x05) | 0x24) /* ARL Entry format */
+#define ARL_SEARCH_RESULT_EXT (S1 | PAGE(0x05) | 0x2c) /* 5350 */
#define VID_ENTRY_0 (S1 | PAGE(0x05) | 0x30)
#define VID_ENTRY_1 (S1 | PAGE(0x05) | 0x32)
+#define ARL_SEARCH_CTL_53115 (S1 | PAGE(0x05) | 0x50)
+#define ARL_SEARCH_ADDRESS_53115 (S2 | PAGE(0x05) | 0x51)
+#define ARL_SEARCH_RESULT_53115 (S8 | PAGE(0x05) | 0x60)
+#define ARL_SEARCH_RESULT_EXT_53115 (S2 | PAGE(0x05) | 0x68)
#define MEMORY_RW_CTL (S4 | PAGE(0x08) | 0x00)
#define MEMORY_RW_CTL_START 0x00080000
@@ -388,6 +393,14 @@
#define DIFFSERV_DSCP_PRIORITYH (S8 | PAGE(0x30) | 0x38)
#define DSCP_TO_QUEUE(_d, _q) ((_q) << (((_d) & 0x3f) * 2))
+/* BCM5395/5397/5398/53115 */
+#define ROBO_VTBL_ACCESS 0x60 /* VLAN table access: 8bit */
+#define ROBO_VTBL_INDX 0x61 /* VLAN table address index: 16bit */
+#define ROBO_VTBL_ENTRY 0x63 /* VLAN table entry: 32bit */
+#define ROBO_VTBL_ACCESS_5395 0x80 /* VLAN table access: 8bit */
+#define ROBO_VTBL_INDX_5395 0x81 /* VLAN table address index: 16bit */
+#define ROBO_VTBL_ENTRY_5395 0x83 /* VLAN table entry: 32bit */
+
#define VLAN_GLOBAL_CTL0 (S1 | PAGE(0x34) | 0x00)
#define VLAN_GLOBAL_CTL0_1Q_ENABLE 0x80
@@ -414,9 +427,21 @@
#define VLAN_TABLE_ACCESS_RW_ENABLE 0x2000
#define VLAN_TABLE_ACCESS_WRITE 0x1000
#define VLAN_TABLE_ACCESS_VID_MASK 0x0fff
+
+#define VLAN_ID_MAX 255
+#define VLAN_ID_MAX5350 15
+#define VLAN_ID_MAX5395 4094
+
+
/* XXX: Valid for BCM535x */
#define VLAN_WRITE (S4 | PAGE(0x34) | 0x08)
-#define VLAN_RW_VALID 0x100000
+#define VLAN_RW_VALID_5350 0x00100000
+#define VLAN_RW_VALID_5380 0x04000000
+#define VLAN_RW_VALID 0x4000
+#define VLAN_RW_UNTAG_SHIFT_5380 13
+#define VLAN_RW_UNTAG_SHIFT_5350 6
+#define VLAN_RW_UNTAG_SHIFT 7
+
#define VLAN_RW_MEMBER(_p) (1 << (_p))
#define VLAN_RW_MEMBER_MASK 0x007f
#define VLAN_RW_MEMBER_SHIFT 0
diff -r f8392f3407da -r fd105b7d9d74 head/sys/dev/switch/rt305x_switch.c
--- a/head/sys/dev/switch/rt305x_switch.c Fri Dec 02 15:27:25 2011 +0200
+++ b/head/sys/dev/switch/rt305x_switch.c Sat Dec 03 22:37:51 2011 +0200
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2010 Aleksandr Rybalko.
+ * Copyright (c) 2010-2011 Aleksandr Rybalko.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -66,11 +66,12 @@
static int get_port_speed(device_t dev, int port);
static int force_port_mode(device_t dev, int port, uint32_t mode);
+#ifdef mustbe_rewriten
static uint32_t stat_good_in_packet_count(device_t dev, int port);
static uint32_t stat_good_out_packet_count(device_t dev, int port);
static uint32_t stat_bad_in_packet_count(device_t dev, int port);
static uint32_t stat_bad_out_packet_count(device_t dev, int port);
-
+#endif
static int rt305x_switch_isr(void *arg);
@@ -81,6 +82,7 @@
res = device_get_ivars(dev);
+//model SWITCHFW RT305X 0x0601 Ralink RT3050F/RT3052F internal switch
/* rt305x internal switch require mem region */
if (res->memres_size < (RT_SW_P5PC - RT_SW_ISR))
return (ENXIO);
@@ -302,7 +304,7 @@
if (isr & MUST_DROP_LAN) {
/* Handle */
- // XXX: check what is it
+ /* XXX: check what is it */
}
if (isr & GLOBAL_QUE_FULL) {
@@ -417,10 +419,10 @@
if (port > (sc->ports - 1))
return (EINVAL);
- reg = READ4(sc, RT_SW_PVIDC0 + port / 2 * 4);
+ reg = READ4(sc, RT_SW_PVIDC0 + ((port / 2) * 4));
reg &= ~(0xfff << (12 * (port % 2)));
reg |= (0xfff & pvid) << (12 * (port % 2));
- WRITE4(sc, RT_SW_PVIDC0 + port / 2 * 4, reg);
+ WRITE4(sc, RT_SW_PVIDC0 + ((port / 2) * 4), reg);
return (0);
}
@@ -435,7 +437,7 @@
if (port > (sc->ports - 1))
return (EINVAL);
- reg = READ4(sc, RT_SW_PVIDC0 + port / 2 * 4);
+ reg = READ4(sc, RT_SW_PVIDC0 + ((port / 2) * 4));
*pvid = (reg >> (12 * (port % 2))) & 0xfff;
return (0);
@@ -679,7 +681,7 @@
reg |= (1 << port);
break;
default:
- //error unsupported media
+ /* error unsupported media */
return (1);
}
@@ -710,6 +712,7 @@
return (0);
}
+#ifdef mustbe_rewriten
static uint32_t
stat_good_in_packet_count(device_t dev, int port)
{
@@ -801,6 +804,137 @@
return (~0);
}
+#endif
+
+#define RT_SW_PCR0 0xc0
+#define PCR0_NWAY_MASK 0xffff0000
+#define PCR0_NWAY_SHIFT 16
+#define PCR0_PHY_READ (1 << 14)
+#define PCR0_PHY_WRITE (1 << 13)
+#define PCR0_REGADDR_MASK 0x00001f00
+#define PCR0_REGADDR_SHIFT 8
+#define PCR0_PHYADDR_MASK 0x0000001f
+#define PCR0_PHYADDR_SHIFT 0
+#define RT_SW_PCR1 0xc4
+#define PCR1_PHYDATA_MASK 0xffff0000
+#define PCR1_PHYDATA_SHIFT 16
+#define PCR1_PHY_READ_DONE (1 << 1)
+#define PCR1_PHY_WRITE_DONE (1 << 0)
+
+static int
+miibus_writereg(device_t dev, int phy, int reg, int value)
+{
+ struct rt305x_switch_softc *sc;
+
+ sc = device_get_softc(dev);
+ WRITE4(sc, RT_SW_PCR1,
+ ((value << PCR1_PHYDATA_SHIFT) & PCR1_PHYDATA_MASK));
+ WRITE4(sc, RT_SW_PCR0,
+ PCR0_PHY_WRITE |
+ (phy << PCR0_PHYADDR_SHIFT) |
+ (reg << PCR0_REGADDR_SHIFT));
+
+ if (WAIT4(sc, RT_SW_PCR1, PCR1_PHY_WRITE_DONE, PCR1_PHY_WRITE_DONE,
+ 1000))
+ return (-1);
+
+ return (0);
+}
+
+static int
+miibus_readreg(device_t dev, int phy, int reg)
+{
+ struct rt305x_switch_softc *sc;
+
+ sc = device_get_softc(dev);
+ WRITE4(sc, RT_SW_PCR0,
+ PCR0_PHY_READ |
+ (phy << PCR0_PHYADDR_SHIFT) |
+ (reg << PCR0_REGADDR_SHIFT));
+
+ if (WAIT4(sc, RT_SW_PCR1, PCR1_PHY_READ_DONE, PCR1_PHY_READ_DONE,
+ 1000))
+ return (0xffff);
+
+ return ((READ4(sc, RT_SW_PCR1) >> PCR1_PHYDATA_SHIFT) & 0xffff);
+}
+
+static int
+get_reg(device_t dev, uint32_t reg, uint32_t *value)
+{
+ struct rt305x_switch_softc *sc;
+
+ sc = device_get_softc(dev);
+ if (reg & 0x80000000)
+ *value = READ4(sc, reg & 0xffff);
+ else if (reg & 0x40000000)
+ *value = miibus_readreg(dev, ((reg >> 8) & 0xff),
+ (reg & 0xff));
+ else
+ *value = 0; /* Raw reg */
+ return (0);
+}
+
+static int
+set_reg(device_t dev, uint32_t reg, uint32_t *value)
+{
+ struct rt305x_switch_softc *sc;
+ uint32_t old;
+
+ sc = device_get_softc(dev);
+ if (reg & 0x80000000) {
+ old = READ4(sc, reg & 0xffff);
+ WRITE4(sc, reg & 0xffff, *value);
+ } else if (reg & 0x40000000) {
+ old = miibus_readreg(dev, ((reg >> 8) & 0xff), (reg & 0xff));
+ *value = miibus_writereg(dev, ((reg >> 8) & 0xff),
+ (reg & 0xff), *value);
+ } else {
+ old = 0; /* Raw reg */
+ }
+
+ *value = old;
+ return (0);
+}
+
+static int
+reset_subsys(device_t dev, int subsys)
+{
+ struct rt305x_switch_softc *sc = device_get_softc(dev);
+ int port;
+
+ switch (subsys & SWITCH_RESETSUB_MASK) {
+ case SWITCH_RESETSUB_SWITCH:
+ WRITE4(sc, RT_SW_STRT, 1);
+ break;
+ case SWITCH_RESETSUB_PORT:
+ if ((subsys & SWITCH_RESETSUB_PORT_MASK) ==
+ SWITCH_RESETSUB_ALLPORTS) {
+ /* Reset all PHYs */
+#ifdef notyet
+ for (port = 0; port < sc->ports; port ++)
+ reset_port(sc, port);
+#endif
+ } else {
+ /* Reset syngle PHY */
+ port = (subsys & SWITCH_RESETSUB_PORT_MASK) >>
+ SWITCH_RESETSUB_PORT_SHIFT;
+#ifdef notyet
+ reset_port(sc, port);
+#endif
+ }
+ break;
+ case SWITCH_RESETSUB_VLANS:
+// if (WAIT4(sc, AR8X16_REG_VLAN_CTRL, AR8X16_VLAN_ACTIVE, 0, 5))
+// return (EBUSY);
+// WRITE4(sc, AR8X16_REG_VLAN_CTRL, AR8X16_VLAN_ACTIVE | AR8X16_VLAN_OP_FLUSH);
+ break;
+ case SWITCH_RESETSUB_QOS:
+ break;
+ }
+
+ return (0);
+}
static device_method_t rt305x_switch_methods[] = {
DEVMETHOD(device_probe, rt305x_switch_probe),
@@ -809,6 +943,9 @@
/* Capability */
DEVMETHOD(switch_get_caps, get_caps),
+ DEVMETHOD(switch_set_reg, set_reg),
+ DEVMETHOD(switch_get_reg, get_reg),
+ DEVMETHOD(switch_reset_subsys, reset_subsys),
/* MAC address table */
DEVMETHOD(switch_find_mac, find_mac_addr),
@@ -823,19 +960,19 @@
DEVMETHOD(switch_get_vid, get_vid),
DEVMETHOD(switch_set_vlanports, set_vlan_ports),
DEVMETHOD(switch_get_vlanports, get_vlan_ports),
-// DEVMETHOD(switch_set_vlanutports, set_vlan_untagged_ports),
-// DEVMETHOD(switch_get_vlanutports, get_vlan_untagged_ports),
/* Port state */
DEVMETHOD(switch_get_portlink, get_port_link),
DEVMETHOD(switch_get_portspeed, get_port_speed),
DEVMETHOD(switch_force_mode, force_port_mode),
+#ifdef mustbe_rewriten
/* Statistics */
DEVMETHOD(switch_good_in_cnt, stat_good_in_packet_count),
DEVMETHOD(switch_good_out_cnt, stat_good_out_packet_count),
DEVMETHOD(switch_bad_in_cnt, stat_bad_in_packet_count),
DEVMETHOD(switch_bad_out_cnt, stat_bad_out_packet_count),
+#endif
{0, 0},
};
diff -r f8392f3407da -r fd105b7d9d74 head/sys/dev/switch/rt305x_switchreg.h
--- a/head/sys/dev/switch/rt305x_switchreg.h Fri Dec 02 15:27:25 2011 +0200
+++ b/head/sys/dev/switch/rt305x_switchreg.h Sat Dec 03 22:37:51 2011 +0200
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2010 Aleksandr Rybalko.
+ * Copyright (c) 2010-2011 Aleksandr Rybalko.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -114,7 +114,19 @@
#define RT_SW_WDTR 0xb8
#define RT_SW_DES 0xbc
#define RT_SW_PCR0 0xc0
+#define PCR0_NWAY_MASK 0xffff0000
+#define PCR0_NWAY_SHIFT 16
+#define PCR0_PHY_READ (1 << 14)
+#define PCR0_PHY_WRITE (1 << 13)
+#define PCR0_REGADDR_MASK 0x00001f00
+#define PCR0_REGADDR_SHIFT 8
+#define PCR0_PHYADDR_MASK 0x0000001f
+#define PCR0_PHYADDR_SHIFT 0
#define RT_SW_PCR1 0xc4
+#define PCR1_PHYDATA_MASK 0xffff0000
+#define PCR1_PHYDATA_SHIFT 16
+#define PCR1_PHY_READ_DONE (1 << 1)
+#define PCR1_PHY_WRITE_DONE (1 << 0)
#define RT_SW_FPA56 0xc8
#define RT_SW_FCT2 0xcc
#define RT_SW_QSS0 0xd0
diff -r f8392f3407da -r fd105b7d9d74 head/sys/dev/switch/rt305x_switchvar.h
--- a/head/sys/dev/switch/rt305x_switchvar.h Fri Dec 02 15:27:25 2011 +0200
+++ b/head/sys/dev/switch/rt305x_switchvar.h Sat Dec 03 22:37:51 2011 +0200
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2010 Aleksandr Rybalko.
+ * Copyright (c) 2010-2011 Aleksandr Rybalko.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -45,5 +45,24 @@
#define WRITE4(_sc, _reg, _val) \
SWITCHB_WRITE4(_sc->parent, _reg, _val)
+#define WAIT4(sc, reg, field, value, timeout_usec) \
+ ({int result; \
+ do { \
+ uint32_t c, timeout = timeout_usec; \
+ while (1) { \
+ c = (READ4(sc, reg) & field); \
+ if (c == (value)) { \
+ result = 0; \
+ break; \
+ } else if (!timeout) { \
+ result = -1; \
+ break; \
+ } else { \
+ DELAY(1); timeout--; \
+ } \
+ } \
+ } while (0); \
+ result;})
+
#endif /* _RT305X_SWITCHVAR_H_ */
diff -r f8392f3407da -r fd105b7d9d74 head/sys/dev/switch/rtl830x_switch.c
--- a/head/sys/dev/switch/rtl830x_switch.c Fri Dec 02 15:27:25 2011 +0200
+++ b/head/sys/dev/switch/rtl830x_switch.c Sat Dec 03 22:37:51 2011 +0200
@@ -68,10 +68,12 @@
static int get_port_speed(device_t dev, int port);
static int force_port_mode(device_t dev, int port, uint32_t mode);
+#ifdef mustbe_rewriten
static uint32_t stat_good_in_packet_count(device_t dev, int port);
static uint32_t stat_good_out_packet_count(device_t dev, int port);
static uint32_t stat_bad_in_packet_count(device_t dev, int port);
static uint32_t stat_bad_out_packet_count(device_t dev, int port);
+#endif
static int
@@ -80,6 +82,7 @@
struct child_res_avl *res;
res = device_get_ivars(dev);
+//model SWITCHFW RTL830x 0x0701 Realtek RTL8306/RTL8309
#define RTL830X_PHYMASK 0x000001ff
@@ -247,7 +250,6 @@
{
struct rtl830x_switch_softc *sc;
int idx = -1;
-// uint32_t reg;
sc = device_get_softc(dev);
@@ -258,9 +260,6 @@
mac_table_write(device_t dev, uint64_t mac, int idx, uint32_t port_map,
uint8_t age, int *hash_idx )
{
-// struct rtl830x_switch_softc *sc = device_get_softc(dev);
-// uint32_t reg;
-
return (0);
}
@@ -682,6 +681,20 @@
return (0);
}
+static void
+rtl830x_tick(device_t dev)
+{
+ struct rtl830x_switch_softc *sc;
+ uint32_t reg;
+
+ sc = device_get_softc(dev);
+ printf("tick\n");
+ reg = READ4(sc, PHY0_CTL);
+
+ return;
+}
+
+#ifdef mustbe_rewriten
static uint32_t
stat_good_in_packet_count(device_t dev, int port)
{
@@ -729,19 +742,6 @@
return (~0);
}
-static void
-rtl830x_tick(device_t dev)
-{
- struct rtl830x_switch_softc *sc;
- uint32_t reg;
-
- sc = device_get_softc(dev);
- printf("tick\n");
- reg = READ4(sc, PHY0_CTL);
-
- return;
-}
-
static uint32_t
stat_bad_in_packet_count(device_t dev, int port)
{
@@ -786,6 +786,7 @@
return (~0);
}
+#endif
static device_method_t rtl830x_switch_methods[] = {
DEVMETHOD(device_probe, rtl830x_switch_probe),
@@ -810,8 +811,6 @@
DEVMETHOD(switch_get_vid, get_vid),
DEVMETHOD(switch_set_vlanports, set_vlan_ports),
DEVMETHOD(switch_get_vlanports, get_vlan_ports),
-// DEVMETHOD(switch_set_vlanutports, set_vlan_untagged_ports),
-// DEVMETHOD(switch_get_vlanutports, get_vlan_untagged_ports),
/* Port state */
DEVMETHOD(switch_get_portlink, get_port_link),
@@ -819,11 +818,13 @@
DEVMETHOD(switch_force_mode, force_port_mode),
DEVMETHOD(switch_tick, rtl830x_tick),
+#ifdef mustbe_rewriten
/* Statistics */
DEVMETHOD(switch_good_in_cnt, stat_good_in_packet_count),
DEVMETHOD(switch_good_out_cnt, stat_good_out_packet_count),
DEVMETHOD(switch_bad_in_cnt, stat_bad_in_packet_count),
DEVMETHOD(switch_bad_out_cnt, stat_bad_out_packet_count),
+#endif
{0, 0},
};
diff -r f8392f3407da -r fd105b7d9d74 head/sys/dev/switch/rtl830x_switchreg.h
--- a/head/sys/dev/switch/rtl830x_switchreg.h Fri Dec 02 15:27:25 2011 +0200
+++ b/head/sys/dev/switch/rtl830x_switchreg.h Sat Dec 03 22:37:51 2011 +0200
@@ -1,11 +1,33 @@
+/*-
+ * Copyright (c) 2011 Aleksandr Rybalko.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
-/*
- * RO Read Only
- * LH Latch High until clear
- * RW Read/Write
- * SC Self Clearing
- * LL Latch Low until clear
- */
+#ifndef _RTL830X_SWITCHREG_H_
+#define _RTL830X_SWITCHREG_H_
enum phy_names {
PHY0 = 0,
@@ -22,41 +44,6 @@
#define ID(_phy, _reg) ((_phy)<<16 | (_reg))
-/*
-
- PHY 0 Register 0: Control
- 0.15 Reset RW/SC 1: PHY reset. This bit is self-clearing. 0
- 0.14 Loopback RW 1: Enable loopback. This will loopback TXD to RXD and 0
- (digital loopback) ignore all activity on the cable media
- 0: Normal operation
- 0.13 Speed Select RW 1: 100Mbps 1
- 0: 10Mbps
- When NWay is enabled, this bit reflects the result of auto-
- negotiation (Read only).
- When NWay is disabled, this bit is strap option
- ‘Force_Speed’ and can be configured through SMI
- (Read/Write).
- 0.12 Auto Negotiation RW 1: Enable auto-negotiation process Pin
- Enable 0: Disable auto-negotiation process En_ANEG
- This bit can be set through SMI (Read/Write). strap option
- 0.11 Power Down RW 1: Power down. All functions will be disabled except SMI 0
- function
- 0: Normal operation
- 0.10 Isolate RW 1: Electrically isolates the PHY from RMII/SMII. 0
- PHY is still able to respond to MDC/MDIO
- 0: Normal operation
- 0.9 Restart Auto RW/SC 1: Restart Auto-Negotiation process 0
- Negotiation 0: Normal operation
- 0.8 Duplex Mode RW 1: Full duplex operation 1
- 0: Half duplex operation
- When NWay is enabled, this bit reflects the result of auto-
- negotiation (Read only).
- When NWay is disabled, this bit is strap option
- ‘Force_Duplex’ and can be configured through SMI
- (Read/Write).
- */
-
-
#define PHY_CTL(p) ID(p, 0)
#define PHY0_CTL ID(PHY0, 0)
#define PHY1_CTL ID(PHY1, 0)
@@ -75,48 +62,6 @@
#define PHY_CTL_ANEG_RESTART (1<< 9)
#define PHY_CTL_FDX (1<< 8)
-/*
-7.1.2. PHY 0 Register 1: Status
- 1.15 100Base_T4 RO 0: No 100Base-T4 capability 0
- 1.14 100Base_TX_FD RO 1: 100Base-TX full duplex capable 1
- 0: Not 100Base-TX full duplex capable
- 1.13 100Base_TX_HD RO 1: 100Base-TX half duplex capable 1
- 0: Not 100Base-TX half duplex capable
- 1.12 10Base_T_FD RO 1: 10Base-TX full duplex capable 1
- 0: Not 10Base-TX full duplex capable
- 1.11 10Base_T_HD RO 1: 10Base-TX half duplex capable 1
- 0: Not 10Base-TX half duplex capable
- 1.6 MF Preamble RO The RTL8309SB will accept management frames with 1
- Suppression preamble suppressed.
- The RTL8309SB accepts management frames without
- preamble. 32 minimum preamble bits are required for the
- first SMI read/write transaction after reset. One idle bit is
- required between any two management transactions as
- defined in the IEEE 802.3u specifications.
- 1.5 Auto-negotiate RO 1: Auto-negotiation process completed. MII Reg.4, 5 are 0
- Complete valid if this bit is set
- 0: Auto-negotiation process not completed
- 1.4 Remote Fault RO/LH 1: Remote fault condition detected 0
- 0: No remote fault
- 1.3 Auto-Negotiation RO 1: NWay auto-negotiation capable (permanently=1) 1
- Ability
- 1.2 Link Status RO/LL 1: Link is established. If the link fails, this bit will be 0 until 0
- after reading this bit again
- 0: Link has failed
- 1.1 Jabber Detect RO/LH 1: Jabber detect enabled 0
- 0: Jabber detect disabled
- The jabber function is disabled in 100Base-TX operation.
- Jabber occurs when a predefined excessively long packet is
- detected for 10Base-T. When the duration of TXEN exceeds
- the jabber timer (21ms), the transmission and loopback
- function are disabled and the COL LED starts blinking. After
- TXEN goes low for more than 500 ms, the transmitter will be
- re-enabled and the COL LED will stop blinking. Jabber
- detect is supported only in 10Base-T operation.
- 1.0 Extended RO 1: Extended register capable (permanently=1) 1
- Capability
-*/
-
#define PHY_STS(p) ID(p, 1)
#define PHY0_STS ID(PHY0, 1)
#define PHY1_STS ID(PHY1, 1)
@@ -139,29 +84,6 @@
#define PHY_STS_JABBER (1<< 1)
#define PHY_STS_EXT_CAP (1<< 0)
-/*
-Note: Whenever the link ability of the RTL8309SB is reconfigured, the auto-negotiation process should be executed again to
-allow the configuration to take effect.
-7.1.3. PHY 0 Register 4: Auto-Negotiation Advertisement
- 4.15 Next Page RO 0: Next Page disabled (Permanently=0) 0
- 4.14 Acknowledge RO Permanently=0. 0
- 4.13 Remote Fault RW 1: Advertises that the RTL8309SB has detected a remote fault 0
- 0: No remote fault detected
- 4.10 Pause RW 1: Advertises that the RTL8309SB possesses 802.3x flow Pin
- control capability En_FCTRL
- 0: No flow control capability strap option
- 4.9 100Base-T4 RO Technology not supported (Permanently=0). 0
- 4.8 100Base-TX-FD RW 1: 100Base-TX full duplex capable 1
- 0: Not 100Base-TX full duplex capable
- 4.7 100Base-TX RW 1: 100Base-TX half duplex capable 1
- 0: Not 100Base-TX half duplex capable
- 4.6 10Base-T-FD RW 1: 10Base-TX full duplex capable 1
- 0: Not 10Base-TX full duplex capable
- 4.5 10Base-T RW 1: 10Base-TX half duplex capable 1
- 0: Not 10Base-TX half duplex capable
- 4.[4:0] Selector Field RO [00001]=IEEE 802.3. 00001
-*/
-
#define PHY_ANEG_ADV(p) ID(p, 4)
#define PHY0_ANEG_ADV ID(PHY0, 4)
#define PHY1_ANEG_ADV ID(PHY1, 4)
@@ -183,40 +105,6 @@
#define PHY_ANEG_ADV_SEL_FLD_SHIFT 0
#define PHY_ANEG_ADV_SEL_FLD_MASK 0x1f
-/*
-7.1.4. PHY 0 Register 5: Auto-Negotiation Link Partner Ability
- 5.15 Next Page RO 1: Link partner desires Next Page transfer 0
- 0: Link partner does not desire Next Page transfer
- 5.14 Acknowledge RO 1: Link Partner acknowledges reception of Fast Link Pulse 0
- (FLP) words
- 0: Not acknowledged by Link Partner
- 5.13 Remote Fault RO 1: Remote Fault indicated by Link Partner 0
- 0: No remote fault indicated by Link Partner
- 5.10 Pause RO 1: Flow control supported by Link Partner 0
- 0: Flow control not supported by Link Partner
- 5.9 100Base-T4 RO 1: 100Base-T4 supported by Link Partner 0
- 0: 100Base-T4 not supported by Link Partner
- 5.8 100Base-TX-FD RO 1: 100Base-TX full duplex supported by Link Partner 0
- 0: 100Base-TX full duplex not supported by Link Partner
- Note: If auto negotiation is disabled and this bit is set, Reg0.13
- and Reg0.8 will be set to 1 after link is established.
- 5.7 100Base-TX RO 1: 100Base-TX half duplex supported by Link Partner 0
- 0: 100Base-TX half duplex not supported by Link Partner
- Note: If auto negotiation is disabled and this bit is set, Reg0.13
- will be set to 1 and Reg0.8 will be set to 0 after link is
- established.
- 5.6 10Base-T-FD RO 1: 10Base-TX full duplex supported by Link Partner 0
- 0: 10Base-TX full duplex not supported by Link Partner
- Note: If auto negotiation is disabled and this bit is set, Reg0.13
- will be set to 0 and Reg0.8 will be set to 1 after link is
- established.
- 5.5 10Base-T RO 1: 10Base-TX half duplex supported by Link Partner 0
- 0: 10Base-TX half duplex not supported by Link Partner
- Note: If auto negotiation is disabled and this bit is set, Reg0.13
- and Reg0.8 will be set to 0 after a link is established.
- 5.[4:0] Selector Field RO [00001]=IEEE802.3. 00001
-*/
-
#define PHY_ANEG_PRTN(p) ID(p, 5)
#define PHY0_ANEG_PRTN ID(PHY0, 5)
#define PHY1_ANEG_PRTN ID(PHY1, 5)
@@ -238,22 +126,6 @@
#define PHY_ANEG_PRTN_SEL_FLD_SHIFT 0
#define PHY_ANEG_PRTN_SEL_FLD_MASK 0x1f
-/*
-7.1.5. PHY 0 Register 6: Auto-Negotiation Expansion
- 6.4 Parallel RO 1: A fault has been detected via the Parallel Detection function 0
- Detection Fault 0: A fault has not been detected via the Parallel Detection
- function
- 6.3 Link Partner RO 0: Link Partner is not Next Pageable (permanently=0) 0
- Next Pageable
- 6.2 Local Next RO 1: The RTL8309SB is Next Pageable 0
- Pageable 0: The RTL8309SB is not Next Pageable
- 6.1 Page Received RO 1: A New Page has been received 0
- 0: A New Page has not been received
- 6.0 Link Partner RO If NWay is enabled, this bit means: 0 (NWay)
- Auto- 1: Link Partner is Auto-Negotiation able or
- Negotiation Able 0: Link Partner is not Auto-Negotiation able 1 (Force)
-*/
-
#define PHY_ANEG_EXP(p) ID(p, 6)
#define PHY0_ANEG_EXP ID(PHY0, 6)
#define PHY1_ANEG_EXP ID(PHY1, 6)
@@ -269,84 +141,6 @@
#define PHY_ANEG_EXP_PG_RCV (1<< 1)
#define PHY_ANEG_EXP_PRTN_ANEG (1<< 0)
-/*
-7.1.6. PHY 0 Register 16: Global Control 0
- 16.[15:13] LED Mode RW 111 -> Mode 7: Speed, Duplex+Collision, Link+Act, SQI
- 110 -> Mode 6: Activity, Speed, Link, SQI
- 101 -> Mode 5: Speed, Duplex, Link+Act, SQI
- 100 -> Mode 4: Collision, Duplex, Link+Act+Speed, SQI
- 011 -> Mode 3: SQI, Duplex+Collision, Link+Act+Speed,10/100.
- 010 -> Mode 2: RxAct+10/100, TxAct+10/100, Link, SQI
- 001 -> Mode 1: Duplex+Collision, 10Link+Act, 100Link+Act, SQI
- 000 -> Mode 0: Duplex+Collision, Bi-color Speed, Bi-color Link+Act, SQI.
- 16.12 Software Reset RW/ 1: Soft reset. This bit is self-clearing 0
- SC If this bit is set to 1, the RTL8309SB will reset all registers in it
- except PHY registers and will not load configurations from
- EEPROM or strapping pins. Software reset is designed to
- provide a convenient way for users to change the configuration
- via SMI. After changing register values in the RTL8309SB
- (except PHY registers) via SMI, the external device must
- execute a soft reset in order to update the configuration by
- setting this bit to 1.
- 16.11 Disable VLAN RW 1: Disable VLAN 1
- 0: Enable VLAN. The default VLAN membership configuration
- by internal register is MII port overlapped with all the other
- ports to form 8 individual VLANs. This default membership
- configuration may be modified by setting internal registers via
- the SMI interface or EEPROM.
- 0
- 16.10 Disable 802.1Q tag RW 1: Disable 802.1Q tagged-VID Aware function. The
- aware VLAN RTL8309SB will not check the tagged VID on received frames
- to perform tagged-VID VLAN mapping. Under this
- configuration, the RTL8309SB only uses the per port VLAN
- index register to perform Port-Based VLAN mapping
- 0: Enable the Member Set Filtering function of VLAN Ingress
- Rule. The RTL8309SB checks the tagged VID on received
- frames with the VIDA[11:0]~VIDH[11:0] to index to a member
- set, then performs VLAN mapping. The RTL8309SB uses
- tagged-VID VLAN mapping for tagged frames but still uses
- port-based VLAN mapping for priority-tagged and untagged
- frames
- 16.9 Disable VLAN RW 1: The switch will not drop a received frame if the ingress port 1
- member set ingress of this packet is not included in the matched VLAN member
- filtering set. It will still forward the packet to the VLAN members
- specified in the matched member set. This setting works on
- both port-based and tag-based VLAN configurations
- 0: The switch will drop the received frame if the ingress port of
- this packet is not included in the matched VLAN member set
- 16.8 Disable VLAN tag RW 1: The switch accepts all frames it receives whether tagged or 1
- admit control untagged
- 0: The switch will only accept tagged frames and will drop
- untagged frames
- 16.7 EEPROM RO 1: EEPROM does not exist (pin EnEEPROM=0 or pin 0
- existence EnEEPROM=1 but EEPROM does not exist)
- 0: EEPROM exists (pin EnEEPROM=1 and EEPROM exists)
- 16.6 Accept Error RW 1: Filter bad packets in normal operation 1
- disable 0: Switch all packets including bad ones. This bit is intended for
- debugging purposes only
- 16.5 IEEE 802.3x RW 1: Determines when to invoke flow control based on 1
- transmit flow auto negotiation results
- control enable 0: Will not enable transmit flow control no matter what the
- auto negotiation result is
- 16.4 IEEE 802.3x RW 1: When the RTL8309SB receives a pause control frame, it has 1
- receive flow the ability to stop the next transmission of a normal frame until
- control enable the timer is expired based on the auto negotiation result
- 0: Will not receive flow control no matter what the
- auto negotiation result is
- 16.3 Broadcast input or RW 1: Broadcast input drop is selected 1
- output drop 0: Broadcast output drop is selected
- 16.2 Aging enable RW 1: Enable aging function 1
- 0: Disable aging function. The addresses learned in the lookup
- table will not be aged out. If the table is full, the last entry in the
- table will be deleted to make room for the new entry
- 16.1 Fast aging enable RW 1: Enable fast aging function. The entry learned in the lookup 0
- table will be aged out if it is not updated within an 800μs period
- 0: Disable fast aging function
- 16.0 Enable ISP MAC RW 1: Enable ISP MAC Address Translation function 0
- Address 0: Disable ISP MAC Address Translation function
- Translation
-*/
-
#define GCNTRL0 ID(PHY0, 16)
#define GCNTRL0_LED_MODE_SHIFT 13
#define GCNTRL0_LED_MODE_MASK 0xe000
@@ -364,124 +158,10 @@
#define GCNTRL0_FAST_AGN (1<<1)
#define GCNTRL0_MACAT (1<<0)
-/*
-7.1.7. PHY 0 Register 17: Global Control 1
- 17.[15:13] 802.1p base RW Classifies priority for incoming 802.1Q packets, if 802.1p 100
- priority priority classification is enabled. User priorit is compared
- against this value.
- >=: Classify as high priority
- <: Classify as low priority
- 17.12 Trunking port RW 1: Combine port 0 and 1 as one trunking port, if trunking is 1
- assignment enabled via strapping pin Dis_Trun
- 0: Combine port 6 and 7 as one trunking port, if trunking is
- enabled via strapping pin Dis_Trunk
- 17.[11:10] Queue weight RW The frame service ratio between the high priority queue and low 11
- priority queue is:
- 11=16:1
- 10=always high priority queue first
- 01=8:1
- 00=4:1
- 17.9 Disable IP priority RW 1: Compare both the source and destination IP address of 0
- for IP address [A] incoming packets against the value, IP address [A] AND IP
- mask [A], to classify packet priority
- 0: Do not compare the source or destination IP address of
- incoming packets against the value IP address [A] AND IP
- mask [A]
- 17.8 Disable IP priority RW 1: Compare both the source and destination IP address of 0
- for IP address [B] incoming packets against the value, IP address [B] AND IP
- mask [B], to classify packet priority
- 0: Do not compare the source or destination IP address of
- incoming packets against the value IP address [B] AND IP
- mask [B]
- 17.7 Enable default high RW 1: The default DiffServ code point listed below will be 1
- priority DiffServ considered as high priority code point if the DiffServ priority
- code point function is enabled.
- EF 101110
- AF 001010, 010010, 011010, 100010
- Network Control 111000, 110000
- 0: The default DiffServ code point will be considered low
- priority
-*/
#define GCNTRL1 ID(PHY0, 17)
-
-/*
-7.1.8. PHY 0 Register 18: Global Control 2
- 18.15 Enable differential RW 1: If differential service priority is enabled, this bit specifies 0
- service code point differential service code point [A] is high priority
- [A] 0: If differential service priority is enabled, this bit specifies
- differential services code point [A] is low priority
- 18.[13:8] Differential service RW Used to specify the high priority differential service code 111111
- code point [A] point A. For example, if these bits are set to 111111, incoming
- packets with a TOS field equal to 111111 will be considered
- high priority packets.
- 18.7 Enable differential RW 1: If differential service priority is enabled, this bit specifies 0
- service code point differential services code point [B] is high priority
- [B] 0: If differential service priority is enabled, this bit specifies
- differential services code point [B] is low priority
- 18.[5:0] Differential service RW Used to specify a high priority differential service code point B. 111111
- code point [B] For example, if these bits are set to 000000, incoming packets
- with a TOS field equal to 000000 will be considered high
- priority packets.
-*/
#define GCNTRL2 ID(PHY0, 18)
-
-/*
-7.1.9. PHY 0 Register 19: Global Control 3
- 19.15 Enable drop for 48 RW 1: Enable drop packet after SRAM full for 48 pass 1 1
- pass 1 0: Disable drop packet after SRAM full for 48 pass 1. This will
- result in SRAM run out
- 19.13 TX IPG RW 1: 90ppm TX IPG (InterPacketGap) compensation 1
- compensation 0: 65ppm TX IPG (InterPacketGap) compensation
- 19.12 Disable loop RW 1: Disable loop detection function 1
- detection 0: Enable loop detection function
- 19.11 Lookup table RW 1: Lookup table is accessible via indirect access registers 0
- accessible enable 0: Lookup table is not accessible
-*/
#define GCNTRL3 ID(PHY0, 19)
-/*
-7.1.10. PHY 0 Register 22: Port 0 Control 0
- 22.13 Local loopback RW 1: Perform local loopback, i.e. loop MACs RX back to TX 0
- 0: Normal operation
- 22.12 Null VID RW 1: The switch will replace a NULL VID with a port VID (12 0
- replacement bits)
- 0: No replacement for a NULL VID
- 22.11 Discard Non PVID RW 1: If the received packets are tagged, the switch will discard 0
- packets packets with a VID that does not match the ingress port default
- VID, which is indexed by port 0 Port-based VLAN ind
- 0: No packets will be dropped
- 22.10 Disable 802.1p RW 1: Disable 802.1p priority classification for ingress packets on Pin
- Dis_VLAN_Pri
- priority port 0
- strap option
- 0: Enable 802.1p priority classification
- Default = 1
- 22.9 Disable Diffserv RW 1: Disable Diffserv priority classification for ingress packets on Pin
- priority port 0 Dis_DS_Pri
- 0: Enable Diffserv priority classification strap option
- Default = 1
- 22.8 Disable port-based RW 1: Disable port priority function Pin
- priority 0: Enable port priority function. Ingress packets from port 0 will Sel_Port_Pri
- be classified as high priority strap option
- Default = 1
- 11
- 22[1:0] VLAN tag RW 11=Do not insert or remove VLAN tags to/from packets sent
- insertion and out from this port.
- removal 10=The switch will add VLAN tags to packets if they are not
- tagged. The switch will not add tags to packets already tagged.
- The inserted tag is the ingress portsDefault t, which is
- indexed by port 0s Port-based VLAN index.
- 01=The switch will remove VLAN tags from packets, if they
- are tagged when these packets are send out from port 0. The
- switch will not modify packets received without tags.
- 00=The switch will remove VLAN tags from packets then add
- new tags to them. The inserted tag is the ingress ports Default
- tag, which is indexed by port 0s Port-based VLAN index.
- This is a replacement processing for tagged packets and an
- insertion for untagged packets.
-*/
-
-
#define PHY_CTRL0(p) ID(p, 22)
#define PHY0_CTRL0 ID(PHY0, 22)
#define PHY1_CTRL0 ID(PHY1, 22)
@@ -504,23 +184,6 @@
#define CTRL0_TAG_R_TG 1 /* Remove Tag on Egress */
#define CTRL0_TAG_IR 0 /* Insert or Replace Tag */
-
-/*
-7.1.11. PHY 0 Register 23: Port 0 Control 1
- 23.11 Transmission RW 1: Enable packet transmission on port 0 1
- enable 0: Disable packet transmission on port 0
- 23.10 Reception enable RW 1: Enable packet reception on port 0 1
- 0: Disable packet reception on port 0
- 23.9 Learning enable RW 1: Enable switch address learning capability 1
- 0: Disable switch address learning capability
- 23.8 Loop status RO 1: A loop has been detected on port 0 0
- 0: No loop exists on port 0
- 23[7:4] Link quality RO 4-bit field indicating the link quality of the receive twisted-pair
- or fiber link.
- 0000: Highest link quality
- 1111: Lowest link quality
-*/
-
#define PHY_CTRL1(p) ID(p, 23)
#define PHY0_CTRL1 ID(PHY0, 23)
#define PHY1_CTRL1 ID(PHY1, 23)
@@ -538,9 +201,6 @@
#define CTRL1_LQ_MASK 0x00f0
#define CTRL1_LQ_SHIFT 4
-
-
-
#define PORT_PVID(p) ID((PHY0+p), 24)
#define VLAN_MEMB(v) ID((PHY0+v), 24)
#define VLAN_ID(v) ID((PHY0+v), 25)
@@ -562,250 +222,5 @@
#define VLAN_A_MEMB_SHIFT 0
#define VLAN_A_MEMB_MASK 0x01ff
-/*
-7.2.6. PHY 1 Register 16~17: IP Priority Address [A]
- 16 IP Address [A] RW The switch will compare both the source and destination IP 0xFFFF
- [31:16] addresses of an incoming packet against the value, IP address
- [A] AND IP mask [A], to classify priority for the packet.
- 17 IP Address [A] RW The switch will both compare the source and destination IP 0xFFFF
- [15:0] addresses of an incoming packet against the value, IP address
- [A] AND IP mask [A], to classify priority for the packet.
-*/
-/*
-7.2.7. PHY 1 Register 18~19: IP Priority Address [B]
- 18 IP Address [B] RW The switch will compare both the source and destination IP 0xFFFF
- [31:16] addresses of an incoming packet against the value, IP address
- [B] AND IP mask [B], to classify priority for the packet, if IP
- priority for IP address [B] is enabled.
- 19 IP Address [B] RW The switch will compare both the source and destination IP 0xFFFF
- [15:0] addresses of an incoming packet against the value, IP address
- [B] AND IP mask [B], to classify priority for the packet, if IP
- priority for IP address [B] is enabled.
+#endif /* _RTL830X_SWITCHREG_H_ */
-*/
-/*
-7.3.6. PHY 2 Register 16~17: IP Priority Mask [A]
- 16 IP Mask [A] RW The switch will compare both the source and destination IP 0xFFFF
- [31:16] addresses of an incoming packet against the value, IP address
- [A] AND IP mask [A], to classify priority for the packet.
- 17 IP Mask [A] [15:0] RW The switch will compare both the source and destination IP 0xFFFF
- addresses of an incoming packet against the value, IP address
- [A] AND IP mask [A], to classify priority for the packet.
-*/
-/*
-7.3.7. PHY 2 Register 18~19: IP Priority Mask [B]
- 18 IP Mask [B] RW The switch will compare both the source and destination IP 0xFFFF
- [31:16] addresses of an incoming packet against the value, IP address
- [B] AND IP mask [B], to classify priority for the packet, if IP
- priority for IP address [B] is enabled.
- 19 IP Mask [B] [15:0] RW The switch will compare both the source and destination IP 0xFFFF
- addresses of an incoming packet against the value, IP address
- [B] AND IP mask [B], to classify priority for the packet, if IP
- priority for IP address [B] is enabled.
- 0010
-*/
-/*
-7.4.6. PHY 3 Register 16~18: Switch MAC Address
-The Switch MAC address is used as the source address in MAC pause control frames.
- 16 Switch MAC RW 16.[15:8] = Switch MAC Address Byte 4. 0x5452
- Address [47:32] 16.[7:0] = Switch MAC Address Byte 5.
- 17 Switch MAC RW 17.[15:8] = Switch MAC Address Byte 2. 0x834C
- Address [31:16] 17.[7:0] = Switch MAC Address Byte 3.
- 18 Switch MAC RW 18.[15:8] = Switch MAC Address Byte 0. 0xB009
- Address [15:0] 18.[7:0] = Switch MAC Address Byte 1.
-*/
-/*
-7.5.6. PHY 4 Register 16~18: ISP MAC Address
-The ISP’s MAC address is used as the source address in MAC address translation functions.
- Reg.bit Name Mode Description Default
- 16 ISP MAC Address RW 16.[15:8] = ISP MAC Address Byte 1. 0x4205
- [15:0] 16.[7:0] = ISP MAC Address Byte 0.
- 17 ISP MAC Address RW 17.[15:8] = ISP MAC Address Byte 3. 0x212F
- [31:16] 17.[7:0] = ISP MAC Address Byte 2.
- 18 ISP MAC Address RW 18.[15:8] = ISP MAC Address Byte 5. 0x5C91
- [47:32] 18.[7:0] = ISP MAC Address Byte 4.
-*/
-/*
-7.6.6. PHY 5 Register 16: MII Port Control 0
- 16.15 Transmission RW 1: Enable packet transmission on MII interface 1
- enable 0: Disable packet transmission on MII interface
- 16.14 Reception enable RW 1: Enable packet reception on MII interface 1
- 0: Disable packet reception on MII interface
- 16.13 Learning enable RW 1: Enable switch address learning capability 1
- 0: Disable switch address learning capability
- 16.12 Enable MII RW 1: Enable local loop back function. The switch will only 0
- loopback forward local and broadcast packets from the input of MII RX
- to the output of MII TX, and will drop unicast packets from the
- input of MII RX. The other ports still can forward packets to the
- MII port
- 0: Disable local loop back function
- 16.11 Disable 802.1p RW 1: Disable 802.1p priority classification for ingress packets on Pin Dis_VLAN_Pri strap option
- priority port 8
- 0: Enable 802.1p priority classification
- Default = 1
- 16.10 Disable Diffserv RW 1: Disable Diffserv priority classification for ingress packets on Pin Dis_DS_Pri strap option
- priority port 8
- 0: Enable Diffserv priority classification
- Default = 1
- 16.9 Disable port-based RW 1: Disable port priority function Pin
- priority 0: Enable port priority function. Ingress packets from port 8 will Sel_Port_Pri
- be classified as high priority strap option
- Default = 1
- 11
- 16.[1:0] VLAN tag RW 11=Do not insert or remove VLAN tags to/from packets sent
- insertion and out from this port.
- removal 10=The switch will add VLAN tags to packets if they are not
- tagged. The switch will not add tags to packets already tagged.
- The inserted tag is the ingress port’s ‘Default tag’, which is
- indexed by the MII port’s ‘Port-based VLAN index’.
- 01=The switch will remove VLAN tags from packets, if they
- are tagged when these packets are send out from MII port. The
- switch will not modify packets received without tags.
- 00=The switch will remove VLAN tags from packets then add
- new tags to them. The inserted tag is the ingress port’s ‘Default
- tag’, which is indexed by MII port’s ‘Port-based VLAN index’.
- This is a replacement processing for tagged packets and an
- insertion for untagged packets.
-*/
-/*
-7.6.7. PHY 5 Register 17: MII Port Control 1 & VLAN Entry [I]
- 17.15 Null VID RW 1: The switch will replace a NULL VID with a port VID 0
- replacement (12 bits)
- 0: No replacement for a NULL VID
- 17.14 Discard Non- RW 1: If the received packets are tagged, the switch will discard 0
- PVID packets packets with a VID that does not match the ingress port default
- VID, which is indexed by the MII port’s ‘Port-based VLAN
- index’
- 0: No packets will be dropped
- 0000
-*/
-/*
-7.6.9. PHY 5 Register 19: CPU Port & WAN Port
- 19.[7:4] WAN Port RW Specify the WAN port on the RTL8309SB. 0111
- 1000=MII Port is WAN Port
- 0111=Port 7 is WAN Port 0110=Port 6 is WAN Port
- 0101=Port 5 is WAN Port 0100=Port 4 is WAN Port
- 0011=Port 3 is WAN Port 0010=Port 2 is WAN Port
- 0001=Port 1 is WAN Port 0000=Port 0 is WAN Port
- 19.[3:0] CPU Port RW Specify the CPU port on the RTL8309SB. 0000
- 1000=MII Port is CPU Port
- 0111=Port 7 is CPU Port 0110=Port 6 is CPU Port
- 0101=Port 5 is CPU Port 0100=Port 4 is CPU Port
- 0011=Port 3 is CPU Port 0010=Port 2 is CPU Port
- 0001=Port 1 is CPU Port 0000=Port 0 is CPU Port
-*/
-/*
-7.8.6. PHY 7 Register 16: indirect Access Control
-PHY 7 register 16 is used for reading or writing data to the MAC address table.
- 16.1 Command RW 1: Trigger a command to read or write the lookup table 0
- execution 0: Indicates this command has completed
- 16.0 Read or write RW 1: Read cycle 0
- operation 0: Write cycle
-*/
-/*
-7.8.7. PHY 7 Register 17~20: Indirect Access Data
- 17 Indirect Data RW Bit 63~48 of indirect data. 0x00
- [63:48] Indirect Data [54] = If this bit is 1, indicates this entry is static
- and will never be aged out. If this bit is 0, indicates this entry is
- dynamically learned, aged, updated, and deleted.
- Indirect Data [53:52] = 2-bit counter for internal aging.
- Indirect Data [51:48] = The source port of this Source MAC
- Address is learned.
- 18 Indirect Data RW Bit 47~32 of indirect data. 0x00
- [47:32] Indirect Data [47:40] = Source MAC Address [39:32].
- Indirect Data [39:32] = Source MAC Address [47:40].
- 19 Indirect Data RW Bit 31~16 of indirect data. 0x00
- [31:16] Indirect Data [31:24] = Source MAC Address [23:16].
- Indirect Data [23:16] = Source MAC Address [31:24].
- 0x00
- 20 Indirect Data RW Bit 15~0 of indirect data.
- [15:0] Indirect Data [15:8] = Source MAC Address [7:0].
- Indirect Data [7:0] = Source MAC Address [15:8].
- Bits 1~0 and Bits 15~8 of this register also determine the
- address of data in the lookup table.
- In a write cycle: Bits 1~0 and Bits 15~8 indirectly map to an
- entry in the lookup table. The written data should be filled in
- Indirect Data [63:0]
- In a read cycle: Bits 1~0 and Bits 15~8 indirectly map to an
- entry in the lookup table. The read back data will be shown in
- Indirect Data [63:0].
-
- 0111
-*/
-/*
-7.9.1. PHY 8 Register 0: Control
-Note: This register only works in MII PHY and SNI PHY mode. In MII MAC mode, these registers have no meaning.
- Table 104. PHY 8 Register 0: Control
- Reg.bit Name Mode Description Default
- 0.15 Reset RO 0: No reset allowed (permanently=0) 0
- 0.14 Loopback RO 0: Normal operation (permanently=0) 0
- (digital loopback)
- 0.13 Speed Select RW 1: 100Mbps Pin MII_SPD
- 0: 10Mbps _STA strap
- When NWay is enabled, this bit reflects the result of auto- option
- negotiation (Read only).
- When NWay is disabled, this bit can be set through SMI
- (Read/Write).
- 0.12 Auto Negotiation RW 1: Enable auto-negotiation process 1
- Enable 0: disable auto-negotiation process
- This bit can be set through SMI (Read/Write).
- 0.11 Power Down RO 0: Normal operation (permanently=0) 0
- 0.10 Isolate RO 0: Normal operation (permanently=0) 0
- 0.9 Restart Auto RO 0: Normal operation (permanently=0) 0
- Negotiation
- 0.8 Duplex Mode RW 1: Full duplex operation Pin MII_DUP
- 0: Half duplex operation _STA strap
- When NWay is enabled, this bit reflects the result of auto- option
- negotiation (Read only).
- When NWay is disabled, this bit may be set through SMI
- (Read/Write).
-*/
-/*
-7.9.2. PHY 8 Register 1: Status
-Note: This register only works in MII PHY and SNI PHY mode. In MII MAC mode, these registers have no meaning.
- Table 105. PHY 8 Register 1: Status
- Reg.bit Name Mode Description Default
- 1.15 100Base_T4 RO 0: No 100Base-T4 capability 0
- 1.14 100Base_TX_FD RO 1: 100Base-TX full duplex capable (permanently=1) 1
- 1.13 100Base_TX_HD RO 1: 100Base-TX half duplex capable (permanently=1) 1
- 1.12 10Base_T_FD RO 1: 10Base-TX full duplex capable (permanently=1) 1
- 1.11 10Base_T_HD RO 1: 10Base-TX half duplex capable (permanently=1) 1
- 1.6 MF Preamble RO The RTL8309SB will accept management frames with 1
- Suppression preamble suppressed (permanently=1)
- 1.5 Auto-negotiate RO 1: Auto-negotiation process completed. MII Reg.4, 5 are valid if 1
- Complete this bit is set (permanently=1)
- 1.4 Remote Fault RO 0: No remote fault (permanently=0) 0
- 1.3 Auto-Negotiation RO 1: NWay auto-negotiation capable (permanently=1) 1
- Ability
- 1.2 Link Status RO 1: Link is established. If the link should ever fail, this bit will be Pin MII_LNK
- 0 until after reading this bit again _STA# strap
- 0: Link failed option
- 1.1 Jabber Detect RO 0: No Jabber detected (permanently=0) 0
- 1.0 Extended RO 1: Extended register capable (permanently=1) 1
- Capability
-*/
-/*
-7.9.3. PHY 8 Register 4: Auto-Negotiation Advertisement
-Note: This register only works in MII PHY and SNI PHY mode. In MII MAC mode, these registers have no meaning.
- Table 106. PHY 8 Register 4: Auto-Negotiation Advertisement
- Reg.bit Name Mode Description Default
- 4.15 Next Page RO 1: Next Page enabled 0
- 0: Next Page disabled (Permanently=0)
- 4.14 Acknowledge RO Permanently=0 0
- 4.13 Remote Fault RO 1: Advertises that the RTL8309S has detected a remote fault 0
- 0: No remote fault detected
- 4.10 Pause RW 1: Advertises that the RTL8309SB possesses 802.3x flow Pin
- control capability MII_FCTRL
- 0: No flow control capability _STA strap
- option
- 4.9 100Base-T4 RO Technology not supported (Permanently=0). 0
- 4.8 100Base-TX-FD RW 1: 100Base-TX full duplex capable 1
- 0: Not 100Base-TX full duplex capable
- 4.7 100Base-TX RW 1: 100Base-TX half duplex capable 1
- 0: Not 100Base-TX half duplex capable
- 4.6 10Base-T-FD RW 1: 10Base-TX full duplex capable 1
- 0: Not 10Base-TX full duplex capable
- 4.5 10Base-T RW 1: 10Base-TX half duplex capable 1
- 0: Not 10Base-TX half duplex capable
- 4.[4:0] Selector Field RO [00001]=IEEE 802.3. 00001
-*/
diff -r f8392f3407da -r fd105b7d9d74 head/sys/dev/switch/rtl830x_switchvar.h
--- a/head/sys/dev/switch/rtl830x_switchvar.h Fri Dec 02 15:27:25 2011 +0200
+++ b/head/sys/dev/switch/rtl830x_switchvar.h Sat Dec 03 22:37:51 2011 +0200
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2010 Aleksandr Rybalko.
+ * Copyright (c) 2011 Aleksandr Rybalko.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff -r f8392f3407da -r fd105b7d9d74 head/sys/dev/switch/switch.c
--- a/head/sys/dev/switch/switch.c Fri Dec 02 15:27:25 2011 +0200
+++ b/head/sys/dev/switch/switch.c Sat Dec 03 22:37:51 2011 +0200
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2011, Aleksandr Rybalko
+ * Copyright (c) 2010-2011, Aleksandr Rybalko
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -47,7 +47,24 @@
#include "switch_if.h"
#include "switchb_if.h"
+#define CREATE_CHILD_MDIO_BUS
+#ifdef CREATE_CHILD_MDIO_BUS
+#include <sys/socket.h>
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/ethernet.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/if_types.h>
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+
+//MODULE_DEPEND(arge, ether, 1, 1, 1);
+//MODULE_DEPEND(arge, miibus, 1, 1, 1);
+
+#include "miibus_if.h"
+#endif
static d_open_t switch_open;
static d_close_t switch_close;
@@ -340,6 +357,14 @@
break;
}
break;
+ case IOCTL_SWITCH_RESETSUB:
+ ret = SWITCH_RESET_SUBSYS(sc->child, *((uint32_t *)kdata));
+ if (ret) {
+ device_printf(sc->sc_dev, "SWITCH_RESET_SUBSYS return error\n");
+ /* XXX: handle error */
+ break;
+ }
+ break;
case IOCTL_VLAN_CONFIG:
ret = vlan_config_sub(sc, (struct vlan_config *)kdata);
if (ret) {
@@ -371,17 +396,117 @@
return (ret);
}
+#ifdef CREATE_CHILD_MDIO_BUS
+int
+switch_miibus_writereg(device_t dev, int phy, int reg, int value)
+{
+ struct switch_softc *sc;
+
+ sc = device_get_softc(dev);
+ if (sc || !sc->child)
+ return (0);
+ return (SWITCH_MIIBUS_WRITEREG(sc->child, phy, reg, value));
+}
+
+int
+switch_miibus_readreg(device_t dev, int phy, int reg)
+{
+ struct switch_softc *sc;
+
+ sc = device_get_softc(dev);
+ if (sc || !sc->child)
+ return (0);
+ return (SWITCH_MIIBUS_READREG(sc->child, phy, reg));
+}
+
+void
+switch_miibus_statchg(device_t dev)
+{
+ struct switch_softc *sc;
+ struct mii_data *mii;
+
+ sc = device_get_softc(dev);
+ mii = device_get_softc(sc->child_miibus);
+
+ if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
+ (IFM_ACTIVE | IFM_AVALID)) {
+ switch (IFM_SUBTYPE(mii->mii_media_active)) {
+ case IFM_10_T:
+ case IFM_100_TX:
+ /* XXX check link here */
+ //sc->flags |= 1;
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+/*
+ * Set media options.
+ */
+static int
+switch_ifmedia_upd(struct ifnet *ifp)
+{
+#ifdef notyet
+ struct rt_softc *sc;
+ struct mii_data *mii;
+ int error = 0;
+
+ sc = ifp->if_softc;
+ RT_SOFTC_LOCK(sc);
+
+ mii = device_get_softc(sc->child_miibus);
+ if (mii->mii_instance) {
+ struct mii_softc *miisc;
+ for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
+ miisc = LIST_NEXT(miisc, mii_list))
+ mii_phy_reset(miisc);
+ }
+ if (mii)
+ error = mii_mediachg(mii);
+ RT_SOFTC_UNLOCK(sc);
+
+ return (error);
+#endif
+ return (0);
+}
+
+/*
+ * Report current media status.
+ */
+static void
+switch_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
+{
+#ifdef notyet
+ struct rt_softc *sc;
+ struct mii_data *mii;
+
+ sc = ifp->if_softc;
+
+ RT_SOFTC_LOCK(sc);
+ mii = device_get_softc(sc->child_miibus);
+ mii_pollstat(mii);
+ ifmr->ifm_active = mii->mii_media_active;
+ ifmr->ifm_status = mii->mii_media_status;
+ ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
+ ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
+ RT_SOFTC_UNLOCK(sc);
+#endif
+}
+#endif /* CREATE_CHILD_MDIO_BUS */
+
int
switch_init(struct switch_softc *sc)
{
- char *var;
+ char *var;
+ int error;
if (sc->child) {
device_printf(sc->sc_dev, "Only one child allowed\n");
return (ENXIO);
}
-
sc->args = malloc(sizeof(struct child_res_avl), M_DEVBUF, M_NOWAIT);
if (sc->args == NULL)
return (1);
@@ -423,6 +548,27 @@
"switch%d", device_get_unit(sc->sc_dev));
sc->sc_cdev->si_drv1 = sc;
+#ifdef CREATE_CHILD_MDIO_BUS
+ sc->ifp = if_alloc(IFT_OTHER);
+ if_initname(sc->ifp, device_get_name(sc->sc_dev),
+ device_get_unit(sc->sc_dev));
+// sc->ifp->if_init = rt_init;
+// sc->ifp->if_ioctl = rt_ioctl;
+// sc->ifp->if_start = rt_start;
+ sc->ifp->if_mtu = 0;
+ IFQ_SET_MAXLEN(&sc->ifp->if_snd, 0);
+ sc->ifp->if_snd.ifq_drv_maxlen = 0;
+ IFQ_SET_READY(&sc->ifp->if_snd);
+
+
+ error = mii_attach(sc->sc_dev, &sc->child_miibus, sc->ifp,
+ switch_ifmedia_upd, switch_ifmedia_sts,
+ BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
+ if (error != 0) {
+ device_printf(sc->sc_dev, "attaching PHYs failed\n");
+ }
+#endif
+
return (0);
}
@@ -441,7 +587,7 @@
switch_tick(struct switch_softc *sc)
{
-// SWITCH_TICK(sc->child);
+ SWITCH_TICK(sc->child);
return (0);
}
diff -r f8392f3407da -r fd105b7d9d74 head/sys/dev/switch/switch_gpio.c
--- a/head/sys/dev/switch/switch_gpio.c Fri Dec 02 15:27:25 2011 +0200
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,33 +0,0 @@
-/*-
- * Copyright (c) 2011, Aleksandr Rybalko <ray at ddteam.net>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-/*
- * switch control attached to GPIO
- */
-
diff -r f8392f3407da -r fd105b7d9d74 head/sys/dev/switch/switch_if.m
--- a/head/sys/dev/switch/switch_if.m Fri Dec 02 15:27:25 2011 +0200
+++ b/head/sys/dev/switch/switch_if.m Sat Dec 03 22:37:51 2011 +0200
@@ -1,5 +1,5 @@
#-
-# Copyright (c) 2011 Aleksandr Rybalko <ray at ddteam.net>
+# Copyright (c) 2010-2011 Aleksandr Rybalko <ray at ddteam.net>
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -129,11 +129,13 @@
return (0);
}
+#ifdef mustbe_rewriten
static uint32_t
null_stat (device_t dev, int port)
{
return (0);
}
+#endif
static void
null_tick (device_t dev)
@@ -152,6 +154,12 @@
{
return (0xffff);
}
+ static int
+ null_reset_subsys(device_t dev, int subsys)
+ {
+
+ return (0);
+ }
};
#
@@ -333,37 +341,38 @@
uint32_t mode;
} DEFAULT null_force_mode;
-#
-# Get count of good packets on port input
-#
-METHOD uint32_t good_in_cnt {
- device_t dev;
- int port;
-} DEFAULT null_stat;
-
-#
-# Get count of good packets on port output
-#
-METHOD uint32_t good_out_cnt {
- device_t dev;
- int port;
-} DEFAULT null_stat;
-
-#
-# Get count of bad packets on port input
-#
-METHOD uint32_t bad_in_cnt {
- device_t dev;
- int port;
-} DEFAULT null_stat;
-
-#
-# Get count of bad packets on port output
-#
-METHOD uint32_t bad_out_cnt {
- device_t dev;
- int port;
-} DEFAULT null_stat;
+## XXX: must be rewriten
+## #
+## # Get count of good packets on port input
+## #
+## METHOD uint32_t good_in_cnt {
+## device_t dev;
+## int port;
+## } DEFAULT null_stat;
+##
+## #
+## # Get count of good packets on port output
+## #
+## METHOD uint32_t good_out_cnt {
+## device_t dev;
+## int port;
+## } DEFAULT null_stat;
+##
+## #
+## # Get count of bad packets on port input
+## #
+## METHOD uint32_t bad_in_cnt {
+## device_t dev;
+## int port;
+## } DEFAULT null_stat;
+##
+## #
+## # Get count of bad packets on port output
+## #
+## METHOD uint32_t bad_out_cnt {
+## device_t dev;
+## int port;
+## } DEFAULT null_stat;
#
# Give a chance to update something
@@ -372,4 +381,11 @@
device_t dev;
} DEFAULT null_tick;
+#
+# Reset/clear some subsystem
+#
+METHOD int reset_subsys {
+ device_t dev;
+ int subsys;
+} DEFAULT null_reset_subsys;
diff -r f8392f3407da -r fd105b7d9d74 head/sys/dev/switch/switch_ioctl.h
--- a/head/sys/dev/switch/switch_ioctl.h Fri Dec 02 15:27:25 2011 +0200
+++ b/head/sys/dev/switch/switch_ioctl.h Sat Dec 03 22:37:51 2011 +0200
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2011, Aleksandr Rybalko <ray at ddteam.net>
+ * Copyright (c) 2010-2011, Aleksandr Rybalko <ray at ddteam.net>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -89,6 +89,18 @@
#define SWITCH_SETREG SWITCH_IOCTL_MAIN_BASE+3
#define IOCTL_SWITCH_SETREG _IOWR('E', SWITCH_SETREG, struct switch_reg)
+#define SWITCH_RESETSUB SWITCH_IOCTL_MAIN_BASE+4
+#define IOCTL_SWITCH_RESETSUB _IOWR('E', SWITCH_RESETSUB, uint32_t)
+#define SWITCH_RESETSUB_MASK 0x000000ff
+#define SWITCH_RESETSUB_SWITCH 1
+#define SWITCH_RESETSUB_PORT 2
+#define SWITCH_RESETSUB_VLANS 3
+#define SWITCH_RESETSUB_QOS 4
+/* If we doing reset for ports, then store port number at upper location */
+#define SWITCH_RESETSUB_ALLPORTS 0x0000ff00
+#define SWITCH_RESETSUB_PORT_MASK 0x0000ff00
+#define SWITCH_RESETSUB_PORT_SHIFT 8
+
enum vlan_type_e {
VLAN_TYPE_NONE = 0,
diff -r f8392f3407da -r fd105b7d9d74 head/sys/dev/switch/switch_mii.c
--- a/head/sys/dev/switch/switch_mii.c Fri Dec 02 15:27:25 2011 +0200
+++ b/head/sys/dev/switch/switch_mii.c Sat Dec 03 22:37:51 2011 +0200
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2009, M. Warner Losh
+ * Copyright (c) 2011, Aleksandr Rybalko
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -73,6 +73,10 @@
DEVMETHOD(switchb_read4, switch_mii_read4),
DEVMETHOD(switchb_write4, switch_mii_write4),
+ /* Child MDIO bus interface */
+ DEVMETHOD(miibus_readreg, switch_miibus_readreg),
+ DEVMETHOD(miibus_writereg, switch_miibus_writereg),
+ DEVMETHOD(miibus_statchg, switch_miibus_statchg),
{ 0, 0 }
};
@@ -85,6 +89,7 @@
};
DRIVER_MODULE(switch, miibus, switch_mii_driver, switch_mii_devclass, 0, 0);
+DRIVER_MODULE(switch, mii, switch_mii_driver, switch_mii_devclass, 0, 0);
static int switch_mii_service(struct mii_softc *, struct mii_data *, int);
static void switch_mii_status(struct mii_softc *);
@@ -99,31 +104,13 @@
static int
switch_mii_probe(device_t dev)
{
- const char *iface;
- const char *pparent;
- /* Get NIC name */
- pparent = device_get_nameunit(
- device_get_parent(
- device_get_parent(dev)));
-
- device_printf(dev, "Parent iface is %s\n", pparent);
-
- /* Get iface name hint */
- if (!resource_string_value(device_get_name(dev),
- device_get_unit(dev),
- "iface", (const char **)&iface)) {
- /* If interface name hinted, check it */
- if (strcmp(pparent, iface) != 0)
- /* Skip interface if not matched */
- return (ENXIO);
-
- /* Attach to interface if matched */
- } else
- return (ENXIO);
-
- return (BUS_PROBE_SPECIFIC);
-// return (BUS_PROBE_DEFAULT);
+ /*
+ * switch_mii have problems with autodeteaction, so attached
+ * dirrectly ny hint. Return just BUS_PROBE_GENERIC, so some more
+ * specific device will have a chance if concurrent.
+ */
+ return (BUS_PROBE_GENERIC);
}
static int
@@ -170,14 +157,10 @@
ma = device_get_ivars(dev);
- /* XXXXXX */
- if (device_get_unit(device_get_parent(device_get_parent(dev))) == 0) {// arge0
- sc->mii_capabilities = BMSR_100TXFDX|BMSR_100TXHDX;
- sc->mii_extcapabilities = 0;
- } else {
- sc->mii_capabilities = BMSR_100TXFDX|BMSR_100TXHDX|BMSR_EXTCAP;
- sc->mii_extcapabilities = EXTSR_1000TFDX|EXTSR_1000THDX;
- }
+ /* XXX: better to ask attached switch driver about supported media */
+ sc->mii_capabilities = BMSR_100TXFDX | BMSR_100TXHDX | BMSR_EXTCAP;
+ sc->mii_extcapabilities = EXTSR_1000TFDX | EXTSR_1000THDX |
+ EXTSR_1000XFDX | EXTSR_1000XHDX;
device_printf(dev, " ");
mii_phy_add_media(sc);
@@ -210,6 +193,8 @@
static int
switch_mii_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
{
+ struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
+ struct switch_mii_softc *ssc = (struct switch_mii_softc *)sc;
switch (cmd) {
case MII_POLLSTAT:
@@ -222,13 +207,43 @@
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
break;
- mii_phy_setmedia(sc);
+ /* Accept assigned media types */
+ /* Should check if attached switch support it */
+ switch (IFM_SUBTYPE(ife->ifm_media)) {
+ case IFM_AUTO:
+ mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
+ mii->mii_media_active = IFM_ETHER | IFM_1000_T |
+ (ife->ifm_media & IFM_FDX)?IFM_FDX:IFM_HDX;
+ break;
+ case IFM_1000_T:
+ mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
+ mii->mii_media_active = IFM_ETHER | IFM_1000_T |
+ (ife->ifm_media & IFM_FDX)?IFM_FDX:IFM_HDX;
+ break;
+ case IFM_100_TX:
+ mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
+ mii->mii_media_active = IFM_ETHER | IFM_100_TX |
+ (ife->ifm_media & IFM_FDX)?IFM_FDX:IFM_HDX;
+ break;
+ case IFM_10_T:
+ mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
+ mii->mii_media_active = IFM_ETHER | IFM_10_T |
+ (ife->ifm_media & IFM_FDX)?IFM_FDX:IFM_HDX;
+ break;
+ case IFM_NONE:
+ /* XXX */
+ mii->mii_media_status = IFM_AVALID;
+ mii->mii_media_active = IFM_ETHER | IFM_1000_T |
+ (ife->ifm_media & IFM_FDX)?IFM_FDX:IFM_HDX;
+ break;
+ default:
+ return (EINVAL);
+ }
break;
case MII_TICK:
- //switch_tick(sc);
- if (mii_phy_tick(sc) == EJUSTRETURN)
- return (0);
+ /* Call switch to do periodic work */
+ switch_tick(&ssc->sc_switch);
break;
}
@@ -244,19 +259,21 @@
switch_mii_status(struct mii_softc *sc)
{
struct mii_data *mii = sc->mii_pdata;
-// struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
- /* XXX: always Up */
- mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
- if (sc->mii_extcapabilities & (EXTSR_1000TFDX|EXTSR_1000THDX)) {
- mii->mii_media_active = IFM_ETHER | IFM_1000_T | IFM_FDX; //AR8216
- } else { //arge1
- mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; //RTL8309
+ /* if not up, set to default */
+ if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) !=
+ (IFM_AVALID | IFM_ACTIVE)) {
+ mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
+ /* If we support 1000base */
+ if (sc->mii_extcapabilities &
+ (EXTSR_1000TFDX|EXTSR_1000THDX))
+ mii->mii_media_active = IFM_ETHER|IFM_1000_T|IFM_FDX;
+ else
+ mii->mii_media_active = IFM_ETHER|IFM_100_TX|IFM_FDX;
}
}
-
static uint32_t
switch_mii_read4(device_t dev, uint32_t r)
{
@@ -286,17 +303,6 @@
-
-
-
-
-
-
-
-
-
-
-
static int plumbphy_probe(device_t dev);
static int plumbphy_attach(device_t dev);
@@ -332,35 +338,8 @@
static int
plumbphy_probe(device_t dev)
{
- struct mii_attach_args *ma;
- struct mii_softc *sc;
- sc = device_get_softc(dev);
- if (!sc)
- return (ENXIO);
-
-// device_printf(dev, "Parent iface is %s\n",
-// device_get_name(device_get_parent(device_get_parent(dev))));
-
- /* XXX */
- if (strcmp(device_get_name(device_get_parent(device_get_parent(dev))),
- "arge") != 0)
- return (ENXIO);
-
- ma = device_get_ivars(dev);
-
- /* XXXXXXXXXXXXXX */
- if (device_get_unit(device_get_parent(device_get_parent(dev))) == 0) {// arge0
- /* Plumb only PHYs great than 0 */
- if ( ma->mii_phyno > 0 )
- return (BUS_PROBE_GENERIC);
- } else { //arge1
- /* Plumb only PHYs great than 0 */
- if ( ma->mii_phyno > 16 )
- return (BUS_PROBE_GENERIC);
- }
-
- return (ENXIO);
+ return (BUS_PROBE_GENERIC);
}
static int
@@ -372,12 +351,15 @@
sc = device_get_softc(dev);
ma = device_get_ivars(dev);
mii_phy_dev_attach(dev, 0, &plumbphy_funcs, 0);
-// mii_phy_setmedia(sc);
- sc->mii_capabilities = BMSR_100TXFDX;// & ma->mii_capmask;
+ sc->mii_capabilities = BMSR_100TXFDX | BMSR_100TXHDX | BMSR_EXTCAP;
+ sc->mii_extcapabilities = EXTSR_1000TFDX | EXTSR_1000THDX |
+ EXTSR_1000XFDX | EXTSR_1000XHDX;
+
device_printf(dev, " ");
mii_phy_add_media(sc);
printf("\n");
+
return (0);
}
@@ -408,11 +390,23 @@
plumbphy_status(struct mii_softc *sc)
{
struct mii_data *mii = sc->mii_pdata;
+ device_t switch_drv, switchdev;
+
+ /* Use hint hint.plumbphy.0.master="ar8x16_switch0" */
+ /* XXX */
+ switch_drv = devclass_get_device(devclass_find("ar8x16_switch"), 0);
+ if (switch_drv) {
+ switchdev = device_get_parent(switch_drv);
+ if (switchdev) {
+ printf("%s: found master %s at %s\n", __func__,
+ device_get_nameunit(switchdev),
+ device_get_nameunit(switch_drv));
+ /* TODO: Ask PHY driver and return here */
+ }
+ }
mii->mii_media_status = IFM_AVALID;
- mii->mii_media_active = IFM_ETHER;
-// mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
+ mii->mii_media_active = IFM_ETHER|IFM_100_TX|IFM_FDX;
}
-
diff -r f8392f3407da -r fd105b7d9d74 head/sys/dev/switch/switch_obio.c
--- a/head/sys/dev/switch/switch_obio.c Fri Dec 02 15:27:25 2011 +0200
+++ b/head/sys/dev/switch/switch_obio.c Sat Dec 03 22:37:51 2011 +0200
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2011 Aleksandr Rybalko.
+ * Copyright (c) 2010-2011 Aleksandr Rybalko.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -104,7 +104,6 @@
return (ENXIO);
}
SWITCH_LOCK_INIT(sc);
-// error = switch_init(&sc->sc_switch);
error = switch_init(sc);
if (error)
return (error);
@@ -228,5 +227,3 @@
static devclass_t switch_obio_devclass;
DRIVER_MODULE(switch, obio, switch_obio_driver, switch_obio_devclass, 0, 0);
-//DRIVER_MODULE(switch, mii, switch_obio_driver, switch_obio_devclass, 0, 0);
-
diff -r f8392f3407da -r fd105b7d9d74 head/sys/dev/switch/switchb_if.m
--- a/head/sys/dev/switch/switchb_if.m Fri Dec 02 15:27:25 2011 +0200
+++ b/head/sys/dev/switch/switchb_if.m Sat Dec 03 22:37:51 2011 +0200
@@ -1,5 +1,5 @@
#-
-# Copyright (c) 2011 Aleksandr Rybalko <ray at ddteam.net>
+# Copyright (c) 2010-2011 Aleksandr Rybalko <ray at ddteam.net>
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
diff -r f8392f3407da -r fd105b7d9d74 head/sys/dev/switch/switchvar.h
--- a/head/sys/dev/switch/switchvar.h Fri Dec 02 15:27:25 2011 +0200
+++ b/head/sys/dev/switch/switchvar.h Sat Dec 03 22:37:51 2011 +0200
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2011, Aleksandr Rybalko <ray at ddteam.net>
+ * Copyright (c) 2010-2011, Aleksandr Rybalko <ray at ddteam.net>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -71,6 +71,8 @@
device_t sc_dev;
device_t child;
struct cdev *sc_cdev;
+ device_t child_miibus;
+ struct ifnet *ifp;
int enable;
struct switch_capability *caps;
@@ -81,6 +83,12 @@
int switch_deinit(struct switch_softc *sc);
int switch_tick(struct switch_softc *sc);
+/* Child MDIO access */
+int switch_miibus_writereg(device_t dev, int phy, int reg, int value);
+int switch_miibus_readreg(device_t dev, int phy, int reg);
+void switch_miibus_statchg(device_t dev);
+
+
#define SWITCH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
#define SWITCH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
#define SWITCH_LOCK_INIT(_sc) \
diff -r f8392f3407da -r fd105b7d9d74 head/sys/dev/switch/template_switch.c
--- a/head/sys/dev/switch/template_switch.c Fri Dec 02 15:27:25 2011 +0200
+++ b/head/sys/dev/switch/template_switch.c Sat Dec 03 22:37:51 2011 +0200
@@ -1,5 +1,5 @@
/*-
- * Copyright (c) 2010 Aleksandr Rybalko.
+ * Copyright (c) 2010-2011 Aleksandr Rybalko.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -64,11 +64,12 @@
static int get_port_speed(device_t dev, int port);
static int force_port_mode(device_t dev, int port, uint32_t mode);
+#ifdef mustbe_rewriten
static uint32_t stat_good_in_packet_count(device_t dev, int port);
static uint32_t stat_good_out_packet_count(device_t dev, int port);
static uint32_t stat_bad_in_packet_count(device_t dev, int port);
static uint32_t stat_bad_out_packet_count(device_t dev, int port);
-
+#endif
static int TEMPLATE_switch_isr(void *arg);
@@ -456,6 +457,7 @@
return (0);
}
+#ifdef mustbe_rewriten
static uint32_t
stat_good_in_packet_count(device_t dev, int port)
{
@@ -515,6 +517,7 @@
return (~0);
}
+#endif
static device_method_t TEMPLATE_switch_methods[] = {
DEVMETHOD(device_probe, TEMPLATE_switch_probe),
@@ -545,11 +548,13 @@
DEVMETHOD(switch_get_portspeed, get_port_speed),
DEVMETHOD(switch_force_mode, force_port_mode),
+#ifdef mustbe_rewriten
/* Statistics */
DEVMETHOD(switch_good_in_cnt, stat_good_in_packet_count),
DEVMETHOD(switch_good_out_cnt, stat_good_out_packet_count),
DEVMETHOD(switch_bad_in_cnt, stat_bad_in_packet_count),
DEVMETHOD(switch_bad_out_cnt, stat_bad_out_packet_count),
+#endif
{0, 0},
};
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